Data Storage Devices

Abstract

To reduce read-out time in a small-size data area related to a data storage apparatus and increase reading speed in the small-size data area.SOLUTION: A data storage apparatus according to an embodiment of the present invention comprises: a first data storage device; a second data storage device that has a longer read-out time than the first data storage device; and a storage controller that classifies data to be stored into a first group when the data size is within a first predetermined range and into a second group when the data size is within a second predetermined range larger than the first predetermined range, and stores the data belonging to the first group in the first storage device and stores the data belonging to the second group in the second data storage device.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to a data storage apparatus, and more particularly to a data storage apparatus that implements a data division and storage technique and a data sorting and storage technique. [Background technology]

[0002] Data storage devices such as SSDs (Solid State Discs) use data storage devices (e.g., NAND Flash). When NAND Flash is used for this data storage device, the first random data read time from receiving a read command from a data arithmetic processing device (e.g., CPU (Central Processing Unit)) to actually outputting the data is extremely long.

[0003] The reason for the slow first read time of random data from NAND Flash is that it takes 30 to 100 μs for the internal preparation time to arrange the data from the internal memory cells in the data register. The time from when the actual data processing unit issues a data read command to when it starts receiving data from the data storage device is the data output time of the data storage device plus the processing time by the storage controller in the data storage device.

[0004] Conventional SSD data storage devices have a slow read speed for small data areas ranging from 512B to 256KB data. In order to increase the speed of such conventional SSD data storage devices, there is no other way than to shorten (1) the control time of the storage controller, (2) the internal data preparation time of the memory device, and (3) the external data transfer time of the memory device.

[0005] In conventional technology, storage controllers have been improved, and a controller with a control time of about 9 μs has been announced (2018 ISSI presentation by Samsung). The internal data preparation time for Flash is generally around 75μs, and the external data transfer time is around 10ns / byte. For large-sized data, a certain improvement in read speed is expected due to the shortening of the control time of the storage controller and the performance improvement of NAND Flash.

[0006] However, the read speed of NAND Flash used in normal data storage devices is extremely slow for small-sized data. In small-sized data areas, the read time never falls below 45 μsec. In small-sized data areas, it is impossible to achieve, for example, 10 μsec using normal NAND Flash in a data storage device.

[0007] Furthermore, the use of multiple channels in memory devices has been studied to improve the speed of data storage devices, but while there has been a noticeable improvement in speed in large data areas, there is almost no effect in small data areas. This is because the internal data preparation time for NAND Flash is required simultaneously for all multi-channel devices, so there is almost no improvement in read time in data size areas of 16KB or less. However, the external data transfer time of NAND Flash is greatly improved by using multiple channels. This is the reason for the noticeable effect of using multiple channels in large data areas, but it does not contribute to the speed increase in the small data area in this case.

[0008] As described above, the conventional technology cannot solve the problem of long read times and low read speeds in small-sized data areas in data storage devices. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2015-46175 A Summary of the Invention [Problem to be solved by the invention]

[0010] An object of the present invention is to reduce the read time in a small-sized data area in a data storage device and to improve the read speed in the small-sized data area.

[0011] NAND Flash is available in SLC (Single Level Cell) and MLC (Multi Level Cell) products. In general, the use of SLC products is effective in improving read speed. However, the use of SLC products instead of MLC products across the board results in a significant increase in costs. SLC products cost about five times as much as MLC products. Therefore, the present invention aims to provide a speed improvement measure that does not significantly increase costs even when using MLC products. [Means for solving the problem]

[0012] In order to solve the above problem, in one embodiment of the present invention, a data storage apparatus according to one embodiment of the present invention is characterized by comprising a first data storage device, a second data storage device having a longer read time than the first data storage device, and a storage controller that divides original data to include a first portion close to the head of the data and a second portion farther from the head of the data, stores the first portion in the first data storage device and the second portion in the second data storage device, and, when reading data, combines and outputs the read first data and second data.

[0013] In another embodiment of the present invention, the system comprises a first data storage device, a second data storage device having a longer read time than the first data storage device, and a storage controller that sorts data to be stored into a first group if the data size is within a first predetermined range, and into a second group if the data size is within a second predetermined range larger than the first predetermined range, and stores the data belonging to the first group in the first data storage device and the data belonging to the second group in the second data storage device. [Brief description of the drawings]

[0014] [Figure 1] FIG. 13 is a diagram showing a read processing time of the data storage device according to each embodiment of the present invention. [Diagram 2] FIG. 13 is a diagram showing the data read time of a data storage device used in the data storage apparatus according to each embodiment of the present invention. [Diagram 3] 1 is a configuration diagram of a data storage device according to a first embodiment of the present invention. [Figure 4] 1 is a configuration diagram of a data storage device according to a first embodiment of the present invention. [Diagram 5] 4 is a diagram illustrating an operation of the storage controller according to the first embodiment of the present invention. [Figure 6] 4 is a diagram illustrating an operation of the storage controller according to the first embodiment of the present invention. [Figure 7] 1 is a diagram illustrating a specific example 1 of a storage controller according to a first embodiment of the present invention. [Figure 8] FIG. 1 is a diagram showing a first modified example of a data storage device according to a first embodiment of the present invention. [Figure 9] FIG. 1 is a diagram showing a first modified example of a data storage device according to a first embodiment of the present invention. [Figure 10] FIG. 11 is a diagram showing a second modified example of the data storage device according to the first embodiment of the present invention. [Figure 11]FIG. 11 is a diagram illustrating the operation of a data storage device according to a second embodiment of the present invention. [Figure 12] FIG. 11 is a diagram illustrating the operation of a data storage device according to a second embodiment of the present invention. [Figure 13] FIG. 11 is a diagram illustrating a specific example 1 of a storage controller according to a second embodiment of the present invention. [Figure 14] FIG. 11 is a diagram illustrating a specific example 1 of a storage controller according to a second embodiment of the present invention. [Figure 15] FIG. 11 is a diagram showing a third modified example of the data storage device according to the first or second embodiment of the present invention. [Figure 16] FIG. 11 is a diagram showing a fourth modified example of the data storage device according to the first or second embodiment of the present invention. [Figure 17] 1 is a chart showing the times required for each operation of a data storage device. [Figure 18] 1 is a graph showing read times (μsec) of a data storage device. [Figure 19] 1 is a chart showing the read speed (MB / sec) of a data storage device. [Figure 20] 11 is a table showing the readout time of concrete example 1 of the first embodiment. [Figure 21] 13 is a graph showing the readout time of Concrete Example 1 of the first embodiment. [Figure 22] 11 is a table showing the readout speed of concrete example 1 of the first embodiment. [Figure 23] 11 is a graph showing the read speed of a specific example 1 of the first embodiment. [Figure 24] 13 is a table showing the read time of a specific example 2 (direct access MRAM) of the first embodiment. [Diagram 25] 13 is a graph showing the read time of a specific example 2 (direct access MRAM) of the first embodiment. [Figure 26] 11 is a table showing the read speed of a specific example 2 (direct access MRAM) of the first embodiment. [Figure 27]13 is a graph showing the read speed of a specific example 2 (direct access MRAM) of the first embodiment. [Figure 28] 13 is a table showing the readout time of concrete example 1 of the second embodiment. [Figure 29] 13 is a graph showing the readout time of a specific example 1 of the second embodiment. [Diagram 30] 13 is a table showing the readout speed of concrete example 1 of the second embodiment. [Diagram 31] 13 is a graph showing the read speed of a specific example 1 of the second embodiment. [Diagram 32] 13 is a chart showing the read time of a specific example 2 (direct access MRAM) of the second embodiment. [Diagram 33] 13 is a graph showing the read time of a specific example 2 (direct access MRAM) of the second embodiment. [Diagram 34] 13 is a table showing the read speed of a specific example 2 (direct access MRAM) of the second embodiment. [Diagram 35] 13 is a graph showing the read speed of a specific example 2 (direct access MRAM) of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The data storage device according to the present invention will be described below with reference to the drawings. The data storage device according to the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the drawings referred to in the present embodiment, the same parts or parts having similar functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[0016] [First embodiment] FIG. 1 is a diagram showing the read processing time of the data storage device 100 according to each embodiment of the present invention. A data arithmetic processing device 200 such as a CPU sends a read command to the data storage device 100. The data storage device 100 is composed of a storage controller 110 and a data storage device 120. The storage controller 110 issues a read command to the data storage device 120. The read control processing time until the storage controller 110 issues a read command to the data storage device 120 is the control processing time 1. Next, the time when the data storage device 120 that received the read command outputs data is the data storage device data processing time, which is composed of the data internal preparation time and the data external transfer time. Next, the output control processing time required for the storage controller 110 to control the output of the read data output by the data storage device to the data arithmetic processing device 200 is the control processing time 2. The time required for the data storage device 100 to read data is the total time of the control processing time 1 + the data internal preparation time + the data external transfer time + the control processing time 2.

[0017] 2 is a diagram showing the data read time of the data storage device 120 used in the data storage apparatus 100 according to each embodiment of the present invention. The data internal preparation time is the time from when the data storage device 120 receives a read command until it starts data (output of the first data). The data storage device is provided with a page buffer, and the read data is set in this page buffer. The data set in the page buffer is then transferred to the outside. The data external transfer time is the time it takes for the data to be transferred to the outside.

[0018] The internal data preparation time varies depending on the type of memory device. For example, it is 35 μs for SLC NAND Flash, 75 μs for MLC NAND Flash, and 0.1 μs for B4-Flash sold by Potos Semiconductor Co., Ltd.

[0019] B4-Flash is a NOR flash memory that uses the write operation principle of B4-HE (Back Bias assisted Band to Band tunneling, Hot Electron). Because it is a NOR flash memory, random access is extremely fast.

[0020] The data external transfer time may or may not vary depending on the type of memory device. For example, for SLC NAND Flash and MLC NAND Flash, it is 10ns x data size (Byte). For B4-Flash, it is (10ns to 20ns) x data size (Byte).

[0021] 3 is a diagram for explaining the internal data preparation time of the data storage device 100 according to the first embodiment of the present invention. The data storage device 100 is connected to a data arithmetic processing device 200. The data storage device 100 comprises a storage controller 110 and n data storage devices 121-124. The internal data preparation times of the n data storage devices 121-124 are t1, t2-tn, respectively, which are not all the same. For example, t1 may be small and t2-tn may be large. t1 <t2<tn-1=tnでもよい。

[0022] 4 is a diagram for explaining the data external transfer time of the data storage apparatus 100 according to the first embodiment of the present invention. The data external transfer times of the n data storage devices 121 to 124 are s1, s2 to sn, respectively, and these are not all the same. For example, there are cases where s1 is small and s2 to sn are large. s1 <s2<sn-1=snでもよい。

[0023] 5 and 6 show the operation of the storage controller 110 according to the first embodiment of the present invention shown in FIG. 3 and FIG. 4. The original data is data before division. The earliest read point is the data header, and the latest read point is the data tail. The data are arranged from the earliest read area to the latest read area according to the output time series at the time of data reading. The storage controller 110 puts a delimiter in the original data according to a preset setting. The delimiter is, for example, V1, V2, V3, . . . Vn-1. The storage controller 110 divides the original data into a maximum of n pieces of data D1 (data from the data header to V1 or less), D2 (data exceeding V1 and V2 or less), D3 (data exceeding V2 and V3 or less), . . . Dn (data exceeding Vn-1).

[0024] As shown in FIG. 6, up to n pieces of data D1 to Dn are stored in data storage device (1) 121, data storage device (2) 122, data storage device (3) 123, ..., data storage device (n) 124, each of which has a different read performance (here, internal data preparation time) (when writing, writing is performed based on this correspondence, and when reading, reading is performed based on this correspondence).

[0025] Data storage device (1) 121, data storage device (2) 122, data storage device (3) 123, ... data storage device (n) 124, which have different read performance, may have different external data transfer times rather than or in addition to different internal data preparation times.

[0026] Fig. 7 shows a specific example 1 of the storage controller 110 according to the first embodiment of the present invention shown in Figs. 5 and 6. The maximum size of the original data before division is 1024 KB. The storage controller 110 divides the data into 8 KB and 64 KB segments. The original data is divided into 8 KB data, 56 KB data, and the remaining 960 KB data from the beginning of the data. The 8 KB data from the beginning of the data is then stored in the high-speed B4-Flash (shortest internal data preparation time), and the 56 KB data is stored in the medium-speed SLC (medium internal data preparation time). The first 960KB of data is stored in the DDR NAND Flash, and the remaining 960KB of data is stored in the slower (longest internal data preparation time) MLC NAND Flash (when writing, writing is performed in this correspondence, and when reading, reading is performed in this correspondence).

[0027] Another specific example 2 is the use of MRAM (Magnetoresistive Random Access Memory). Unlike B4-Flash and NAND Flash, MRAM can use direct access without converting physical addresses and logical addresses. In this case, it is possible to operate at extremely high speed since it does not go through the file system provided by the storage controller 110. And it becomes even faster by a total of 9 μs of the control processing time 1 and the control processing time 2 of the storage controller 110. The maximum size of the original data before division is 1024 KB. The storage controller 110 divides the data into 1 KB, 8 KB, and 64 KB. The original data is divided into 1 KB data, 7 KB data, 56 KB data, and the remaining 960 KB data from the beginning of the data. The first 1KB of data is stored in the fastest MRAM (zero control processing time and extremely short internal data preparation time), 7KB of data is stored in the high-speed B4-Flash (short internal data preparation time), 56KB of data is stored in the medium-speed SLC NAND Flash (medium internal data preparation time), and the remaining 960KB of data is stored in the slow-speed MLC NAND Flash (longest internal data preparation time) (this correspondence is used when writing, and this correspondence is used when reading).

[0028] [Variation 1: Saving division information] 8 is a diagram showing a data write operation of the data storage device 100 according to the first embodiment of the present invention. A storage area 130 is provided for storing division information (including V1, V2, V3, . . . Vn-1, which are data indicating delimiters when dividing the original data). The storage area 130 may be provided inside the storage controller 110 or outside the storage controller 110. The storage controller 110 stores the division information in the storage area 130. The storage controller 110 may be able to set specific values ​​of V1, V2, V3, . . . Vn-1, which are data indicating delimiters when dividing the original data, by receiving a predetermined command from the data processing device 200.

[0029] 9 is a diagram showing a data read operation of the data storage device according to the first embodiment of the present invention. When a data read request is made from the data processing device 200, the storage controller 110 reads the division information from the division information storage area 130, and performs reading from the data storage devices 121 to 124 based on this value. In this way, the read divided data D1, D2, D3, and Dn are recombined and output to the data processing device 200.

[0030] [Variation 2: Saving the original data] FIG. 10 is a diagram showing a second modification of the data storage device 100 according to the first embodiment of the present invention. In addition to the above embodiment, a data storage device 140 is added. The original data is stored in this data storage device 140 as is. As a result, consistency between the divided data and the data before division is ensured. In particular, when used together with the second modification, there is an advantage that the original data can be restored even if the division information is changed.

[0031] [Second embodiment] 11 shows the operation of the storage controller 110 according to the second embodiment of the present invention. The original data Data1, Data2,..., Datam have various data sizes. The storage controller 110 sorts each of these original data by data size. The threshold data sizes are V1, V2, V3..., Vn-1 (unit: Byte). The storage controller 110 sorts each of the original data into group 1 (data whose data size is V1 or less), group 2 (data whose data size exceeds V1 and is V2 or less), group 3 (data whose data size exceeds V2 and is V3 or less),..., group n (data whose data size exceeds Vn-1).

[0032] 12 shows the operation (continuation) of the storage controller 110 according to the second embodiment of the present invention. The original data sorted by the storage controller 110 is shown. Data3 is sorted into group 1, Data4 into group 2, Data1 and Data6 into group 3, and Data2 and Datam into group n. The storage controller 110 stores the data sorted into these groups in data storage devices 120 with different read performances (here, data internal preparation times). The data of group 1 is stored in data storage device (1) 121, the data of group 2 in data storage device (2) 122, the data of group 3 in data storage device (3) 123, and the data of group n in data storage device (n) 124.

[0033] Data storage device (1) 121, data storage device (2) 122, data storage device (3) 123, ... data storage device (n) 124, which have different read performance, may have different external data transfer times rather than or in addition to different internal data preparation times.

[0034] 13 and 14 show a specific example 1 of the storage controller 110 according to the second embodiment of the present invention shown in FIGS. 11 and 12. The original data before sorting has various data sizes. The storage controller 110 sorts the data using thresholds of 8 KB and 64 KB. Group 1 is data with a data size of 8 KB or less, group 2 is data with a data size exceeding 8 KB and 64 KB or less, and group 3 is data with a data size exceeding 64 KB. The storage controller 110 then stores group 1 of data in high-speed B4-Flash, group 2 of data in SLC NAND Flash, and group 3 of data in MLC NAND Flash.

[0035] Another specific example 2 is an example using MRAM. The original data before sorting has various data sizes. The storage controller 110 sorts the data using thresholds of 1KB, 8KB, and 64KB. Group 1 is data with a data size of 1KB or less, group 2 is data with a data size of more than 1KB and less than 8KB, group 3 is data with a data size of more than 8KB and less than 64KB, and group 4 is data with a data size of more than 64KB. The storage controller 110 then stores group 1 data in direct access MRAM, group 2 data in high-speed B4-Flash, group 3 data in SLC NAND Flash, and group 4 data in MLC NAND Flash.

[0036] When the data storage device 100 according to the second embodiment receives a data read command from the data processing device 200, the storage controller 110 reads the data from the data storage device in which the corresponding data is stored, and then transfers the read data to the data processing device 200.

[0037] [Variation 3: Example of using a data storage device group, etc.] FIG. 15 is a diagram showing a third modified example of the data storage device 100 according to the first or second embodiment of the present invention. A plurality of data storage devices having the same memory characteristics (various characteristics including read performance such as internal preparation time and data transfer time) are grouped. The data storage devices (1-1) 1211 to (1-m1) 121m have the same memory characteristic c1. The data storage devices (2-1) 1221 to (2-m2) 122m have the same memory characteristic c2. The data storage devices (n-1) 12n1 to (n-mn) 12nm have the same memory characteristic cn. In the first embodiment, the storage controller 110 divides the original data into n and stores the divided data according to the memory characteristics, and in the second embodiment, the storage controller 110 divides the original data into n groups and stores them in different groups of data storage devices.

[0038] The data storage device(s) may each be a NAND Flash or B4-Flash chip. The storage controller 110 may be an independent LSI, or the data storage device(s) may each be provided within a NAND Flash or B4-Flash chip. The storage controller 110 may be an independent LSI, or may be configured in a so-called tree shape, with a main storage controller and multiple sub-storage controllers, each corresponding to an individual data storage device(s).

[0039] Some of the data storage devices 121 (1211 to 121m) may be formed in one semiconductor chip together with the storage controller 110, and the remaining data storage devices 122 (1221 to 122m) to 124 (12n1 to 12nm)) may be configured as external chips.

[0040] Specifically, a desirable example would be to mount a small-capacity B4-Flash, which has an extremely short internal data preparation time, together with a storage controller 110 that is mainly composed of logic circuits, while a NAND Flash, which is becoming increasingly three-dimensional and has an extremely complicated manufacturing process that makes it unsuitable for mounting together with logic circuits, would be configured as an external semiconductor chip.

[0041] [Variation 4: Example of using multiple areas with different memory characteristics within one memory device] 16 is a diagram showing a fourth modified example of the data storage device 100 according to the first or second embodiment of the present invention. A plurality of areas (a1) 151, (a2) 152, (an-1) 15n-1, (an) 15n with different memory characteristics are provided in one memory device 150. In the first embodiment, the storage controller 110 divides the original data into n parts and stores the divided data according to the memory characteristics, while in the second embodiment, the original data is sorted into n groups and stored in different memory device areas.

[0042] In the fourth modification, in combination with the third modification, some of the data storage devices 121 may be formed in one semiconductor chip together with the storage controller 110, and the other data storage devices 122 may be external, and a plurality of areas (a2) 152, (a3) ​​153 with different memory characteristics may be provided inside the external data storage device 122. Specifically, the data storage device 121, which is made of a small-capacity B4-Flash and requires an extremely short internal data preparation time, is mounted together with the storage controller 110, which is mainly composed of a logic circuit. The data storage device 122, which is made of NAND Flash and is not suitable for mounting together with a logic circuit because of its extremely complicated manufacturing process due to its advanced three-dimensional structure, is configured as an external semiconductor chip. The data storage device 122 is provided with an SLC area (a2) 152 and an MLC area (a3) ​​153. EXAMPLES

[0043] [Verification by practical example] The data storage device 120 used to verify the effects of the above embodiment of the present invention is a combination of three types of flash: B4-Flash, SLC NAND Flash, and MLC NAND Flash. The time required for each operation of the data storage device is shown in Figure 17. The number of channels operating independently was four.

[0044] The read time (μsec) and read speed (MB / sec) of the data storage device 100 using the data storage device 120 shown in FIG. 17 are as shown in FIGS. 18 and 19. By using B4-Flash for the data storage device 120, the data storage device can achieve high speed in small data areas. The effect of high speed is visible at 64KByte, but is more noticeable at 8KByte or less. However, since B4-Flash is more expensive than NAND Flash (more than 10 times more expensive than MLC NAND Flash, and more than twice more expensive than SLC NAND Flash), if the data storage device 120 is composed only of B4-Flash, the data storage device will become extremely expensive.

[0045] [Verification of Specific Example 1 of the First Embodiment] The first concrete example of the first embodiment used in the verification is as follows. That is, the maximum size of the original data before division is 1024KB. The storage controller 110 divides the data into 8K and 64KB. The original data is divided into 8KB data, 56KB data, and the remaining 960KB data from the beginning of the data. Then, the 8KB data from the beginning of the data is stored in the high-speed B4-Flash (shortest data internal preparation time), the 56KB data is stored in the medium-speed SLC NAND Flash (medium data internal preparation time), and the remaining 960KB data is stored in the low-speed MLC NAND Flash (longest data internal preparation time). Figure 20 shows the read time of the first concrete example of the first embodiment, and Figure 21 shows a graph of the read time. Figure 22 shows the read speed of the first concrete example of the first embodiment, and Figure 23 shows a graph of the read speed.

[0046] Data of 8KB or less is read only from the B4-Flash area. For data exceeding 8KB but not exceeding 64KB, the partial data of the B4-Flash area up to 8KB of the data and the partial data of the SLC NAND area over 8KB but not exceeding 64KB are read and combined. For data exceeding 64KB, the partial data of the B4-Flash area up to 8KB of the data and the partial data of the SLC NAND area over 8KB but not exceeding 64KB, and the partial data of the MLC NAND area over 64KB are read and combined. When reading data from the MLC NAND area, the data in the MLC NAND area can be pre-read into the buffer area of ​​the storage controller before the partial data of the SLC NAND area over 8KB but not exceeding 64KB is read, making it faster than when reading only B4-Flash or only SLC NAND.

[0047] Thus, according to the first embodiment, in the small data area, the speed is almost the same as that of the B4-Flash, which was the fastest in the prior art, and in the medium data area, the speed is almost the same as that of the B4-Flash. In the large data area of ​​128 KB or more, the effect of read-ahead of the improved MLC NAND data is realized, and the fastest speed is realized.

[0048] The cost required to obtain such an effect will be considered. Consider a 1T (tera) Byte data storage device that stores an average of 1MB of data. The number of files to be saved is 1M. Since it is necessary to prepare 1M data sets for each of the 8KB B4-Flash area and the 56KB SLC NAND area for all file data, the B4-Flash requires a capacity of 8GB and the SLC NAND requires a capacity of 56GB. However, for a total capacity of 1TB, the B4-Flash only requires a capacity of 0.8% and the SLC NAND only requires a memory capacity of 5.6%. If the B4-Flash is 10 times the cost of the MLC NAND and the SLC NAND is 5 times the cost, the cost of the conventional data storage device 1TB will increase by 8% + 28% = 36%, but the performance cannot be achieved by other technologies. If the entire 1TB is realized with B4-Flash to obtain the highest performance, the total cost will be 10 times, so the cost reduction effect of this embodiment is large.

[0049] [Verification of Specific Example 2 of the First Embodiment] The concrete example 2 of the first embodiment used for the verification is as follows. That is, the maximum size of the original data before division is 1024KB. The storage controller 110 divides the data into 1KB, 8KB, and 64KB. The original data is divided into 1KB data, 7KB data, 56KB data, and the remaining 960KB data from the beginning of the data. Then, the 1KB data from the beginning of the data is stored in the ultra-fast MRAM (direct access with the shortest internal data preparation time), the 7KB data in the high-speed B4-Flash (short internal data preparation time), the 56KB data in the medium-speed SLC NAND Flash (medium internal data preparation time), and the remaining 960KB data in the low-speed MLC NAND Flash (longest internal data preparation time). Since the MRAM is a direct access, it does not go through the file system (logical address / physical address conversion) by the storage controller 110, so that the overhead time of 9 μs can be saved. FIG. 24 shows the read time of the concrete example 2 of the first embodiment, and FIG. 25 shows a graph of the read time. FIG. 26 shows the read speed of the second specific example of the first embodiment, and FIG. 27 shows a graph of the same.

[0050] As can be seen from these tables and graphs, the speed improvement effect is extremely high in areas of 1KB or less. This is because, in the verification of Specific Example 1, the control time required for the operation of the storage controller of the data storage device is a fixed time, and affects the speed when the amount of data is small. In contrast, MRAM has the same fast data writing and reading speed as the reading speed of B4-Flash, and when direct access is used, data can be processed without going through a file system. However, since MRAM costs about 1000 times more than MLC NAND, it was impossible to use large-capacity products as data storage devices for data storage devices.

[0051] In the second concrete example, by taking advantage of the advantages of MRAM and compensating for its disadvantage of high cost, it was possible to realize ultra-high-speed transfer of extremely small data in a data storage device. The data of 8KB or less stored in the B4-Flash area in the first concrete example is further divided into 1KB or less from the beginning of the data and 7KB of data exceeding 1KB and 8KB or less, the former is stored in the MRAM area, and the latter is stored in the B4-Flash area. The data in the MRAM area is stored by a direct memory access method as data without using a file system, so MRAM operation is simplified and it can operate in 0.1μsec. In the above verification, the control time when directly accessing MRAM was set to 0.2μsec. In addition, although there are several types of MRAM performance, the currently available data internal preparation time = 0.1μsec and data external output time = 10ns / Byte were set.

[0052] The verification results of Specific Example 2 show that in areas of 1KB or less, even greater speedups are achieved than in Specific Example 1. To store 1M files on a 1TB data storage device, 1KB*1M=1GB of MRAM is required. Considering that MRAM costs 1000 times more than MLC NAND, this adds 100% of the cost to the additional cost of Specific Example 1. In other words, the cost is more than double that of a data storage device using conventional MLC NAND, but it achieves speeds that are not possible anywhere else.

[0053] [Verification of Specific Example 1 of the Second Embodiment] The specific example 1 of the second embodiment used in the verification is as follows. That is, the storage controller classifies data ordered to be stored by the data processing device into group 1, which has a data size of 8 KB or less, group 2, which has a data size of over 8 KB and 64 KB or less, and group 3, which has a data size of over 64 KB. Groups 1 to 3 are stored in order of the data internal preparation time of the storage device. The data of group 1 is stored in B4-Flash, the data of group 2 is stored in SLC NAND, and the data of group 3 is stored in MLC NAND. Figure 28 shows the read time of specific example 1 of the second embodiment, and Figure 29 shows a graph of the read time. Figure 30 shows the read speed of specific example 1 of the second embodiment, and Figure 31 shows a graph of the read speed.

[0054] From the verification results of Specific Example 1 of the second embodiment, the following facts can be understood. In small size data areas up to 8 KB, the same effect as in Specific Example 1 of the first embodiment is obtained, but in medium size data areas exceeding 8 KB up to 64 KB, the read speed is exactly the same as that of a data storage device using only SLC NAND, and in large size data areas exceeding 64 KB, the read speed is exactly the same as that of a data storage device using only MLC NAND. This is because the effect of pre-reading small data portions in medium size data obtained in Specific Example 1 of the first embodiment is not obtained in this embodiment. The same is true for large size data areas.

[0055] In this specific example, the hardware configuration of the device is the same as that of specific example 1 of the first embodiment, and the cost is also the same, but the internal operation procedure of the storage controller is simplified, and the software development load is reduced. In addition, the effect of shortening the control time of the storage controller can be expected.

[0056] [Verification of Specific Example 1 of the Second Embodiment] The second embodiment of the specific example used in the verification is as follows. That is, the storage controller classifies data ordered to be stored by the data processing device into group 1, which has a data size of 1 KB or less, group 2, which has a data size of over 1 KB and 8 KB or less, group 3, which has a data size of over 8 KB and 64 KB or less, and group 4, which has a data size of over 64 KB. Groups 1 to 4 are stored in order of the shortest internal data preparation time of the storage device. The data of group 1 is stored in MRAM (direct access), the data of group 2 in B4-Flash, the data of group 3 in SLC NAND, and the data of group 4 in MLC NAND. Figure 32 shows the read time of the second embodiment of the specific example 2, and Figure 33 shows a graph of the read time. Figure 34 shows the read speed of the second embodiment of the specific example 2, and Figure 35 shows a graph of the read speed.

[0057] [Other variations] In the above specific example, SLC NAND, MLC NAND, B4-Flash, MRAM, etc. are used as data storage devices. However, non-volatile memory such as 3DXpoint or ReRAM may also be used, and volatile memory such as DRAM may also be used. However, when using volatile memory, separate measures for handling when the power is turned off are required. Specifically, a battery backup is required.

[0058] In the above specific examples, an independent data storage device has been described as an example, but it may also be configured as separate independent units with some or all of its functions separated out, and all or some of its functions may be implemented within one or more semiconductor chips. [Explanation of symbols]

[0059] 100 Data storage device 110 Storage Controller 120~124 Data storage devices 200 Data Processing Unit

Claims

1. a first data storage device; a second data storage device having a longer read time than the first data storage device; a third data storage device having a longer read time than the second data storage device; a storage controller which classifies data to be stored into a first group when the data size is within a first predetermined range, into a second group when the data size is within a second predetermined range larger than the first predetermined range, and into a third group when the data size is within a third predetermined range larger than the second predetermined range, and stores the data belonging to the first group in the first data storage device, the data belonging to the second group in the second data storage device, and the data belonging to the third group in the third data storage device; Equipped with The data storage apparatus, wherein the storage controller, upon receiving a data read command, reads the data from a data storage device in which the data is stored.

2. 2. The data storage device of claim 1, wherein the first data storage device is an MRAM.

3. 2. The data storage device of claim 1, wherein said first data storage device is a DRAM.

4. 2. The data storage system of claim 1, wherein the first data storage device is capable of utilizing direct access.

5. 2. The data storage device of claim 1, wherein the first data storage device is a B4-Flash and the second data storage device is a NAND Flash.

6. 2. The data storage device of claim 1, wherein the second data storage device is an SLC NAND Flash and the third data storage device is an MLC NAND Flash.

7. 2. The data storage device according to claim 1, further comprising a memory area for storing information relating to a boundary separating the first group from the second group and information relating to a boundary separating the second group from the third group.

8. The data storage apparatus of claim 1, further comprising a plurality of first data storage devices having identical memory characteristics; A data storage apparatus, characterized in that data belonging to said first group is stored in said plurality of first data storage devices.

9. In the data storage device described in claim 8, the storage controller is characterized in that it is configured in a tree shape from a main storage controller and a plurality of sub-storage controllers, each of which corresponds to each of the plurality of first data storage devices.

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