Semiconductor Integrated Circuit

Abstract

To improve voltage waveform delays when receiving voltage with delayed waveforms at external terminals.SOLUTION: A semiconductor integrated circuit has a voltage detection unit that detects a falling or rising change in the voltage received at an external terminal, a pulse generation unit that generates a pulse signal in response to the detection of the voltage change by the voltage detection unit, and a voltage change acceleration unit that accelerates the change in the voltage received via the external terminal in response to the pulse signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor integrated circuit. [Background technology]

[0002] In an automatic fire notification system having fire detectors and fire receivers connected to each other via a detector line, a method has been proposed for detecting deterioration of electrical wires over time by determining the degree of distortion of the waveform of the communication signal (see, for example, Patent Document 1).

[0003] In addition, a method has been proposed for reducing power consumption in a slave unit of an automatic fire alarm system by switching the receiving unit, which receives signals from the master unit, between a receiving operation state or a reception stop state depending on whether or not operating power is provided to the receiving unit (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-130048 A [Patent Document 2] JP 2017-37433 A Summary of the Invention [Problem to be solved by the invention]

[0005] For example, in a system that transmits information by changing the voltage supplied to a transmission line, the falling or rising edge of the voltage waveform may be delayed due to the parasitic capacitance of the receiving unit that receives the voltage. If the voltage waveform is delayed, it takes longer for the change in the voltage waveform to be transmitted to the downstream circuit, and the response of the downstream circuit to the voltage change is delayed.

[0006] The disclosed technology aims to improve the delay in a voltage waveform when a voltage with a delayed waveform is received at an external terminal. [Means for solving the problem]

[0007] In order to solve the above technical problem, a semiconductor integrated circuit according to one aspect of the present invention is a semiconductor integrated circuit having a voltage input to an external terminal. Falling a pulse generating section that generates a pulse signal in response to the detection of the voltage change by the voltage detecting section; and a voltage change accelerating section that accelerates the change in the voltage received via the external terminal in response to the pulse signal. the voltage detection unit has a first voltage divider circuit that divides the voltage received at the external terminal to generate a first divided voltage, a second voltage divider circuit that divides the voltage received at the external terminal to generate a second divided voltage higher than the first divided voltage, a first input terminal that receives the first divided voltage, and a second input terminal that receives the second divided voltage, a comparator that compares the first divided voltage with the second divided voltage, and a load connected to either the first input terminal or the second input terminal, and the pulse generation unit generates a pulse signal in response to a comparison result signal output from the comparator in accordance with a change in the falling edge of the voltage. Effect of the Invention

[0008] When a voltage with a delayed waveform is received at an external terminal, the delay of the voltage waveform can be improved. [Brief description of the drawings]

[0009] [Figure 1] 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention. [Diagram 2] 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit of FIG. [Diagram 3] FIG. 11 is a circuit diagram showing an example of another semiconductor integrated circuit. [Figure 4] FIG. 11 is a circuit diagram showing another example of another semiconductor integrated circuit. [Diagram 5] FIG. 2 is a circuit diagram showing a second embodiment of a semiconductor integrated circuit according to the present invention. [Figure 6] 6 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit of FIG. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described with reference to the drawings. In the following, the voltage lines, terminals, and nodes through which voltages are transmitted are designated by the same reference numerals as the voltage names, and the signal lines, terminals, and nodes through which signals are transmitted are designated by the same reference numerals as the signal names. In each drawing, the same components are designated by the same reference numerals, and duplicated descriptions may be omitted.

[0011] (First embodiment) Fig. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit of the present invention. The semiconductor integrated circuit 100 shown in Fig. 1 has a function of improving a delay of a falling edge waveform of a voltage when the voltage Rx received via an external terminal Rx is transmitted to a downstream circuit. The semiconductor integrated circuit 100 has a voltage detection unit 10 that detects a change in the falling edge of the voltage Rx, a pulse generation unit 20, and a voltage change acceleration unit 30. For example, the semiconductor integrated circuit 100 is mounted on a receiver of a communication system and has a function of receiving a voltage signal transmitted from a transmitter of the communication system.

[0012] The voltage detection unit 10 includes resistive elements R11, R12, R13, and R14, a capacitive element C11, and a comparator CMP11. The resistive elements R11 and R12 are connected in series between the external terminal Rx and the ground terminal GND via a connection node to the negative input terminal IN- of the comparator CMP11. Hereinafter, the voltage line connected to the external terminal Rx is also referred to as the voltage line Rx. The resistive elements R13 and R14 are connected in series between the voltage line Rx and the ground line GND via a connection node to the positive input terminal IN+ of the comparator CMP11. The capacitive element C11 is connected between the input terminal IN- and the ground line GND.

[0013] The resistor elements R11 and R12 are an example of a first voltage dividing circuit that generates a first divided voltage at the connection node of the resistor elements R11 and R12 and supplies the generated first divided voltage to the input terminal IN-. The resistor elements R13 and R14 are an example of a second voltage dividing circuit that generates a second divided voltage at the connection node of the resistor elements R13 and R14 and supplies the generated second divided voltage to the input terminal IN+. The resistance values ​​of the resistor elements R11, R12, R13, and R14 are set so that the voltage of the input terminal IN+ (second divided voltage) is higher than the voltage of the input terminal IN- (first divided voltage) when the voltage Rx is maintained constant.

[0014] 1, since a load (capacitive element C11) is connected to the input terminal IN-, when the voltage Rx drops, the rate at which the voltage IN- drops can be made slower than the rate at which the voltage IN+ drops. This allows the voltage IN+ to be temporarily lower than the voltage IN- when the voltage Rx falls, and as will be described later, a low-level pulse signal (COUT) can be output from the comparator CMP11.

[0015] In the falling edge of the voltage Rx, when the voltage IN+ becomes lower than the voltage IN-, the rate of decrease from the high level value of the voltage Rx is almost the same regardless of the high level value. Therefore, for example, regardless of the specifications of the high level value of the voltage R, the decrease of the voltage Rx can be accelerated when the voltage Rx decreases to a certain ratio (for example, 70%) of the high level value. Here, the certain ratio is the ratio of the voltage Rx when the difference between the high level value and the low level value of the voltage Rx is set to 100%. Therefore, even if the electrical specifications of the high level value of the voltage Rx differ for each system in which the semiconductor integrated circuit 100 is mounted, the n-channel transistor NM of the voltage change acceleration unit 30 described later can be turned on when the voltage Rx decreases to the certain ratio. Although not limited to these, for example, the high level value of the voltage Rx is 34V, 24V, or 10V, and the low level value of the voltage Rx is 8V, 6V, or 2V.

[0016] The comparator CMP11 outputs a high-level output signal COUT when the voltage received at the input terminal IN+ is greater than the voltage received at the input terminal IN-. The comparator CMP11 outputs a low-level output signal COUT when the voltage received at the input terminal IN+ is less than the voltage received at the input terminal IN-. Although not limited to this, the comparator CMP11 is a hysteresis comparator. The output signal COUT is an example of a comparison result signal.

[0017] The pulse generating unit 20 includes inverters IV11 and IV12, a resistive element R15, a capacitive element C12, and an OR gate OR. The inverter IV11 and the resistive element R15 are connected in series between the output node COUT of the comparator CMP11 and one input of the OR gate OR. One end of the capacitive element C12 is connected between the resistive element R15 and one input of the OR gate OR, and the other end of the capacitive element C12 is connected to a ground line GND. The resistive element R15 and the capacitive element C12 function as a time constant circuit (delay circuit) that delays the output signal from the inverter IV11 for a predetermined time. The predetermined time to be delayed by the time constant circuit is determined according to the amount required for the pulse width of the pulse signal PLS described later.

[0018] The OR gate OR receives the output signal COUT and a signal obtained by inverting the output signal COUT by an inverter IV11 and delaying it by a predetermined time. The OR gate OR outputs a low-level pulse signal PLS0 in synchronization with the falling edge of the output signal COUT. The inverter IV12 inverts the logic of the low-level pulse signal PLS0 and outputs a high-level pulse signal PLS. Therefore, the semiconductor integrated circuit 100 outputs a high-level pulse signal PLS as a falling detection signal in response to detection of a falling edge of the voltage Rx.

[0019] The voltage change acceleration unit 30 has an n-channel transistor NM that receives the pulse signal PLS at its gate (control terminal), has its drain connected to the voltage line Rx, and has its source connected to the ground line GND. For example, the n-channel transistor NM is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited to a MOSFET and may be a switch element having a control terminal such as an NPN bipolar transistor. In response to the transition of the pulse signal PLS to a high level, the n-channel transistor NM conducts (ON) between the drain and the source, and draws charge from the voltage line Rx during the high level period. In this way, the n-channel transistor NM functions as a discharge element. This makes it possible to increase the falling speed when the voltage Rx falls, and improve the delay of the falling waveform of the voltage Rx supplied via the external terminal Rx.

[0020] As described later, when the voltage Rx falls, the comparator CMP11 outputs a low-level pulse signal. Therefore, if the accuracy of the pulse width of the pulse signal PLS is not required, the pulse generating unit 20 may not be provided, and the output of the comparator CMP11 may be connected to the gate of the n-channel transistor NM via only the inverter IV12.

[0021] Fig. 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit 100 of Fig. 1. For example, when the voltage Rx received at the external terminal Rx is maintained at a high level or a low level, the voltage IN+ supplied to the input terminal IN+ becomes higher than the input voltage IN- supplied to the input terminal IN-. Therefore, the comparator CMP11 outputs a high-level output signal COUT. The low-level value of the voltage Rx is a predetermined voltage determined by the electrical specifications of the semiconductor integrated circuit 100 and is higher than the ground voltage GND.

[0022] In the example shown in Fig. 2, when the voltage Rx changes to a low level value, the falling edge of the waveform is delayed due to the parasitic capacitance of the circuit connected to the external terminal Rx. For example, assume that a diode bridge is connected to the external terminal Rx, and the voltage Rx is supplied to the external terminal Rx from the diode bridge, or a surge absorber is connected to the external terminal Rx. In this case, the waveform when the voltage Rx changes is delayed due to the parasitic capacitance of the diode bridge or the surge absorber.

[0023] In Fig. 2, as the voltage Rx drops, the voltages IN+ and IN- drop. At this time, the fall speed of the voltage IN- at the input terminal IN- to which the load of the capacitance element C11 is connected is slower than the fall speed of the voltage IN+. In other words, the voltage IN- drops later than the voltage IN+ due to the effect of the capacitance element C11.

[0024] As a result, the voltage IN+ becomes lower than the voltage IN-, and the comparator CMP11 changes the output signal COUT from high to low. The pulse generating unit 20 outputs a high-level pulse signal PLS in response to the falling edge of the output signal COUT. The n-channel transistor NM turns on during the period when the pulse signal PLS is at a high level, and draws charge from the voltage line Rx, accelerating the falling speed of the voltage Rx.

[0025] The high-level period of the pulse signal PLS is set by a time constant circuit consisting of a resistive element R15 and a capacitive element C12. Therefore, by using an appropriate time constant circuit, the voltage Rx can be quickly set to a predetermined low-level value while preventing the voltage Rx from dropping below the low-level value. The dashed line shown in the waveform of the voltage Rx is the waveform when the semiconductor integrated circuit 100 does not have the voltage detection unit 10, the pulse generation unit 20, and the voltage change acceleration unit 30.

[0026] As described above, in the first embodiment, the falling speed of the voltage Rx received at the external terminal Rx can be increased, and the delay of the falling waveform of the voltage Rx can be improved. This allows the processing of the downstream circuit that operates in response to the falling edge of the voltage Rx to start early, and the performance of the semiconductor integrated circuit 100 or the performance of the system including the semiconductor integrated circuit 100 can be improved. Alternatively, the malfunction of the downstream circuit can be prevented, and the reliability of the semiconductor integrated circuit 100 or the system including the semiconductor integrated circuit 100 can be improved.

[0027] By supplying the two divided voltages generated by resistor division to the input terminals IN+ and IN- of the comparator CMP11, respectively, it is possible to make the voltage IN+ higher than the voltage IN- when the voltage Rx is maintained constant. Also, because a load (capacitive element C11) is connected to the input terminal IN-, it is possible to make the rate at which the voltage IN- drops slower than the rate at which the voltage IN+ drops when the voltage Rx drops. This makes it possible to make the voltage IN+ temporarily lower than the voltage IN- when the voltage Rx falls, and to output a low-level pulse signal (COUT) from the comparator CMP11.

[0028] Furthermore, by providing the pulse generating unit 20, the on-period of the n-channel transistor NM can be set to any period by the time constant circuit. Also, by drawing out the charge from the voltage line Rx by the n-channel transistor NM, the delay of the falling waveform of the voltage Rx can be improved by a simple discharge element.

[0029] When the voltage Rx falls, the rate of decrease from the high level value of the voltage Rx when the voltage IN+ becomes lower than the voltage IN- is substantially the same regardless of the high level value. Therefore, even if the electrical specifications of the high level value of the voltage Rx differ for each system in which the semiconductor integrated circuit 100 is mounted, the n-channel transistor NM can be turned on when the voltage Rx decreases to a certain rate.

[0030] In the first embodiment, an example has been described in which the voltage of the input terminal IN+ is set to be higher than the voltage of the input terminal IN- when the voltage Rx is maintained constant by resistive division, and the capacitive element C11 is connected to the input terminal IN-. However, it is also possible to set the voltage of the input terminal IN- to be higher than the voltage of the input terminal IN+ when the voltage Rx is maintained constant by resistive division, and to connect the capacitive element C11 to the input terminal IN+.

[0031] In this case, the comparator CMP11 temporarily outputs a high-level output signal COUT when it detects a drop in the voltage Rx. In order to output a high-level pulse signal PLS in response to a rising edge of the output signal COUT, the pulse generating unit 20 has, for example, an AND gate instead of the OR gate OR and the inverter IV12 in FIG.

[0032] Fig. 3 is a circuit diagram showing an example (comparative example) of another semiconductor integrated circuit. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description will be omitted. The semiconductor integrated circuit 102 shown in Fig. 3 has a voltage detection unit 12, a pulse generation unit 22, and a voltage change acceleration unit 30. For example, the semiconductor integrated circuit 102 is mounted on a receiver of a communication system, and has a function of receiving a voltage signal transmitted from a transmitter of the communication system.

[0033] The voltage detection unit 12 has a voltage dividing circuit including resistor elements R21 and R22, a reference voltage generating circuit 18, and a comparator CMP11. For example, a divided voltage generated by the voltage dividing circuit is supplied to an input terminal IN- of the comparator CMP11. The reference voltage generating circuit 18 generates a reference voltage VREF and supplies the generated reference voltage VREF to an input terminal IN+ of the comparator CMP11.

[0034] When the divided voltage is lower than the reference voltage VREF, the comparator CMP11 outputs a high-level output signal COUT. When the divided voltage is higher than the reference voltage VREF, the comparator CMP11 outputs a low-level output signal COUT.

[0035] The pulse generating unit 22 has an inverter IV11, a resistive element R15, a capacitive element C12, and an AND gate AND. The pulse generating unit 22 has the same configuration as the pulse generating unit 20 in FIG. 1, except that the pulse generating unit 22 has an AND gate AND instead of the OR gate OR and the inverter IV12. The pulse generating unit 22 outputs a high-level pulse signal PLS in synchronization with the rising edge of the output signal COUT from the comparator CMP11. The falling edge of the voltage Rx is accelerated by the n-channel transistor NM that is turned on by the high-level pulse signal PLS.

[0036] In the voltage detection unit 12 shown in FIG. 3, the comparator CMP11 compares the reference voltage VREF, which has a fixed voltage value. Therefore, when the voltage Rx falls and becomes lower than the reference voltage VREF, the pulse signal PLS is generated. In other words, the amount of decrease in the voltage Rx until the n-channel transistor NM turns on differs depending on whether the electrical specification of the high-level value of the voltage Rx is high or low. Therefore, when it is necessary to accelerate the decrease in the voltage Rx when the voltage Rx decreases to 70% of the high-level value based on the electrical specification of multiple types of systems in which the semiconductor integrated circuit 102 is mounted, the semiconductor integrated circuit 102 cannot be used.

[0037] Fig. 4 is a circuit diagram showing another example (comparative example) of another semiconductor integrated circuit. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description will be omitted. The semiconductor integrated circuit 104 shown in Fig. 4 has a voltage detection unit 14 and a voltage change acceleration unit 30. For example, the semiconductor integrated circuit 104 is mounted on a receiver of a communication system, and has a function of receiving a voltage signal transmitted from a transmitter of the communication system.

[0038] The voltage detection unit 14 includes resistors R41, R42, R43, and R44, a capacitor C41, an n-channel transistor NM41, and a buffer circuit BUF. The resistor R41 is connected between the external terminal Rx and one end of the capacitor C41. The resistors R42 and R43 are connected in series between the power supply line VDD and the ground line GND via the other end of the capacitor C41.

[0039] The resistor element R44 and the n-channel transistor NM are connected in series between the power supply line VDD and the ground line GND. The gate of the n-channel transistor NM41 is connected to the other end of the capacitive element C41. The drain of the n-channel transistor NM41 is connected to the resistor element R44 and the input terminal of the buffer circuit BUF.

[0040] The buffer circuit BUF operates on a power supply voltage VDD. The buffer circuit BUF outputs a high level when the drain voltage of the n-channel transistor NM is higher than the logical threshold voltage, and outputs a low level when the drain voltage of the n-channel transistor NM is lower than the logical threshold voltage. The n-channel transistor NM is turned on during the period when the buffer circuit BUF outputs a high level, and draws charge from the voltage line Rx.

[0041] 4, when the voltage Rx drops, the gate voltage of the n-channel transistor NM41 temporarily drops due to AC coupling of the capacitance element C41. This causes the drain-source resistance of the n-channel transistor NM41 to drop, and when the input voltage of the buffer circuit BUF becomes equal to or higher than the logic threshold voltage, the buffer circuit BUF outputs a high level. Then, the n-channel transistor NM turns on.

[0042] 4, however, a relatively large capacitance element C41 is required to detect a drop in voltage Rx using AC coupling of capacitance element C41, which increases the circuit size of semiconductor integrated circuit 104. In addition, if the voltage Rx drops in a frequency band outside the frequency band determined by capacitance element C41 and resistance elements R42 and R43, charge cannot be extracted from the voltage line Rx. In contrast, the semiconductor integrated circuit 100 shown in FIG. 1 can extract charge from the voltage line Rx without being limited to the frequency band when the voltage Rx drops.

[0043] Second Embodiment FIG. 5 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit of the present invention. The same elements as those in FIG. 1 are given the same reference numerals, and detailed description is omitted. The semiconductor integrated circuit 106 shown in FIG. 5 has a function of improving the delay of the rising waveform of a voltage when the voltage Rx received via the external terminal Rx is transmitted to a subsequent circuit. The semiconductor integrated circuit 106 has a voltage detection unit 16 that detects a change in the rising edge of the voltage Rx, a pulse generation unit 26, and a voltage change acceleration unit 36. For example, the semiconductor integrated circuit 106 is mounted on a receiver of a communication system, and has a function of receiving a voltage signal transmitted from a transmitter of the communication system.

[0044] The voltage detection unit 16 has the same configuration as the voltage detection unit 10 in FIG. 1, except that the capacitive element C11 is connected to the input terminal IN+ of the comparator CMP11. Like the voltage detection unit 10 in FIG. 1, the voltage detection unit 16 is set so that the voltage of the input terminal IN+ is higher than the voltage of the input terminal IN- when the voltage Rx is maintained constant. Then, when the voltage Rx rises, the voltage IN+ temporarily becomes lower than the voltage IN-. This causes the comparator CMP11 to output a low-level pulse signal (COUT) during the period when the voltage IN+ is temporarily lower than the voltage IN-.

[0045] The pulse generating unit 26 has the same configuration as the pulse generating unit 20 in Fig. 1 except that the inverter IV12 is removed. That is, the pulse generating unit 26 outputs a pulse signal PLS from an OR gate OR. When the pulse generating unit 26 receives a low-level pulse signal (COUT) from the comparator CMP11, it outputs the low-level pulse signal PLS as a rising edge detection signal.

[0046] The voltage change acceleration unit 36 ​​has a p-channel transistor PM that receives the pulse signal PLS at its gate (control terminal), has its drain connected to the external terminal Rx, and has its source connected to the power supply line VDD. For example, the p-channel transistor PM is a MOSFET, but is not limited to a MOSFET and may be a switching element having a control terminal such as a PNP bipolar transistor. The p-channel transistor PM conducts (ON) between the drain and the source during a period when the pulse signal PLS is at a low level, and supplies charge from the power supply line VDD to the voltage line Rx. In this way, the p-channel transistor PM functions as a charge element. This makes it possible to increase the rising speed when the voltage Rx rises, and improve the delay in the rising waveform of the voltage Rx.

[0047] As described later, when the voltage Rx rises, the comparator CMP11 outputs a low-level pulse signal. Therefore, if the accuracy of the pulse width is not required, the output of the comparator CMP11 may be directly connected to the gate of the p-channel transistor PM without providing the pulse generating unit 26. Furthermore, in addition to the p-channel transistor PM, the voltage change accelerating unit 36 ​​may have an n-channel transistor that receives the pulse signal PLS at its gate, has a source connected to the voltage line Rx, and has a drain connected to the power supply line VDD. That is, the voltage change accelerating unit 36 ​​may have a CMOS (Complementary Metal Oxide Semiconductor) transmission gate.

[0048] 1, in the voltage detection unit 16, when the voltage Rx is maintained constant, the voltage IN+ can be made higher than the voltage IN-. This allows the voltage IN+ to be temporarily made lower than the voltage IN- when the voltage Rx rises, and a low-level pulse signal can be output from the comparator CMP11.

[0049] Furthermore, when the voltage Rx rises, the rate of increase from the low level value of the voltage Rx when the voltage IN+ becomes lower than the voltage IN- is substantially the same regardless of the low level value. Therefore, for example, when the voltage Rx rises to a certain ratio (for example, 30%) of the low level value, the rise of the voltage Rx can be accelerated. Here, the certain ratio is the ratio of the voltage Rx when the difference between the high level value and the low level value of the voltage Rx is set to 100%. Therefore, even if the electrical specifications of the low level value of the voltage Rx differ for each system in which the semiconductor integrated circuit 106 is mounted, the p-channel transistor PM can be turned on when the voltage Rx rises to the certain ratio.

[0050] Fig. 6 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit 106 of Fig. 5. Detailed description of the same operation as in Fig. 2 will be omitted. Note that the low level value of the voltage Rx is a predetermined voltage determined by the electrical specifications of the semiconductor integrated circuit 106 and is higher than the ground voltage GND.

[0051] In the example shown in Fig. 6, when the voltage Rx changes to a high level, the rising waveform is delayed due to the parasitic capacitance of the diode bridge or surge absorber connected to the external terminal Rx. In Fig. 6, the voltages IN+ and IN- rise as the voltage Rx rises. The voltage IN+ rises later than the voltage IN- due to the effect of the capacitance element C11.

[0052] During the period when the voltage IN+ is temporarily lower than the voltage IN-, the comparator CMP11 changes the output signal COUT from high to low. The pulse generating unit 26 outputs a low-level pulse signal PLS in synchronization with the falling edge of the output signal COUT. The p-channel transistor PM turns on during the period when the pulse signal PLS is low, supplies charge to the voltage line Rx, and accelerates the rising speed of the voltage Rx. The dashed line shown in the waveform of the voltage Rx is the waveform when the semiconductor integrated circuit 106 does not have the voltage detection unit 16, the pulse generating unit 26, and the voltage change acceleration unit 36.

[0053] As described above, in the second embodiment, the rising speed of the voltage Rx received at the external terminal Rx can be increased, and the delay in the rising waveform of the voltage Rx can be improved. This allows the processing of the downstream circuit that operates in response to the rising of the voltage Rx to start early, and the performance of the semiconductor integrated circuit 106 or the performance of the system including the semiconductor integrated circuit 106 can be improved. Alternatively, the malfunction of the downstream circuit can be prevented, and the reliability of the semiconductor integrated circuit 106 or the system including the semiconductor integrated circuit 106 can be improved.

[0054] By supplying the two divided voltages generated by resistor division to the input terminals IN+ and IN- of the comparator CMP11, respectively, it is possible to make the voltage IN+ higher than the voltage IN- when the voltage Rx is maintained constant. Also, because a load (capacitive element C11) is connected to the input terminal IN+, it is possible to make the rate at which the voltage IN+ drops slower than the rate at which the voltage IN- drops when the voltage Rx drops. This makes it possible to make the voltage IN+ temporarily lower than the voltage IN- when the voltage Rx rises, and to output a low-level pulse signal (COUT) from the comparator CMP11.

[0055] The voltage detection unit 16 outputs a low-level pulse signal (COUT) when the voltage Rx drops. Therefore, for example, even if the output signal COUT is directly output to the gate of the p-channel transistor PM without providing the pulse generation unit 26, the rising speed of the voltage Rx can be increased and the delay of the rising waveform of the voltage Rx can be improved. Furthermore, by providing the pulse generation unit 26, the on-period of the p-channel transistor PM can be set to an arbitrary period by a time constant circuit. Also, by supplying charge to the voltage line Rx by the p-channel transistor PM, the delay of the rising waveform of the voltage Rx can be improved by a simple charge element.

[0056] During the rise of the voltage Rx, the rate of increase from the low level value of the voltage Rx when the voltage IN+ becomes lower than the voltage IN- is substantially the same regardless of the low level value. Therefore, even if the electrical specifications of the low level value of the voltage Rx differ for each system in which the semiconductor integrated circuit 106 is mounted, the p-channel transistor PM can be turned on when the voltage Rx rises to a certain rate.

[0057] In the second embodiment, an example has been described in which the voltage of the input terminal IN+ is set to be higher than the voltage of the input terminal IN- when the voltage Rx is maintained constant by resistive division, and the capacitive element C11 is connected to the input terminal IN+. However, it is also possible to set the voltage of the input terminal IN- to be higher than the voltage of the input terminal IN+ when the voltage Rx is maintained constant by resistive division, and to connect the capacitive element C11 to the input terminal IN-.

[0058] In this case, when the comparator CMP11 detects an increase in the voltage Rx, it temporarily outputs a high-level output signal COUT. For this reason, the pulse generating unit 20 has, for example, a NAND gate (AND gate + inverter) instead of the OR gate OR in FIG. 5 in order to output a low-level pulse signal PLS in response to the rising edge of the output signal COUT.

[0059] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form. [Explanation of symbols]

[0060] 10, 12, 14, 16 Voltage detection section 18 Reference voltage generation circuit 20, 22, 26 Pulse generation unit 30, 36 Voltage change acceleration section 100, 102, 104, 106 Semiconductor integrated circuit BUF Buffer circuit C11, C12, C41 Capacitor elements CMP11 Comparator COUT Output signal GND ground wire IN+, IN- input terminals IV11, IV12 inverter NM, NM41 n-channel transistor PLS0, PLS pulse signal PM p-channel transistor R11, R12, R13, R14, R15 Resistor elements R21, R22 resistor elements R41, R42, R43, R44 resistor elements Rx external terminal VDD power line VREF Reference voltage

Claims

1. a voltage detection unit that detects a falling edge change in a voltage received at an external terminal; a pulse generating unit that generates a pulse signal in response to detection of a change in the voltage by the voltage detecting unit; a voltage change acceleration unit that accelerates a change in the voltage received via the external terminal in response to the pulse signal; having The voltage detection unit a first voltage dividing circuit that divides the voltage received at the external terminal to generate a first divided voltage; a second voltage dividing circuit that divides the voltage received at the external terminal to generate a second divided voltage higher than the first divided voltage; a comparator having a first input terminal for receiving the first divided voltage and a second input terminal for receiving the second divided voltage, the comparator comparing the first divided voltage with the second divided voltage; a load connected to either the first input terminal or the second input terminal; The pulse generating unit generates a pulse signal in response to a comparison result signal output from the comparator in response to a falling edge change of the voltage. A semiconductor integrated circuit comprising:

2. When the voltage drops, the drop in the voltage input to one of the first input terminal or the second input terminal connected to the load is delayed compared to the drop in the voltage input to the other of the first input terminal or the second input terminal.

2. The semiconductor integrated circuit according to claim 1 .

3. When the voltage is maintained constant, the first divided voltage and the second divided voltage are different from each other, When the voltage is maintained constant, the load is connected to an input terminal which receives a lower divided voltage out of the first input terminal and the second input terminal.

3. The semiconductor integrated circuit according to claim 1 or 2.

4. The pulse generating section generates a falling edge detection signal in response to detection of a falling edge of the voltage by the voltage detecting section.

4. The semiconductor integrated circuit according to claim 1, wherein:

5. The voltage change acceleration unit receives the falling edge detection signal at a control terminal, and has a switch having one terminal connected to the external terminal and another terminal connected to a ground line.

5. The semiconductor integrated circuit according to claim 4.

6. The pulse generating unit has a delay circuit including a resistive element and a capacitive element, and changes a waveform of the pulse signal output to the control terminal in accordance with a time constant of the delay circuit.

6. The semiconductor integrated circuit according to claim 5,

7. a voltage detection unit that detects a change in a rising edge of a voltage received at an external terminal; a pulse generating unit that generates a pulse signal in response to detection of a change in the voltage by the voltage detecting unit; a voltage change acceleration unit that accelerates a change in the voltage received via the external terminal in response to the pulse signal; having The voltage detection unit a first voltage dividing circuit that divides the voltage received at the external terminal to generate a first divided voltage; a second voltage dividing circuit that divides the voltage received at the external terminal to generate a second divided voltage higher than the first divided voltage; a comparator having a first input terminal for receiving the first divided voltage and a second input terminal for receiving the second divided voltage, the comparator comparing the first divided voltage with the second divided voltage; a load connected to either the first input terminal or the second input terminal; The pulse generating unit generates a pulse signal in response to a comparison result signal output from the comparator in response to a change in a rising edge of the voltage. A semiconductor integrated circuit comprising:

8. When the voltage is maintained constant, the first divided voltage and the second divided voltage are different from each other, When the voltage is maintained constant, the load is connected to the input terminal which receives the higher divided voltage out of the first input terminal and the second input terminal.

8. The semiconductor integrated circuit according to claim 7,

9. The pulse generating unit generates a rising edge detection signal in response to detection of a rising edge of the voltage by the voltage detecting unit.

9. The semiconductor integrated circuit according to claim 7 or 8.

10. The voltage change acceleration unit receives the rising edge detection signal at a control terminal, and has a switch having one terminal connected to the external terminal and another terminal connected to a power line.

10. The semiconductor integrated circuit according to claim 9.

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