Power chip, power chip testing system and testing method

Abstract

The present invention relates to the field of measurement and testing technology, and in particular to a power chip, a power chip testing system and a testing method, the method comprising: obtaining output voltage data of a power chip; determining the filtering weight of the output voltage data at each moment; filtering the noise in the output voltage data based on the filtering weight to obtain filtered voltage data; and performing a ripple test on the power chip based on the filtered voltage data. When testing the power chip, the method uses the filtered voltage data as calculation data, and the filtered voltage data retains the ripple information as much as possible when filtering the noise, so that the performance test of the power chip can be made more accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of measurement and testing, and in particular to a power chip, a power chip testing system and a testing method in the technical field of measurement and testing. Background Art

[0002] When the power chip is working, it is expected to output a stable, non-fluctuating voltage. However, in actual work, due to environmental interference, the fixed frequency of internal electronic components and other factors, the output of the power chip fluctuates within a certain range. The test for this fluctuation is the ripple noise test in the power chip packaging test stage.

[0003] Ripple and noise exist simultaneously in the output voltage of the power chip. When testing some indicators of the output voltage (such as voltage stability), it is necessary to separate the ripple and noise in the power chip, and then calculate the voltage fluctuation range based on the signal after filtering the noise to obtain the performance indicator of voltage stability.

[0004] The existing ripple and noise separation methods mostly use simple filtering methods such as low-pass filters or mean filters to filter noise, which can easily cause the ripple waveform to be distorted, thereby affecting the fault diagnosis of the power chip. Therefore, in the ripple and noise test of the power chip, there is a ripple waveform distortion caused by improper ripple and noise separation methods, resulting in inaccurate performance testing of the power chip. Summary of the invention

[0005] In order to solve the technical problem of inaccurate performance test of power chip in the prior art, the purpose of the present invention is to provide a power chip, a power chip testing system and a testing method. The technical scheme adopted is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a power chip testing method, the method comprising:

[0007] Get the output voltage data of the power chip;

[0008] Determining the filtering weight of the output voltage data at each moment;

[0009] Based on the filtering weight, filtering the noise in the output voltage data to obtain filtered voltage data;

[0010] Based on the filtered voltage data, a ripple test is performed on the power chip.

[0011] In a second aspect, a power chip testing system is provided, the system comprising:

[0012] An acquisition module, used to acquire output voltage data of a power chip;

[0013] A determination module, used to determine the filtering weight of the output voltage data at each moment;

[0014] A filtering module, configured to filter the noise in the output voltage data based on the filtering weight to obtain filtered voltage data;

[0015] A testing module is used to perform a ripple test on the power chip based on the filtered voltage data.

[0016] In a third aspect, a power chip is provided, comprising: a memory for storing executable program code; and a processor for calling and running the executable program code from the memory, so that the power chip executes the method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0017] In a fourth aspect, a computer program product is provided, comprising: a computer program code, which, when executed on a computer, enables the computer to execute the method in the first aspect or any possible implementation of the first aspect.

[0018] In a fifth aspect, a computer-readable storage medium is provided, which stores a computer program code. When the computer program code runs on a computer, the computer executes the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0019] The present invention has the following beneficial effects: after obtaining the output voltage data of the power supply chip, the filter weights of the output voltage data at each moment are determined, and based on the filter weights, the noise in the output voltage data is filtered to obtain the filtered voltage data; in this way, the output voltage data is filtered by the filter weights at each moment, which can improve the filtering efficiency and make the obtained filtered data more accurate. Afterwards, the power supply chip is subjected to a ripple test by using the filtered voltage data. In this way, when testing the power supply chip, the filtered voltage data is used as the calculation data, and the filtered voltage data retains the ripple information as much as possible when filtering the noise, so that the performance test of the power supply chip can be made more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1It is a schematic diagram of an implementation flow of a power chip testing method provided by an embodiment of the present invention;

[0022] Figure 2 It is another implementation flow diagram of a power chip testing method provided by an embodiment of the present invention;

[0023] Figure 3 It is another implementation flow diagram of a power chip testing method provided by an embodiment of the present invention;

[0024] Figure 4 It is another implementation flow diagram of a power chip testing method provided by an embodiment of the present invention;

[0025] Figure 5 It is a schematic diagram of the composition structure of a power chip testing system provided in an embodiment of the present application;

[0026] Figure 6 It is a structural schematic diagram of a power chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following is a detailed description of a power chip testing method proposed by the present invention, its specific implementation, structure, features and effects, in combination with the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "another embodiment" does not necessarily refer to the same embodiment. In addition, specific features, structures or characteristics in one or more embodiments may be combined in any suitable form.

[0028] Among them, in the description of the embodiments of the present invention, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a way to describe the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present invention, "multiple" refers to two or more than two.

[0029] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0030] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0031] A specific scheme of a power chip testing method provided by the present invention is described in detail below with reference to the accompanying drawings.

[0032] See also Figure 1 , which shows a flow chart of a power chip testing method provided by an embodiment of the present invention, the method comprising:

[0033] 101, obtaining output voltage data of a power chip.

[0034] Here, the voltage signal of the power chip and the switching frequency of the power chip are obtained, and the voltage signal and the switching frequency are determined as the output voltage data. In this way, the output voltage data includes: the switching frequency and the voltage signal of the power chip, so that the output voltage data is convenient for calculating the filter weight and filtering the voltage signal in the output voltage data.

[0035] In some possible implementations, the output voltage quality of the power chip is detected, so the outlet of the power chip is measured by an oscilloscope to obtain an electrical signal data, which is recorded as a voltage signal. The data form of the voltage signal is a vector, and the sampling interval of the voltage signal is 0.1 microseconds, where the tth element represents the voltage output by the power chip at time t. At the same time, the power chip has a switching frequency when it is designed. The switching frequency refers to the number of switching operations of the switching device (such as transistors, metal-oxide-semiconductor field-effect transistors (MOSFET), etc.) in the switching power supply per unit time. The switching frequency is one of the key factors for power conversion efficiency and output ripple noise. Therefore, the switching frequency F of the target test chip is obtained through the design parameters of the chip. If the switching frequency requires an empirical value, 10k Hz can be taken.

[0036] 102. Determine the filtering weight of the output voltage data at each moment.

[0037] Here, the filtering weight at each moment is the weight of filtering the voltage signal in the output voltage data at each moment. Since the output voltage data includes the voltage signal and the switching frequency, the burr intensity at each moment can be calculated by the voltage signal, and thus the filtering weight at each moment can be calculated by the burr intensity.

[0038] In some possible implementations, the above step 102 can be performed by Figure 2 The steps shown achieve:

[0039] 201. Determine the burr intensity at each moment based on the output voltage data.

[0040] Here, the burr intensity at each moment is used to characterize the noise size of the voltage signal at each moment. In some possible implementations, the above step 201 can be implemented by the following process: First, in the voltage signal in the output voltage data, the first window data and the second window data are respectively selected. Then, based on the first window data and the second window data, the burr intensity at each moment is determined. In this way, by combining the selected two window data of different lengths, the burr intensity at each moment can be analyzed more accurately.

[0041] In some possible implementations, first, the window peak-to-peak value is determined by the maximum value element and the minimum value element in the first window data; wherein the window peak-to-peak value is the peak-to-peak value corresponding to the first window data. Then, the difference between the window mean of the first window data and the window mean of the second window data is determined; for example, the window mean of the first window data is subtracted from the window mean of the second window data and the absolute value is taken to obtain the difference. Finally, the burr intensity at each moment is determined by the window peak-to-peak value and the difference. In this way, by combining the window peak-to-peak value of the first window data with the difference between the two window means, the burr intensity at each moment can be obtained quickly and accurately.

[0042] Among them, the length of the first window data is less than the length of the second window data. In the voltage signal, the noise is mostly caused by factors such as parasitic capacitance and parasitic inductance of the internal circuit of the chip. Its waveform appears as burrs and has a high frequency. Therefore, the traditional noise filtering method uses low-pass filters, mean filters and other methods for processing. The ripples in the voltage signal are divided into low-frequency ripples and high-frequency ripples: low-frequency ripples are mainly related to the capacity of the filter capacitor, and their frequency is relatively low. The frequency is close to the circuit switching frequency inside the chip, and the waveform is smooth. The use of mean filtering is easy to cause distortion of low-frequency ripples. High-frequency ripples mainly come from high-frequency power switching conversion circuits, and their frequency is relatively high. If low-pass filters or mean filtering methods are used for processing, the information of this part of the ripples is easily lost. Therefore, the embodiment of the present invention proposes a power chip output voltage noise filtering method based on the waveform characteristics of noise and ripples, which retains the ripple information in the output voltage as much as possible and improves the accuracy of the power chip ripple noise test.

[0043] The noise in the voltage signal is mostly caused by factors such as parasitic capacitance and parasitic inductance in the internal circuit of the chip. The noise waveform caused by parasitic capacitance and parasitic inductance in the circuit is mostly burrs, and its waveform shape is quite different from the low-frequency ripple and high-frequency ripple. Therefore, the similarity between the voltage signal waveform at time t and the burr shape can be calculated. The more the voltage signal waveform at time t resembles a burr and the higher the burr intensity, the more likely noise is to occur at this time, and the more noise filtering is needed.

[0044] The glitch phenomenon in the signal refers to the signal suddenly increasing or decreasing by a large value, and returning to the value before the increase or decrease in a short time. Therefore, the part where the glitch phenomenon occurs in the signal usually has a higher peak-to-peak value, and the glitch has a smaller impact on the signal mean. Therefore, the signal mean when the glitch occurs is similar to the signal mean at other times. The embodiment of the present invention identifies the glitch phenomenon in the voltage signal through the peak-to-peak value characteristics and mean characteristics of the glitch phenomenon.

[0045] At time t, a window with a length of A=21 (i.e., the first window data) is taken for the voltage signal, and the center position of the window is at time t. The mean of all elements in the window is calculated and recorded as the short window mean μs t (i.e. the window mean of the first window data). Get the maximum and minimum values ​​of all elements in the window, subtract the minimum value element from the maximum value element, and record it as the short window peak-to-peak value PP t .

[0046] Further, at time t, a window with a length of B = 201 is taken for the voltage signal (i.e., the second window data), the center position of the window is at time t, and the mean of all elements in the window is calculated, which is recorded as the long window mean μl t (i.e. the window mean of the second window data).

[0047] In particular, when the data of some element positions in the window are empty, other elements in the window can be used for calculation, which has no effect on the final result. The burr intensity at time t is shown in formula (1):

[0048]

[0049] Among them, Fb t is the glitch intensity at time t. The larger the window peak-to-peak value, the more likely the signal at time t suddenly increases or decreases, and the more likely it is a glitch at time t. If the signal at time t returns to the value before the increase or decrease in a short time after a sudden increase or decrease, then the smaller the difference between the short window mean and the long window mean, the more likely the sudden increase or decrease of the signal at time t is a glitch phenomenon of noise, rather than a smooth increase or decrease of the signal of ripple. z is to prevent the minimum value of the denominator from being 0 from taking 1. Finally, the glitch intensity is obtained at time t. The larger the value, the more likely the glitch phenomenon representing noise appears at time t.

[0050] 202. Determine the filtering weight at each moment based on the burr intensity.

[0051] Here, the filter weight at each moment is used to filter the voltage signal at each moment. The filter weight at each moment is calculated by combining the burr strength at each moment with the switching frequency in the output voltage data. In this way, by analyzing the voltage signal in the output voltage data, the burr strength at each moment is calculated, so that the filter weight at each moment can be calculated by the burr strength, and then the noise in the voltage signal can be filtered through the filter weight.

[0052] In some possible implementations, since the noise is caused by the parasitic capacitance and parasitic inductance of the circuit in the power chip, it will appear periodically with the switching of the transistors, MOSFET and other structures in the power chip, so the burrs will appear periodically in the power signal with the switching frequency as the frequency of occurrence. Due to factors such as electromagnetic interference in the external environment, the burr phenomenon may not be prominent at certain moments. For example, the peak-to-peak value of the burr phenomenon at a certain moment is low, which will cause the burr intensity at that moment to be small, resulting in insufficient filtering strength for the burr phenomenon at that moment. However, since the burr phenomenon appears periodically, the problem that the burr phenomenon is not prominent at a certain moment can be solved by the periodic characteristics of the burr phenomenon. Therefore, the embodiment of the present invention calculates the filtering weight according to the periodic occurrence characteristics of the burr and the burr intensity. The larger the filtering weight value, the more likely the burr phenomenon is to occur at time t, and the more high-intensity filtering operations are required. The above step 202 can be implemented by the following steps 221 to 223 (not shown in the figure):

[0053] 221. For any moment among the moments, obtain a candidate switching frequency corresponding to the any moment from the switching frequencies in the output voltage data.

[0054] Here, taking any time as time t as an example, the switching frequency of the power chip is obtained, and the inverse of the switching frequency is recorded as the switching period TS. The candidate switching frequency is the switching frequency of the power chip at time t.

[0055] 222. Based on the candidate switching frequency, obtain the burr intensity corresponding to each period.

[0056] Here, at time t, the burr strength at time t-TS, time t-2×TS, time t-3×TS… time tn×TS… time tN×TS is obtained. In this embodiment, N=9. If the burr strength cannot be obtained at time tn×TS due to insufficient voltage signal length, the burr strength at time tn×TS is not obtained, and the calculation is performed using the burr strength that can be obtained, which does not affect the final result.

[0057] 223 , normalize the burr strength corresponding to each period to obtain the filtering weight at any moment.

[0058] Here, the average of all acquired burr intensities is calculated and recorded as the average burr intensity at time t. The larger the average burr intensity is, the more likely it is that a burr will appear at time t, and the more filtering should be performed to filter out noise at time t.

[0059] Further, a window with a time length of TS is taken at time t, and the center of the window is at time t. The mean burr intensity of all elements in the window is obtained, and all the mean burr intensity in the window is normalized. After the normalization, the element at the position at time t is recorded as the filter weight β t The larger the filter weight, the more likely it is that a burr phenomenon will occur at time t, and the more intense the filtering operation must be to filter out the noise. In particular, when the data of some element positions in the window is empty, other elements in the window can be used for calculation, which has no effect on the final filter weight. In this way, by combining the switching frequency in the output voltage data with the burr intensity corresponding to each cycle, the filter weight at each moment can be calculated quickly and accurately.

[0060] 103. Filter the noise in the output voltage data based on the filtering weight to obtain filtered voltage data.

[0061] Here, the voltage signal in the output voltage data is subjected to wavelet decomposition to retain low-frequency ripples in the voltage signal, and then the voltage signal in the output voltage data is subjected to noise filtering based on the filtering weights to obtain filtered voltage data.

[0062] In some possible implementations, the above step 103 can be performed by Figure 3 The steps shown achieve:

[0063] 301 , decompose a voltage signal in the output voltage data to obtain a plurality of decomposed signals.

[0064] Here, since the frequency of the low-frequency ripple is close to the switching frequency of the power chip, for each decomposed signal after wavelet decomposition, if the difference between its frequency and the switching frequency is greater, it is more likely that it is not a low-frequency ripple, and the filtering intensity of the sub-signal should be greater to avoid affecting the low-frequency ripple in the voltage signal. At a certain moment, if its filtering weight is larger, it is more likely that burrs will appear at this moment, and its filtering intensity should be greater to avoid affecting the high-frequency ripple in the voltage signal. First, the voltage signal is decomposed by wavelet, and the specific process is as follows:

[0065] The voltage signal is used as input and decomposed by wavelet decomposition algorithm. The necessary parameters are: the wavelet type is Haar wavelet, the number of classifications is M, and M=7 in the embodiment of the present invention; the output is M decomposed signals. For the mth decomposed signal, a window with a time length of S is set at time t, and the center of the window is at time t. In this embodiment, S=10×TS, and then the decomposed signal in the window is used as input, and the fast Fourier transform algorithm is used to calculate and output a spectrum diagram. The data storage form of the spectrum diagram is a matrix with two rows and multiple columns. Assuming that the spectrum diagram has R columns, the first row of the rth column represents the frequency, and the second row of the rth column represents the amplitude of the signal at the frequency. When the data of some element positions in the window is empty, other elements in the window can be used for calculation, which has no effect on the final result.

[0066] 302 : Based on the center frequencies of the multiple decomposed signals and the switching frequency of the output voltage signal, correct the filter weight to obtain a corrected weight.

[0067] Here, the center frequency is calculated by the spectrum diagram of the data of the mth decomposition signal at time t. The difference between the center frequency and the switching frequency of the output voltage signal is multiplied by the filter weight, thereby realizing the correction of the filter weight and obtaining the correction weight.

[0068] 303 : Filter the multiple decomposed signals based on the modified weights to obtain the filtered voltage data.

[0069] Here, the traditional noise filtering method uses low-pass filter or mean filter for filtering, wherein low-pass filter easily causes loss of high-frequency ripple information, and mean filter easily causes distortion of the ripple waveform. Therefore, the embodiment of the present invention combines the filtering weight and uses the wavelet denoising method to filter the noise.

[0070] In some possible implementations, by fusing any decomposed signal with the corresponding correction weight, a correction signal value corresponding to any decomposed signal is obtained; and based on the correction signal value, the filtered voltage data is determined. For example, the correction weight is multiplied with the corresponding decomposed signal to obtain the correction signal value, and then the respective correction signal values ​​are averaged to obtain the filtered voltage data. In this way, by performing wavelet decomposition on the voltage information, low-frequency ripples can be retained in the obtained decomposed signal, and then the decomposed signal is filtered by the correction weight, so that low-frequency ripples can be well retained in the filtered voltage data, and noise can be filtered out.

[0071] Among them, the center frequency is calculated from the spectrum of the mth decomposition signal at time t. The center frequency calculation method is:

[0072] First, obtain the elements of the second row of the spectrum graph, perform ratio normalization on the elements of the second row, and obtain a vector of length R, recorded as the ratio vector, in which the rth element represents the ratio of the frequency component of the rth column of the spectrum graph in the spectrum graph.

[0073] Further calculate the center frequency: Among them, mf m,t is the center frequency of the mth decomposition signal at time t, R is the number of columns of the spectrum of the mth decomposition signal at time t, and f r,m,t is the frequency represented by the rth column of the spectrum of the mth decomposition signal at time t, b r,m,t It indicates the proportion of the frequency in the rth column of the spectrum of the mth decomposition signal at time t in the spectrum. The greater the difference between the center frequency of the mth decomposition signal at time t and the switching frequency F, the less likely it is to be a signal component of low-frequency ripple, and the greater the intensity of the filtering operation should be.

[0074] The process of filtering the decomposed signal is as follows: for the mth decomposed signal at time t, take a window with a length of A = 21, the center position of the window is at time t, and calculate the mean of all elements in the window except at time t, which is recorded as the corrected signal value μV m,t .

[0075] In particular, when the data of some element positions in the window are empty, the other elements in the window can be used for calculation, which has no effect on the final result. Among them, the filtered voltage data can be obtained by formulas (2) and (3):

[0076] α m,t = norm(|mf m,t -F|)×β t (2);

[0077] Vr m,t =V m,t ×(1-α m,t )+μV m,t ×α m,t (3);

[0078] Among them, α m,t is the modified weight, norm() is to normalize the elements in the brackets to the maximum value, mf m,t is the center frequency of the mth decomposition signal at time t, F is the switching frequency of the target detection chip, β t is the filter weight at time t, Vr m,t is the filtered signal value of the mth decomposed signal at time t, V m,t is the signal value of the mth decomposed signal at time t, μV m,t is the corrected signal value of the mth decomposed signal at time t.

[0079] Among them, at time t of the mth signal, the greater the difference between the center frequency of the signal and the switching frequency, the more the mth signal contains noise, and the stronger the filtering operation is performed on it; the larger the filtering weight, the more obvious the noise at time t, and the stronger the filtering operation; finally, the corrected weight is obtained, and the larger the value, the stronger the filtering intensity of the m decomposed signals at time t.

[0080] Among them, the corrected signal value is to take the mean value of the signal at the adjacent position at time t as the signal value without noise interference at time t; further, the correction weight is used as the weight to weigh the proportion of the signal value and the corrected signal value in the filtered signal value, and complete the filtering operation of the mth decomposed signal at time t. In this way, the signal value of each moment of the M signals is calculated in this way to obtain M filtered decomposed signals, and finally the M filtered decomposed signals are used as input, and the inverse wavelet change algorithm is used for calculation, and the output is a synthetic signal, which is recorded as the filtered voltage signal (i.e., the filtered voltage data), to complete the separation of ripples and noise in the voltage signal. Since this embodiment analyzes the noise waveform and frequency in the voltage signal, identifies the noise position through the characteristic value, and filters the voltage signal in combination with the wavelet decomposition algorithm, the ripple information is retained as much as possible while filtering the noise, thereby improving the separation effect of ripples and noise.

[0081] 104. Perform a ripple test on the power chip based on the filtered voltage data.

[0082] Here, the filtered voltage data is input into the oscilloscope, and the peak-to-peak value on the oscilloscope is read, which is recorded as the ripple peak-to-peak value; at the same time, the mean of the filtered voltage signal is calculated to obtain the mean voltage; finally, the ripple peak-to-peak value is divided by the mean voltage to obtain a ratio, which is recorded as the voltage stability, representing the stability of the output voltage of the power chip. Figure 4 As shown, this can be achieved by following the steps below:

[0083] 401, measuring the voltage signal of the power chip and obtaining the switching frequency.

[0084] 402, calculating a filtering weight based on the voltage signal.

[0085] 403 , performing wavelet decomposition filtering according to the filtering weight to obtain a filtered voltage signal.

[0086] 404 , input the filtered voltage signal into an oscilloscope to obtain a peak-to-peak value.

[0087] 405 , calculating a voltage mean based on the filtered voltage signal.

[0088] 406 , calculating voltage stability based on the peak-to-peak value and the voltage mean value.

[0089] Since the present embodiment uses the filtered voltage signal as calculation data when measuring voltage stability, and the filtered voltage signal retains ripple information as much as possible when filtering noise, the present embodiment can provide a more accurate measurement result when measuring voltage stability.

[0090] In an embodiment of the present invention, the filtering weight of the output voltage data at each moment is determined, and based on the filtering weight, the noise in the output voltage data is filtered to obtain the filtered voltage data; in this way, the output voltage data is filtered by the filtering weight at each moment, which can improve the filtering efficiency and make the obtained filtered data more accurate. Afterwards, the power chip is subjected to a ripple test by using the filtered voltage data. In this way, when testing the power chip, the filtered voltage data is used as the calculation data, and the filtered voltage data retains the ripple information as much as possible when filtering the noise, so that the performance test of the power chip can be made more accurate.

[0091] The embodiment of the present invention provides a power chip testing system, such as Figure 5 As shown, the system 500 includes:

[0092] An acquisition module 501 is used to acquire output voltage data of a power chip;

[0093] A determination module 502, used to determine the filtering weight of the output voltage data at each moment;

[0094] A filtering module 503, configured to filter the noise in the output voltage data based on the filtering weight to obtain filtered voltage data;

[0095] The testing module 504 is configured to perform a ripple test on the power chip based on the filtered voltage data.

[0096] In some possible implementations, the acquisition module 501 is further used to acquire a voltage signal of the power chip and a switching frequency of the power chip; and determine the voltage signal and the switching frequency as the output voltage data.

[0097] In some possible implementations, the determination module 502 is further configured to determine the burr intensity at each moment based on the output voltage data; and determine the filtering weight at each moment based on the burr intensity.

[0098] In some possible implementations, the determination module 502 is also used to select first window data and second window data from the voltage signal in the output voltage data, respectively; wherein the length of the first window data is smaller than the length of the second window data; and based on the first window data and the second window data, determine the burr intensity at each moment.

[0099] In some possible implementations, the determination module 502 is further used to determine the window peak-to-peak value based on the maximum value element and the minimum value element in the first window data; determine the difference between the window mean of the first window data and the window mean of the second window data; and determine the burr intensity at each moment based on the short window peak-to-peak value and the difference.

[0100] In some possible implementations, the determination module 502 is further used to obtain, for any of the moments, a candidate switching frequency corresponding to the any moment in the switching frequency in the output voltage data; obtain the burr strength corresponding to each cycle based on the candidate switching frequency; and normalize the burr strength corresponding to each cycle to obtain the filtering weight at any moment.

[0101] In some possible implementations, the filtering module 503 is also used to decompose the voltage signal in the output voltage data to obtain multiple decomposed signals; based on the center frequency of the multiple decomposed signals and the switching frequency of the output voltage signal, the filtering weight is corrected to obtain the corrected weight; based on the corrected weight, the multiple decomposed signals are filtered to obtain the filtered voltage data.

[0102] In some possible implementations, the filtering module 503 is further used to fuse any decomposed signal and a corresponding correction weight to obtain a correction signal value corresponding to any decomposed signal; and determine the filtered voltage data based on the correction signal value.

[0103] Optionally, the transmission medium can be a wired link (such as but not limited to coaxial cable, optical fiber and digital subscriber line (DSL)) or a wireless link (such as but not limited to wireless Fidelity (WIFI), Bluetooth and mobile device network).

[0104] It should be noted that: the device provided in the above embodiment is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computer device is divided into different functional modules to complete all or part of the functions described above. In addition, the method embodiments provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0105] Figure 6 is a schematic diagram of the structure of a power chip provided by an embodiment of the present invention. For example, Figure 6As shown, the power chip 600 includes: a memory 601, a processor 602, and a computer program 603 stored in the memory 601 and running on the processor 602, wherein when the processor 602 executes the computer program 603, the power chip can execute any of the power chip testing methods described above. In addition, an embodiment of the present invention also protects a device, which may include a memory and a processor, wherein an executable program code is stored in the memory, and the processor is used to call and execute the executable program code to execute a power chip testing method provided by an embodiment of the present invention.

[0106] This embodiment can divide the functional modules of the device according to the above method example. For example, it can correspond to each functional module, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation. In the case of dividing each module corresponding to each function, the device may also include a signal uploading module, a determination module, an adjustment module, etc. It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, which will not be repeated here.

[0107] It should be understood that the device provided in this embodiment is used to perform the above-mentioned power chip testing method, so the same effect as the above-mentioned implementation method can be achieved. In the case of an integrated unit, the device may include a processing module and a storage module. Among them, when the device is applied to a device, the processing module can be used to control and manage the actions of the device. The storage module can be used to support the device to execute mutual program codes, etc. Among them, the processing module can be a processor or a controller, which can implement or execute various exemplary logic boxes, modules and circuits described in conjunction with the disclosure of the present invention. The processor can also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc., and the storage module can be a memory.

[0108] In addition, the device provided in the embodiment of the present invention may be a chip, a component or a module, and the chip may include a connected processor and a memory; wherein the memory is used to store instructions, and when the processor calls and executes the instructions, the chip can execute a power chip testing method provided in the above embodiment. This embodiment also provides a computer-readable storage medium, in which a computer program code is stored, and when the computer program code is run on a computer, the computer executes the above-mentioned related method steps to implement a power chip testing method provided in the above embodiment.

[0109] This embodiment also provides a computer program product. When the computer program product is run on a computer, the computer executes the above-mentioned related steps to implement a power chip test method provided in the above embodiment. Among them, the device, computer-readable storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here. Through the description of the above implementation mode, the technicians in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In practical applications, the above-mentioned function allocation can be completed by different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In the embodiments provided by the present invention, it should be understood that the disclosed device and method can be implemented in other ways. For example, the device embodiment described above is only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, which may be electrical, mechanical or other forms.

[0110] It should be noted that the sequence of the above-mentioned embodiments of the present invention is only for description and does not represent the advantages and disadvantages of the embodiments. The process depicted in the accompanying drawings does not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-tasking and parallel processing are also possible or may be advantageous. The various embodiments in this specification are described in a progressive manner, and the same and similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments. The above content is only a specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered within the protection scope of the present invention.

Claims

1. A power chip testing method, characterized in that: The method comprises: Get the output voltage data of the power chip; Determining the filtering weight of the output voltage data at each moment; Based on the filtering weight, filtering the noise in the output voltage data to obtain filtered voltage data; Based on the filtered voltage data, performing a ripple test on the power chip; The determining the filtering weight of the output voltage data at each moment includes: Based on the output voltage data, determining the burr intensity at each moment; Determining the filtering weight at each moment based on the burr intensity; The step of determining the burr intensity at each moment based on the output voltage data comprises: In the voltage signal in the output voltage data, first window data and second window data are respectively selected; wherein the length of the first window data is smaller than the length of the second window data; Determining the burr intensity at each moment based on the first window data and the second window data; The determining the burr intensity at each moment based on the first window data and the second window data includes: Determine a window peak-to-peak value based on a maximum value element and a minimum value element in the first window data; Determine a difference between a window mean of the first window data and a window mean of the second window data; The burr intensity at each moment is determined based on the window peak-to-peak value and the difference.

2. A power chip testing method according to claim 1, characterized in that: The obtaining of output voltage data of the power chip includes: Acquiring a voltage signal of the power chip and a switching frequency of the power chip; The voltage signal and the switching frequency are determined as the output voltage data.

3. A power chip testing method according to claim 1, characterized in that: The determining the filtering weight at each moment based on the burr intensity includes: For any moment among the moments, from the switching frequencies in the output voltage data, obtain a candidate switching frequency corresponding to the any moment; Based on the candidate switching frequency, obtaining the burr intensity corresponding to each period; The burr intensities corresponding to the respective periods are normalized to obtain the filtering weight at any moment.

4. A power chip testing method according to claim 1, characterized in that: The filtering of the noise in the output voltage data based on the filtering weight to obtain filtered voltage data includes: Decomposing a voltage signal in the output voltage data to obtain a plurality of decomposed signals; Based on the center frequencies of the multiple decomposed signals and the switching frequency of the output voltage signal, the filter weight is modified to obtain a modified weight; The plurality of decomposed signals are filtered based on the modified weights to obtain the filtered voltage data.

5. A power chip testing method according to claim 4, characterized in that: The filtering the multiple decomposed signals based on the modified weights to obtain the filtered voltage data includes: Fusing any decomposed signal and the corresponding correction weight to obtain a correction signal value corresponding to the any decomposed signal; Based on the correction signal value, the filtered voltage data is determined.

6. A power chip testing system, characterized in that: The system is used to perform the method according to any one of claims 1 to 5, and the system comprises: An acquisition module, used to acquire output voltage data of a power chip; A determination module, used to determine the filtering weight of the output voltage data at each moment; A filtering module, configured to filter the noise in the output voltage data based on the filtering weight to obtain filtered voltage data; A testing module is used to perform a ripple test on the power chip based on the filtered voltage data.

7. A power chip, characterized in that: The power chip comprises: A memory for storing executable program codes; A processor, configured to call and run the executable program code from the memory, so that the power chip executes the method according to any one of claims 1 to 5.

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