High-reliability memory chip packaging test method and system

Abstract

The invention relates to the technical field of electronic information, and discloses a high-reliability storage chip packaging test method and system.The method comprises the steps that firstly, a to-be-tested storage chip and original parameter information of the to-be-tested storage chip are obtained, packaging structure data are collected to construct a three-dimensional model, chip feature data are extracted, then the chip feature data are compared with standard reference data, and potential defect information is mined; suspicious packaging parts are screened, the sensitivity of the suspicious packaging parts to environmental parameters is monitored, then fault risk types are evaluated, weak links are positioned, performance is detected, specific problem points are found out, then a test planning target is formulated, test means and standards are clarified, a test operation instruction is generated, finally, packaging testing is executed, electrical performance data are collected, and stability is verified. And generating a packaging test report. The stability of the memory chip can be improved.

Description

Technical Field

[0001] The invention relates to a high-reliability storage chip packaging test method and system, belonging to the field of electronic information technology. Background Art

[0002] In today's era of rapid development of digital information, data has become the core asset for the development of various industries. As a key component for carrying and protecting this data, the performance and reliability of storage chips directly determine the data storage and processing capabilities of various electronic devices.

[0003] At present, traditional memory chip packaging and testing methods have gradually exposed many problems in meeting the ever-increasing storage needs. On the one hand, as the capacity of memory chips continues to increase and the size continues to shrink, the circuit layout inside the chip becomes more compact. Traditional packaging materials and technologies are difficult to effectively protect the chip from external environmental factors (such as temperature, humidity, mechanical stress, etc.), thereby reducing the reliability and service life of the memory chip; on the other hand, traditional tests often only test some basic functions of the memory chip, and it is difficult to discover potential minor defects and performance risks. For some problems that may occur under extreme working conditions (such as high temperature, high pressure, high frequency, etc.), traditional testing methods are even more unable to effectively predict and evaluate. This leads to serious faults such as data loss and read and write errors in the memory chip during actual use, thereby affecting the stability of the memory chip. Therefore, a high-reliability memory chip packaging and testing method is needed to improve the stability of the memory chip. Summary of the invention

[0004] The present invention provides a high-reliability memory chip packaging test method and system, the main purpose of which is to improve the stability of the memory chip.

[0005] To achieve the above object, the present invention provides a high-reliability memory chip packaging test method, comprising: Acquire original parameter information corresponding to the memory chip to be tested, collect package structure data in the original parameter information, construct a three-dimensional model corresponding to the memory chip to be tested based on the package structure data, perform feature extraction on the three-dimensional model, and obtain chip feature data; Compare and analyze the chip feature data with reference data of a standard memory chip to obtain difference analysis data, mine potential defect information in the difference analysis data, screen suspicious packaging parts corresponding to the potential defect information, and monitor the real-time working environment parameters of the memory chip to be tested in real time to calculate the sensitivity value of the suspicious packaging parts affected by the environmental parameters; Based on the sensitivity value, evaluate the possible fault risk type of the memory chip to be tested, locate the weak link in the package of the memory chip to be tested based on the fault risk type, perform performance detection on the weak link, obtain the link performance status, and find the specific problem point in the link performance status; Based on the specific problem points, formulate a test planning target corresponding to the memory chip to be tested, analyze the test means in the test planning target, and query the test standard corresponding to the test means, and generate a test operation instruction corresponding to the memory chip to be tested based on the test standard; After applying the test operation instruction to the memory chip to be tested, a packaging test operation is performed on the memory chip to be tested to obtain a packaging test chip, electrical performance data corresponding to the packaging test chip is collected, and stability verification is performed on the electrical performance data to obtain verification result data, and based on the verification result data, a packaging test report corresponding to the memory chip to be tested is generated.

[0006] Optionally, extracting features from the three-dimensional model to obtain chip feature data includes: Identifying contour edge lines corresponding to internal structures in the three-dimensional model; Performing grid processing on the contour edge lines to obtain regular grid units; Analyzing the connection relationship between adjacent grids of the regular grid unit; Based on the connection relationship, determining the topological structure point corresponding to the three-dimensional model; Based on the topological structure points, feature extraction is performed on the three-dimensional model to obtain chip feature data.

[0007] Optionally, the comparing and analyzing the chip feature data with reference data of a standard memory chip to obtain difference analysis data includes: Determine the data dimension corresponding to the chip characteristic data and the reference data of the standard memory chip; Based on the data dimension, calculating the absolute difference between the chip characteristic data and the reference data of the standard memory chip; Performing data statistics on the absolute differences to obtain a difference statistics set; Based on a preset threshold range, dividing the data threshold points in the difference statistical set; Based on the data threshold point, the chip characteristic data is compared and analyzed with reference data of a standard memory chip to obtain difference analysis data.

[0008] Optionally, the calculating, based on the data dimension, an absolute difference between the chip feature data and reference data of a standard memory chip includes: The absolute difference between the chip characteristic data and the reference data of the standard memory chip is calculated using the following formula: in, represents the absolute difference between the chip characteristic data and the reference data of the standard memory chip, Indicates the total number corresponding to the data dimension, Indicates the quantity index corresponding to the data dimension, Indicated in The characteristic data value corresponding to the chip characteristic data in the data dimension, Indicated in The reference data value corresponding to the standard storage chip in the data dimension is: Indicates The importance coefficient corresponding to each data dimension.

[0009] Optionally, calculating the sensitivity value of the suspicious packaging part affected by the environmental parameters includes: The following formula is used to calculate the sensitivity value of the suspected packaging part affected by the environmental parameters: in, Indicates the sensitivity value of the suspected packaging part affected by environmental parameters, Indicates the number of types corresponding to environmental parameters, Indicates the quantity index corresponding to the environmental parameters, Indicates The range of change corresponding to the environmental parameters, Indicates The weight coefficient of the influence of various environmental parameters on the suspicious packaging parts, and Respectively represent the start time and end time of the evaluation period, Indicates at time The performance change function corresponding to the suspicious packaging part at the moment.

[0010] Optionally, locating the weak link in the memory chip package to be tested based on the failure risk type includes: Analyze the factor impact weights corresponding to the fault risk factors in the fault risk type; Based on the factor influence weights, the fault risk factors are sorted to obtain a risk factor sequence; Constructing a correlation map between the risk factor sequence and the packaging components corresponding to the memory chip to be tested; Filtering strongly associated nodes in the association graph; Based on the strongly associated nodes, weak links in the memory chip package to be tested are located.

[0011] Optionally, the step of finding a specific problem point in the link performance state includes: Analyze the status performance indicators corresponding to the performance status of the link; Constructing a mapping relationship framework corresponding to the state performance indicators; Based on the mapping relationship framework, analyzing the preliminary classification problems corresponding to the performance status of the links; Collect historical case data corresponding to the preliminary classification questions; Based on the historical case data, find the specific problem points in the performance status of the link.

[0012] Optionally, formulating a test planning target corresponding to the memory chip to be tested based on the specific problem point includes: Analyzing the relationship characteristics between the specific problem points and the functional modules in the memory chip to be tested; Based on the relationship characteristics, identifying the module impact degree corresponding to the functional module in the memory chip to be tested; Performing hierarchical processing on the impact degree of the modules to obtain hierarchical results; According to the stratification results, determine the functional module scope corresponding to the key test; Based on the functional module scope, a test planning target corresponding to the memory chip to be tested is formulated.

[0013] Optionally, the generating, based on the test standard, a test operation instruction corresponding to the memory chip to be tested includes: Analyze the project terms and conditions corresponding to the test standards; Based on the project terms and conditions, sort out the project test phases corresponding to the memory chip to be tested; Extract key test elements in the project testing phase; Based on the key test elements, determining the operation test process corresponding to the memory chip to be tested; Based on the operation test process, a test operation instruction corresponding to the memory chip to be tested is generated.

[0014] In order to solve the above problems, the present invention also provides a high-reliability memory chip packaging and testing system, the system comprising: A feature extraction module is used to obtain original parameter information corresponding to the memory chip to be tested, collect package structure data in the original parameter information, construct a three-dimensional model corresponding to the memory chip to be tested based on the package structure data, and perform feature extraction on the three-dimensional model to obtain chip feature data; A sensitivity calculation module is used to compare and analyze the chip feature data with the reference data of the standard memory chip to obtain difference analysis data, mine potential defect information in the difference analysis data, screen suspicious packaging parts corresponding to the potential defect information, and monitor the real-time working environment parameters of the memory chip to be tested in real time to calculate the sensitivity value of the suspicious packaging parts affected by the environmental parameters; A problem finding module is used to evaluate the possible fault risk type of the memory chip to be tested based on the sensitivity value, locate the weak link in the package of the memory chip to be tested based on the fault risk type, perform performance detection on the weak link, obtain the link performance status, and find the specific problem point in the link performance status; An instruction generation module is used to formulate a test planning target corresponding to the memory chip to be tested based on the specific problem point, analyze the test means in the test planning target, and query the test standard corresponding to the test means, and generate a test operation instruction corresponding to the memory chip to be tested based on the test standard; A report generation module is used to apply the test operation instruction to the memory chip to be tested, perform a packaging test operation on the memory chip to be tested, obtain a packaging test chip, collect electrical performance data corresponding to the packaging test chip, and perform stability verification on the electrical performance data to obtain verification result data, and generate a packaging test report corresponding to the memory chip to be tested based on the verification result data.

[0015] Compared with the problems described in the background technology, the present invention obtains the original parameter information corresponding to the memory chip to be tested and collects the packaging structure data in the original parameter information, which helps to deeply understand the internal structure and physical characteristics of the chip, provides a basic basis for subsequent performance evaluation, and can accurately determine whether the chip meets specific design and production standards to ensure product quality. The present invention compares and analyzes the chip feature data with the reference data of the standard memory chip to obtain difference analysis data, which can accurately locate the deviation of the chip in performance, structure, etc., provide a clear direction for quality control, and help to screen out unqualified products in a timely manner. Furthermore, based on the sensitivity value, the present invention evaluates the type of failure risk that may occur in the memory chip to be tested, and can predict the possible type of failure in advance. type, providing a clear direction for preventive maintenance, reducing the probability of sudden failures of the chip in actual use, and improving the stability of the system. Furthermore, based on the specific problem points, the present invention formulates the test planning goals corresponding to the memory chip to be tested, which can achieve precise focus on the test, avoid waste of resources and time consumption caused by blind comprehensive testing, and improve the quality and reliability of the memory chip. Finally, the present invention applies the test operation instructions to the memory chip to be tested, performs a packaging test operation on the memory chip to be tested, and obtains a packaging test chip, which can effectively guarantee the packaging quality of the memory chip, and can accurately detect problems that may occur in the chip packaging process, such as poor pin connection, poor packaging sealing, etc., so as to make timely improvements and improve the overall stability of the chip. Therefore, the high-reliability memory chip packaging test method and system provided by the embodiment of the present invention can improve the stability of the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a process flow of a high reliability memory chip packaging test method provided by an embodiment of the present invention; Figure 2 A schematic diagram of modules for implementing the high-reliability memory chip packaging and testing system provided by one embodiment of the present invention.

[0017] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0018] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0019] The embodiment of the present application provides a high-reliability memory chip packaging and testing method. The execution subject of the high-reliability memory chip packaging and testing method includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided by the embodiment of the present application. In other words, the high-reliability memory chip packaging and testing method can be executed by software or hardware installed in a terminal device or a server device. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0020] Embodiment 1: Reference Figure 1 FIG. 1 is a flow chart of a high reliability memory chip packaging and testing method provided by an embodiment of the present invention. In this embodiment, the high reliability memory chip packaging and testing method includes: S1. Obtain original parameter information corresponding to the memory chip to be tested, and collect packaging structure data in the original parameter information, build a three-dimensional model corresponding to the memory chip to be tested based on the packaging structure data, extract features from the three-dimensional model, and obtain chip feature data.

[0021] The present invention obtains the original parameter information corresponding to the memory chip to be tested and collects the packaging structure data in the original parameter information, which helps to gain an in-depth understanding of the internal structure and physical characteristics of the chip, provides a basic basis for subsequent performance evaluation, and can accurately determine whether the chip meets specific design and production standards to ensure product quality.

[0022] The memory chip to be tested refers to a chip individual that needs to be evaluated and verified for performance, reliability, etc. during the production, research and development or quality inspection of the memory chip. It can be a new chip that has just been produced and has not been inspected, or a chip sample used to test new designs and new process effects during the research and development stage; the original parameter information refers to various inherent parameter data of the memory chip to be tested in the initial state. These parameters include the basic technical specifications of the chip, such as storage capacity (for example, 1TB, 2TB, etc.), data transmission rate (such as how many GB of data can be transmitted per second), operating voltage range (specifying the voltage range required for the normal operation of the chip), and interface type (such as common SATA, NVMe and other interface standards) , as well as circuit design parameters and logic structure parameters inside the chip; the package structure data refers to data describing the package form and internal structure of the memory chip to be tested, including the type of packaging material (such as plastic packaging, ceramic packaging, etc.), the geometric dimensions of the package (specific values ​​of length, width, and height), the number, arrangement, and functional definition of pins (different pins are responsible for different functions such as power supply, data transmission, and control signals), and the connection method between the bare die and the package inside the chip (such as wire bonding, flip chip, and other connection technology related information). Optionally, the acquisition of the original parameter information corresponding to the memory chip to be tested can be achieved by electronic testing equipment, such as an oscilloscope, a logic analyzer, etc., by connecting the chip pins to obtain the original parameter information related to the electrical signal; the acquisition of the package structure data in the original parameter information can be achieved by three-dimensional X-ray detection technology, such as: using three-dimensional X-ray detection technology to penetrate the chip package, clearly present a three-dimensional image of the internal structure, and then extract the package structure data.

[0023] Furthermore, the present invention constructs a three-dimensional model corresponding to the memory chip to be tested based on the packaging structure data, which can realize visual display and more intuitively understand the internal structure and packaging details of the chip. It can perform virtual simulation and testing, and predict the performance of the chip in different environments and working conditions before actual operation, discover potential problems in advance, and reduce R&D costs and time.

[0024] Among them, the three-dimensional model refers to a three-dimensional digital model constructed based on the packaging structure data of the memory chip to be tested by means of computer graphics, three-dimensional modeling software or algorithms, etc. It comprehensively and intuitively presents the external packaging form of the memory chip with precise size and shape, including the geometric outline of the package, the position and arrangement of the pins, etc., and can also show the internal structural layout of the chip, such as the position of the chip die, the connection method between the chip and the package (such as wire bonding, flip chip, etc.), the direction of the internal lines and other details. The model can not only provide the spatial structure information of the chip, but also integrate parameters such as material properties into the model, so as to perform various simulation analyses on the chip in a virtual environment, such as heat conduction analysis, mechanical properties analysis, etc. Optionally, the construction of the three-dimensional model corresponding to the memory chip to be tested can be achieved through a three-dimensional modeling tool, such as: SolidWorks, AutoCAD 3D and other tools.

[0025] Furthermore, the present invention obtains chip feature data by extracting features from the three-dimensional model, which can provide a strong basis for accurate classification and identification of chips, facilitate rapid differentiation of different types of chips during production and quality inspection, and help to deeply analyze the performance bottlenecks and potential defects of chips, providing key references for optimizing design and improving processes, thereby improving the overall quality and performance of chips.

[0026] Among them, the chip feature data refers to the data set that can comprehensively and accurately describe the chip structure and performance characteristics after performing the above-mentioned series of feature extraction operations on the three-dimensional model. These data include but are not limited to the geometric parameters of the contour edge lines, the attribute parameters of the regular grid cells, the characteristic description of the connection relationship, and the relevant information of the topological structure points.

[0027] As an embodiment of the present invention, the feature extraction of the three-dimensional model to obtain chip feature data includes: identifying contour edge lines corresponding to the internal structure in the three-dimensional model; gridding the contour edge lines to obtain regular grid units; analyzing the connection relationship between adjacent grids of the regular grid units; based on the connection relationship, determining the topological structure points corresponding to the three-dimensional model; based on the topological structure points, feature extraction of the three-dimensional model to obtain chip feature data.

[0028] The contour edge lines refer to the boundary lines between the internal structure of the chip (such as chip die, pins, connecting wires, etc.) and the surrounding space or other structures in the three-dimensional model. These lines accurately outline the outlines of each component inside the chip, which can be identified from the geometric information of the three-dimensional model and can intuitively reflect the basic characteristics of the chip's internal structure, such as shape and size; the regular grid unit refers to a small unit with a uniform shape and size obtained by gridding the contour edge lines. These grid units can be squares, triangles or other regular geometric shapes, which are evenly covered in the area surrounded by the contour edge lines. Through this gridding process, the complex chip internal structure area is divided into multiple simple, easy-to-analyze small units; the connection relationship refers to the mutual relationship between adjacent grids in the regular grid unit. This connection relationship may include shared edges and shared vertices of adjacent grids, as well as the relative position and direction information between grids; the topological structure point refers to a key node that can represent the topological structure characteristics of the three-dimensional model based on the connection relationship between adjacent grids. These points are usually located at important positions of the connection relationship, such as the intersection of multiple grids, the position where the connection relationship changes, etc. The topological structure point can reflect the topological form of the chip's internal structure, such as whether there are branches, loops, etc.

[0029] Furthermore, the identification of the contour edge lines corresponding to the internal structure in the three-dimensional model can be achieved by an edge detection algorithm, such as the Canny edge detection algorithm. When the three-dimensional model is converted into a two-dimensional projection image or the algorithm is applied to a two-dimensional slice of the three-dimensional model, the contour edge lines can be identified; the meshing of the contour edge lines can be achieved by a triangulation algorithm, such as constructing a triangular mesh according to the points on the contour edge lines so that the mesh is as close to an equilateral triangle as possible, thereby obtaining a regular mesh unit; the analysis of the connection relationship between adjacent meshes of the regular mesh unit can be achieved by an adjacency matrix method, such as by constructing a matrix in which the elements of the matrix represent the connection relationship between mesh units (adjacent is 1, non-adjacent is 0), and the connection relationship between adjacent meshes can be clearly analyzed; the determination of the topological structure points corresponding to the three-dimensional model can be achieved by a model simplification algorithm, such as in the process of simplifying the three-dimensional model, the key points that have a greater impact on the overall shape of the model are the topological structure points; the feature extraction of the three-dimensional model can be achieved by a principal component analysis algorithm, such as extracting the main feature components from multiple dimensional data (such as size, shape, etc.) of the three-dimensional model to obtain chip feature data.

[0030] S2. Compare and analyze the chip feature data with the reference data of the standard memory chip to obtain difference analysis data, mine the potential defect information in the difference analysis data, screen the suspicious packaging parts corresponding to the potential defect information, monitor the real-time working environment parameters of the memory chip to be tested in real time, and calculate the sensitivity value of the suspicious packaging parts affected by the environmental parameters.

[0031] The present invention obtains difference analysis data by comparing and analyzing the chip feature data with reference data of a standard memory chip, which can accurately locate deviations in chip performance, structure, etc., provide a clear direction for quality control, and help to screen out unqualified products in a timely manner.

[0032] Among them, the reference data of standard memory chips refers to a set of standardized data covering physical structure, performance parameters and internal structure, which includes standard package size, pin characteristics, material specifications, and clear performance indicators such as storage capacity, transmission rate, operating voltage, as well as standard chip die size and internal connection method and other information; the difference analysis data refers to the comparison result of comprehensive chip feature data and standard memory chip reference data, which is a data set that can comprehensively reflect the difference between the two after a series of processing and analysis. For example, it will clearly point out which data dimensions have significant differences, what impact these differences may have on the performance, reliability and stability of the chip, and whether these differences are within an acceptable range.

[0033] As an embodiment of the present invention, the chip feature data is compared and analyzed with the reference data of the standard memory chip to obtain difference analysis data, including: determining the data dimensions corresponding to the chip feature data and the reference data of the standard memory chip; based on the data dimensions, calculating the absolute difference between the chip feature data and the reference data of the standard memory chip; performing data statistics on the absolute difference to obtain a difference statistics set; based on a preset threshold range, dividing the data threshold points in the difference statistics set; based on the data threshold points, the chip feature data is compared and analyzed with the reference data of the standard memory chip to obtain difference analysis data.

[0034] Among them, the data dimension refers to the data classification method used to describe the chip characteristics, which covers the attribute information of the chip in different aspects. For example, in the memory chip, the data dimension can include the physical structure dimension, such as the chip package size, the number of pins and the arrangement method, etc.; performance parameter dimensions, such as storage capacity, read and write speed, power consumption, etc.; electrical characteristics dimensions, such as operating voltage, current, etc.; the absolute difference refers to the absolute value of the difference between the chip characteristic data and the standard memory chip reference data under the same data dimension, which eliminates the positive and negative direction effects of the difference and only focuses on the difference in the values ​​of the two. For example, if the storage capacity in the chip characteristic data is 512GB, and the storage capacity in the reference data of the standard memory chip is 1024GB, then the absolute difference in the data dimension of storage capacity is 1024GB. The value is |512-1024|=512GB; the difference statistical set refers to the data set formed after statistical analysis of multiple absolute differences, which contains the results of various statistical operations on the absolute differences, such as mean, median, mode, standard deviation, etc., which can reflect the overall average deviation of the chip feature data from the standard reference data; the standard deviation can reflect the discrete degree of these absolute differences, that is, the fluctuation of the data; the data threshold point refers to a numerical point with specific meaning determined in the difference statistical set based on a preset threshold range. For example, for the data dimension of the read and write speed of the storage chip, it may be preset that when the absolute difference exceeds a certain value (such as 50MB / s), the difference is considered to have a greater impact, then this 50MB / s is a data threshold point.

[0035] Furthermore, the determination of the data dimensions corresponding to the chip feature data and the reference data of the standard storage chip can be achieved through metadata management tools, such as Apache Atlas and other tools, to match and determine the data dimensions corresponding to the chip feature data and the reference data; the calculation of the absolute difference between the chip feature data and the reference data of the standard storage chip can be achieved through the following calculation companies; the data statistics of the absolute difference can be achieved through statistical analysis tools, such as SPSS and other tools; the division of the data threshold points in the difference statistical set can be achieved through a clustering algorithm, such as clustering the absolute difference data, determining the center and boundaries of different categories based on the clustering results, and using the boundary points as data threshold points; the comparative analysis of the chip feature data and the reference data of the standard storage chip can be achieved through a multidimensional data analysis method, such as the principal component analysis method, forming a data matrix of the chip feature data and the reference data, applying the PCA algorithm to reduce the dimension and extract features, and performing comparative analysis in a low-dimensional space to obtain difference analysis data.

[0036] As an embodiment of the present invention, the calculating, based on the data dimension, the absolute difference between the chip feature data and the reference data of the standard memory chip includes: The absolute difference between the chip characteristic data and the reference data of the standard memory chip is calculated using the following formula: in, represents the absolute difference between the chip characteristic data and the reference data of the standard memory chip, Indicates the total number corresponding to the data dimension, Indicates the quantity index corresponding to the data dimension, Indicated in The characteristic data value corresponding to the chip characteristic data in the data dimension, Indicated in The reference data value corresponding to the standard storage chip in the data dimension is: Indicates The importance coefficient corresponding to each data dimension.

[0037] In detail, the absolute difference refers to the absolute value of the difference between the chip characteristic data and the reference data of the standard memory chip in each data dimension, which is a value obtained by comprehensive calculation after weighting by considering the importance coefficient of each data dimension, and is used to measure the overall difference between the chip characteristic data and the standard reference data; the characteristic data value refers to the specific value of the chip actually measured or obtained in each data dimension, which reflects the actual performance, specifications and other characteristics of the chip; the reference data value refers to the value specified or expected to be achieved by the standard memory chip in each data dimension, which is a benchmark for comparison with the actual chip characteristic data value to evaluate whether the chip meets the standard or expected performance and specifications; the importance coefficient refers to a value used to represent the relative importance of each data dimension in the overall evaluation. Different data dimensions have different degrees of influence on the performance, quality, applicability and other aspects of the chip, and the importance coefficient is used to quantify this difference.

[0038] By mining the potential defect information in the difference analysis data, the present invention can provide early warning of possible chip performance problems or potential failures, provide a key basis for quality control in the production process, and help to adjust the production process in a timely manner to reduce the defective rate.

[0039] Among them, the potential defect information refers to various types of information hidden in the difference analysis results between chip feature data and standard storage chip reference data, which has not yet been clearly manifested, but may have adverse effects on chip performance, reliability, stability, etc. For example, slight differences in certain data dimensions may indicate potential process defects in the internal structure of the chip, or performance deviation trends that may cause failures under specific working conditions, etc. Optionally, the mining of potential defect information in the difference analysis data can be achieved through information mining tools, such as: Minitab, TensorFlow and other tools.

[0040] Furthermore, the present invention can accurately locate the packaging area where problems may exist by screening the suspicious packaging parts corresponding to the potential defect information and monitoring the real-time working environment parameters of the memory chip to be tested in real time, thereby providing a clear direction for subsequent troubleshooting and repair and improving maintenance efficiency.

[0041] Among them, the suspicious packaging parts refer to the physical locations of the chip that may have packaging problems after the potential defect information is mined through the difference analysis between the chip feature data and the standard reference data. These parts can be the shell, pins, sealing areas and other parts of the chip package. For example, when it is found that the electrical performance parameters of the chip are different from the standard values, after in-depth analysis, it is speculated that the connection between the pin and the package body is not firm, resulting in unstable signal transmission. In this case, the connection part between the pin and the package body is a suspicious packaging part; the real-time working environment parameters refer to various dynamic physical quantities of the environment in which the memory chip to be tested is located during actual operation, which mainly include parameters such as ambient temperature, humidity, air pressure, electromagnetic interference intensity, etc. Ambient temperature that is too high or too low can be It may affect the performance and stability of the chip, or even cause chip damage, so real-time monitoring of temperature is very important. Changes in humidity may cause condensation of water vapor inside the chip, causing problems such as short circuits, so humidity is also an important monitoring parameter. Optionally, the screening of suspicious packaging parts corresponding to the potential defect information can be achieved through a fault tree analysis method, such as: through fault tree analysis, the packaging level and specific parts that may cause the problem can be traced back, such as specific pin connections or internal circuit areas, thereby determining the suspicious packaging parts; the real-time monitoring of the real-time working environment parameters of the memory chip to be tested can be achieved through a sensor network, such as: installing a high-precision temperature sensor on the chip test platform, which can obtain the temperature changes around the chip in real time, thereby obtaining real-time working environment parameters.

[0042] Furthermore, the present invention can quantify the specific degree of influence of environmental factors on the suspicious packaging parts by calculating the sensitivity value of the suspicious packaging parts affected by environmental parameters, provide an accurate basis for formulating targeted protective measures, and help improve the stability and reliability of the chip in different environments.

[0043] Among them, the sensitivity value refers to a comprehensive indicator used to quantify the sensitivity of the suspicious packaging part to changes in environmental parameters. The larger the value, the more susceptible the suspicious packaging part is to changes in environmental parameters, thereby causing changes in chip performance or the emergence of potential defects.

[0044] As an embodiment of the present invention, the calculating of the sensitivity value of the suspicious packaging part affected by the environmental parameters includes: The following formula is used to calculate the sensitivity value of the suspected packaging part affected by the environmental parameters: in, Indicates the sensitivity value of the suspected packaging part affected by environmental parameters, Indicates the number of types corresponding to environmental parameters, Indicates the quantity index corresponding to the environmental parameters, Indicates The range of change corresponding to the environmental parameters, Indicates The weight coefficient of the influence of various environmental parameters on the suspicious packaging parts, and Respectively represent the start time and end time of the evaluation period, Indicates at time The performance change function corresponding to the suspicious packaging part at the moment.

[0045] In detail, the variation range refers to the range or degree of variation of each environmental parameter under certain conditions. For example, for temperature environmental parameters, the variation range can be the difference between the highest and lowest temperature values ​​within a period of time; for humidity environmental parameters, it can be the maximum fluctuation value of humidity, etc.; the influence weight coefficient refers to a value used to measure the importance of each environmental parameter on the suspected packaging part. Different environmental parameters have different influences on the packaging part. A weight coefficient is assigned to each environmental parameter; the evaluation time period refers to a specific time interval used to observe and calculate the influence of environmental parameters on the suspected packaging part, which is from the start time to the end time. and end time Determine that during this time period, monitor and collect data on changes in environmental parameters and performance changes in suspicious packaging parts in order to calculate the sensitivity value; the performance change function refers to a function that describes the performance of the suspicious packaging part over time. A mathematical function of the change that reflects how the performance of the suspected package part (such as resistance, capacitance, signal transmission quality, etc.) changes over time due to changes in environmental parameters during the evaluation period.

[0046] S3. Based on the sensitivity value, evaluate the possible failure risk type of the memory chip to be tested, locate the weak link in the package of the memory chip to be tested based on the failure risk type, perform performance testing on the weak link, obtain the performance status of the link, and find the specific problem points in the performance status of the link.

[0047] The present invention evaluates the possible failure risk types of the memory chip to be tested based on the sensitivity value, can predict the possible failure types in advance, provide a clear direction for preventive maintenance, reduce the probability of sudden failures of the chip in actual use, and improve the stability of the system.

[0048] Among them, the failure risk type refers to various types of failure manifestations and categories that may be caused by the suspicious packaging parts of the storage chip being affected by environmental parameters, for example, thermal stress failures caused by temperature changes may cause the package to crack or damage the internal structure of the chip; short circuit or leakage failures may be caused by humidity; packaging sealing failure caused by air pressure changes; and signal transmission errors or data loss failures that may occur in an electromagnetic interference environment, etc. Optionally, the evaluation of the possible failure risk types of the storage chip to be tested can be achieved through machine learning algorithms, such as: decision tree algorithms, support vector machines and other algorithms.

[0049] Furthermore, the present invention locates the weak links in the memory chip package to be tested based on the fault risk type, can accurately focus on the problem area, provide a clear direction for subsequent optimization and improvement work, avoid blind troubleshooting, and improve R&D and production efficiency.

[0050] Among them, the weak links refer to those parts or components in the memory chip package to be tested that are relatively susceptible to failure risk factors and thus cause chip failure. These weak links are finally located through a series of steps such as analyzing the factor influence weights, sorting the risk factor sequence, constructing the correlation map, and screening the strongly correlated nodes. These links may be due to material properties, structural design, manufacturing process, etc.

[0051] As an embodiment of the present invention, locating the weak links in the memory chip package to be tested based on the fault risk type includes: parsing the factor influence weights corresponding to the fault risk factors in the fault risk type; sorting the fault risk factors based on the factor influence weights to obtain a risk factor sequence; constructing an association map between the risk factor sequence and the corresponding package components of the memory chip to be tested; screening the strongly associated nodes in the association map; and locating the weak links in the memory chip package to be tested based on the strongly associated nodes.

[0052] Among them, the factor influence weight refers to the value used to measure the influence of each fault risk factor in the fault risk type on the memory chip packaging failure, which reflects the relative importance of each risk factor in causing problems in the chip packaging. Different fault risk factors, such as temperature changes, humidity fluctuations, mechanical stress, etc.; the risk factor sequence refers to an ordered list formed by sorting the fault risk factors according to the factor influence weights. In this sequence, each fault risk factor is arranged in order from large to small (or small to large, depending on the specific sorting rules) according to its weight value; the association map refers to a graphical representation method, which displays The figure shows the relationship between the risk factor sequence and the package components corresponding to the memory chip to be tested. In this graph, risk factors are one type of node and package components are another type of node. The association between the two is represented by a line. The thickness or color of the line and other attributes can be used to represent the strength of the association. The strongly associated nodes refer to the package component nodes that have a strong association with the risk factors in the association graph. The package components corresponding to these nodes are more susceptible to the risk factors. If the association strength threshold is set to 0.5, the package shell nodes and pin solder joint nodes whose association strength with the temperature change node is greater than 0.5 are strongly associated nodes.

[0053] Furthermore, the analysis of the factor influence weights corresponding to the fault risk factors in the fault risk type can be achieved through a weight analysis tool, such as MATLAB, SPSS and other tools; the sorting of the fault risk factors can be achieved through a sorting algorithm, such as bubble sort, quick sort and other algorithms; the construction of an association graph between the risk factor sequence and the packaging components corresponding to the memory chip to be tested can be achieved through a graph construction method, such as using a graph database (such as Neo4j) to store and manage these entities and relationships, taking risk factors and packaging components as nodes, and relationships as edges to construct an association graph; the screening of strongly associated nodes in the association graph can be achieved through a threshold-based screening method, such as traversing all edges in the association graph, and screening out the packaging component nodes connected to the edges with an association strength greater than a threshold as strongly associated nodes; the positioning of the weak links in the packaging of the memory chip to be tested can be achieved through a link positioning tool, such as ATE, ANSYS and other tools.

[0054] The present invention performs performance testing on the weak links to obtain link performance status, which can accurately and intuitively understand the actual operating conditions of the weak links and provide definite data support for subsequent optimization and improvement.

[0055] Among them, the link performance status refers to the comprehensive performance of various performance indicators presented by the weak link in the storage chip package after performance testing, which covers the physical, electrical and other characteristics of the weak link, such as the mechanical strength and thermal conductivity of the weak parts of the packaging shell, the conductivity of weak parts such as pin solder joints, connection stability, etc. Optionally, the performance testing of the weak link can be achieved through machine learning algorithms, such as support vector machines, neural networks and other algorithms.

[0056] Furthermore, by finding specific problem points in the performance status of the links, the present invention can achieve a detailed diagnosis of weak links, identify specific factors leading to poor performance, and provide a strong basis for precise policy implementation.

[0057] Among them, the specific problem point refers to the precise fault location or cause of the performance abnormality determined after a comprehensive analysis of the performance status of the link. It is the final result obtained after a series of steps such as analyzing status performance indicators, building a mapping relationship framework, determining preliminary classification problems, and referring to historical case data. The specific problem point can be actual fault conditions such as the cracking of a solder joint in the chip package, the short circuit of a certain circuit, and the aging of the material of a certain component.

[0058] As an embodiment of the present invention, the search for specific problem points in the performance status of the link includes: analyzing the status performance indicators corresponding to the performance status of the link; constructing a mapping relationship framework corresponding to the status performance indicators; based on the mapping relationship framework, analyzing the preliminary classification problems corresponding to the performance status of the link; collecting historical case data corresponding to the preliminary classification problems; and based on the historical case data, searching for specific problem points in the performance status of the link.

[0059] Among them, the state performance indicators refer to a series of quantitative parameters used to measure and describe the performance status of weak links. These indicators can reflect the performance characteristics of weak links from multiple dimensions. For example, in terms of electrical performance, they can include resistance, capacitance, inductance, signal transmission delay, etc.; in terms of thermal performance, they cover thermal conductivity, thermal resistance, temperature distribution, etc.; in terms of mechanical properties, there are strength, hardness, elastic modulus, etc.; the mapping relationship framework refers to a logical structure that establishes a connection between state performance indicators and the types of problems that may occur. Through in-depth research on the physical characteristics, working principles and past failure experiences of weak links, it summarizes the correspondence between changes in different performance indicators and corresponding problems. This framework can help quickly locate the potential problem direction caused by abnormal performance indicators; the preliminary classification problem refers to the mapping Under the guidance of the relationship framework, according to the abnormal conditions of the performance status indicators of the links, a preliminary classification of possible problems is carried out. It is not a specific problem point, but a rough division of the problems according to their nature and category, narrowing the scope of problem search, and determining the problem category to which the performance anomaly can be attributed through matching analysis of the status performance indicators and the mapping relationship framework, such as electrical fault category, thermal performance fault category, mechanical structure fault category, etc.; the historical case data refers to records of situations similar to the current preliminary classification problems that have occurred in similar memory chip packages or related electronic components in the past. These data contain information such as the performance status indicators at the time, the specific problems found, the methods for solving the problems, and the final processing results.

[0060] Furthermore, the analysis of the state performance indicators corresponding to the performance states of the links can be implemented through a filtering algorithm, such as: when the temperature sensor collects the chip package temperature data, the data is predicted and updated through the Kalman filtering algorithm to remove noise interference and obtain more accurate temperature performance indicator data; the construction of the mapping relationship framework corresponding to the state performance indicators can be implemented through an association rule mining algorithm, such as: by analyzing the electrical performance indicator data of a large number of chips and the electrical fault data that occurs, mining the association rules between a certain electrical performance indicator (such as capacitance value) and a certain electrical fault (such as short circuit) when it changes within a certain range, thereby constructing a mapping relationship framework; the analysis of the link performance The preliminary classification problem corresponding to the energy state can be solved by data analysis tools, such as Excel and other tools, which can analyze and organize the performance indicator data through pivot tables and other functions to assist in the preliminary classification problem; the collection of historical case data corresponding to the preliminary classification problem can be achieved through web crawler tools, such as writing a Scrapy crawler program to capture posts about chip packaging failures from electronic technology forums and extract historical case data from them; the search for specific problem points in the performance state of the link can be achieved through a logic analyzer, such as using a logic analyzer to collect the digital signal of the chip, analyze the timing relationship and logic state of the signal, and find out the specific problem points caused by the signal abnormality.

[0061] S4. Based on the specific problem points, formulate the test planning goals corresponding to the memory chip to be tested, analyze the test means in the test planning goals, and query the test standards corresponding to the test means, and based on the test standards, generate the test operation instructions corresponding to the memory chip to be tested.

[0062] Based on the specific problem points, the present invention formulates the test planning goals corresponding to the memory chip to be tested, which can achieve precise focus on the test, avoid waste of resources and time consumption caused by blind comprehensive testing, and improve the quality and reliability of the memory chip.

[0063] Among them, the test planning goal refers to a detailed test plan and expected test results formulated for the memory chip to be tested based on the determined functional module scope, which includes clarifying the specific content of the test, such as which performance indicators are tested for each functional module, and which test methods and tools are used; determining the execution order of the tests, and reasonably arranging the order of testing each functional module to improve the test efficiency; setting the expected results of the test, that is, the chip performance indicators and functional requirements that are expected to be achieved through the test; and also including resource allocation plans, such as the allocation of manpower, material resources and time.

[0064] As an embodiment of the present invention, the test planning objectives corresponding to the memory chip to be tested are formulated based on the specific problem points, including: analyzing the relationship characteristics corresponding to the specific problem points and the functional modules in the memory chip to be tested; based on the relationship characteristics, identifying the module impact degrees corresponding to the functional modules in the memory chip to be tested; performing layered processing on the module impact degrees to obtain layered results; according to the layered results, determining the functional module range corresponding to the key test; based on the functional module range, formulating the test planning objectives corresponding to the memory chip to be tested.

[0065] Among them, the functional module refers to an independent component with a specific function in the memory chip to be tested. These modules work together to realize various functions of the memory chip, such as data storage, reading, erasing, etc. Each functional module has its own unique circuit structure and design purpose. For example, the address decoding module is responsible for converting the input address signal into the corresponding storage unit selection signal; the storage array module is the place where data is actually stored, which is composed of a large number of storage units; the control logic module is used to coordinate the work of each module to ensure the correct reading and writing of data and the normal operation of the chip; the module impact degree refers to the size and scope of the impact of a specific problem point on the performance and normal operation of each functional module in the memory chip. This impact degree The degree can be measured in many ways, such as the probability of a problem point causing a functional module failure, the extent of the functional module performance degradation, the impact of the functional module on the criticality of the entire chip function due to the problem point, etc.; the stratification result refers to the result obtained after classifying and hierarchical division of the module impact degree. Through certain rules and standards, each functional module is divided into different levels according to the degree to which it is affected by a specific problem point; the functional module range refers to the set of functional modules that need to be tested in focus according to the stratification result. This range clarifies the functional modules that need to be focused on and tested during the test process to ensure that functional module failures that may be caused by specific problem points can be discovered and resolved in a timely manner.

[0066] Furthermore, the analysis of the relationship characteristics between the specific problem points and the functional modules in the memory chip to be tested can be achieved through the FMEA method, such as: in the FMEA analysis, for the control logic module of the memory chip, considering that its failure mode may include logic errors, signal transmission delays, etc., the signal interference problem in the specific problem point is associated with it, and its impact on the function of the module is analyzed, thereby determining the relationship characteristics between the two; the identification of the module impact degree corresponding to the functional module in the memory chip to be tested can be achieved through automatic testing equipment, such as: when testing the data transmission module, using ATE to input different data sequences, and at the same time introducing the conditions of the specific problem point (such as signal attenuation), and measuring the error rate of data transmission through ATE, thereby quantifying the module impact degree; the impact degree on the module The stratification processing can be achieved through a threshold-based stratification method, such as: setting different impact thresholds, comparing the impact of functional modules with them, dividing them into different levels, and finally obtaining stratification results; the determination of the functional module range corresponding to the key test can be achieved through data visualization tools, such as: visually displaying the module impact data in Tableau, and intuitively determining the functional module range of the key test by setting different screening conditions and color markings; the formulation of the test planning goals corresponding to the storage chip to be tested can be achieved through test management tools, such as: inputting the functional module range, specific problem points and other information of the storage chip in the TestLink tool, and formulating test cases and test plans for each functional module according to its template and function, thereby generating test planning goals.

[0067] The present invention can ensure the scientificity and standardization of the testing means by analyzing the testing means in the test planning objectives and querying the testing standards corresponding to the testing means. Operating according to clear testing standards helps to discover possible deficiencies or unreasonable aspects in the test plan, and make timely adjustments and improvements to make the test plan more reasonable and efficient.

[0068] Among them, the testing means refers to the specific methods, techniques, tools and operating procedures used when testing the memory chip to achieve the test planning objectives, which includes practical measures for detecting various aspects such as chip functions, performance, reliability, etc. For example, when testing the data reading and writing functions of the memory chip, the testing means can be to use special storage testing equipment to write specific data sequences to the chip and then read the data to check the accuracy of reading and writing; it can also be to use software tools to simulate different reading and writing operation environments, such as different data transmission rates, different storage capacity loads, etc. for testing; the testing standard refers to a series of specifications, criteria and indicators that are widely recognized in the field of memory chip testing to measure whether the test results are qualified. These standards are usually formulated by industry organizations, national standards organizations or chip manufacturers themselves based on factors such as chip type, purpose and performance requirements. The test standards cover various performance dimensions of the chip, including functional integrity, performance indicator range (such as read and write speed, storage capacity, power consumption, etc.), reliability indicators (such as life, fault tolerance, etc.) and safety requirements, etc. Optionally, the test means in the analysis of the test planning objectives can be achieved through a function-oriented analysis method, such as: for the data storage function module of the storage chip, analyze how to test storage capacity, storage speed, data retention capability and other functions, so as to determine the corresponding test means; the query of the test standards corresponding to the test means can be achieved through a standard database retrieval method, such as: using a professional standard database, by entering the relevant parameters of the storage chip (such as chip type, functional characteristics, application scenarios, etc.) as search conditions, query the corresponding test standards.

[0069] Furthermore, the present invention generates test operation instructions corresponding to the memory chip to be tested based on the test standard, which can achieve standardization and normalization of test operations, ensure that each test is performed according to a unified standard, reduce human errors, and improve the consistency and repeatability of the test.

[0070] Among them, the test operation instructions refer to converting each operation step into specific and executable instructions according to the operation test process. These instructions are usually presented in concise and clear language or specific code form to guide testers or automated test systems to perform actual test operations. The test operation instructions should be detailed and accurate, and include information such as the object of the operation, the content of the operation and the requirements of the operation.

[0071] As an embodiment of the present invention, the test operation instructions corresponding to the memory chip to be tested are generated based on the test standard, including: parsing the project clause details corresponding to the test standard; based on the project clause details, sorting out the project test phases corresponding to the memory chip to be tested; extracting key test elements in the project test phases; based on the key test elements, determining the operation test process corresponding to the memory chip to be tested; based on the operation test process, generating the test operation instructions corresponding to the memory chip to be tested.

[0072] The project clauses and details refer to the specific provisions in the test standards that specify the test contents in detail, which include detailed information on the purpose of the test, scope of application, test conditions, test methods, qualification criteria, etc. For example, in the read and write speed test standard of the memory chip, the project clauses and details will clearly specify the data block size used in the test, the frequency of read and write operations, the temperature and humidity range of the test environment, and other specific parameters; the project test phase refers to dividing the entire test process into different phases according to the project clauses and details. Each phase has its specific test objectives and tasks, and there is a certain logical order between the various phases. For example, the test of memory chips can usually be divided into the initial detection phase, the functional test phase, the performance test phase, the reliability test phase, and the performance test phase. Environmental adaptability test phase, etc.; the key test elements refer to the factors that play a key role in achieving the test objectives during the project testing phase. These elements include test equipment, test methods, test environment conditions, number of test samples, etc. For example, in the performance testing phase of memory chips, the accuracy and stability of the test equipment, the scientific nature of the test methods, and the temperature and humidity control of the test environment are all key test elements; the operation test process refers to a process formed by arranging the various operation steps in the test process in sequence based on the key test elements. It describes in detail the entire process from test preparation to test completion, including how to connect the test equipment, how to set the test parameters, how to perform test operations, how to record test data, and how to deal with problems encountered during the test.

[0073] Furthermore, the parsing of the project clause details corresponding to the test standard can be achieved through a syntactic analysis tool, such as: using a syntactic analysis tool, the logical relationship between key terms and clauses can be extracted, and finally the project clause details are obtained; the combing of the project test phases corresponding to the storage chip to be tested can be achieved through a work breakdown structure method, such as: according to the functional characteristics and test requirements of the storage chip, the test is divided into different stages such as initialization test, functional test, performance test, reliability test, etc., and finally the project test phase is obtained; the extraction of key test elements in the project test phase can be achieved through a principal component analysis method, such as: PCA analysis is performed through the Scikit-learn library in Python to find out the key indicators that have a greater impact on the test results, that is, the key test elements; the determination of the operation test process corresponding to the storage chip to be tested can be achieved through a Petri net modeling method, such as: using CPN The Tools software establishes a Petri net model for storage chip testing, and optimizes and determines the operation test process through model reachability analysis and simulation; the generation of test operation instructions corresponding to the storage chip to be tested can be implemented through a scripting language tool, such as: for the read and write function test of the storage chip, use Python's unittest framework to write specific test cases and operation instructions, and finally obtain the test operation instructions.

[0074] S5. After applying the test operation instruction to the memory chip to be tested, perform a packaging test operation on the memory chip to be tested to obtain a packaging test chip, collect electrical performance data corresponding to the packaging test chip, and perform stability verification on the electrical performance data to obtain verification result data; based on the verification result data, generate a packaging test report corresponding to the memory chip to be tested.

[0075] The present invention applies the test operation instruction to the memory chip to be tested, and then performs a packaging test operation on the memory chip to be tested to obtain a packaged test chip. This can effectively ensure the packaging quality of the memory chip, and can accurately detect problems that may occur during the chip packaging process, such as poor pin connection, poor packaging sealing, etc., so as to make timely improvements and enhance the overall stability of the chip.

[0076] Among them, the packaged test chip refers to a chip product that has been transformed from a bare chip to a complete physical form and has undergone comprehensive performance testing after packaging and testing operations. After the chip is manufactured, it is first packaged in a specific shell, which not only protects the internal circuit of the chip, but also provides electrical connection and physical support for the chip. Subsequently, according to strict test operation instructions, it is subjected to a full range of performance tests, covering electrical performance, mechanical performance, environmental adaptability and other aspects. Optionally, the application of the test operation instructions to the memory chip to be tested can be achieved through automated testing equipment, such as: importing the written test operation instructions into the ATE system, and then connecting the ATE to the interface of the memory chip to be tested, and automatically testing the chip according to the instructions; the execution of the packaged test operation on the memory chip to be tested can be achieved through a packaged test platform, such as: placing the memory chip to be tested on a test fixture, monitoring the temperature, pressure, humidity and other parameters of the chip in the packaging process in real time through sensors, and comparing and analyzing them with preset standard values, and finally obtaining a packaged test chip.

[0077] Furthermore, the present invention collects electrical performance data corresponding to the packaged test chip and verifies the stability of the electrical performance data to obtain verification result data, which can timely discover potential problems in the electrical performance of the chip, such as voltage fluctuation, current instability, etc., and the verification result data provides a key basis for evaluating whether the chip meets the use standards, ensuring that the chips put into use have stable and reliable electrical performance and reducing the risk of failure in actual applications.

[0078] Among them, the electrical performance data refers to a set of key parameters that characterize the electrical characteristics of the packaged test chip, covering values ​​such as resistance, capacitance, inductance, voltage, current, signal transmission delay, frequency response, etc., reflecting the electrical performance of the chip under different working conditions; the verification result data refers to the analysis results obtained after the stability verification of the electrical performance data, including stability assessment conclusions, data fluctuation range, abnormal data records, and comparisons with standards. Optionally, the collection of electrical performance data corresponding to the packaged test chip can be achieved through electrical testing instruments, such as: taking an oscilloscope as an example, connecting the probe to the relevant pins of the packaged test chip, setting a suitable sampling frequency and time range, and collecting the voltage, current, signal waveform and other data of the chip under different working conditions to finally obtain electrical performance data; the stability verification of the electrical performance data can be achieved through SPC tools, such as: drawing a control chart, and judging the stability of the electrical performance data by observing whether the data points in the control chart exceed the control limits and whether there are abnormal fluctuation trends, and finally obtaining verification result data.

[0079] Furthermore, the present invention generates a packaging test report corresponding to the memory chip to be tested based on the verification result data, providing a comprehensive and objective evaluation record for the packaging quality and performance of the chip, facilitating a clear understanding of the actual situation of the chip. The report can serve as an important basis for quality control, helping to promptly discover problems and trace causes during the production process, and take effective improvement measures to improve product quality.

[0080] Among them, the packaging test report refers to a detailed record and summary document of the packaging test process and results of the memory chip, which covers the basic information of the chip, including model, specifications, etc.; lists the test items in detail, such as electrical performance, mechanical performance, environmental adaptability and other test contents; focuses on presenting the verification result data, such as the stability assessment conclusion of the electrical performance data, the specific values ​​of various performance indicators and the comparison with the standards; it will also give a comprehensive evaluation to determine whether the chip has passed the test, and if it has not passed, point out the existing problems and improvement suggestions. Optionally, the generation of the packaging test report corresponding to the memory chip to be tested can be achieved through a report generation tool, such as: entering the verification result data and related test information (such as test items, test methods, test equipment, etc.) into the TestRail system, and the system will automatically generate a packaging test report with a standard format according to a preset template.

[0081] Compared with the problems described in the background technology, the present invention obtains the original parameter information corresponding to the memory chip to be tested and collects the packaging structure data in the original parameter information, which helps to deeply understand the internal structure and physical characteristics of the chip, provides a basic basis for subsequent performance evaluation, and can accurately determine whether the chip meets specific design and production standards to ensure product quality. The present invention compares and analyzes the chip feature data with the reference data of the standard memory chip to obtain difference analysis data, which can accurately locate the deviation of the chip in performance, structure, etc., provide a clear direction for quality control, and help to screen out unqualified products in a timely manner. Furthermore, based on the sensitivity value, the present invention evaluates the type of failure risk that may occur in the memory chip to be tested, and can predict the possible type of failure in advance. type, providing a clear direction for preventive maintenance, reducing the probability of sudden failures of the chip in actual use, and improving the stability of the system. Furthermore, based on the specific problem points, the present invention formulates the test planning goals corresponding to the memory chip to be tested, which can achieve precise focus on the test, avoid waste of resources and time consumption caused by blind comprehensive testing, and improve the quality and reliability of the memory chip. Finally, the present invention applies the test operation instructions to the memory chip to be tested, performs a packaging test operation on the memory chip to be tested, and obtains a packaging test chip, which can effectively guarantee the packaging quality of the memory chip, and can accurately detect problems that may occur in the chip packaging process, such as poor pin connection, poor packaging sealing, etc., so as to make timely improvements and improve the overall stability of the chip. Therefore, the high-reliability memory chip packaging test method and system provided by the embodiment of the present invention can improve the stability of the memory chip.

[0082] Embodiment 2: like Figure 2 FIG. 1 is a functional module diagram of a high-reliability memory chip packaging and testing system of the present invention.

[0083] The high reliability memory chip packaging and testing system 200 of the present invention can be installed in an electronic device. According to the functions to be implemented, the high reliability memory chip packaging and testing system can include a feature extraction module 201, a sensitivity calculation module 202, a problem search module 203, an instruction generation module 204 and a report generation module 205. The module of the present invention can also be called a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0084] In the embodiment of the present invention, the functions of each module / unit are as follows: The feature extraction module 201 is used to obtain original parameter information corresponding to the memory chip to be tested, collect package structure data in the original parameter information, build a three-dimensional model corresponding to the memory chip to be tested based on the package structure data, and perform feature extraction on the three-dimensional model to obtain chip feature data; The sensitivity calculation module 202 is used to compare and analyze the chip feature data with the reference data of the standard memory chip to obtain difference analysis data, mine the potential defect information in the difference analysis data, screen the suspicious packaging parts corresponding to the potential defect information, and monitor the real-time working environment parameters of the memory chip to be tested in real time to calculate the sensitivity value of the suspicious packaging parts affected by the environmental parameters; The problem finding module 203 is used to evaluate the possible fault risk type of the memory chip to be tested based on the sensitivity value, locate the weak link in the package of the memory chip to be tested based on the fault risk type, perform performance detection on the weak link, obtain the link performance status, and find the specific problem point in the link performance status; The instruction generation module 204 is used to formulate a test planning target corresponding to the memory chip to be tested based on the specific problem point, analyze the test means in the test planning target, and query the test standard corresponding to the test means, and generate a test operation instruction corresponding to the memory chip to be tested based on the test standard; The report generation module 205 is used to apply the test operation instruction to the memory chip to be tested, perform a packaging test operation on the memory chip to be tested, obtain a packaging test chip, collect electrical performance data corresponding to the packaging test chip, and perform stability verification on the electrical performance data to obtain verification result data, and generate a packaging test report corresponding to the memory chip to be tested based on the verification result data.

[0085] In detail, each module in the high reliability memory chip packaging and testing system 200 of the embodiment of the present invention is used in the same manner as described above. Figure 1 The high-reliability memory chip packaging and testing method described in the present invention has the same technical means and can produce the same technical effects, so it will not be repeated here.

[0086] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A high reliability memory chip packaging test method, characterized in that: The method comprises: Acquire original parameter information corresponding to the memory chip to be tested, collect package structure data in the original parameter information, construct a three-dimensional model corresponding to the memory chip to be tested based on the package structure data, perform feature extraction on the three-dimensional model, and obtain chip feature data; Compare and analyze the chip feature data with reference data of a standard memory chip to obtain difference analysis data, mine potential defect information in the difference analysis data, screen suspicious packaging parts corresponding to the potential defect information, and monitor the real-time working environment parameters of the memory chip to be tested in real time to calculate the sensitivity value of the suspicious packaging parts affected by the environmental parameters; Based on the sensitivity value, evaluate the possible fault risk type of the memory chip to be tested, locate the weak link in the package of the memory chip to be tested based on the fault risk type, perform performance detection on the weak link, obtain the link performance status, and find the specific problem point in the link performance status; Based on the specific problem points, formulate a test planning target corresponding to the memory chip to be tested, analyze the test means in the test planning target, and query the test standard corresponding to the test means, and generate a test operation instruction corresponding to the memory chip to be tested based on the test standard; After applying the test operation instruction to the memory chip to be tested, a packaging test operation is performed on the memory chip to be tested to obtain a packaging test chip, electrical performance data corresponding to the packaging test chip is collected, and stability verification is performed on the electrical performance data to obtain verification result data, and based on the verification result data, a packaging test report corresponding to the memory chip to be tested is generated.

2. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The step of extracting features from the three-dimensional model to obtain chip feature data includes: Identifying contour edge lines corresponding to internal structures in the three-dimensional model; Performing grid processing on the contour edge lines to obtain regular grid units; Analyzing the connection relationship between adjacent grids of the regular grid unit; Based on the connection relationship, determining the topological structure point corresponding to the three-dimensional model; Based on the topological structure points, feature extraction is performed on the three-dimensional model to obtain chip feature data.

3. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The step of comparing and analyzing the chip characteristic data with reference data of a standard memory chip to obtain difference analysis data includes: Determine the data dimension corresponding to the chip characteristic data and the reference data of the standard memory chip; Based on the data dimension, calculating the absolute difference between the chip characteristic data and the reference data of the standard memory chip; Performing data statistics on the absolute differences to obtain a difference statistics set; Based on a preset threshold range, dividing the data threshold points in the difference statistical set; Based on the data threshold point, the chip characteristic data is compared and analyzed with reference data of a standard memory chip to obtain difference analysis data.

4. The high reliability memory chip packaging and testing method according to claim 3, characterized in that: The step of calculating the absolute difference between the chip feature data and reference data of a standard memory chip based on the data dimension includes: The absolute difference between the chip characteristic data and the reference data of the standard memory chip is calculated using the following formula: in, represents the absolute difference between the chip characteristic data and the reference data of the standard memory chip, Indicates the total number corresponding to the data dimension, Indicates the quantity index corresponding to the data dimension, Indicated in The characteristic data value corresponding to the chip characteristic data in the data dimension, Indicated in The reference data value corresponding to the standard storage chip in the data dimension is: Indicates The importance coefficient corresponding to each data dimension.

5. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The calculating the sensitivity value of the suspicious packaging part affected by the environmental parameters includes: The following formula is used to calculate the sensitivity value of the suspected packaging part affected by the environmental parameters: in, Indicates the sensitivity value of the suspected packaging part affected by environmental parameters, Indicates the number of types corresponding to environmental parameters, Indicates the quantity index corresponding to the environmental parameters, Indicates The range of change corresponding to the environmental parameters, Indicates The weight coefficient of the influence of various environmental parameters on the suspicious packaging parts, and Respectively represent the start time and end time of the evaluation period, Indicates at time The performance change function corresponding to the suspicious packaging part at the moment.

6. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The locating the weak link in the memory chip package to be tested based on the failure risk type includes: Analyze the factor impact weights corresponding to the fault risk factors in the fault risk type; Based on the factor influence weights, the fault risk factors are sorted to obtain a risk factor sequence; Constructing a correlation map between the risk factor sequence and the packaging components corresponding to the memory chip to be tested; Filtering strongly associated nodes in the association graph; Based on the strongly associated nodes, weak links in the memory chip package to be tested are located.

7. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The step of searching for specific problem points in the performance status of the link includes: Analyze the status performance indicators corresponding to the performance status of the link; Constructing a mapping relationship framework corresponding to the state performance indicators; Based on the mapping relationship framework, analyzing the preliminary classification problems corresponding to the performance status of the links; Collect historical case data corresponding to the preliminary classification questions; Based on the historical case data, find the specific problem points in the performance status of the link.

8. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The formulating of a test planning target corresponding to the memory chip to be tested based on the specific problem point includes: Analyzing the relationship characteristics between the specific problem points and the functional modules in the memory chip to be tested; Based on the relationship characteristics, identifying the module impact degree corresponding to the functional module in the memory chip to be tested; Performing hierarchical processing on the impact degree of the modules to obtain hierarchical results; According to the stratification results, determine the functional module scope corresponding to the key test; Based on the functional module scope, a test planning target corresponding to the memory chip to be tested is formulated.

9. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The step of generating a test operation instruction corresponding to the memory chip to be tested based on the test standard includes: Analyze the project terms and conditions corresponding to the test standards; Based on the project terms and conditions, sort out the project test phases corresponding to the memory chip to be tested; Extract key test elements in the testing phase of the project; Based on the key test elements, determining the operation test process corresponding to the memory chip to be tested; Based on the operation test process, a test operation instruction corresponding to the memory chip to be tested is generated.

10. A high reliability memory chip packaging and testing system, characterized in that: The system comprises: A feature extraction module is used to obtain original parameter information corresponding to the memory chip to be tested, collect package structure data in the original parameter information, construct a three-dimensional model corresponding to the memory chip to be tested based on the package structure data, and perform feature extraction on the three-dimensional model to obtain chip feature data; A sensitivity calculation module is used to compare and analyze the chip feature data with the reference data of the standard memory chip to obtain difference analysis data, mine potential defect information in the difference analysis data, screen suspicious packaging parts corresponding to the potential defect information, and monitor the real-time working environment parameters of the memory chip to be tested in real time to calculate the sensitivity value of the suspicious packaging parts affected by the environmental parameters; A problem finding module is used to evaluate the possible fault risk type of the memory chip to be tested based on the sensitivity value, locate the weak link in the package of the memory chip to be tested based on the fault risk type, perform performance detection on the weak link, obtain the link performance status, and find the specific problem point in the link performance status; An instruction generation module is used to formulate a test planning target corresponding to the memory chip to be tested based on the specific problem point, analyze the test means in the test planning target, and query the test standard corresponding to the test means, and generate a test operation instruction corresponding to the memory chip to be tested based on the test standard; A report generation module is used to apply the test operation instruction to the memory chip to be tested, perform a packaging test operation on the memory chip to be tested, obtain a packaging test chip, collect electrical performance data corresponding to the packaging test chip, and perform stability verification on the electrical performance data to obtain verification result data, and generate a packaging test report corresponding to the memory chip to be tested based on the verification result data.

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