Manufacturing method of semiconductor element mounting package substrate

Abstract

A method for manufacturing a package substrate for mounting a semiconductor element, which includes an insulating layer and a wiring conductor provided on the insulating layer, includes the following steps: (a) forming a laminate in which a first metal layer, a first insulating resin layer, and a second metal layer, each having a thickness of 1 μm to 70 μm and capable of being peeled from the core resin layer, are arranged on both sides of a core resin layer having a thickness of 1 μm to 80 μm, and the laminate is heated and pressurized all at once to form a first substrate; (b) patterning forming a pattern on the second metal layer of the first substrate; (c) forming a second substrate by heating and pressurizing a laminate formed by arranging a second insulating resin layer and a third metal layer on the surface of the second metal layer of the first substrate; and (d) peeling off a third substrate comprising the first metal layer, the first insulating resin layer, the second metal layer, the second insulating resin layer, and the third metal layer from the core resin layer.

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a package substrate for mounting a semiconductor element. [Background technology]

[0002] In recent years, the trend toward high functionality and miniaturization of semiconductor packages, which are widely used in electronic devices, communication devices, personal computers, etc., has been accelerating. Accordingly, there is a demand for thinner printed wiring boards and package substrates for mounting semiconductor elements in semiconductor packages. Usually, printed wiring boards and package substrates for mounting semiconductor elements are fabricated by laminating a layer that will become a circuit pattern (hereinafter also simply referred to as "wiring conductor") and an insulating material on a support substrate.

[0003] As a manufacturing method of such a package substrate for mounting a semiconductor element, for example, a method has been disclosed in which a circuit-forming substrate made of an ultra-thin copper foil with a carrier foil having a first insulating resin provided on the carrier foil surface is used, a first wiring conductor is formed by pattern electrolytic copper plating, a second insulating resin is further laminated, and then a second wiring conductor is formed (see, for example, Patent Document 1 below). Also disclosed is a manufacturing technique for a printed wiring board using a laminate consisting of a resin plate-shaped carrier and a metal foil releasably adhered to at least one surface of the carrier (see, for example, Patent Document 2 below). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2005-101137 A [Patent Document 2] International Publication No. WO2014 / 046291 Summary of the Invention [Problem to be solved by the invention]

[0005] As a method for manufacturing a package substrate for mounting a semiconductor element, a method using a circuit-forming substrate formed by building up an insulating layer such as prepreg and a metal foil on both sides of a copper-clad laminate with a core resin layer as a core, is known. When the circuit-forming substrate has four layers of metal foil, it is also called a "four-layer coreless shield plate." For example, the four-layer coreless shield plate is then subjected to a patterning process or the like to become a six-layer coreless shield plate, and each substrate (laminate) provided on both sides of the core resin layer is peeled off.

[0006] Generally, in a manufacturing method of a circuit-forming substrate, a metal layer is placed on both sides of a core resin layer, and then a first pressing step is performed by applying heat and pressure to form a copper-clad laminate, and then a resin layer, etc. is laminated and then a second pressing step is performed to form the circuit-forming substrate. In response to this, with the development of alignment and pressing technologies, etc., the formation of circuit-forming boards in one go is being considered from the perspective of reducing the number of processes. When forming circuit-forming boards in one go, the first pressing process for forming the copper-clad laminate is omitted, and only the second pressing process is carried out to form the circuit-forming board.

[0007] In this way, when the circuit-forming substrate is formed in a lump, one pressing step can be omitted, and the manufacturing efficiency of the circuit-forming substrate and the semiconductor element-mounting package substrate using the same can be improved. However, when the circuit-forming substrate is produced in a lump, when each substrate provided on both sides of the core resin layer is peeled off from the core resin layer, wrinkles or unevenness may occur on the metal foil on the peeled core resin layer side. The wrinkled or uneven metal foil causes patterning defects, and as a result, when the circuit-forming substrate is formed in a lump, the yield of the semiconductor element-mounting package substrate may be reduced.

[0008] SUMMARY OF THE PRESENT DISCLOSURE In order to solve the above problems, an object of the present invention is to provide a method for manufacturing a package substrate for mounting semiconductor elements, which has high production efficiency and excellent yield. [Means for solving the problem]

[0009] <1> A method for manufacturing a package substrate for mounting a semiconductor element, the method comprising the steps of: a first substrate forming step (a) of forming a laminate in which a first metal layer having a thickness of 1 μm to 70 μm and peelable from the core resin layer, a first insulating resin layer, and a second metal layer are arranged in this order on both sides of a core resin layer having a thickness of 1 μm to 80 μm, and the laminate is heated and pressurized all at once to form a first substrate; A patterning step (b) of forming a pattern on the second metal layer of the first substrate; a second substrate forming step (c) of forming a second substrate by heating and pressurizing a laminate formed by arranging a second insulating resin layer and a third metal layer in this order on the surface of the second metal layer of the first substrate; a peeling step (d) of peeling a third substrate having the first metal layer, the first insulating resin layer, the second metal layer, the second insulating resin layer, and the third metal layer in this order from the core resin layer; A method for manufacturing a package substrate for mounting a semiconductor element, comprising: <2> The method further includes a wiring conductor forming step (e) of forming a non-through hole on the surface of the third substrate, the non-through hole reaching the surface of the second metal layer, applying electrolytic copper plating and / or electroless copper plating to the inner wall of the non-through hole, connecting the second metal layer to each of the first metal layer and the third metal layer, forming a fourth metal layer on the surface of the third substrate, and forming a pattern on the fourth metal layer to form the wiring conductor. <1> 2. A method for manufacturing the package substrate for mounting a semiconductor element according to claim 1 . <3> The third substrate has a thickness of 5 μm to 100 μm. <1> or <2> 2. A method for manufacturing the package substrate for mounting a semiconductor element according to claim 1 . <4> The first metal layer has a release layer, and the laminate is disposed so that the release layer and the core resin layer are in contact with each other. <1> ~ <3> 2. A method for producing a package substrate for mounting a semiconductor element according to claim 1 , <5> the third metal layer includes a carrier layer, and after the first substrate is heated and pressed in the second substrate forming step (c), the carrier layer is removed from the third metal layer; <1> ~ <4> 2. A method for producing a package substrate for mounting a semiconductor element according to claim 1 , <6> At least one of the first metal layer, the second metal layer, and the third metal layer is a copper foil. <1> ~ <5> 2. A method for producing a package substrate for mounting a semiconductor element according to claim 1 , <7> At least one of the core resin layer, the first insulating resin layer, and the second insulating resin layer is a prepreg in which a base material is impregnated with a resin. <1> ~ <6> 2. A method for producing a package substrate for mounting a semiconductor element according to claim 1 , Effect of the Invention

[0010] According to the present invention, it is possible to provide a method for manufacturing a package substrate for mounting semiconductor elements, which has high production efficiency and excellent yield. [Brief description of the drawings]

[0011] [Figure 1] 1A to 1C are schematic diagrams illustrating an embodiment of a method for manufacturing a package substrate for mounting a semiconductor element according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the present invention will be described by way of an embodiment, but the aspects of the present invention are not limited to the embodiment described below.

[0013] The method for manufacturing a package substrate for mounting a semiconductor element according to the present embodiment (hereinafter, sometimes simply referred to as the "manufacturing method according to the present embodiment") is as follows: A method for manufacturing a package substrate for mounting a semiconductor element, the method comprising the steps of: a first substrate forming step (a) of forming a laminate in which a first metal layer having a thickness of 1 μm to 70 μm and peelable from the core resin layer, a first insulating resin layer, and a second metal layer are arranged in this order on both sides of a core resin layer having a thickness of 1 μm to 80 μm, and the laminate is heated and pressurized all at once to form a first substrate; A patterning step (b) of forming a pattern on the second metal layer of the first substrate; a second substrate forming step (c) of forming a second substrate by heating and pressurizing a laminate formed by arranging a second insulating resin layer and a third metal layer in this order on the surface of the second metal layer of the first substrate; a peeling step (d) of peeling a third substrate having the first metal layer, the first insulating resin layer, the second metal layer, the second insulating resin layer, and the third metal layer in this order from the core resin layer; Includes.

[0014] In the manufacturing method of the package substrate for mounting a semiconductor element of this embodiment, a laminate is formed on both sides of a core resin layer having a thickness of 1 μm to 80 μm, in which a first metal layer having a thickness of 1 μm to 70 μm and peelable from the core resin layer, a first insulating resin layer, and a second metal layer are arranged in this order, and the laminate is heated and pressed all at once to form a first substrate. The first substrate corresponds to a substrate for forming a circuit. Here, the "substrate for forming a circuit" refers to a laminate including a core resin layer, a metal foil, and a resin layer, and means a state in which the metal foil is not patterned. In the manufacturing method of this embodiment, the first substrate (substrate for forming a circuit) is formed all at once. Here, "forming the first substrate (substrate for forming a circuit) in one go" means that in the first substrate forming process (a), a core resin layer is placed at the center, and on both sides of the core resin layer, a first metal layer, a first insulating resin layer, and a second metal layer are arranged in that order, and then the layers are heated and pressurized (a pressing process is performed) to form the first substrate (substrate for forming a circuit). This means that the pressing process for forming a copper-clad laminate (a state in which only the first metal layer is laminated on both sides of the core resin layer) is omitted, and the first substrate is formed by performing a single pressing process.

[0015] Furthermore, the manufacturing method of this embodiment uses a core resin layer having a thickness of 1 μm to 80 μm. That is, by using a core resin layer having a thickness of 1 μm to 80 μm, the manufacturing method of this embodiment can suppress the occurrence of wrinkles and unevenness in the metal layer on the core resin layer side of the substrate (third substrate) peeled from the core resin layer in the peeling step (d) even if the first substrate (substrate for forming a circuit) is formed in a lump. Therefore, the manufacturing method of this embodiment can improve the yield of package substrates for mounting semiconductor elements because the production efficiency is increased by forming the first substrate (substrate for forming a circuit) in a lump, and furthermore, the occurrence of wrinkles and unevenness in the metal layer that causes patterning defects is suppressed. The manufacturing method of this embodiment will be described in detail below.

[0016] [First substrate formation step (a)] The first substrate forming step (a) is a step of forming a laminate in which a first metal layer having a thickness of 1 μm to 70 μm and peelable from the core resin layer, a first insulating resin layer, and a second metal layer are arranged in this order on both sides of a core resin layer having a thickness of 1 μm to 80 μm, and the laminate is heated and pressed all at once to form a first substrate. The configuration of the first substrate (substrate for forming a circuit) will be described with reference to FIG. 1. FIG. 1 is a schematic diagram for explaining one embodiment of a method for manufacturing a package substrate for mounting a semiconductor element of the present invention. As shown in FIG. 1(A) and FIG. 1(B), the substrate for forming a circuit (first substrate) 1 has a core resin layer 2 (e.g., a prepreg) on ​​both sides thereof, and a first metal layer 3, a first insulating resin layer 4, and a second metal layer are provided in this order from the surface side of the core resin layer 2.

[0017] In the first substrate forming step (a), a first metal layer, a first insulating resin layer, and a second metal layer are arranged in this order on both sides of a core resin layer to form a laminate, which is then heated and pressed to form a first substrate. At this time, a pressing step for forming a copper-clad laminate (a state in which only the first metal layer is laminated on both sides of the core resin layer) is not performed, and the first substrate is formed by performing a single pressing step after laminating the first insulating resin layer and the second metal layer. The lamination method and conditions for forming the laminate are not particularly limited, but for example, the laminate can be vacuum pressed under conditions of a temperature of 220±2°C, a pressure of 5±0.2 MPa, and a holding time of 60 minutes to form a first substrate. In addition, in order to obtain adhesion between each metal layer and the core resin layer or each insulating resin layer, a roughening treatment may be applied to the surface of each metal layer. The roughening treatment is not particularly limited, and known means can be used as appropriate, for example, a means using a copper surface roughening liquid can be mentioned.

[0018] (Core resin layer) The core resin layer in the first substrate formation process (a) is not particularly limited, but may be, for example, a prepreg in which a base material such as glass cloth is impregnated with an insulating resin material (insulating material) such as a thermosetting resin, or an insulating film material. The thickness of the core resin layer is 1 μm to 80 μm. If the thickness of the core resin layer is less than 1 μm, molding defects of the resin occur, and if it exceeds 80 μm, when the first substrate is formed in one go, wrinkles and unevenness occur in the metal layer on the surface of the third substrate peeled off from the core resin layer after the peeling step. From the viewpoint of laminate moldability, the thickness of the core resin layer is preferably 3 μm to 40 μm, and more preferably 10 μm to 25 μm.

[0019] A "prepreg" is a material obtained by impregnating or coating a substrate with an insulating material such as a resin composition. The substrate is not particularly limited, and any well-known substrate used in various laminates for electrical insulating materials can be used as appropriate. Materials constituting the substrate include, for example, inorganic fibers such as E glass, D glass, S glass, or Q glass; organic fibers such as polyimide, polyester, or tetrafluoroethylene; and mixtures thereof. The substrate is not particularly limited, and may be, for example, a woven fabric, nonwoven fabric, roving, chopped strand mat, surfacing mat, or other shape. The material and shape of the substrate are selected according to the intended use and performance of the molded product, and one or more types of materials and shapes can be used as necessary.

[0020] The thickness of the substrate is not particularly limited as long as the thickness of the core resin layer is in the range of 1 μm to 80 μm, but usually, a substrate having a thickness of 10 μm to 30 μm can be used. In addition, the substrate can be surface-treated with a silane coupling agent or mechanically opened, and these substrates are suitable in terms of heat resistance, moisture resistance, and processability.

[0021] The insulating material is not particularly limited, and a known resin composition used as an insulating material for printed wiring boards can be appropriately selected and used. The resin composition can be based on a thermosetting resin having good heat resistance and chemical resistance. The thermosetting resin is not particularly limited, but examples thereof include phenol resin, epoxy resin, cyanate resin, maleimide resin, isocyanate resin, benzocyclobutene resin, vinyl resin, etc. The thermosetting resin may be used alone or in combination of two or more types.

[0022] Among thermosetting resins, epoxy resins are excellent in heat resistance, chemical resistance, and electrical properties, and are relatively inexpensive, so they can be suitably used as insulating materials. Examples of epoxy resins include bisphenol A type epoxy resins, bisphenol F type epoxy resins, bisphenol S type epoxy resins, alicyclic epoxy resins, aliphatic chain epoxy resins, phenol novolac type epoxy resins, cresol novolac type epoxy resins, bisphenol A novolac type epoxy resins, diglycidyl ethers of biphenols, diglycidyl ethers of naphthalene diols, diglycidyl ethers of phenols, diglycidyl ethers of alcohols, and alkyl-substituted, halogenated, and hydrogenated versions of these. One type of epoxy resin may be used alone, or two or more types may be mixed together. The curing agent used together with this epoxy resin can be any agent capable of curing the epoxy resin, and examples of such agents include polyfunctional phenols, polyfunctional alcohols, amines, imidazole compounds, acid anhydrides, organic phosphorus compounds, and halides thereof. These epoxy resin curing agents may be used alone or in combination of two or more.

[0023] The cyanate resin is a resin that generates a cured product having a triazine ring as a repeating unit by heating, and the cured product has excellent dielectric properties. Therefore, it is suitable for cases where high frequency properties are particularly required. The cyanate resin is not particularly limited, but examples thereof include 2,2-bis(4-cyanatophenyl)propane, bis(4-cyanatophenyl)ethane, 2,2-bis(3,5dimethyl-4-cyanatophenyl)methane, 2,2-(4-cyanatophenyl)-1,1,1,3,3,3-hexafluoropropane, α,α'-bis(4-cyanatophenyl)-m-diisopropylbenzene, cyanate esters of phenol novolac and alkylphenol novolac, and the like. Among them, 2,2-bis(4-cyanatophenyl)propane is preferable because it has a particularly good balance between the dielectric properties and curability of the cured product and is inexpensive. These cyanate resins such as cyanate ester compounds may be used alone or in combination of two or more. In addition, the cyanate ester compounds may be partially oligomerized in advance to a trimer or a pentamer.

[0024] Furthermore, a curing catalyst or a curing accelerator can be used in combination with the cyanate resin. As the curing catalyst, for example, metals such as manganese, iron, cobalt, nickel, copper, zinc, etc. can be used, and specifically, organic metal salts such as 2-ethylhexanoate and octylate, and organic metal complexes such as acetylacetone complex can be mentioned. The curing catalyst may be used alone or in combination of two or more kinds. As the curing accelerator, it is preferable to use phenols, and it is possible to use monofunctional phenols such as nonylphenol and paracumylphenol, bifunctional phenols such as bisphenol A, bisphenol F and bisphenol S, and polyfunctional phenols such as phenol novolac and cresol novolac. One type of curing accelerator may be used alone, or two or more types may be mixed and used.

[0025] The resin composition used as the insulating material may be blended with a thermoplastic resin in consideration of dielectric properties, impact resistance, film processability, etc. The thermoplastic resin is not particularly limited, but examples thereof include fluororesin, polyphenylene ether, modified polyphenylene ether, polyphenylene sulfide, polymethyl ether, polyetherimide, polyetheretherketone, polyacrylate, polyamide, polyamideimide, polybutadiene, etc. The thermoplastic resin may be used alone or in combination of two or more types.

[0026] Among thermoplastic resins, polyphenylene ether and modified polyphenylene ether are useful in terms of improving the dielectric properties of the cured product. Examples of polyphenylene ether and modified polyphenylene ether include poly(2,6-dimethyl-1,4-phenylene) ether, an alloy polymer of poly(2,6-dimethyl-1,4-phenylene) ether and polystyrene, an alloy polymer of poly(2,6-dimethyl-1,4-phenylene) ether and styrene-butadiene copolymer, an alloy polymer of poly(2,6-dimethyl-1,4-phenylene) ether and styrene-maleic anhydride copolymer, an alloy polymer of poly(3,6-dimethyl-1,4-phenylene) ether and polyamide, and an alloy polymer of poly(2,6-dimethyl-1,4-phenylene) ether and styrene-butadiene-acrylonitrile copolymer. In order to impart reactivity or polymerizability to the polyphenylene ether, a functional group such as an amine group, an epoxy group, a carboxyl group, or a styryl group may be introduced to a polymer chain end, or a functional group such as an amine group, an epoxy group, a carboxyl group, a styryl group, or a methacryl group may be introduced to a polymer chain side chain.

[0027] Among thermoplastic resins, polyamideimide resins are useful from the viewpoint of excellent moisture resistance and good adhesiveness to metals. The raw materials of polyamideimide resins are not particularly limited, but examples of acidic components include trimellitic anhydride and trimellitic anhydride monochloride, and examples of amine components include metaphenylenediamine, paraphenylenediamine, 4,4'-diaminodiphenyl ether, 4,4'-diaminodiphenylmethane, bis[4-(aminophenoxy)phenyl]sulfone, and 2,2'-bis[4-(4-aminophenoxy)phenyl]propane. The polyamideimide resin may be siloxane-modified to improve drying properties, and in this case, siloxane diamine can be used as the amino component. Considering film processability, it is preferable to use polyamideimide resins with a molecular weight of 50,000 or more.

[0028] Although the above-mentioned thermoplastic resins have been described as insulating materials mainly used for prepregs, the use of these thermoplastic resins is not limited to prepregs. For example, the above-mentioned thermoplastic resins processed into a film (film material) may be used as the core resin layer in the circuit-forming substrate.

[0029] The resin composition used as the insulating material may be mixed with an inorganic filler. The inorganic filler is not particularly limited, but examples thereof include alumina, aluminum hydroxide, magnesium hydroxide, clay, talc, antimony trioxide, antimony pentoxide, zinc oxide, fused silica, glass powder, quartz powder, and shirasu balloons. These inorganic fillers may be used alone or in combination of two or more.

[0030] The resin composition used as an insulating material may contain an organic solvent. The organic solvent is not particularly limited, and may be an aromatic hydrocarbon solvent such as benzene, toluene, xylene, or trimethylbenzene; a ketone solvent such as acetone, methyl ethyl ketone, or methyl isobutyl ketone; an ether solvent such as tetrahydrofuran; an alcohol solvent such as isopropanol or butanol; an ether alcohol solvent such as 2-methoxyethanol or 2-butoxyethanol; or an amide solvent such as N-methylpyrrolidone, N,N-dimethylformamide, or N,N-dimethylacetamide, if desired. The amount of the solvent in the varnish used to prepare the prepreg is preferably in the range of 40 to 80% by mass based on the entire resin composition. The viscosity of the varnish is preferably in the range of 20 to 100 cP (20 to 100 mPa·s).

[0031] The resin composition used as the insulating material may contain a flame retardant. The flame retardant is not particularly limited, but may be any of the known flame retardants such as bromine compounds such as decabromodiphenyl ether, tetrabromobisphenol A, tetrabromophthalic anhydride, and tribromophenol, phosphorus compounds such as triphenyl phosphate, trixylyl phosphate, and cresyl diphenyl phosphate, metal hydroxides such as magnesium hydroxide and aluminum hydroxide, red phosphorus and its modified products, antimony compounds such as antimony trioxide and antimony pentoxide, and triazine compounds such as melamine, cyanuric acid, and melamine cyanurate.

[0032] If necessary, the resin composition used as the insulating material may further contain the above-mentioned curing agent and curing accelerator, as well as various additives and fillers such as thermoplastic particles, colorants, ultraviolet opacifiers, antioxidants, and reducing agents.

[0033] In this embodiment, the prepreg can be obtained as a semi-cured (B-stage) prepreg by, for example, impregnating or coating a base material with a resin composition (including varnish) so that the amount of the resin composition adhering to the base material is 20 to 90 mass % in terms of the resin content in the dried prepreg, and then drying by heating for 1 to 30 minutes at a temperature of 100 to 200° C. As such a prepreg, for example, GHPL-830NSF series (product name) manufactured by Mitsubishi Gas Chemical Company can be used.

[0034] (First metal layer) The first metal layer is made of a metal foil having a thickness of 1 μm to 70 μm and capable of being peeled off from the core resin layer. If the thickness of the first metal layer is less than 1 μm, the first to third substrates will be poorly molded, and if it exceeds 70 μm, the surface will be defective. From the viewpoint of circuit formation, the thickness of the first metal layer is preferably 1 μm to 12 μm, and more preferably 2 μm to 5 μm.

[0035] As described later, the third substrate is peeled off from the interface between the core resin layer and the first metal layer in the peeling step. The surface roughness (10-point average roughness (Rzjis) shown in JIS B0601:2001) of the first metal layer when peeled off from the core resin layer in the peeling step is preferably 1 μm to 3 μm, more preferably 1 μm to 2 μm, and particularly preferably 1 μm to 1.5 μm, from the viewpoint of reducing peeling failure. The surface roughness of the first metal layer can be measured, for example, by cutting a sample to a size of 5×5 cm, and then measuring an area of ​​1×1 cm using a microscope VR-3100 (manufactured by Keyence Corporation).

[0036] The first metal layer may be, for example, a copper foil. The copper foil may be, for example, a peelable type. The "peelable type" copper foil is an extremely thin copper foil having a peelable layer, and the peelable layer is, for example, a peelable copper foil. When a peelable type copper foil is used, the first metal layer is laminated so that the peelable layer is in contact with the core resin layer.

[0037] The release layer may be, for example, a layer containing at least a silicon compound, and may be formed, for example, by applying a silicon compound consisting of a single or multiple combinations of silane compounds to a copper foil or an ultra-thin copper foil. The means for applying the silicon compound is not particularly limited, and for example, known means such as coating can be used. The bonding surface of the copper foil with the release layer may be subjected to a rust-proofing treatment (a rust-proofing layer may be formed). The rust-proofing treatment may be performed using nickel, tin, zinc, chromium, molybdenum, cobalt, or an alloy thereof.

[0038] The thickness of the release layer is not particularly limited, but from the viewpoint of removability and peelability, it is preferably 5 nm to 100 nm, more preferably 10 nm to 80 nm, and particularly preferably 20 nm to 60 nm.

[0039] (First insulating resin layer) The first insulating resin layer can be made of the same material as the core resin layer (e.g., prepreg). The thickness of the first insulating resin layer is not particularly limited since it is appropriately set according to the desire, but can be, for example, 10 μm to 100 μm, preferably 10 μm to 50 μm, and more preferably 10 μm to 30 μm.

[0040] (Second metal layer) The second metal layer may be made of the same material as the first metal layer (e.g., copper foil). The thickness of the second metal layer is not particularly limited since it is appropriately set according to the desire, but may be, for example, 2 μm to 70 μm, preferably 2 μm to 18 μm, and more preferably 2 μm to 12 μm. The second metal layer may be, for example, an ultra-thin copper foil with a carrier. In this case, the second metal layer is disposed so that the copper foil or the like is in contact with the second insulating resin layer, and the carrier is peeled off after the first substrate is formed by heating and pressing.

[0041] [Patterning process (b)] The patterning step (b) is a step of forming a pattern on the second metal layer of the above-mentioned first substrate (substrate for forming a circuit). Through the patterning step (b), a pattern is formed on the second metal layer 5 of the substrate for forming a circuit 1, as shown in FIG. 1(C). The means for forming the pattern of the second metal layer is not particularly limited, but it can be formed, for example, by the following steps.

[0042] The patterning step (b) is not particularly limited, but for example, the second metal layer is surface-treated, a dry film resist is laminated, and a negative mask is attached, after which a circuit pattern is printed using an exposure machine, and the dry film resist is developed using a developer to form an etching resist. Thereafter, an etching process is performed, and copper in the area without the etching resist is removed using an aqueous ferric chloride solution, and the resist is then removed, thereby forming a pattern on the second metal layer.

[0043] The resist is not particularly limited, and for example, a known resist such as a commercially available dry film resist can be appropriately selected and used. In addition, the photolithography (including exposure, development, and removal of the resist) for forming a pattern on the second metal layer is not particularly limited, and can be performed using known means and devices.

[0044] The pattern width of the second metal layer is not particularly limited and can be appropriately selected depending on the application, and can be, for example, 5 to 100 μm, and preferably 10 to 30 μm.

[0045] [Second substrate formation process (c)] The second substrate forming step (c) is a step of forming a second substrate by heating and pressurizing a laminate formed by arranging a second insulating resin layer and a third metal layer in this order on the surface of the second metal layer of the first substrate. Through the second substrate forming step (c), a second substrate 8 can be obtained in which a second insulating resin layer 6 and a third metal layer 7 are laminated on a second metal layer 5, as shown in FIG. 1(D).

[0046] (Second insulating resin layer) The second insulating resin layer can be made of the same material as the core resin layer (e.g., prepreg). The thickness of the second insulating resin layer is not particularly limited because it is appropriately set according to the need, but can be, for example, 10 μm to 100 μm, preferably 10 μm to 50 μm, and more preferably 10 μm to 30 μm.

[0047] (Third metal layer) The third metal layer may be made of the same material as the first metal layer (e.g., copper foil). The thickness of the third metal layer is not particularly limited since it is appropriately set according to the desire, but may be, for example, 2 μm to 70 μm, preferably 2 μm to 18 μm, and more preferably 2 μm to 5 μm. The third metal layer may be, for example, an ultra-thin copper foil with a carrier. In this case, the third metal layer is disposed so that the copper foil or the like is in contact with the second insulating resin layer, and the carrier is peeled off after the second substrate is formed by heating and pressing.

[0048] (Lamination method and conditions) The method and conditions for laminating the second insulating resin layer and the third metal layer to obtain the second substrate are not particularly limited, but for example, the second substrate can be formed by laminating the second insulating resin layer and the third metal layer on the first substrate, and then performing vacuum pressing under conditions of a temperature of 220±2° C., a pressure of 5±0.2 MPa, and a holding time of 60 minutes. In addition, in order to obtain adhesion between the second metal layer and the second insulating resin layer, the surface of the second metal layer may be subjected to a roughening treatment.

[0049] [Peeling process (d)] The peeling step (d) is a step of peeling off the third substrate having the first metal layer, the first insulating resin layer, the second metal layer, the second insulating resin layer, and the third metal layer in this order from the core resin layer. After the peeling step (d), as shown in FIG. 1(E), the second substrate is separated at the interface between the core resin layer 2 and the first metal layer 3 arranged on both sides thereof, to obtain two third substrates 9 having the first metal layer 3, the first insulating resin layer 4, the second metal layer 5, the second insulating resin layer 6, and the third metal layer 7 in this order. The thickness of the third substrate is not particularly limited since it is appropriately set according to desire, but can be, for example, 5 μm to 400 μm, preferably 5 μm to 200 μm, and more preferably 5 μm to 100 μm.

[0050] In the peeling step (d), it is preferable that the core resin layer is peeled off at the interface between the core resin layer and the first metal layer, but for example, when the first metal layer has a peeling layer, a part of it may be peeled off together with the core resin layer. Also included is an embodiment in which the core resin layer is peeled off together with the peeling layer at the interface between the peeling layer of the first metal layer and the copper foil. When the peeling layer remains on the first metal layer, for example, the peeling layer can be removed using a sulfuric acid-based or hydrogen peroxide-based etching solution. The sulfuric acid-based or hydrogen peroxide-based etching solution is not particularly limited, and one used in the industry can be used.

[0051] [Wiring conductor formation process (e)] The manufacturing method of this embodiment may further include a wiring conductor forming step (e) of forming a non-through hole on the surface of the third substrate, the non-through hole reaching the surface of the second metal layer, applying electrolytic copper plating and / or electroless copper plating to the inner wall of the non-through hole, connecting the second metal layer to each of the first metal layer and the third metal layer, forming a fourth metal layer on the surface of the third substrate, and forming a pattern on the fourth metal layer to form the wiring conductor. After the wiring conductor forming step (e), as shown in FIG. 1(I), a package substrate 12 for mounting a semiconductor element can be obtained in which wiring conductors 11 are formed on both sides of an insulating layer 10. The insulating layer 10 is composed of a first insulating resin layer 4 and a second insulating resin layer 6, and the wiring conductor 11 is formed by interlayer connection of the first metal layer 3, the second metal layer 5, and the third metal layer 7, which are patterned, by electrolytic copper plating and / or electroless copper plating.

[0052] (Formation of non-through holes) In the wiring conductor forming process (e), non-through holes reaching the surface of the second metal layer are formed on the surface of the third substrate. As shown in FIG. 1(F), non-through holes 13 are provided on both sides of the third substrate 9. That is, from the upper side of the paper in FIG. 1(F), non-through holes 13 are formed in the second insulating resin layer 6 via the third metal layer 7. Similarly, from the lower side of the paper in FIG. 1(F), non-through holes 13 are formed in the first insulating resin layer 4 via the first metal layer 3.

[0053] The means for forming the non-through holes is not particularly limited, and for example, known means such as a laser such as a carbon dioxide gas laser or a drill can be used. The number and size of the non-through holes can be appropriately selected as desired. After the non-through holes are formed, a desmear treatment can be performed using an aqueous solution of sodium permanganate or the like.

[0054] (Interlayer Connection and Formation of Fourth Metal Layer) In the wiring conductor forming step (e), as shown in FIG. 1(G), after forming the non-through hole 13, electrolytic copper plating and / or electroless copper plating are performed to form a copper plating film on the inner wall of the non-through hole 13, and the first metal layer 3, the second metal layer 5, and the third metal layer 7, which are patterned, are electrically connected. Furthermore, the thickness of the first and third metal layers on both sides of the third substrate is increased by the electrolytic copper plating and / or electroless copper plating, thereby forming a fourth metal layer 14. The method of performing the electrolytic copper plating and / or electroless plating is not particularly limited, and a known method can be adopted. The copper plating may be either electrolytic copper plating or electroless plating, but it is preferable to perform both electrolytic copper plating and electroless plating.

[0055] (Film thickness adjustment) In the wiring conductor formation process (e), as shown in FIG. 1(H), after the electrolytic / electroless copper plating process, if necessary, a known process such as an etching process can be performed so that the fourth metal layer 14 has a desired thickness, thereby adjusting the film thickness of the fourth metal layer 14. The thickness of the fourth substrate after adjustment is not particularly limited since it is appropriately set as desired, but can be, for example, 5 μm to 30 μm, preferably 5 μm to 20 μm, and more preferably 5 μm to 12 μm.

[0056] (Patterning) In the wiring conductor forming process (e), the surface of the fourth metal layer 14 is adjusted as necessary, then a dry film resist or the like is laminated, and a negative mask is attached, after which a circuit pattern is printed using an exposure machine, and the dry film resist is developed using a developer to form an etching resist. Then, an etching process is performed, and copper in the area without the etching resist is removed using an aqueous ferric chloride solution or the like, and the resist is then removed, whereby wiring conductors 11 can be formed on both sides of the insulating layer 10, as shown in FIG. 1(I).

[0057] Other interlayer connection methods that can be applied in this embodiment include a method in which chemical copper plating is applied to a known laser-formed blind via portion (a method in which a wiring circuit is formed by laser processing, and then patterning and interlayer connection are performed by chemical copper plating), a method in which a metal bump (preferably a copper bump) formed in advance by plating or etching a metal foil is used to pierce the insulating layer to perform interlayer connection, and a method in which a metal paste containing solder or a metal filler such as silver or copper in an insulating resin is bump-printed at predetermined locations by screen printing or the like, the paste is hardened by drying, and electrical conductivity between the inner and outer layers is ensured by heating and pressurization.

[0058] 1, which illustrates the present embodiment, the package substrate 12 for mounting a semiconductor element is a package substrate for mounting a semiconductor element having a three-layer structure, but the present invention is not limited thereto, and a package substrate for mounting a semiconductor element having a further build-up structure such as a five-layer structure can be formed. For example, in the wiring conductor forming step (e), after the wiring conductor is formed, an insulating resin layer and a metal layer are further laminated, and patterning and interlayer connection are repeatedly performed, thereby making it possible to manufacture a package substrate for mounting a semiconductor element having a build-up structure.

[0059] <<Method of manufacturing a package substrate for mounting semiconductor elements>> In the method for manufacturing a package substrate for mounting a semiconductor element of this embodiment, after the package substrate for a semiconductor element is formed as described above, a semiconductor element such as a bare chip can be mounted thereon as desired.

[0060] The semiconductor element is not particularly limited and a desired element can be used as appropriate. For example, a bare chip having gold bumps formed on aluminum electrodes by ball bonding of gold wires can be used. The semiconductor element can be mounted on the wiring conductor of the package substrate for mounting the semiconductor element via a bonding material. The bonding material is not particularly limited as long as it has a conductive means, and for example, solder (for example, solder balls, solder paste, etc.) can be used. In addition, after surface treatment is performed on the wiring conductor of the package substrate for mounting the semiconductor element, the semiconductor element can be mounted via the bonding material. The surface treatment is not particularly limited, and examples include the formation of a nickel layer or a gold plating layer. When solder is used as the bonding material, a process such as reflow can be performed after mounting the semiconductor element on the wiring conductor. At this time, the reflow temperature is appropriately selected depending on the melting point of the bonding material, and can be, for example, 260°C or higher. EXAMPLES

[0061] The production method of the present invention will now be described in detail with reference to examples.

[0062] [Comparative Example 1] A prepreg (core resin layer: thickness 0.087 mm: Mitsubishi Gas Chemical Company, GHPL-830NSF FX64) made by impregnating glass cloth (glass fiber) with bismaleimide triazine resin (BT resin) to bring it to the B stage was placed on both sides of the prepreg, and a copper foil (manufactured by JX Nippon Mining & Metals Corporation, product name: PCS) with a copper foil thickness of 2 μm and a release layer applied thereto was placed so that the release layer surface was adhered to the prepreg. Further, a 12 μm copper foil (manufactured by Mitsui Mining & Smelting Co., Ltd., product name: 3EC-VLP) made by impregnating glass cloth (glass fiber) with bismaleimide triazine resin (BT resin) to bring it to the B stage was laminated on top of the prepreg (thickness 0.025 mm: Mitsubishi Gas Chemical Company, GHPL-830NSF FF70) using a vacuum press under conditions of pressure 2.5 ± 0.2 MPa, temperature 220 ± 2 ° C, and holding time 60 minutes.

[0063] The obtained substrate surface was smoothed and then a dry film resist (product name: NIT225, manufactured by Nichigo-Morton Co., Ltd.) was laminated at a temperature of 110±10°C and a pressure of 0.50±0.02MPa. A negative mask was then attached, and a circuit pattern was printed using a parallel exposure machine. The dry film resist was developed using a 1% aqueous solution of sodium carbonate to form an etching resist, and the copper in the areas without the etching resist was removed using an aqueous solution of ferric chloride. The dry film resist was then removed using an aqueous solution of sodium hydroxide to form the circuit pattern.

[0064] The surface of the substrate on which the circuit pattern was formed was roughened using a copper surface roughening liquid (product name: CZ-8100, manufactured by MEC Co., Ltd.), and a prepreg (thickness: 0.025 mm: GHPL-830NSF FF70, manufactured by Mitsubishi Gas Chemical Co., Ltd.) made by impregnating bismaleimide triazine resin (BT resin) into glass cloth (glass fiber) to make it into the B stage was laminated on both sides of the substrate with a 2 μm copper foil with an 18 μm carrier copper foil (product name: MTEx, manufactured by Mitsui Mining & Smelting Co., Ltd.) using a vacuum press under conditions of a pressure of 2.5 ± 0.2 MPa, a temperature of 220 ± 2°C, and a holding time of 60 minutes, and then the 18 μm carrier copper foil was peeled off.

[0065] The obtained substrate was peeled off by applying physical force to the boundaries between the core resin layer, PCS, and copper foil. However, the copper foil surface at the peeled surface was uneven, which reduced the yield during laser processing and circuit formation.

[0066] [Example 1] <First substrate forming step (a)> A prepreg (core resin layer 2 in FIG. 1(A); thickness 25 μm: GHPL-830NSF FF70 manufactured by Mitsubishi Gas Chemical Co., Ltd.) made by impregnating bismaleimide triazine resin (BT resin) into glass cloth (glass fiber) to bring it to the B stage) was placed on both sides of a copper foil with a release layer (first metal layer 3 in FIG. 1(A)) in which a release layer (manufactured by JX Nippon Mining & Metals Corporation, product name: PCS) was applied to a copper foil thickness of 2 μm, so that the release layer surface was in contact with the core resin layer. Further on top of that, a prepreg (first insulating resin layer 4 in FIG. 1(A); thickness 0.025 mm: GHPL-830NSF FF70 manufactured by Mitsubishi Gas Chemical Co., Ltd.) made by impregnating bismaleimide triazine resin (BT resin) into glass cloth (glass fiber) to bring it to the B stage was placed on top of that. A 12 μm copper foil (second metal layer 5 in FIG. 1(A); manufactured by Mitsui Mining & Smelting Co., Ltd., product name: 3EC-VLP) was laminated on top of a 12 μm thick copper foil (FF70) using a vacuum press under conditions of a pressure of 2.5±0.2 MPa, a temperature of 220±2°C, and a holding time of 60 minutes to produce a first substrate (a circuit-forming substrate (first substrate) 1 in FIG. 1(B)).

[0067] <Patterning process (b)> Next, the surface of the first substrate was prepared, and a dry film resist (manufactured by Nichigo-Morton Co., Ltd., product name: NIT225) was laminated on the surface of the second metal layer at a temperature of 110±10°C and a pressure of 0.50±0.02MPa. Thereafter, a negative mask was attached, a circuit pattern was printed using a parallel exposure machine, and the dry film resist was developed using a 1% aqueous solution of sodium carbonate to form an etching resist. After removing the copper in the areas without the etching resist using an aqueous solution of ferric chloride, the dry film resist was removed using an aqueous solution of sodium hydroxide, and a pattern was formed on the second metal layer 5 (see FIG. 1(C)).

[0068] <Second substrate forming step (c)> Next, the surface of the patterned second metal layer 5 was roughened using a copper surface roughening liquid (manufactured by MEC Co., Ltd., product name: CZ-8100), and a prepreg (second insulating resin layer 6 in FIG. 1(D); thickness 0.025 mm: Mitsubishi Gas Chemical Co., Ltd. GHPL-830NSF FF70) was impregnated with bismaleimide triazine resin (BT resin) to form a B-stage prepreg on the surface of the second metal layer 5 provided on both sides of the circuit-forming substrate 1. A 2 μm copper foil with a carrier copper foil of 18 μm (third metal layer 7 in FIG. 1(D); manufactured by Mitsui Mining & Smelting Co., Ltd., product name: MTEx) was laminated by a vacuum press under conditions of pressure 2.5 ± 0.2 MPa, temperature 220 ± 2 ° C., and holding time 60 minutes. Thereafter, the 18 μm carrier copper foil was peeled off to produce a second substrate (second substrate 8 in FIG. 1(D)).

[0069] <Peeling process (d)> In the second substrate, physical force was applied to the boundary between the copper foil with the release layer (first metal layer 3) and the prepreg (core resin layer 2) to separate them, and a third substrate (third substrate 9 in FIG. 1(E)) was obtained. The unevenness of the copper foil surface on the peeled surface was measured by the following method. The unevenness of the copper foil surface on the peeled surface was 2.25 μm. The unevenness of the copper foil surface on the peeled side was measured. A microscope VR-3100 (Kinence Co., Ltd.) was used to measure the surface unevenness, and a 1 x 1 cm area was measured with the same device on a sample cut to 5 x 5 cm.

[0070] <Wiring conductor formation process (e)> A carbon dioxide laser processing machine (manufactured by Hitachi Via Mechanics, Ltd., product name: LC-1C / 21) was used to process one hole at a time on both sides of the third substrate under conditions of a beam irradiation diameter of Φ0.21 mm, a frequency of 500 Hz, and a pulse width of 10 μs, to form a non-through hole (non-through hole 13 in FIG. 1(F)) on both sides of the third substrate. Next, a desmear treatment was performed using a sodium permanganate aqueous solution having a concentration of 55±10 g / L at a temperature of 80±5° C. Further, after electroless copper plating to a thickness of 0.4 to 0.8 μm, electrolytic copper plating was performed to a thickness of 8 μm to form a fourth metal layer (fourth metal layer 14 in FIG. 1(G)). As a result, the first and third metal layers were electrically connected by non-penetrating holes via the second metal layer. Next, the surface of the fourth metal layer was smoothed, and a dry film resist (manufactured by Nichigo-Morton Co., Ltd., product name: NIT225) was laminated at a temperature of 110±10°C and a pressure of 0.50±0.02 MPa. Thereafter, a negative mask was attached, and a circuit pattern was baked using a parallel exposure machine, and the dry film resist was developed with a 1% sodium carbonate aqueous solution to form an etching resist, and the copper in the area without the etching resist was removed with a ferric chloride aqueous solution. Thereafter, the dry film resist was removed with an aqueous sodium hydroxide solution, and a pattern was formed on the fourth metal layer to produce a package substrate for mounting a semiconductor element (a package substrate 12 for mounting a semiconductor element in which wiring conductors 11 are formed on both sides of the insulating layer 10 in FIG. 1(I)).

[0071] The obtained package substrate for mounting a semiconductor element was subjected to a solder resist forming process and a gold plating finish, and was then cut to a package size to obtain the package substrate for mounting a semiconductor element of Example 1.

[0072] [Example 2] A package substrate for mounting a semiconductor element was obtained in the same manner as in Example 1, except that a prepreg (GHPL-830NSF FF67 manufactured by Mitsubishi Gas Chemical Company; thickness 20 μm) in which bismaleimide triazine resin (BT resin) was impregnated into glass cloth (glass fiber) to make it into a B-stage was used as the core resin layer 2 in Example 1. The unevenness of the copper foil surface on the peeled surface was measured in the same manner as in Example 1. The unevenness of the copper foil surface on the peeled surface was 1.79 μm.

[0073] [Example 3] A package substrate for mounting a semiconductor element was obtained in the same manner as in Example 1, except that a prepreg (GHPL-830NSF FF74 manufactured by Mitsubishi Gas Chemical Company, thickness 30 μm) in which bismaleimide triazine resin (BT resin) was impregnated into glass cloth (glass fiber) to make it into a B-stage was used as the core resin layer 2 in Example 1. The unevenness of the copper foil surface on the peeled surface was measured in the same manner as in Example 1. The unevenness of the copper foil surface on the peeled surface was 3.15 μm.

[0074] [Example 4] A package substrate for mounting a semiconductor element was obtained in the same manner as in Example 1, except that a prepreg (GHPL-830NSF FF78 manufactured by Mitsubishi Gas Chemical Company, thickness 35 μm) in which bismaleimide triazine resin (BT resin) was impregnated into glass cloth (glass fiber) to make it into a B-stage was used as the core resin layer 2 in Example 1. The unevenness of the copper foil surface on the peeled surface was measured in the same manner as in Example 1. The unevenness of the copper foil surface on the peeled surface was 3.32 μm.

[0075] In the package substrates for mounting semiconductor elements in Examples 1 to 4, the circuit-forming substrate (first substrate) is formed in a single process, and therefore the production efficiency is better than in the comparative example, and there are fewer defective products and the yield is excellent during laser processing and circuit formation.

[0076] [Comparative Example 2] A package substrate for mounting a semiconductor element was obtained in the same manner as in Example 1, except that a prepreg (GHPL-830NXA manufactured by Mitsubishi Gas Chemical Company; thickness 110 μm) in which bismaleimide triazine resin (BT resin) was impregnated into glass cloth (glass fiber) to form a B-stage was used as the core resin layer 2 in Example 1. The unevenness of the copper foil surface on the peeled surface was measured in the same manner as in Example 1. The unevenness of the copper foil surface on the peeled surface was 6.00 μm, and the resist adhesion in the next process of forming a circuit was reduced, resulting in a reduced product yield.

[0077] The disclosure of Japanese Patent Application No. 2018-234665, filed on December 14, 2018, is incorporated herein by reference in its entirety. In addition, all publications, patent applications, and technical standards mentioned in the specification are herein incorporated by reference to the same extent as if each individual publication, patent application, and technical standard was specifically and individually indicated to be incorporated by reference. [Explanation of symbols]

[0078] 1 Circuit formation substrate (first substrate), 2 Core resin layer, 3 First metal layer, 4 First insulating resin layer, 5 Second metal layer, 6 Second insulating resin layer, 7 Third metal layer, 8 Second substrate, 9 Third substrate, 10 Insulating layer, 11 Wiring conductor, 12 Package substrate for mounting semiconductor element, 13 Non-through hole, 14 Fourth metal layer

Claims

1. A method for manufacturing a package substrate for mounting a semiconductor element, the method comprising the steps of: a first substrate forming step (a) of forming a laminate in which a first metal layer, which is a copper foil having a thickness of 2 μm to 5 μm and is coated with a release layer containing a silane compound and can be peeled off from the core resin layer, a first insulating resin layer, and a second metal layer are arranged in this order on both sides of a core resin layer which is a prepreg having a thickness of 20 μm to 35 μm and which is B-staged by impregnating a bismaleimide triazine resin into a glass cloth, and the laminate is heated and pressurized all at once to form a first substrate; A patterning step (b) of forming a pattern on the second metal layer of the first substrate; a second substrate forming step (c) of forming a second substrate by heating and pressurizing a laminate formed by arranging a second insulating resin layer and a third metal layer in this order on the surface of the second metal layer of the first substrate; a peeling step (d) of peeling a third substrate having the first metal layer, the first insulating resin layer, the second metal layer, the second insulating resin layer, and the third metal layer in this order from the core resin layer; Including, The laminate has the first metal layer disposed so that the release layer and the core resin layer are in contact with each other. A method for manufacturing a package substrate for mounting a semiconductor element.

2. 2. The method for manufacturing a package substrate for mounting a semiconductor element according to claim 1, further comprising a wiring conductor forming step (e) of forming a non-through hole in a surface of the third substrate, the non-through hole reaching a surface of the second metal layer, applying electrolytic copper plating and / or electroless copper plating to an inner wall of the non-through hole, connecting the second metal layer to each of the first metal layer and the third metal layer, forming a fourth metal layer on the surface of the third substrate, and forming a pattern in the fourth metal layer to form the wiring conductor.

3. 3. The method for manufacturing a package substrate for mounting a semiconductor element according to claim 1, wherein the third substrate has a thickness of 5 μm to 100 μm.

4. The method for manufacturing a package substrate for mounting a semiconductor element according to any one of claims 1 to 3, wherein the third metal layer has a carrier layer, and after the first substrate is heated and pressurized in the second substrate formation process (c), the carrier layer is removed from the third metal layer.

5. 5. The method for manufacturing a package substrate for mounting a semiconductor element according to claim 1, wherein at least one of the first metal layer, the second metal layer, and the third metal layer is a copper foil.

6. A method for manufacturing a package substrate for mounting a semiconductor element described in any one of claims 1 to 5, wherein at least one of the first insulating resin layer and the second insulating resin layer is a prepreg in which a base material is impregnated with resin.

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