Device and method for simulating semiconductor device

Abstract

To provide a simulation device and a simulation method which can determine occurrence of a defective mode such as peeling without setting an empirical threshold.SOLUTION: In a simulation device 10 of a semiconductor device in which a semiconductor element is mounted on a mounting member and is sealed together with a part of the mounting member by a sealing member, a model generation part 2 generates a model having no defective mode in the semiconductor device, and a simulation part calculates a first simulation value. Similarly, the model generation part 2 generates a model generating a defective mode in a specified region, and the simulation part calculates a second simulation value. A determination part 6 compares the first simulation value with the second simulation value, and determines whether or not the defective mode is generated.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device simulation apparatus and a simulation method for determining whether or not a failure mode occurs in a semiconductor device having a structure in which a semiconductor element is mounted on a mounting member and sealed with a sealing member. [Background technology]

[0002] Generally, when determining whether or not various failure modes such as peeling will occur within a semiconductor device, the determination is made by comparing a calculated simulation value for a specified physical property value with an empirically obtained threshold value.

[0003] For example, whether peeling occurs as a failure mode in a semiconductor device is determined as follows. First, semiconductor devices are fabricated with different dimensions and physical properties of the components to confirm whether peeling occurs. Meanwhile, a simulation device is used to simulate the internal stress of each of a number of semiconductor devices in which peeling has occurred. The minimum value of this simulation value becomes the specific value (A) of internal stress at which peeling occurs. Similarly, internal stress is simulated for semiconductor devices in which peeling does not occur. The maximum value of this simulation value becomes the specific value (B) of internal stress at which peeling does not occur. The person performing the simulation sets these two specific values ​​as a threshold value (X). Alternatively, a value between the two specific values ​​may be set as the threshold value (X).

[0004] On the other hand, for the semiconductor device to be simulated, data such as dimensions and physical properties of its constituent members are input into a simulation device to set up a model, and an internal stress simulation is performed to obtain a simulation value (Y).

[0005] This simulation value (Y) is compared with a previously set threshold value (X) to determine whether peeling will occur. For example, when a specific value (A) and a specific value (B) are set as the threshold value (X), if the simulation value (Y) is greater than the threshold value (X: specific value A), it is determined that peeling will occur. Alternatively, if the simulation value (Y) is less than the threshold value (X: specific value B), it is determined that peeling will not occur. This type of simulation device is disclosed in, for example, Patent Document 1. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-174927 A Summary of the Invention [Problem to be solved by the invention]

[0007] In the conventional simulation device and simulation method, a threshold value obtained empirically is compared with a simulation value to determine whether or not a failure mode occurs. However, an empirically obtained threshold value is not necessarily appropriate as a threshold value for determining the occurrence of a failure mode of a semiconductor device to be simulated. In addition, it is difficult to confirm whether a simulation value to be compared with the threshold value matches an actual measurement value. In other words, the conventional determination method is a prediction method that compares two uncertain values ​​and lacks accuracy. In view of the above situation, the present invention aims to provide a simulation device and a simulation method for a semiconductor device that can determine the occurrence of a failure mode such as peeling without setting an empirical threshold value. [Means for solving the problem]

[0008] In order to achieve the above-mentioned object, the invention of claim 1 of the present application provides a simulation device for a semiconductor device in which a semiconductor element is mounted on a mounting member and sealed together with a part of the mounting member with a sealing member, the simulation device determining whether or not a failure mode occurs in the semiconductor device, the simulation device comprising: a calculation means for simulating a model in which there is no failure mode in a specified area in the semiconductor device, calculating a first simulation value, and a simulation means for simulating a model in which a failure mode has occurred in a specified area in the semiconductor device, calculating a second simulation value; and a determination means for comparing the first simulation value with the second simulation value, and determining whether or not the failure mode has occurred in the specified area.

[0009] The invention of claim 2 of the present application is characterized in that, in the simulation apparatus for a semiconductor device according to claim 1, the calculation means is means for calculating internal stress in a specified region in the semiconductor device as the first simulation value or the second simulation value, and the determination means is means for determining that the failure mode will not occur when the first simulation value is smaller than the second simulation value, or for determining that the failure mode will occur when the second simulation value is smaller than the first simulation value.

[0010] The invention of claim 3 of the present application is characterized in that, in the simulation device for a semiconductor device according to claim 1 or 2, the failure mode is any one of peeling between the semiconductor element and the mounting member, peeling between the semiconductor element and the sealing member, peeling between the mounting member and the sealing member, destruction of the semiconductor element, destruction of the mounting member, and destruction of the sealing member.

[0011] The invention of claim 4 of the present application is a method for simulating a semiconductor device in which a semiconductor element is mounted on a mounting member and sealed with a sealing member together with a part of the mounting member, for determining whether or not a failure mode occurs in the semiconductor device, the method comprising the steps of: simulating a model in which there is no failure mode in a specified region in the semiconductor device and calculating a first simulation value; simulating a model in which a failure mode has occurred in a specified region in the semiconductor device and calculating a second simulation value; and comparing the first simulation value with the second simulation value to determine whether or not the failure mode has occurred.

[0012] The invention of claim 5 of the present application is characterized in that, in the simulation method for a semiconductor device according to claim 4, the step of calculating the first simulation value and the step of calculating the second simulation value are steps of calculating internal stress in specified regions in the semiconductor device, respectively, and the step of determining whether or not the failure mode will occur is a step of determining that the failure mode will not occur when the first simulation value is smaller than the second simulation value, or determining that the failure mode will occur when the second simulation value is smaller than the first simulation value.

[0013] The invention of claim 6 of the present application is characterized in that, in the simulation method for a semiconductor device according to claim 4, the step of calculating the first simulation value and the step of calculating the second simulation value are steps of respectively calculating internal stresses in a plurality of regions along an edge of a specified region in the semiconductor device, and the step of determining whether or not the failure mode will occur is a step of determining that the failure mode will not occur when there are consecutive regions in which the first simulation value is smaller than the second simulation value for the plurality of regions along the edge, or determining that the failure mode will occur when there is a region in which the second simulation value is smaller than the first simulation value and there are no consecutive regions in which the first simulation value is smaller than the second simulation value. Effect of the Invention

[0014] The semiconductor device simulation device and simulation method of the present invention make it possible to determine whether or not a failure mode will occur simply by comparing simulation values ​​calculated from a model without a failure mode and a model in which a failure mode has occurred. Since the present invention does not require the setting of a threshold value for determination, it is easy to simulate a semiconductor device with a new structure.

[0015] The present invention makes it possible to predict and determine the occurrence of various failure modes as long as a model can be set, and thus makes it possible to easily predict and determine the occurrence of various failure modes. [Brief description of the drawings]

[0016] [Figure 1] FIG. 2 is an explanatory diagram of a simulation device for a semiconductor device according to the present invention; [Diagram 2] FIG. 2 is an explanatory diagram of a semiconductor device that is a simulation target of the first embodiment of the present invention and in which peeling does not occur. [Diagram 3]FIG. 2 is an explanatory diagram of a semiconductor device in which peeling has occurred, which is a simulation target of the first embodiment of the present invention. [Figure 4] FIG. 2 is a diagram illustrating a determination method according to the first embodiment of the present invention. [Diagram 5] FIG. 2 is a diagram for explaining a design change of a semiconductor device that is a simulation target of the first embodiment of the present invention. [Figure 6] FIG. 11 is an explanatory diagram of a semiconductor device that is a simulation target of the second embodiment of the present invention, in which no peeling occurs. [Figure 7] FIG. 13 is an explanatory diagram of a semiconductor device in which peeling has occurred, which is a simulation target of the second embodiment of the present invention. [Figure 8] FIG. 11 is a diagram illustrating a determination method according to a second embodiment of the present invention. [Figure 9] FIG. 13 is a diagram for explaining a design change of a semiconductor device that is a simulation target of the second embodiment of the present invention. [Figure 10] FIG. 13 is an explanatory diagram of a semiconductor device that is a simulation target of the third embodiment of the present invention and in which peeling does not occur. [Figure 11] FIG. 13 is an explanatory diagram of a semiconductor device in which peeling has occurred, which is a simulation target of the third embodiment of the present invention. [Figure 12] FIG. 11 is a diagram illustrating a determination method according to a third embodiment of the present invention. [Figure 13] FIG. 11 is a diagram illustrating a determination method according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The simulation device and simulation method for a semiconductor device of the present invention are intended to simulate a semiconductor device having a structure in which a semiconductor element is mounted on a mounting member and at least a part of the semiconductor element and the mounting member are sealed with a sealing member. Also, the simulation device and simulation method are intended to determine whether or not a predicted failure mode occurs in the semiconductor device. Hereinafter, a description will be given of a simulation method for determining whether or not a failure mode occurs in the semiconductor device to be simulated, using the simulation device for a semiconductor device of the present invention.

[0018] Fig. 1 is an explanatory diagram of an example of a semiconductor device simulation device 10 of the present invention. The simulation device 10 shown in Fig. 1 can be configured with an arithmetic device such as a personal computer, and is configured with an input unit 1 for inputting commands such as starting a simulation and creating a model, a model generation unit 2 for generating a desired model, a data group storage unit 3 for storing a plurality of data required for model generation, a simulation unit 4 for performing a simulation for the model generated by the model generation unit 2, a simulation value storage unit 5 for storing the simulation results, a judgment unit 6 for judging whether or not a failure mode occurs from the simulation values, and an output unit 7 for displaying the judgment results.

[0019] 1, the data group storage unit 3 is not necessarily required if the necessary data is input from the input unit 1, or if the necessary data is stored in the model generation unit 2. Similarly, the simulation value storage unit 5 is not necessarily required if the simulation unit 4 or the judgment unit 6 is configured to store the simulation values ​​performed by the simulation unit 4. Furthermore, the judgment result output from the judgment unit 6 to the output unit 7 is not limited to the case where it clearly indicates the presence or absence of the occurrence of a failure mode, but may be displayed in a manner recognizable by the person executing the simulation, for example, by changing the display method of the simulation value depending on whether it is determined that a failure mode will occur or not.

[0020] The semiconductor device simulation method of the present invention includes the following steps. First, it is determined what failure mode is to be simulated for the semiconductor device to be simulated. As in a simulation method using a normal simulation device, the person executing the simulation inputs information about the semiconductor device and information about the failure mode required to start the simulation to the input unit 1. The model generation unit 2 reads out data stored in the data group storage unit 3 as necessary and generates a model of the semiconductor device to be simulated. At this time, the model generation unit 2 generates a model in which there is no failure mode in the semiconductor device and a model in which a failure mode has occurred in the semiconductor device.

[0021] The simulation unit 4 performs a simulation using a model in which there is no failure mode in a specified region in the semiconductor device, obtains a first simulation value, and stores it in the simulation value storage unit 5. The first simulation value calculated here is a physical property value that affects the occurrence of a failure mode, and is a value to be compared with a second simulation value described later.

[0022] Similarly, a simulation is performed by the simulation unit 4 using a model in which a failure mode is generated in a specified region within the semiconductor device that is the same as the region in which the first simulation was performed by the model generation unit 2, and a second simulation value is obtained and stored in the simulation value memory unit 5.

[0023] When the simulation by the simulation unit 4 ends, the judgment unit 6 reads out the first simulation value and the second simulation value from the simulation value storage unit 5, judges whether or not a failure mode occurs according to a preset judgment method, and outputs the judgment result to the output unit 7. The judgment result is displayed on the output unit 7, so that the person executing the simulation can know the simulation result.

[0024] The judgment method in the judgment unit 6 may be such that the relationship between the magnitude relationship between the first simulation value and the second simulation value and the presence or absence of the occurrence of the failure mode is set by combining the assumed failure mode and the physical property values ​​to be simulated (the first simulation value and the second simulation value). Hereinafter, the embodiment of the present invention will be described in detail. EXAMPLES

[0025] As a first embodiment of the present invention, a case will be described in which it is determined whether or not peeling occurs between a semiconductor element and a mounting member.

[0026] 2 is a cross-sectional view of a semiconductor device 20 to be simulated in this embodiment. A semiconductor element 23 is mounted on a mounting member 21 made of a lead frame via an adhesive member 22. A part of the mounting member 21 and the semiconductor element 23 are sealed with a sealing member 24 made of sealing resin. In this embodiment, in the semiconductor device 20 having such a structure, it is determined whether peeling occurs at the interface between the mounting member 21 and the sealing member 24 as one of the failure modes.

[0027] The semiconductor device 20 shown in FIG. 2 is a case where no peeling occurs. On the other hand, the semiconductor device 20A shown in FIG. 3 is a case where peeling occurs in the peeling formation region 25 between the mounting member 21 and the sealing member 24. As in the normal simulation, the physical properties and dimensions of the respective sealing members stored in the data group storage unit 3 are read for the semiconductor device 20 and the semiconductor device 20A, and a model is formed in the model generation unit 2. Specifically, a model where the mounting member 21 and the sealing member 24 are continuous and no peeling occurs (corresponding to the semiconductor device 20 shown in FIG. 2) and a model where the mounting member 21 and the sealing member 24 are not continuous in the peeling formation region 25 (corresponding to the semiconductor device 20A shown in FIG. 3) are formed. In addition, models are also formed for cases where the type of the mounting member 21 is changed.

[0028] Next, a simulation of internal stress is performed. Here, the internal stress in the vicinity of the region to be simulated (the joint between the mounting member 21 and the sealing member 24) is simulated. In an actual semiconductor device, after sealing with a sealing member (for example, sealing temperature 175°C), temperatures such as room temperature (25°C), a reliability test process (-65°C), and a reflow process for mounting (for example, reflow temperature 260°C) are applied, so it is assumed that a similar thermal history is also applied. Although it is possible to compare the simulation values ​​at each temperature, it is decided to compare the simulation values ​​at the temperature at which the stress is smallest, which in this case is the same temperature as the sealing temperature.

[0029] In Figure 4, sample No. 1 shows the simulation result of the internal stress when a typical 42 alloy frame is used as the lead frame, and sample No. 2 shows the simulation result of the internal stress when a copper frame is used. The first simulation result value is the simulation result of a model without peeling (corresponding to the first simulation value), and the second simulation result is the simulation result of a model with peeling (corresponding to the second simulation value).

[0030] The determination of whether peeling will occur is performed as follows. The first value is compared with the second value, and when the first value is smaller than the second value, the state showing the first value can be said to be a more static steady state than the state showing the second value. In other words, the state without peeling can be said to be a more static steady state than the state in which peeling will occur. According to this determination method, it is determined that peeling will not occur in the semiconductor device of Sample No. 1. When the actual semiconductor device was observed for the presence or absence of peeling, it was confirmed that no peeling was found, which agreed with the determination result.

[0031] Conversely, when the second value is smaller than the first value, the state showing the second value can be said to be a more static steady state than the state showing the first value. In other words, the state in which peeling occurs can be said to be a more static steady state than the state in which peeling does not occur. From this result, it was determined that peeling would occur in the semiconductor device of sample No. 2, and when the actual semiconductor device was observed, it was confirmed that peeling was present, which agreed with the determination result.

[0032] In the conventional simulation method, the first value is compared with an empirically obtained threshold value to predict whether or not peeling will occur. In contrast, in this embodiment, a threshold value is not used, and instead, the magnitude relationship between the first value and the second value is compared, which shows that it is possible to obtain a judgment result that coincides with the actual observation result.

[0033] Incidentally, in the generation of the model used in this embodiment, as explained in the conventional example, it is difficult to increase the accuracy of the model, that is, to make the simulation value coincide with the true value. However, in this embodiment, instead of comparing the absolute values ​​of the simulation values, a configuration is adopted in which it is determined whether the model without peeling or the model in which peeling has occurred is in the steady state, thereby eliminating the need to obtain the accuracy of the absolute values ​​of the simulation values. In addition, in order to obtain a semiconductor device in which peeling does not occur, it is preferable to generate multiple models and perform the determination for those models.

[0034] Next, an example of applying the present invention to a method for designing a semiconductor device will be described. Peeling occurs in a semiconductor device having the structure of sample No. 2 shown in Fig. 4. We will consider what structure can be used to prevent peeling from occurring in this semiconductor device.

[0035] For example, regarding peeling between the mounting member 21 and the sealing member 24, it will be considered whether peeling can be prevented by forming a through hole 26 in the mounting member 21 and utilizing the anchor effect.

[0036] 5 shows a semiconductor device 20B in which a through hole 26 is formed in a part of a peeling formation region 25 of a mounting member 21. As shown in FIG. 5, a model is formed in which a sealing member 24 is filled in the through hole 26.

[0037] The simulation result of the internal stress is sample No. 3 in FIG. 4. As described above, a determination is made as to whether peeling occurs or not. Comparing the first value and the second value of the simulation result, the first value is smaller than the second value. This result indicates that peeling does not occur in this semiconductor device 20B. When the actual semiconductor device was observed to determine whether peeling occurred or not, it was confirmed that there was no peeling, which coincided with the determination result.

[0038] In this way, according to the semiconductor device simulation apparatus and simulation method of the present invention, it becomes possible to easily design a semiconductor device. EXAMPLES

[0039] Next, as a second embodiment, a case will be described in which it is determined whether or not peeling occurs between the mounting member 21 and the sealing member 24 in a semiconductor device in which the shape of the mounting member 21 is different from that in the first embodiment.

[0040] 6 is a cross-sectional view of a semiconductor device 30 to be simulated in this embodiment. A semiconductor element 23 is mounted on a mounting member 21 made of a lead frame via an adhesive member 22. A part of the mounting member 21 and the semiconductor element 23 are sealed on only one side by a sealing member 24 made of sealing resin. In the semiconductor device 30 having such a structure, it is determined whether peeling occurs as one of the failure modes in a peeling formation region 25 between the mounting member 21 and the sealing member 24.

[0041] The semiconductor device 30 shown in Fig. 6 is a case where no peeling occurs. On the other hand, the semiconductor device 30A shown in Fig. 7 is a case where peeling occurs in a part of the peeling formation region 25 between the mounting member 21 and the sealing member 24. As in a normal simulation, for the semiconductor device 30 and the semiconductor device 30A, the physical properties and dimensions of the respective sealing members stored in the data group storage unit 3 are read out, and a model is formed in the model generation unit 2. Specifically, a model where the mounting member 21 and the sealing member 24 are continuous and no peeling occurs (corresponding to the semiconductor device 30 shown in Fig. 6) and a model where the mounting member 21 and the sealing member 24 are not continuous in the peeling formation region 25 (corresponding to the semiconductor device 30A shown in Fig. 7) are formed.

[0042] Next, a simulation of internal stress is performed. Here, the internal stress in the vicinity of the region to be simulated (the joint between the mounting member 21 and the sealing member 24) is simulated. In an actual semiconductor device, after sealing with a sealing member (for example, sealing temperature 160°C), temperatures such as room temperature (25°C), reliability test process (-65°C), and reflow process for mounting (for example, reflow temperature 260°C) are added, so it is assumed that a similar thermal history is also added. It is possible to compare the simulation values ​​at each temperature, but it is decided to compare the simulation values ​​at the temperature at which the stress is smallest, which in this case is the same temperature as the sealing temperature.

[0043] In Fig. 8, sample No. 4 is a simulation result of the internal stress of each of the semiconductor devices 30 and 30A shown in Fig. 6 and Fig. 7. The first value of the simulation result is the simulation result of a model without peeling (corresponding to the first simulation value), and the second value is the simulation result of a model with peeling (corresponding to the second simulation value).

[0044] The determination of whether peeling occurs is performed as follows. The first value is compared with the second value, and when the first value is smaller than the second value, the state showing the first value can be said to be a more static steady state than the state showing the second value. In other words, the state without peeling can be said to be a more static steady state than the state without peeling. Conversely, when the second value is smaller than the first value, the second state can be said to be a more static steady state than the first state. In other words, the state with peeling occurring can be said to be a more static steady state than the state without peeling. According to this determination method, the semiconductor device of sample No. 4 is determined to have peeling. When the actual semiconductor device 30A was observed for the presence or absence of peeling, it was confirmed that peeling was present, which coincided with the determination result.

[0045] Next, regarding peeling between the mounting member 21 and the sealing member 24, we will consider whether it is possible to prevent peeling by forming a recess 27 in the mounting member 21 and utilizing the anchor effect. Figure 9 shows a semiconductor device 30B in which a recess 27 is formed in a part of the mounting member 21. As shown in Figure 9, a model is created in which the recess 27 is filled with the sealing member 24.

[0046] The simulation result of the internal stress is sample No. 5 in FIG. 8. As described above, a determination is made as to whether or not peeling occurs. When the first value and the second value of the simulation result are compared, the second value is smaller than the first value. This result indicates that peeling occurs in this semiconductor device 30B. When the actual semiconductor device was observed to determine whether or not peeling occurs, peeling was observed, and it was confirmed that this coincided with the determination result.

[0047] In the semiconductor device 30B of this embodiment, simulations were performed by changing the shape of the mounting member 21 and the shape of the recess 27 in various ways, and it was concluded that the occurrence of peeling cannot be suppressed by changing the shape alone. In this way, the semiconductor device simulation device and simulation method of the present invention can also be used to identify semiconductor devices in which the occurrence of failure modes cannot be suppressed. EXAMPLES

[0048] Next, as a third embodiment of the present invention, a case will be described in which it is determined whether or not peeling occurs between the mounting member 21 and the sealing member 24 in a semiconductor device in which the shape of the mounting member 21 is different from that in the first and second embodiments described above.

[0049] 10 is a cross-sectional view of a semiconductor device 40 to be simulated in this embodiment. A semiconductor element 23 is mounted on a mounting member 21 made of a lead frame via an adhesive member 22. Parts of the mounting members 21, 21A and the semiconductor element 23 are sealed on only one side by a sealing member 24 made of sealing resin. In the semiconductor device 40 having such a structure, it is determined whether peeling occurs as one of the failure modes in a peeling formation region 25 between the mounting member 21A and the sealing member 24.

[0050] The semiconductor device 40 shown in Fig. 10 is a case where no peeling occurs. On the other hand, the semiconductor device 40A shown in Fig. 11 is a case where peeling occurs in a part of the peeling formation region 25 between the mounting member 21A and the sealing member 24. As in the normal simulation, the physical properties and dimensions of the respective sealing members stored in the data group storage unit 3 are read for the semiconductor device 40 and the semiconductor device 40A, and a model is formed in the model generation unit 2. Specifically, a model where the mounting member 21 and the sealing member 24 are continuous and no peeling occurs (corresponding to the semiconductor device 40 shown in Fig. 10) and a model where the mounting member 21 and the sealing member 24 are not continuous in the peeling formation region 25 (corresponding to the semiconductor device 40A shown in Fig. 11) are formed.

[0051] In particular, in the model in which the mounting member 21A and the sealing member 24 are not continuous in this embodiment, the peeling formation region 25 is divided into small areas, which is different from the first and second embodiments. FIG. 12 is a cross-sectional view along the surface of the mounting member 21A, in which the mounting member 21A is surrounded by the sealing member 24. In the semiconductor device 40A, the sealing member 24 is formed on the surface of the mounting member 21A, and a model is formed in which the mounting member 21A and the sealing member 24 are not continuous in multiple areas. Specifically, a model is formed in which independent peeling formation regions 25 are formed in the vicinity of multiple points shown in FIG. 12(a).

[0052] This peeling formation region 25 is divided into meshes that are used in ordinary simulation devices and simulation methods, and is disposed at the nodes of the divided region.

[0053] Next, a simulation of internal stress is performed. The internal stress in the vicinity of the region to be simulated (the joint between the mounting member 21A and the sealing member 24) is simulated. In an actual semiconductor device, after sealing with a sealing member (for example, sealing temperature 160°C), temperatures such as room temperature (25°C), reliability test process (-65°C), and reflow process for mounting (for example, reflow temperature 260°C) are added, so it is assumed that a similar thermal history is also added. Although it is possible to compare the simulation values ​​at each temperature, it is decided to compare the simulation values ​​at the temperature at which the stress is smallest, which in this case is the same temperature as the sealing temperature.

[0054] In each peeling formation region 25, a simulation result of the first value and the second value is obtained as in the first or second embodiment. The first value is compared with the second value, and when the first value is smaller than the second value, the state showing the first value can be said to be a more static steady state than the state showing the second value. In other words, the state without peeling can be said to be a more static steady state than the state where peeling occurs. Conversely, when the second value is smaller than the first value, the second state can be said to be a more static steady state than the first state. In other words, the state where peeling occurs can be said to be a more static steady state than the state without peeling.

[0055] In each peeling formation region 25, a region determined not to cause peeling is indicated by "◯" in Fig. 12(b). In each peeling formation region 25, a region determined to cause peeling is not shown.

[0056] The determination of whether peeling will occur is performed as follows. If peeling does not occur in any of the peeling formation regions 25, it is naturally determined that peeling will not occur. Also, it is determined that peeling will not occur in a region that is continuously surrounded by the respective determination results of the multiple peeling formation regions 25. In the example shown in FIG. 12(b), multiple regions along the edge of the mounting member 21A in which it has been determined that peeling will not occur are continuous, so it is determined that peeling will not occur. When the actual semiconductor device 40A was observed for the presence or absence of peeling, it was confirmed that there was no peeling, which agreed with the determination result.

[0057] The results of a similar simulation performed on a mounting member 21A made of a different material are shown in Fig. 13. As in the case shown in Fig. 12, the peeling formation region 25 is divided into meshes used in a typical simulation device and simulation method, and is placed at the nodes of the divided region.

[0058] Simulation results of the first value and the second value are obtained for each peeling formation region 25. In each peeling formation region 25, the region determined to be free of peeling is indicated by "◯" in Fig. 13(b). In each peeling formation region 25, the region determined to be free of peeling is not shown.

[0059] The determination of whether peeling will occur is performed as follows. As described above, it is determined that peeling will not occur in areas where the determination results of the multiple peel formation areas 25 are continuously surrounding. Conversely, when there is no continuously surrounding area, it is determined that peeling will occur. In the example shown in FIG. 13(b), the areas determined not to cause peeling in the multiple areas along the edge of the mounting member 21A are not continuous, so it is determined that peeling will occur. When the actual semiconductor device was observed for the presence or absence of peeling, peeling was observed, and it was confirmed that this coincided with the determination result.

[0060] The simulation method of this embodiment is effective when the area of ​​the peeling formation region 25 is small. For example, when the area of ​​the peeling formation region 25 is 0.1 mm 2In the case of the size of about 100 nm or less, there were cases where the simulation results did not match the observation results of the actual semiconductor device in the simulation methods described in the first and second embodiments. In this case, a simulation was performed using the simulation method of this embodiment, and it was confirmed that the simulation results matched the observation results of the actual semiconductor device.

[0061] The simulation apparatus and simulation method of this embodiment can also be used in the design of semiconductor devices, and in identifying semiconductor devices in which the occurrence of failure modes cannot be suppressed.

[0062] Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments. For example, the failure mode is not limited to peeling between the mounting member and the sealing member, but peeling between the semiconductor element and the mounting member, or peeling between the semiconductor element and the sealing member can be simulated in the same way. Furthermore, in addition to peeling, for example, destruction (cracks) of the semiconductor element, destruction (cracks) of the mounting member, and destruction (cracks) of the sealing member can be simulated in the same way.

[0063] In the above embodiment, the physical property value to be simulated is the internal stress, but the physical property value is not limited to this. For example, the physical property value can be variously changed to the energy stored at a predetermined position, strain energy, etc. [Explanation of symbols]

[0064] 1: input unit, 2: model generation unit, 3: data group storage unit, 4: simulation value storage unit, 5: simulation unit, 6: judgment unit, 7: output unit, 10: Simulation device, 20, 20A, 30, 30A, 30B, 40, 40A: Semiconductor device, 21, 21A: mounting member, 22: adhesive member, 23: semiconductor element, 24: sealing member, 25: peeling formation region, 26: through hole, 27: recess

Claims

1. A simulation apparatus for a semiconductor device for determining whether or not a failure mode occurs in a semiconductor device having a semiconductor element mounted on a mounting member and sealed together with a part of the mounting member with a sealing member, comprising: a calculation means for simulating a model in which a failure mode is not present in a specified region of the semiconductor device to calculate a first simulation value, and for simulating a model in which a failure mode is generated in a specified region of the semiconductor device to calculate a second simulation value; and a determination means for comparing the first simulation value with the second simulation value and determining whether or not the failure mode occurs in the specified region.

2. 2. The semiconductor device simulation apparatus according to claim 1, the calculation means is means for calculating an internal stress of a designated region in the semiconductor device as the first simulation value or the second simulation value, The simulation device for a semiconductor device, characterized in that the judgment means judges that the failure mode will not occur when the first simulation value is smaller than the second simulation value, or judges that the failure mode will occur when the second simulation value is smaller than the first simulation value.

3. 3. The semiconductor device simulation apparatus according to claim 1, the failure mode being any one of peeling between the semiconductor element and the mounting member, peeling between the semiconductor element and the sealing member, peeling between the mounting member and the sealing member, destruction of the semiconductor element, destruction of the mounting member, and destruction of the sealing member.

4. A method for simulating a semiconductor device, comprising the steps of: determining whether or not a failure mode occurs in a semiconductor device having a semiconductor element mounted on a mounting member and sealed together with a part of the mounting member by a sealing member, the method comprising the steps of: performing a simulation of a model in which there is no failure mode in a specified region in the semiconductor device, and calculating a first simulation value; performing a simulation of a model in which a failure mode is generated in a specified region in the semiconductor device, and calculating a second simulation value; comparing the first simulation value with the second simulation value to determine whether or not the failure mode occurs.

5. 5. The semiconductor device simulation method according to claim 4, the step of calculating the first simulation value and the step of calculating the second simulation value are steps of calculating internal stresses of designated regions in the semiconductor device, a step of determining whether or not the failure mode occurs comprising: determining that the failure mode will not occur when the first simulation value is smaller than the second simulation value; or determining that the failure mode will occur when the second simulation value is smaller than the first simulation value.

6. 5. The semiconductor device simulation method according to claim 4, the step of calculating the first simulation value and the step of calculating the second simulation value are steps of calculating internal stresses of a plurality of regions along an edge of a specified region in the semiconductor device, a step of determining whether or not the failure mode will occur comprising: determining that the failure mode will not occur when there are consecutive regions along the edge where the first simulation value is smaller than the second simulation value; or determining that the failure mode will occur when there is a region where the second simulation value is smaller than the first simulation value and there are no consecutive regions where the first simulation value is smaller than the second simulation value.

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