Multijunction solar cell with patterned emitter and method for making same

Abstract

To provide a multijunction solar cell employing a patterned emitter and a method of making the solar cell.SOLUTION: A multijunction solar cell includes a base substrate comprising a Group IV semiconductor and a dopant of a first carrier type. A patterned emitter is formed at a first surface of the base substrate. The patterned emitter comprises a plurality of well regions doped with a dopant of a second carrier type in the Group IV semiconductor. The base substrate including the patterned emitter form a first solar subcell. The multijunction solar cell further comprises an upper structure comprising one or more additional solar subcells over the first solar subcell. Methods of making a multijunction solar cell are also described.SELECTED DRAWING: None

Description

[Technical field]

[0001] Detailed Description Technical Field of the Disclosure The present disclosure relates to multijunction solar cells using patterned emitters and methods for making same. [Background technology]

[0002] Improving solar cell efficiency is a continuing goal of solar cell manufacturers. Providing multiple solar cell junctions on a single solar cell is a known method to increase efficiency. Such multijunction solar cells may include a bottom subcell formed on a germanium substrate. One or more additional junctions are formed on the bottom subcell. FIG. 1 shows an example of such a conventional multijunction solar cell 10 having a p-type germanium substrate 12 with a diffused emitter region 18. A GaInAs middle subcell 14 and a GaInP top subcell 16 are formed as part of a monolithic semiconductor stack on the substrate 12. The middle subcell 14 and the top subcell 16 include second and third junctions (not shown) in addition to the first junction provided by the emitter region 18. An n-type nucleation layer 20, an n-type GaInAs buffer layer 22, tunnel junctions 24, 26, and a cap layer 28 are also disposed in a superstructure formed on the substrate 12. The n-type emitter 18 in the bottom subcell is formed by diffusion into the substrate 12 during III / V growth of the nucleation and / or buffer layers to form an unpatterned n-type layer of uniform thickness across the entire substrate surface. While the blanket diffusion process used to form the emitter provides a convenient method for fabricating the bottom subcell, such an emitter structure provides a non-ideal path for loss of photogenerated carriers, reducing the efficiency of the solar cell.

[0003] There remains a need in the art for multijunction solar cells with improved efficiency. Summary of the Invention

[0004] The present disclosure relates to a multijunction solar cell. The multijunction solar cell comprises a base substrate including a group IV semiconductor and a dopant of a first carrier type. A patterned emitter is formed on a first surface of the base substrate. The patterned emitter comprises a plurality of well regions doped in the group IV semiconductor with a dopant of a second carrier type. The base substrate including the patterned emitter forms a first solar subcell. The multijunction solar cell further comprises a superstructure comprising one or more additional solar subcells above the first solar subcell.

[0005] The present disclosure relates to a method of fabricating a multijunction solar cell. The method includes providing a base substrate comprising a group IV semiconductor and a dopant of a first carrier type, the base substrate having a first major surface and a second major surface opposite the first major surface. A patterned emitter is formed on the first major surface of the base substrate. The patterned emitter comprises a plurality of well regions doped in the group IV semiconductor with a dopant of the second carrier type. The base substrate including the patterned emitter forms a first solar subcell. The method further includes a superstructure comprising one or more additional solar subcells above the first solar subcell.

[0006] The present disclosure also relates to a method of manufacturing a solar cell substrate. The method includes providing a base substrate including a group IV semiconductor and a dopant of a first carrier type, the base substrate having a first major surface and a second major surface opposite the first major surface. A patterned emitter is formed in the first major surface of the base substrate and includes a plurality of well regions doped in the group IV semiconductor with a dopant of the second carrier type. The base substrate including the patterned emitter forms a solar subcell. The method includes preparing the first major surface of the base substrate to receive an epitaxial layer.

[0007] The present disclosure also relates to a solar cell substrate. The solar cell substrate comprises a base substrate including a group IV semiconductor and a dopant of a first carrier type. The base substrate has a first major surface and a second major surface opposite the first major surface, the first major surface being epitaxially ready. A patterned emitter is formed on the first major surface of the base substrate. The patterned emitter comprises a plurality of well regions doped in the group IV semiconductor with a dopant of the second carrier type. The base substrate comprises the patterned emitter forming a first solar subcell.

[0008] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present teachings as claimed. [Brief description of the drawings]

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate aspects of the present teachings and, together with the description, serve to explain the principles of the present teachings. [Figure 1] 1 shows a schematic cross-sectional view of a conventional multi-junction solar cell. [Diagram 2] 1 shows a schematic cross-section of an exemplary multi-junction solar cell of the present disclosure. [Diagram 3] FIG. 2 shows a schematic top view of a patterned emitter of the present disclosure including multiple well regions. [Figure 4] 1 illustrates lateral current collection and diffusion between patterned emitter well regions in an exemplary device of the present disclosure. [Diagram 5] FIG. 1 shows a schematic cross-sectional view of an exemplary organic subcell that can be used in the multijunction solar cell of the present disclosure. [Figure 6] FIG. 1 shows a schematic cross-sectional view of an exemplary organic subcell that can be used in the multijunction solar cell of the present disclosure. [Figure 7] An example of a method for preparing a base substrate for multi-junction solar cell fabrication is shown in a flow diagram. [Figure 8]1 is a graph of the estimated voltage of a germanium subcell having fewer emitter contacts that are considered ideal under a III / V multijunction solar cell according to an example of the present disclosure. [Figure 9] 1 shows a multi-junction solar cell of the present disclosure with multiple patterned emitters.

[0010] It should be noted that some details of the drawings have been illustrated in a simplified manner to facilitate understanding, rather than to maintain strict structural accuracy, detail, and scale. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Reference will now be made in detail to the present teachings, examples of which are illustrated in the accompanying drawings, in which like reference numerals are used throughout to refer to identical elements. In the following description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the present teachings may be practiced. Accordingly, the following description is by way of example only.

[0012] FIG. 2 illustrates an exemplary multijunction solar cell 100 of the present disclosure. The multijunction solar cell 100 comprises a base substrate comprising a group IV semiconductor and a background dopant of a first carrier type. A patterned emitter 104 is formed on a first surface of the base substrate 102. The term "patterned emitter" refers to selectively forming emitter doped well regions 106 on only a portion of the surface of the first major surface of the base substrate 102, as opposed to forming diffused doped regions on the entire surface of the base substrate 102. As described in more detail below, any pattern that substantially reduces the total surface area covered by the emitter regions on the first major surface of the base substrate 102 can be used. An optional passivation layer 132 is formed on the first surface of the base substrate 102. The superstructure 120 comprises one or more of the subcells 122, 124 on the surface of the base substrate 102 on which the patterned emitter 104 is formed. A plurality of contacts 126, 128 are arranged to connect the multi-junction solar cell to a circuit 130. By way of example, such a circuit may be for powering a photovoltaic power device and / or for charging a battery. Any desired circuit design may be employed, and examples of suitable circuits that may be used in connection with the solar cells of the present disclosure are well known in the art.

[0013] The base substrate 102 may include any suitable Group IV semiconductor material. Examples of Group IV semiconductors include materials selected from germanium and silicon. The base substrate 102 is doped to provide a first subcell (sometimes referred to herein as the "first solar subcell") of a multi-junction solar cell, as described in more detail below.

[0014] FIG. 2 shows a partial cross-sectional view of a single doped well region 106 of a patterned emitter 104 formed adjacent to a background doped region 110 of a base substrate 102. The background doped region 110 is doped with a background dopant of a first carrier type. The patterned emitter 104 may comprise a plurality of such doped well regions 106, as shown in the schematic top view of FIG. 3. Each doped well region 106 is doped with a dopant of a second carrier type that is different from the background dopant having the first carrier type. The background dopant of the first carrier type and the dopant of the second carrier type are selected such that the patterned emitter 104 forms a first pn junction (also referred to herein as a solar cell junction) 108 with the background doped region 110. For example, the background dopant of the first carrier type may be a p-type dopant and the dopant of the second carrier type used in the patterned emitter 104 is an n-type dopant. Alternatively, the background dopant of the first carrier type may be an n-type dopant and the dopant of the second carrier type is a p-type dopant. Minority carrier collection occurs through a p-n junction, as indicated by the arrows in the base substrate 102 in FIG.

[0015] Referring again to FIG. 3, the doped well regions 106 of the patterned emitter 104 are shown as being arranged in an array of dots. The well regions of the present disclosure may be arranged in any suitable array or random pattern that allows for desired carrier collection during operation of the solar cell. Additionally, the doped well regions 106 are shown as having a circular top surface, as seen from the overhead view of FIG. 3, but may have any suitable top surface shape, such as a square, a rectangle, a checkerboard, lines, crossed lines (e.g., to form a grid), etc. The doped well regions 106 are shown as being separated by counter-doped background doped regions 110 and / or passivation layers 132, but may be continuous. Thus, any pattern that substantially reduces the total surface area covered by the emitter regions on the first major surface of the base substrate 102 may be used. For example, the emitter region can cover about 1% to about 50%, such as about 5% to about 40%, or about 10% to about 30%, of a total surface area of ​​the first major surface, the first major surface being a major planar face of the base substrate on which the emitter is formed.

[0016] The distance between adjacent doped well regions 106 can be selected to be shorter than the diffusion length of minority carriers in the base substrate 102 so that the generated carriers can reach the emitter. Referring to FIG. 3, the pitch, which is the shortest distance between two adjacent well regions, can range, for example, from about 0.1 microns to about 1 mm, or from about 1 micron to about 100 microns. For circular doped well regions as shown in FIG. 3, the diameter D can have any suitable length to result in both the patterned emitter covering the desired total surface area of ​​the base substrate and the doped well regions 106 being positioned to have the desired distance between adjacent well regions as described above.

[0017] The doped well region 106 is thicker than the passivation layer 132 and extends well through the passivation layer 132 into the background doped region of the base substrate 102, allowing the doped well region 106 to function as an emitter, as in Figure 2. Moreover, the concentration of dopant in the doped well region 106 is also higher than the concentration of dopant in the passivation layer 132. Here, because the concentration of dopant in the well region is higher than the concentration of dopant in the passivation layer, the concentration in the passivation layer provides any reference concentration necessary to determine which concentration is considered relatively "high."

[0018] The use of patterned emitters, such as those shown in Figures 2 and 3, allows the emitter volume to be reduced compared to continuous layer emitters, thus reducing the Shockley-Read-Hall recombination losses of carriers that occur during operation of the solar cell. All things being equal, reduced recombination losses of carriers result in increased efficiency of the solar cell. Thus, the emitter dimensions can be selected to reduce the emitter area and volume, thereby reducing recombination losses.

[0019] Referring again to FIG. 2, the passivation layer 132 is located between the doped well regions 106 of the patterned emitter 104 and is a diffusion region in the base substrate 102 that contains a dopant of the same carrier type as the background dopant of the base substrate 102. Any suitable dopant that provides the desired carrier type can be used, such as any suitable n-type or p-type dopant. Optionally, if the layer formed on the base substrate 102 is a III-V material, the dopant can be one of the group III or group V elements of the III-V material itself. For example, if GaInAs is epitaxially grown on a III-V substrate, either Ga, In or As may be diffused into the base substrate 102 depending on the desired carrier type used to form the passivation layer 132.

[0020] The dopant concentration in the passivation layer 132 can be higher than the concentration of the background dopant in the base substrate 102 to create a surface field ("FSF") at the junction with the background doped region 110 (e.g., a p+ / p junction if the background dopant is p-type, or an n+ / n junction if the background dopant is n-type). The passivation layer 132 is optional. If used, the passivation layer 132 can prevent or reduce minority carrier losses caused by interface recombination by creating a surface field at the base substrate surface.

[0021] The pn junction 108 forms the cell junction of the first subcell of the multi-junction solar cell 100. At least one additional solar subcell is formed on the base substrate 102 as part of the superstructure 120. For example, the superstructure 120 can include a middle subcell 122 and a top subcell 124. Any desired number of subcells can be formed in the superstructure 120, for example, 1 to 10 subcells, or 2 to 6 subcells. Any suitable design, material, and technique can be used to form the additional subcell structures of the superstructure 120. By way of example, one or more of the subcells 122, 124 can each comprise at least one pn junction formed in a semiconductor material. Suitable semiconductor materials can include, for example, Group IV semiconductors such as single crystal silicon, amorphous silicon, or compound semiconductor materials such as III / V or I / IV heteroepitaxial layers. Any suitable III / V heteroepitaxial materials (e.g., GaAs, GaInAs, etc.) or other materials may be used. Any suitable II / IV heteroepitaxial material (e.g., CdTe, CuInGaSe2) or other II / IV material may be used. Techniques for depositing such layers are well known in the art, and any suitable technique may be used. For example, the layers may be epitaxially grown on any of the group IV-based substrates described herein (e.g., Si or Ge). Appropriate dopants may be added to the layers to provide the desired conductivity or other subcell junction properties, as is well known in the art.

[0022] One or more additional optional layers may also be used as part of the multijunction solar cell 100, including tunnel junction layers 136, 138, nucleation layer 140, buffer layer 144, and cap layer 148. For example, the tunnel junctions 136, 138 may be formed in III / V heteroepitaxial layers between a patterned emitter in the base substrate 102 and one or more subcells in a monolithic epitaxial growth structure, as shown in FIG. 2. Such tunnel junctions are well known and include relatively heavily doped pn junctions configured to allow electrons to tunnel between the subcells of a multijunction solar cell. Suitable methods for forming the tunnel junctions 136, 138 are well known in the art.

[0023] The tunnel junction layers 136 and 138, the nucleation layer 140, and the buffer layer 144 may comprise any suitable semiconductor material with various dopants and / or dopant concentrations in the different layers that provide the desired electrical properties, which may be the same or different as those used for the subcells 122, 124. Suitable semiconductor materials may include, for example, Group IV semiconductors such as single crystal silicon or germanium, or compound semiconductor materials such as III / V or I / IV heteroepitaxial layers. Any suitable III / V heteroepitaxial material may be used, for example, GaAs, GaInAs, or other III / V materials. Any suitable II / IV heteroepitaxial material (e.g., CdTe, CuInGaSe2) or other II / IV materials may be used. Techniques for depositing such layers are well known in the art, and any suitable technique may be used. For example, these layers may be epitaxially grown on any of the Group IV based substrates (e.g., Si or Ge) described herein. As is well known in the art, appropriate dopants can be added to these layers to provide desired electrical properties.

[0024] Nucleation layer 140 may be epitaxially grown on base substrate 102 to provide a suitable surface for growing subsequent epitaxial layers, such as buffer layer 144. The nucleation layer may have the same majority carrier type as patterned emitter 104. Although any suitable nucleation layer may be used, one example of a nucleation layer is gallium indium phosphide. Other suitable nucleation layers are known in the art.

[0025] The nucleation layer can have any desired thickness that enables the growth of a bulk heteroepitaxial layer thereon. Examples of suitable nucleation layer thicknesses can range from about 10 angstroms to about 500 angstroms, such as from about 50 angstroms to about 200 angstroms, or from about 70 angstroms to about 100 angstroms.

[0026] As shown in FIG. 2, a buffer layer 144 may be disposed between the nucleation layer 140 and the middle subcell 122. The buffer layer 144 may be epitaxially grown on the nucleation layer 140 and may have the same majority carrier type as the patterned emitter 104. The buffer layer 144 may include any group IV semiconductor or compound semiconductor material as taught herein. By way of example, both the nucleation layer 140 and the buffer layer 144 include a group III / V material such as GaAs, GaInAs, or other group III / V material doped as described herein to provide the desired electrical conductivity. Techniques for epitaxially growing the buffer layer 144 are well known in the art. Any suitable epitaxial growth technique may be used.

[0027] The growth conditions of the nucleation layer 140 and the buffer layer 144 can be selected to control the diffusion of desired dopants, such as Ga, In, or As, into the base substrate 102 during the growth of these layers. In particular, when growth of III / V materials is utilized to form the buffer layer 144, the nucleation layer can be selected to allow diffusion through one of the group III or group V elements while forming a selective barrier against the other element. Thus, the nucleation layer 140 can allow group III elements, which may function as p-type dopants, to diffuse through the nucleation layer 140 into the base substrate 102 to form the passivation layer 132 while blocking the diffusion of group V elements. Alternatively, the nucleation layer 140 can allow group V elements, which may function as n-type dopants, to diffuse through the nucleation layer 140 into the base substrate 102 to form the passivation layer 132 while forming a barrier against group III elements. The nucleation and buffer layer growth conditions are selected such that the amount of dopant diffusion into the base substrate is not so great as to counterdope the doped well regions 106 and change the majority carrier type of the doped well regions 106 (e.g., if the doped well regions 106 are n-type, the p-type group-III dopant diffusion is small enough so that the n-type emitters do not return to the p-type regions, and vice versa). It is within the skill of one in the art to select the appropriate nucleation material to provide the desired control of diffusion of group-III and / or group-V elements.

[0028] A limitation of solar cells with the patterned emitter structures of the present disclosure is the potential for reduced lateral current collection and increased diffusion current between the patterned emitter well regions, as indicated by the arrows in FIG. 4. To remedy this potential problem, the nucleation layer 140 and / or the buffer layer 144 can be doped with a sufficiently high dopant concentration to provide a desired level of lateral conductivity. The desired level of lateral conductivity depends on several factors, including the spacing between the patterned emitters, the specific design of the emitters, and the application of the solar cell (e.g., space solar cells vs. concentrator solar cells). Increased conductivity (or reduced resistivity) in the layers above the patterned emitters translates to reduced resistance to lateral current flow from the emitters to the superstructure 120, which in turn can reduce series resistance losses and increase efficiency of the solar cell. As an example, the nucleation layer 140 and / or the buffer layer 144 may be doped with a sufficient concentration of a dopant such that the lateral conductivity is high enough that the patterned emitter does not contribute significantly to the overall series resistance loss of the cell. The resistivity of the nucleation layer and / or the buffer layer may range from about 0.1 mΩ·cm to about 10,000 mΩ·cm, such as from about 0.5 mΩ·cm to about 500 mΩ·cm.

[0029] A cap layer 148 may be formed on the top subcell. This cap layer 148 performs the function of the transition between metal and semiconductor. The cap layer 148 may be low resistance and provide an ohmic contact (non-rectifying) between the metal and the semiconductor. This reduces losses due to parasitic resistance or unintended diode behavior in the reverse direction of the solar cell, which may reduce the efficiency of the device. The cap layer 148 may also provide a place for mechanical attachment of contacts (external cables) to the semiconductor due to the intervening metal layer. Such cap layers for use in solar cells are generally known in the art.

[0030] With reference to Figure 2, the rear electrical contact 126 and the front electrical contact 128 can be deposited using any suitable technique. Additionally, other configurations of positive and negative can be employed. For example, instead of the front and rear contacts of Figure 2, both the positive and negative contacts could potentially be formed on the front side of the device, or could be formed on the back side of the device, such as by etching contact vias to make electrical contact to one or more layers within the device. It is within the skill of one in the art to determine the appropriate technique for forming such solar cell contacts.

[0031] In addition to or instead of the rear electrical contact 126, a reflective layer can be formed adjacent to the base substrate 102. The reflective layer 127 can be deposited, for example, between the base substrate 102 and the back electrode 126. In some cases, the rear contact 126 can include a portion of the reflective layer. Suitable reflective layers and methods for making such structures for solar cells are well known in the art. For example, in a Si device, it is known to deposit a thin Al2O3 layer between the silicon and the rear contact of the device. This acts as a back reflector for the light being emitted from the solar cell.

[0032] The buffer layers, tunnel junctions, subcells, and optional nucleation layers of the superstructure 120 may be monolithic, meaning that the layers are all formed as part of a single stack of subcells that share a set of electrical contacts. Alternatively, each subcell of the multijunction solar cell stack can have its own set of contacts to form a tandem structure, as is commonly known in the art. In one example, the tandem solar cell structure does not use a tunnel junction as part of the superstructure 120.

[0033] The superstructure 120 may include one or more organic subcells. For example, each of the one or more subcells includes a perovskite material. An example organic subcell is shown in FIG. 5, where a conductive layer 150 is disposed between the base substrate 102 and the organic subcell. The base substrate 102, including the patterned emitter 104 and the passivation layer 132, is as described above with reference to FIG. 2. In one example, the group IV semiconductor material used as the base substrate 102 is single crystal silicon, such as n-doped or p-doped silicon, although single crystal germanium substrates can also be used. The conductive layer 150 may include any suitable conductive material, including doped or intrinsically conductive materials. The material of the conductive layer 150 may have a majority carrier type opposite to that of the base substrate 102 (e.g., if the background dopant in the base substrate 102 is n-type, the conductive layer 150 includes a p-type material, and vice versa). Selecting a suitable conductive material for conductive layer 150 is within the purview of one skilled in the art.

[0034] An organic hole transport medium ("HTM") 152 is disposed over the conductive layer 150. One example of an organic hole transport medium is Spiro-OmeTAD, although any other suitable organic HTM may be used. A semiconducting perovskite layer 154 is disposed over the hole transport medium 152. Any other suitable A semiconducting perovskite material may be used, for example, a halide organometallic perovskite material such as lead methylamine iodide ("MAPbI3"). A second conductive layer 156, which functions as an emitter, is disposed over the semiconducting perovskite layer 154. In general, the conductive layer 146 may include any suitable conductive material, including either n-type or p-type materials. For example, the second conductive layer 156 may include an n-type conductive metal oxide material, such as indium tin oxide ("ITO"), aluminum tin oxide ("ATO"), aluminum doped ITO), or combinations thereof. The second conductive layer 156 has the same majority carrier type as the background dopant of the base substrate 102 (e.g., n-type if the background dopant is n-type, or p-type if the background dopant is p-type). The second conductive layer 156 may optionally be transparent to visible light, such as when it comprises a conductive metal oxide such as ITO or ATO. The front contact 128 may be disposed on the second conductive layer 156.

[0035] The multijunction solar cell 100 of FIG. 6 and the solar cell of FIG. 5 are similar, except that the solar cell of FIG. 6 includes a second passivation layer 160 disposed between the base substrate 102 and one or more subcells of the superstructure 120. In general, the second passivation layer 160 may be used in the case of a non-epitaxial top junction. For example, the second passivation layer 160 may be disposed directly on the first passivation layer 132 and the patterned emitter 104. Alternatively, the second passivation layer 160 may be used instead of the passivation layer 132. The second passivation layer 160 may serve to reduce or prevent carrier recombination in the background doped regions of the base substrate 102, similar to the function of the passivation layer 132. The second passivation layer 160 may include any suitable electrically insulating material that is compatible with the multijunction solar cell 100. For example, the second passivation layer 160 may include an insulating material selected from oxides such as aluminum oxide (Al2O3), sapphire, microcrystalline silicon, or amorphous silicon. Conductive vias 162 extend through the second passivation layer 160 and electrically connect each of the multiple doped well regions 106 of the patterned emitter 104 with one or more subcells.

[0036] Although the patterned emitter 104 is described herein as being formed in the bottom subcell of the base substrate 102, the concept is general and can be applied to any subcell in the stack. For example, the patterned emitter 104 can be formed in the epitaxially grown layers of subcells 122 and 124, as shown in FIG. 9. To form the emitter, the epitaxial process can be stopped at a desired location in the stack where the emitter is positioned and then the emitter can be patterned. After the emitter is formed, the epitaxial growth continues to form the top subcell in a multi-stage epitaxial growth process. This process is repeated as each emitter is formed.

[0037] 2-6 and 9 of the present disclosure show various device elements, including substrates, doped regions, and layers, of the multijunction solar cells of the present disclosure. Each of the device elements, including any substrate, doped region, and / or layer, may be in direct contact with any other device element shown adjacent in the figures. Alternatively, any two or more device elements depicted adjacent to one another may not be in direct contact, but may have intervening device elements, not shown, between them. The terms "on" and "over" as used herein to describe the relationship between device elements are broadly defined to include intervening device elements, and thus do not require direct physical contact or any particular spatial relationship (e.g., a layer that is disposed "on" a substrate may be disposed above, below, or to the side of the substrate, and one or more intervening layers may be present between the layer and the substrate). The phrases "directly" or "in direct contact" are defined to mean that there is direct physical contact.

[0038] As illustrated in the flow diagram of FIG. 7, the present disclosure also relates to a method of preparing a base substrate 102 for multi-junction solar cell fabrication. The method includes providing an initial monocrystalline substrate including a group IV semiconductor and a background dopant of a first carrier type. The substrate includes a first major surface and a second major surface opposite the first major surface. Such group IV semiconductor substrates are well known and are readily available, for example, in wafer form. A surface of the substrate may be optionally prepared for processing by any desired method, including cleaning the substrate, removing native oxides, and the like.

[0039] A patterned emitter 104 is then formed on the first surface of the substrate. Any suitable technique may be used to form the doped well regions 106 of the patterned emitter 104. For example, dopants may be introduced into the base substrate 102 by masking and depositing a dopant material, by printing a dopant material, or by ion implantation techniques to form the doped well regions 106. Either during or after the introduction of the dopants into the base substrate, one or more annealing processes may be performed to provide the desired diffusion of the dopants. As an example of a doping technique, the base substrate 102 may be patterned with a mask layer, such as a protective oxide, nitride, or photoresist. A plurality of doped well regions 106 are then formed by introducing a second carrier type dopant into the group IV semiconductor material of the base substrate 102, such as by depositing and diffusing the dopant in areas of the substrate not over which the mask layer is formed. In another example, a dopant paste (e.g., a phosphorus-doped paste) is screen printed onto a base substrate in a desired well region pattern and then annealed to diffuse the dopant from the paste into the substrate. Other suitable techniques, including dopants and / or laser-induced diffusion techniques, such as inkjet printing of nanoparticle-containing inks, can be used to form the doped well regions. Such techniques are generally known in the art.

[0040] The first major surface of the substrate is then optionally prepared for the formation of additional solar cell structures. For example, if additional subcells are to be formed in the monocrystalline III-V semiconductor stack deposited on the base substrate, the base substrate may be polished to an epitaxial-ready state using any suitable technique, such as chemical mechanical polishing. Alternatively, polishing may occur prior to the formation of the patterned emitter 104. The polished substrate may then be chemically treated to clean the substrate and remove native oxide from the surface including the patterned emitter. The prepared base substrate may then be maintained in an epitaxial-ready state, optionally by storing it in an inert atmosphere to inhibit the growth of native oxide thereon.

[0041] Processing of the base substrate may continue to form one or more additional solar cell device structures on the base substrate to complete the fabrication of the multijunction solar cell, or the base substrate may be provided to a third party solar cell manufacturer to complete the fabrication of the multijunction solar cell.

[0042] Formation of the passivation layer 132 may occur before, during, or after deposition of the superstructure 120. The passivation layer 132 is in a doped region in the group IV semiconductor material of the base substrate 102. Any suitable method for forming such a doped region may be used. As an example, p-type or n-type dopants may be diffused from the nucleation layer 140 and / or the buffer layer 144 into the base substrate 102 to form the passivation layer 132. As mentioned above, the dopant is the same dopant type (e.g., p-type or n-type) as that used as the background dopant of the base substrate 102.

[0043] FIG. 8 is a graph of the estimated voltage for a germanium subcell with fewer emitter contacts that are considered ideal under III / V multijunction solar cells. This estimate is based on the same emitter pattern shown in FIG. 3, where the emitters are circular dots with a diameter (D) of 50 microns at a depth of 0.7 microns. The pitch (the distance between the centers of adjacent dots) is varied from about 2 times the diameter to about 10 times the diameter. As can be seen in FIG. 8, as the pitch increases (indicating a decrease in the emitter volume), the subcell voltage (Voc) increases. It is believed that the decrease in emitter volume reduces Shockley-Read-Hall recombination throughout the emitter, thereby increasing the subcell voltage. The increase in voltage assumes that the interfacial recombination velocity ("So") between the diffusion regions is low (e.g., So approximately equal to 0 cm / sec). The practical effect of this approach is to increase the efficiency of converting sunlight into electrical power, thereby making the solar cell more economical.

[0044] Additionally, the disclosure includes embodiments according to the following provisions: Clause 1. A multijunction solar cell comprising: a base substrate comprising a Group IV semiconductor and a dopant of a first carrier type; a patterned emitter formed on a first surface of the base substrate, the patterned emitter comprising a plurality of well regions doped in the Group IV semiconductor with a dopant of a second carrier type, the base substrate including the patterned emitter forming a first solar subcell; and a superstructure comprising one or more additional solar subcells above the first solar subcell. Clause 2. The multijunction solar cell of clause 1, further comprising a passivation layer on the first surface of the base substrate, the passivation layer being disposed between the patterned emitter well regions and comprising a dopant of a first carrier type. Clause 3. The multijunction solar cell of clause 1 or 2, wherein the Group IV semiconductor comprises a material selected from germanium and silicon. Clause 4. The multijunction solar cell of any one of clauses 1 to 3, wherein the dopant of the first carrier type is a p-type dopant and the dopant of the second carrier type is an n-type dopant. Clause 5. The multijunction solar cell of any one of clauses 1 to 4, wherein the dopant of the first carrier type is an n-type dopant and the dopant of the second carrier type is a p-type dopant. Clause 6. A multijunction solar cell according to any one of clauses 1 to 5, wherein the patterned emitter well regions are arranged in an array. Clause 7. The multijunction solar cell of any one of clauses 1 to 6, wherein the base substrate comprises monocrystalline germanium and one or more additional solar subcells, each having a pn junction formed in a III / V heteroepitaxial layer. Clause 8. The multijunction solar cell of clause 7, further comprising a tunnel junction formed in the III / V heteroepitaxial layer between the patterned emitter and one or more additional solar subcells.

[0045] Clause 9. The multijunction solar cell of clause 7 or 8, further comprising a current spreading layer between the patterned emitter and one or more additional solar subcells. Clause 10. A multijunction solar cell according to any one of clauses 1 to 9, wherein the or each of the additional solar sub-cells comprises a p-n junction formed from a semiconducting perovskite material. Clause 11. The multijunction solar cell of clause 10, further comprising a conductive layer between the patterned emitter and the one or more additional solar subcells. Clause 12. The multijunction solar cell of clause 10 or 11, further comprising a passivation layer between the base substrate and the one or more additional solar subcells, the passivation layer comprising an insulating material, and conductive vias extending through the passivation layer to electrically connect each of the multiple well regions of the patterned emitter with the one or more additional solar subcells. Clause 13. The multijunction solar cell of any one of clauses 1 to 12, further comprising a plurality of contacts arranged to connect the multijunction solar cell to a circuit. Clause 14. A method for manufacturing a multijunction solar cell, the method including: providing a base substrate comprising a Group IV semiconductor and a dopant of a first carrier type, the base substrate having a first major surface and a second major surface opposite the first major surface; forming a patterned emitter on the first major surface of the base substrate, the patterned emitter comprising a plurality of well regions doped in the Group IV semiconductor with a dopant of the second carrier type, the base substrate including the patterned emitter forming a first solar subcell; and forming a superstructure over the first solar subcell, the superstructure including one or more additional solar subcells. Clause 15. The method of clause 14, wherein the one or more additional solar subcells each include a pn junction formed in a III / V heteroepitaxial layer. Clause 16. The method of clause 15, further comprising forming a tunnel junction in the III / V heteroepitaxial layer between the patterned emitter and one or more additional solar subcells. Clause 17. The method of clause 15, further comprising a current spreading layer between the patterned emitter and the one or more additional solar subcells. Clause 18. The method of any one of clauses 14 to 17, wherein the or each of the additional solar subcells comprises a pn junction formed from a semiconducting perovskite material. Clause 19. The method of clause 18, further comprising a conductive layer between the patterned emitter and the one or more additional solar subcells. Clause 20. The method of clause 18 or 19, further comprising a passivation layer between the base substrate and the one or more additional solar subcells, the passivation layer comprising an insulating material, and conductive vias extending through the passivation layer to electrically connect each of the multiple well regions of the patterned emitter with the one or more additional solar subcells. Clause 21. A method for manufacturing a solar cell substrate, the method including: providing a base substrate comprising a Group IV semiconductor and a dopant of a first carrier type, the base substrate having a first major surface and a second major surface opposite the first major surface; forming a patterned emitter on the first major surface of the base substrate, the patterned emitter comprising a plurality of well regions doped in the Group IV semiconductor with a dopant of the second carrier type, the base substrate including the patterned emitter forming a first solar subcell; and preparing the first major surface of the base substrate to receive an epitaxial layer. Clause 22. The method of clause 21, wherein preparing the first major surface of the base substrate to receive the epitaxial layer includes polishing the base substrate; chemically treating the base substrate after polishing; and storing the chemically treated base substrate in an inert atmosphere to inhibit growth of a native oxide thereon. Clause 23. The method of clause 21 or 22, wherein the base substrate comprises single crystal germanium.

[0046] Clause 24. The method of any one of clauses 21 to 23, further comprising providing the base substrate to a solar cell manufacturer for manufacturing a solar cell. Clause 25. A solar cell substrate comprising: a base substrate comprising a Group IV semiconductor and a dopant of a first carrier type, the base substrate having a first major surface and a second major surface opposite the first major surface, the first major surface being capable of epitaxial growth; and a patterned emitter formed on the first major surface of the base substrate, the patterned emitter comprising a plurality of well regions doped in the Group IV semiconductor with a dopant of the second carrier type, the base substrate including the patterned emitter forming a first solar subcell. Clause 26. The solar cell substrate of clause 25, wherein the base substrate is single crystal germanium.

[0047] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the present disclosure are approximations, the numerical values ​​set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein should be understood to include any and all subranges subsumed therein.

[0048] Although the present teachings have been described with one or more embodiments, changes and / or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. Also, while a particular feature of the present teachings may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of other embodiments, if desired and advantageous for any given or specific function. Still further, in any of the detailed description and claims, to the extent that the terms "including," "includes," "having," "has," "with," or variations thereof are used, such terms are intended to be as inclusive as the term "comprising." Furthermore, in the discussion and claims herein, the term "about" indicates that the recited values ​​may be somewhat altered, provided that such changes do not cause incompatibility of the process or structure for the intended purpose described herein. Finally, "exemplary" indicates that the description is used as an example, rather than implying ideality.

[0049] It will be appreciated that the above-disclosed and other features and functions, or alternatives thereof, may be combined into many other different systems or applications. Various presently unforeseen or unanticipated alternatives, modifications, variations or improvements thereon may be subsequently made by those skilled in the art, but are encompassed by the following claims.

Claims

1. A method for manufacturing a solar cell substrate, comprising the steps of: providing a base wafer (102), the base wafer (102) comprising a Group IV semiconductor and a dopant of a first carrier type in a background doped region of the base wafer, the base wafer having a first major surface and a second major surface opposite the first major surface; forming a patterned emitter (104) on the first major surface of the base substrate, the patterned emitter comprising a plurality of well regions (106) doped with a dopant of a second carrier type in the group IV semiconductor, the base substrate including the patterned emitter forming a solar subcell, the first major surface of the base substrate (102) including a passivation layer between the plurality of well regions and having a thickness less than the plurality of well regions (106), the passivation layer including the group IV semiconductor doped with a dopant of the first carrier type at a dopant concentration greater than a dopant concentration of the background doped regions; and preparing the first major surface of the base substrate to receive an epitaxial layer after forming the patterned emitter, the Group IV semiconductor being exposed so as to be epitaxially grown directly on both the well region and the passivation layer; Including, Preparing the first major surface of the base substrate (102) to receive an epitaxial layer, polishing the base substrate; chemically treating the base substrate after polishing; and storing said chemically treated base substrate in an inert atmosphere to inhibit growth of native oxide thereon. A method comprising:

2. The method of claim 1 , wherein the base substrate (102) comprises single crystal germanium.

3. The method of claim 1 or 2, further comprising providing the base substrate (102) to a solar cell manufacturer for manufacturing a solar cell.

4. The method of claim 1 , wherein the plurality of well regions of the patterned emitter are arranged in an array.

5. The method of claim 1 , wherein the plurality of well regions (106) have a top view shape selected from a circle, a square, a rectangle, a checkerboard, a line, and a crossed line.

6. The method of claim 1 , wherein the plurality of well regions (106) have circular upper surfaces.

7. The method of claim 1 , wherein the distance between adjacent well regions of the patterned emitter is less than the diffusion length of minority carriers in the base substrate.

8. The method of claim 1 , wherein the plurality of well regions are separated by the background doped regions.

9. The method of claim 1 , further comprising epitaxially growing a nucleation layer on the base substrate.

10. A solar cell substrate, a base substrate (102) comprising a Group IV semiconductor and a dopant of a first carrier type in a background doped region of the base substrate, the base substrate having a first major surface and a second major surface opposite the first major surface, the first major surface being capable of epitaxial growth; a patterned emitter (104) formed on the first major surface of the base substrate, the patterned emitter comprising a plurality of well regions (106) doped in the group IV semiconductor with a dopant of a second carrier type, the base substrate (102) including the patterned emitter forming a first solar subcell, the first major surface of the base substrate (102) including a passivation layer between the plurality of well regions (106) having a thickness less than the plurality of well regions (106), the passivation layer including the group IV semiconductor doped with a dopant of the first carrier type at a dopant concentration greater than a dopant concentration of the background doped region; Equipped with the group IV semiconductor is exposed so that it can be epitaxially grown directly on both the well region (106) and the passivation layer; Solar cell substrate.

11. The solar cell substrate of claim 10, wherein the base substrate (102) comprises single crystal germanium.

12. The solar cell substrate of claim 10 , wherein the plurality of well regions of the patterned emitter are arranged in an array.

13. The solar cell substrate of claim 10 , wherein the plurality of well regions have a top surface shape selected from a circle, a square, a rectangle, a checkerboard, a line, and a crossed line.

14. The solar cell substrate of claim 10 , wherein the plurality of well regions have circular upper surfaces.

15. The solar cell substrate of claim 10 , wherein the distance between adjacent well regions of the patterned emitter is less than the diffusion length of minority carriers in the base substrate.

16. The solar cell substrate of claim 10 , wherein the well regions are separated by the background doped regions.

17. The solar cell substrate of claim 10 further comprising a nucleation layer epitaxially grown on the base substrate.

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