Information processing device and control method

Abstract

To provide an information processing apparatus that reduces data corruption in a SSD and ensures data readout from the SSD for a certain period of time when power is not being supplied.SOLUTION: An information processing apparatus 1 is configured with a multi-bit cell for storing multiple bit data in one memory cell, and comprises a SSD (Solid State Drive) that includes an electrically rewritable non-volatile storage unit, and a main control unit for executing processing based on data stored in the SSD. The SSD is a storage control unit for controlling access to the non-volatile storage unit, and includes a memory control unit 420 for executing storage processing capable of changing the variation width of threshold voltages when storing the multiple bit data in the multi-bit cell.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an information processing device and a control method. [Background technology]

[0002] In recent years, personal computers and other information processing devices equipped with SSDs (Solid State Drives) instead of HDDs (Hard Disk Drives) have become widespread (see, for example, Patent Document 1). In addition, in order to increase capacity, some SSDs are known to be equipped with flash memory using memory cells (hereinafter referred to as multi-bit cells) capable of storing data equivalent to multiple bits per memory cell, such as MLC (Multiple Level Cell), TLC (Triple Level Cell), and QLC (Quad Level Cell). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-154674 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in conventional information processing devices, the use of multiple bit cells allows the SSD to have a large capacity, but the data retention (data retention period) tends to be shorter. In addition, in conventional information processing devices, even if the EOL (End Of Life) is reached due to replacement with a new information processing device, for example, it may be required to guarantee that data can be read from the SSD for a certain period of time. However, in conventional information processing devices, the use of multiple bit cells may make it impossible to guarantee that data can be read from the SSD for a certain period of time in a state where power is not supplied, for example, after the EOL is reached.

[0005] The present invention has been made to solve the above problems, and its purpose is to provide an information processing device and a control method that can reduce data corruption in an SSD when power is not supplied and ensure that data can be read from the SSD for a certain period of time. [Means for solving the problem]

[0006] In order to solve the above problem, one aspect of the present invention is a solid state drive (SSD) including an electrically rewritable non-volatile memory unit configured with multi-bit cells that store multiple bits of data in one memory cell, and a main control unit that executes processing based on data stored in the SSD, the SSD including a memory control unit that controls access to the non-volatile memory unit and executes a storage process that can change the variation width of a threshold voltage when storing the multiple bits of data in the multi-bit cells. The storage control unit stores the multiple bits of data in a specific area set by the main control unit among the storage areas of the non-volatile storage unit so that the variation width of the threshold voltage is narrower than in other areas, and when the device itself reaches EOL (End Of Life), the main control unit sets the specific area in the non-volatile storage unit and stores important data that needs to be read out later in the specific area. It is an information processing device.

[0008] Furthermore, one aspect of the present invention is such that, in the above-mentioned information processing device, the SSD includes a position information storage unit that stores logical position information of the specific area in the non-volatile storage unit, and when the storage control unit stores data at a designated logical position, which is a logical position specified by the main control unit, the storage control unit determines whether the designated logical position is the specific area based on the logical position information stored in the position information storage unit, and if the designated logical position is the specific area, stores data at the designated logical position using a high-quality storage mode in which the variation range of the threshold voltage is narrower than in a normal storage mode.

[0009] In addition, in one aspect of the present invention, in the above-mentioned information processing device, when the specified logical location is not the specific area, the storage control unit may execute the storage process in the normal storage mode in which the variation range of the threshold voltage is wider than in the high-quality storage mode and the storage period, which is the period required for storage in the multiple-bit cells, is shorter than in the high-quality storage mode.

[0010] In addition, in one aspect of the present invention, in the above-mentioned information processing device, the memory control unit may perform, in the high-quality memory mode, an application process of applying a voltage to store data to the multiple bit cells for a predetermined period that is a division of the application period, a confirmation process of confirming whether the threshold voltage has become within a variation range of the threshold voltage after the application process, and a repetitive process of repeating the application process and the confirmation process until the threshold voltage becomes within the variation range of the threshold voltage.

[0012] Also, one aspect of the present invention is a control method for the information processing device described above, the information processing device including an SSD (Solid State Drive) including an electrically rewritable non-volatile storage unit configured by multi-bit cells that store multiple bits of data in one memory cell, and a main control unit that executes processing based on data stored in the SSD, the method including a step of a storage control unit of the SSD controlling access to the non-volatile storage unit, the step including a step of executing a storage process capable of changing a variation width of a threshold voltage when storing the multiple bits of data in the multi-bit cells. In the step, the storage control unit stores the multiple bits of data in a specific area set by the main control unit among the storage areas of the non-volatile storage unit so that the variation width of the threshold voltage is narrower than in other areas, and when the device itself reaches EOL (End Of Life), the main control unit sets the specific area in the non-volatile storage unit and stores important data that needs to be read out later in the specific area. It is a control method. Effect of the Invention

[0013] According to the present invention, it is possible to reduce data corruption in an SSD when power is not being supplied, and to ensure that data can be read from the SSD for a certain period of time. [Brief description of the drawings]

[0014] [Figure 1] 1 is a diagram illustrating an example of a main hardware configuration of an information processing device and an SSD according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a functional block diagram showing an example of a functional configuration of the information processing device according to the present embodiment. [Diagram 3] 2 is a diagram showing an example of an area of ​​an SSD of the information processing device according to the present embodiment. FIG. [Figure 4]11 is a diagram showing an example of Vth distribution in a normal storage mode of an SSD of the information processing device according to the present embodiment. FIG. [Diagram 5] 11 is a diagram showing an example of Vth distribution in a high-quality storage mode of an SSD of the information processing device according to the present embodiment. FIG. [Figure 6] 10 is a flowchart illustrating an example of a permanent partition setting process performed by the information processing device according to the present embodiment. [Figure 7] 11 is a flowchart showing an example of a storage process in an SSD by the information processing device according to the present embodiment. [Figure 8] 10 is a flowchart showing an example of a storage process in a high quality storage mode by the information processing device according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus and a control method according to an embodiment of the present invention will be described below with reference to the drawings.

[0016] FIG. 1 is a diagram illustrating an example of a main hardware configuration of an information processing device 1 and an SSD 40 according to the first embodiment. As shown in FIG. 1, the information processing device 1 is, for example, a notebook personal computer, and includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, an embedded controller 31, an input unit 32, a power supply circuit 33, and an SSD 40.

[0017] A CPU (Central Processing Unit) 11 executes various arithmetic processes under program control, and controls the information processing device 1 as a whole.

[0018] The main memory 12 is a writable memory used as a read area for the execution program of the CPU 11 or as a work area for writing processing data for the execution program. The main memory 12 is composed of, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. The execution program includes an OS (operating system), various drivers for operating peripheral devices, various services / utilities, application programs, etc.

[0019] Video subsystem 13 is a subsystem for implementing functions related to image display, and includes a video controller. This video controller processes drawing commands from CPU 11, writes the processed drawing information to a video memory, and also reads the drawing information from the video memory and outputs it to display unit 14 as drawing data (display data).

[0020] The display unit 14 is, for example, a liquid crystal display, and displays a display screen based on drawing data (display data) output from the video subsystem 13.

[0021] The chipset 21 includes controllers such as a Universal Serial Bus (USB), a Serial AT Attachment (Serial ATA), a Serial Peripheral Interface (SPI) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express bus, and a Low Pin Count (LPC) bus, and is connected to a plurality of devices. In FIG. 1, a BIOS memory 22 and an SSD 40 are connected to the chipset 21 as examples of devices. In this embodiment, the CPU 11 and the chip set 21 correspond to the main control unit 10.

[0022] The BIOS (Basic Input Output System) memory 22 is composed of an electrically rewritable non-volatile memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash ROM (flash memory). The BIOS memory 22 stores the BIOS and system firmware for controlling the embedded controller 31 and the like.

[0023] The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) regardless of the system state of the information processing device 1. The embedded controller 31 also has a power management function that controls the power circuit 33. The embedded controller 31 is composed of a CPU, ROM, RAM, etc. (not shown), and also has A / D input terminals for multiple channels, D / A output terminals, a timer, and digital input / output terminals. For example, an input unit 32 and a power circuit 33 are connected to the embedded controller 31 via these input / output terminals, and the embedded controller 31 controls the operations of these.

[0024] The input unit 32 is, for example, an input device such as a keyboard or a pointing device such as a touch pad.

[0025] The power supply circuit 33 includes, for example, a DC / DC converter, a charge / discharge unit, an AC / DC adapter, and the like, and converts, for example, a DC voltage supplied from an external power supply via the AC / DC adapter or from a battery into a plurality of voltages required to operate the information processing device 1. The power supply circuit 33 also supplies power to each unit of the information processing device 1 based on the control of the embedded controller 31.

[0026] The SSD (Solid State Drive) 40 is a memory drive device having a rewritable non-volatile memory, and stores an OS, various drivers, various services / utilities, application programs, and various data. The information processing device 1 executes various information processes using the data stored in the SSD 40. The SSD 40 is connected to the chipset 21 by, for example, a serial ATA or a PCI-Express bus. The SSD 40 also includes a plurality of flash memories 41 and an SSD controller 42 .

[0027] The flash memory 41 is, for example, a NAND flash memory. The flash memory 41 includes, for example, floating gate type memory cells, charge trap type memory cells that do not include a floating gate and store data by trapping electrons in a charge trap layer, and the like. The memory cells of the flash memory 41 are multi-bit cells that store multiple bits of data in one memory cell, such as MLC (Multiple Level Cell), TLC (Triple Level Cell), and QLC (Quad Level Cell). Here, the multi-bit cell is a memory cell that can store the equivalent of multiple bits in one memory cell by providing multiple data write thresholds.

[0028] The SSD controller 42 is, for example, a processor including a CPU, a ROM, a RAM, etc. (not shown), and performs overall control of the SSD 40. The SSD controller 42 performs, for example, control processing of a host interface (host I / F) with the chipset 21, control processing of a memory interface (memory I / F) with the flash memory 41, data management processing of the flash memory 41, and other processes.

[0029] The SSD controller 42 controls, for example, a storage process for storing data in a multi-bit cell (a write process for writing data) and a read process for reading data from a multi-bit cell.

[0030] Next, the functional configuration of the information processing device 1 according to the present embodiment will be described with reference to FIG. FIG. 2 is a functional block diagram showing an example of a functional configuration of the information processing device 1 according to the present embodiment.

[0031] 2, the information processing device 1 includes a main control unit 10, an SSD 40, and a storage unit 50. The SSD 40 includes an SSD storage unit 410 and a memory control unit 420.

[0032] The SSD storage unit 410 is a storage unit realized by, for example, the flash memory 41 of the SSD 40, and includes a management information storage unit 411, a mode information storage unit 412, and a data storage unit 413.

[0033] The management information storage unit 411 is, for example, a storage unit realized by the flash memory 41, and stores management information of the SSD 40. The management information storage unit 411 stores, for example, conversion table information between physical addresses and logical addresses (for example, LBA: Logical Block Addressing (logical location information)) of the flash memory 41, management information of free areas and used areas of the flash memory 41, and area range information indicating the range of a permanent partition area (LBA information (logical location information) of a permanent partition), which will be described later, and the like.

[0034] The mode information storage unit 412 is, for example, a storage unit realized by the flash memory 41, and stores write control information for a normal storage mode (normal write mode) and a high-quality storage mode (high-quality write mode) described later. The write control information includes, for example, the application period (application time) of the divided write voltage, the variation range (tolerance range) of Vth, and the like.

[0035] In the normal memory mode, the Vth variation range (tolerance range) is wider than that in the high-quality memory mode, and the write time required for writing is shorter. In the high-quality memory mode, the Vth variation range (tolerance range) is narrower than that in the normal memory mode, and the write time required for writing is longer.

[0036] The data storage unit 413 is, for example, a storage unit realized by the flash memory 41, and stores various data. The data storage unit 413 stores, for example, various data of the information processing device 1. Here, the data area of ​​the data storage unit 413 will be described with reference to FIG.

[0037] FIG. 3 is a diagram showing an example of an area of ​​the SSD 40 of the information processing device 1 according to the present embodiment. In the example shown in FIG. 3, the data storage unit 413 is allocated to an EFI area (Extensible Firmware Interface area), an OS area, a user data area, and a permanent partition.

[0038] The EFI area is an area A1 that stores EFI programs. The OS area is an area A2 that stores OS programs such as Windows (registered trademark). The user data area is an area A3 that stores various programs and data processed on the OS.

[0039] The permanent partition is, for example, an area A4 that is set when the information processing device 1 becomes EOL, and is a data area for storing important data that needs to be read out at a later date. The permanent partition is an example of a specific area, and is set by a main control unit described later.

[0040] Each area of ​​the data storage unit 413 can be accessed from the main control unit 10 using an LBA (logical block address). In the example shown in Fig. 3, an area A1 from LBA0 to LBAX1 is an EFI area, and an area A2 from LBAX1 to LBAX2 is an OS area. An area A3 from LBX2 to LBAX3 is a user data area, and an area A4 from LBAX3 to LBAX4 is a permanent partition (specific area).

[0041] 2, the memory control unit 420 (an example of a storage control unit) is a functional unit realized by, for example, causing a CPU (not shown) of the SSD controller 42 to execute a program stored in a ROM (not shown). The memory control unit 420 controls access to the SSD storage unit 410.

[0042] The memory control unit 420 executes a storage process capable of changing the variation width of Vth (threshold voltage) when storing multiple bits of data in a multiple bit cell of the SSD storage unit 410. The memory control unit 420 stores multiple bits of data in a permanent partition (specific area) set by the main control unit 10 among the storage areas of the SSD storage unit 410 so that the variation width of Vth is narrower than other areas. The memory control unit 420 includes an area setting processing unit 421 , a writing processing unit 422 , and a reading processing unit 423 .

[0043] The area setting processing unit 421 sets various partitions (storage areas) in response to a request from the main control unit 10. The area setting processing unit 421 stores the set partitions (storage areas) in the management information storage unit 411. The area setting processing unit 421 sets, for example, a permanent partition (specific area) in response to a request from the main control unit 10, and stores area range information (LBA range information) of the permanent partition in the management information storage unit 411.

[0044] The write processing unit 422 executes a storage process (write process) of data to a multi-bit cell of the SSD storage unit 410. The write processing unit 422 executes a storage process (write process) in which the Vth variation range and the write time required for writing are changed based on the setting information for each mode stored in the mode information storage unit 412. The write processing unit 422 has a normal storage mode and a high-quality storage mode. The write processing unit 422 executes a storage process in the high-quality storage mode for the above-mentioned permanent partition (specific area), and executes a storage process in the normal storage mode for other areas (e.g., user data area, etc.).

[0045] When storing data in a designated LBA, which is an LBA designated by the main control unit 10, the write processing unit 422 determines whether or not the designated LBA is a permanent partition, based on the LBA information stored in the management information storage unit 411. If the designated LBA is a permanent partition (specific area), the write processing unit 422 stores data in the designated LBA in a high-quality storage mode. If the designated LBA is not a permanent partition (specific area), the write processing unit 422 stores data in the designated LBA in a normal storage mode.

[0046] The write processing unit 422 performs an application process to apply a voltage for storing data to a plurality of bit cells for a predetermined period obtained by dividing the application period in the high quality storage mode, and performs a check process to check whether Vth is within the Vth variation range after the application process. The write processing unit 422 performs a repetitive process to repeat the application process and the check process until Vth is within the Vth variation range in the high quality storage mode.

[0047] The read processing unit 423 reads data of a specified LBA designated by the main control unit 10 based on the management information stored in the management information storage unit 411 , and outputs the data to the main control unit 10 .

[0048] Next, the difference between the above-mentioned normal storage mode and the high-quality storage mode in the storage process for a multi-bit cell will be described with reference to FIGS. FIG. 4 is a diagram showing an example of distribution of Vth in the normal storage mode of the SSD 40 of the information processing device 1 according to this embodiment.

[0049] In FIG. 4, the horizontal axis of the graph indicates Vth when a storage process (write process) corresponding to each data is performed in the normal storage mode, and the vertical axis indicates the number of cells. 4, waveform W11 shows the Vth distribution when data "001" is stored in a multi-bit cell in the normal storage mode, waveform W12 shows the Vth distribution when data "010" is stored in a multi-bit cell in the normal storage mode, waveform W13 shows the Vth distribution when data "011" is stored in a multi-bit cell in the normal storage mode, and waveform W14 shows the Vth distribution when data "100" is stored in a multi-bit cell in the normal storage mode.

[0050] The write processing unit 422 executes data storage processing in the normal storage mode according to the write data (storage data) with a distribution having a Vth variation width D1 as shown by waveforms W11 to W14 in FIG.

[0051] Furthermore, when reading data from a multi-bit cell, the read processing unit 423 determines the data to be "001" if Vth is between voltages Vt1 and Vt2, and determines the data to be "010" if Vth is between voltages Vt2 and Vt3. Furthermore, when reading data from a multi-bit cell, the read processing unit 423 determines the data to be "011" if Vth is between voltages Vt3 and Vt4, and determines the data to be "100" if Vth is between voltages Vt4 and Vt5.

[0052] Waveform W13E shows an example in which Vth has shifted downward due to degradation of the multi-bit cell or the passage of time since data was written. In this case, Vth in some multi-bit cells falls below voltage Vt3, causing data corruption.

[0053] FIG. 5 is a diagram showing an example of distribution of Vth in the high quality storage mode of the SSD 40 of the information processing device 1 according to this embodiment.

[0054] In FIG. 5, the horizontal axis of the graph indicates Vth when a storage process (write process) corresponding to each data is performed in the high quality storage mode, and the vertical axis indicates the number of cells. 5, waveform W21 shows the Vth distribution when data "001" is stored in multiple bit cells in the high quality storage mode, waveform W22 shows the Vth distribution when data "010" is stored in multiple bit cells in the high quality storage mode, waveform W23 shows the Vth distribution when data "011" is stored in multiple bit cells in the high quality storage mode, and waveform W24 shows the Vth distribution when data "100" is stored in multiple bit cells in the high quality storage mode.

[0055] The write processing unit 422 executes data storage processing in the high-quality storage mode according to the write data (storage data) with a distribution having a Vth variation width D2 as shown by waveforms W21 to W24 in Fig. 5. Note that the Vth variation width D2 in the high-quality storage mode is narrower than the Vth variation width D1 in the normal storage mode.

[0056] 2, the storage unit 50 is, for example, a storage unit realized by the main memory 12 or the SSD 40, and stores various information used by the information processing device 1. The storage unit 50 includes an area range storage unit 51.

[0057] The area range storage unit 51 is, for example, a storage unit realized by the main memory 12, and stores information indicating the LBA range of the above-mentioned permanent partition (specific area).

[0058] The main control unit 10 is a functional unit realized by the CPU 11 and the chipset 21 executing a program stored in the main memory 12, and executes various processes based on the OS. The main control unit 10 executes various processes based on data stored in the SSD 40, for example. The main control unit 10 includes an AP processing unit 101 and an SSD device driver unit 102.

[0059] The AP processing unit 101 is a functional unit that processes application programs executed on the OS. For example, when the information processing device 1 (its own device) becomes EOL, the AP processing unit 101 sets a permanent partition (specific area) in the SSD storage unit 410 of the SSD 40, and stores important data that needs to be read later in the permanent partition (specific area).

[0060] When the AP processing unit 101 sets a permanent partition (specific area), it stores information indicating the LBA range of the permanent partition (specific area) in the area range storage unit 51. Furthermore, when writing important data to the permanent partition (specific area), the AP processing unit 101 recognizes the LBA range of the permanent partition (specific area) based on the information stored in the area range storage unit 51. The AP processing unit 101 accesses the SSD 40 via an SSD device driver unit 102, which will be described later.

[0061] The SSD device driver unit 102 is a functional unit that realizes a device driver for accessing the SSD 40. The SSD device driver unit 102 transmits a write request to the SSD 40 to store (write) data of a specified LBA, and stores the data in the specified LBA. The SSD device driver unit 102 also transmits a read request to the SSD 40 to read data of the specified LBA, and reads the data of the specified LBA.

[0062] Next, the operation of the information processing device 1 according to the present embodiment will be described with reference to the drawings. FIG. 6 is a flowchart showing an example of a permanent partition setting process performed by the information processing device 1 according to this embodiment.

[0063] 6, the main control unit 10 of the information processing device 1 first receives a specified range of a permanent partition and stores it in the area range storage unit 51 (step S101). The AP processing unit 101 of the main control unit 10 stores, for example, the range of a permanent partition received from the input unit 32 in the area range storage unit 51.

[0064] Next, the AP processing unit 101 requests the SSD 40 to generate a permanent partition (step S102). The AP processing unit 101 requests the SSD device driver unit 102 to generate a permanent partition, and the SSD device driver unit 102 transmits a request to the SSD 40 to generate a permanent partition.

[0065] Next, the SSD 40 creates a permanent partition area (step S103). The area setting processing unit 421 of the SSD 40 creates a permanent partition area in response to a permanent partition creation request received from the SSD device driver unit 102. The area setting processing unit 421 creates a permanent partition area by storing the LBA range of the permanent partition area specified in the creation request in the management information storage unit 411.

[0066] Next, the AP processing unit 101 saves the data in the area of ​​the permanent partition (step S104). The AP processing unit 101 transmits a request to the write processing unit 422 of the SSD 40 via the SSD device driver unit 102 to store important data in the LBA of the range of the permanent partition stored in the area range storage unit 51. The write processing unit 422 stores the important data in the area of ​​the permanent partition of the SSD storage unit 410. After the process of step S104, the AP processing unit 101 ends the process.

[0067] Next, a storage process in the SSD 40 by the information processing device 1 will be described with reference to FIG. FIG. 7 is a flowchart showing an example of a storage process in the SSD 40 by the information processing device 1 according to the present embodiment.

[0068] As shown in FIG. 7, the memory control unit 420 of the SSD 40 judges whether or not the LBA designated for writing (designated LBA) is within the range of a permanent partition in response to a storage request (write request) from the main control unit 10 (step S201). The write processing unit 422 of the memory control unit 420 judges whether or not the designated LBA is within the range of a permanent partition based on information indicating the range of the LBA of the permanent partition stored in the management information storage unit 411. If the designated LBA is within the range of the permanent partition (step S201: YES), the write processing unit 422 advances the process to step S202. If the designated LBA is outside the range of the permanent partition (step S201: NO), the write processing unit 422 advances the process to step S203.

[0069] In step S202, the write processing unit 422 executes a storage process (write process) in the high quality storage mode. The write processing unit 422 acquires setting information of the high quality storage mode from the mode information storage unit 412, and executes a storage process (write process) in the high quality storage mode as shown in Fig. 5 based on the setting information. After the process of step S202, the write processing unit 422 ends the process.

[0070] In addition, in step S203, the write processing unit 422 executes a storage process (write process) in a normal storage mode. The write processing unit 422 acquires setting information for the normal storage mode from the mode information storage unit 412, and executes a storage process (write process) in the normal storage mode as shown in Fig. 4 based on the setting information. After the process of step S203, the write processing unit 422 ends the process.

[0071] Next, the storage process in the high quality storage mode, which is the process in step S202 described above, will be described in detail with reference to FIG. FIG. 8 is a flowchart showing an example of storage processing in the high quality storage mode by the information processing device 1 according to this embodiment.

[0072] 8, the write processing unit 422 of the memory control unit 420 applies a write voltage for a set predetermined period to write data into a memory cell (step S301). The write processing unit 422 applies the write voltage to a multi-bit cell of a specified LBA for the application period (predetermined period) of the high quality storage mode stored in the mode information storage unit 412.

[0073] Next, the write processing unit 422 reads the data and detects Vth (step S302). The write processing unit 422 executes a read check to detect the written Vth.

[0074] Next, the write processing unit 422 judges whether or not the Vth is within the range of the variation width of the Vth according to the data (step S303). The write processing unit 422 judges whether or not the detected Vth is within the range of the variation width of the Vth according to the write data (within the allowable range) (confirmation process). If the detected Vth is within the range of the variation width of the Vth according to the write data (step S303: YES), the write processing unit 422 ends the storage process (write process). If the detected Vth is not within the range of the variation width of the Vth according to the write data (step S303: NO), the write processing unit 422 returns the process to step S301.

[0075] In this way, the write processing unit 422 repeats the processes of steps S301 and S302 until Vth falls within the range of the Vth variation width according to the write data. As a result, the write processing unit 422 executes writing with the Vth variation width D2 as shown in FIG.

[0076] In the normal storage mode, the write processing unit 422 may widen the range of the predetermined period and the variation width of Vth compared to the high quality storage mode, and execute the same process as that shown in Fig. 8. In the normal storage mode, the write processing unit 422 may execute the storage process (write process) in a preset application period of one write voltage.

[0077] As described above, the information processing device 1 according to this embodiment includes an SSD 40 and a main control unit 10. The SSD 40 is configured with multi-bit cells that store multiple bits of data in one memory cell, and includes an electrically rewritable SSD storage unit 410 (non-volatile storage unit). The main control unit 10 executes processing based on the data stored in the SSD 40. The SSD 40 includes a memory control unit 420 (storage control unit) that controls access to the SSD storage unit 410, and the memory control unit 420 executes storage processing that can change the variation width of Vth (threshold voltage) when storing multiple bits of data in the multi-bit cells.

[0078] As a result, the information processing device 1 according to this embodiment can execute a storage process that can change the variation width of Vth (threshold voltage) when storing multiple bits of data in a multiple bit cell, and therefore, for example, it is possible to switch to a high-quality storage process depending on the storage location, and data retention (data retention period) can be extended. Therefore, the information processing device 1 according to this embodiment can reduce data corruption in the SSD and guarantee data reading of the SSD 40 for a certain period of time in a state where power is not being supplied, such as after EOL.

[0079] In addition, in a conventional information processing device, when power is supplied, a management process is performed to periodically check and correct data corruption in a multi-bit cell, but when power is not supplied, such a management process is not performed. Therefore, in the conventional information processing device, it is difficult to guarantee that data can be read from the SSD 40 for a certain period of time when power is not supplied, for example, after EOL. In contrast, the information processing device 1 according to the present embodiment can guarantee that data can be read from the SSD 40 for a certain period of time when power is not supplied by switching to a high-quality storage process.

[0080] Furthermore, in this embodiment, the memory control unit 420 stores multiple bits of data in a permanent partition (specific area) set by the main control unit 10 within the memory area of ​​the SSD storage unit 410 so that the Vth variation range is narrower than in other areas.

[0081] As a result, the information processing device 1 according to this embodiment sets a permanent partition (specific area) and makes the Vth variation range narrower for the permanent partition (specific area) than for other areas, thereby reducing data corruption in the SSD in the permanent partition (specific area).

[0082] Furthermore, in this embodiment, the SSD 40 includes a management information storage unit 411 (position information storage unit) that stores LBA (logical location) information of a permanent partition in the SSD storage unit 410. When storing data in a designated LBA (designated logical location) that is an LBA designated by the main control unit 10, the memory control unit 420 determines whether the designated LBA is a permanent partition based on the LBA information stored in the management information storage unit 411. If the designated LBA is a permanent partition, the memory control unit 420 stores data in the designated LBA in a high-quality storage mode in which the variation in Vth is narrower than in a normal storage mode.

[0083] This allows the information processing device 1 according to the present embodiment to switch between storage processing in the high quality storage mode and storage processing in the normal storage mode depending on whether the partition is permanent or not.

[0084] Furthermore, in this embodiment, when the specified LBA is not a permanent partition, the memory control unit 420 executes a storage process in which the Vth variation is wider in the normal storage mode than in the high quality storage mode, and the storage period, which is the period required for storage in a multi-bit cell, is shorter than in the high quality storage mode.

[0085] As a result, the information processing device 1 according to this embodiment can switch between storage processing in the normal storage mode and storage processing in the high-quality storage mode, thereby achieving both high performance by shortening the storage processing period (write period) and long-term data retention (data retention period) guaranteed by a narrow range of variation in Vth.

[0086] In this embodiment, the memory control unit 420 executes an application process, a check process, and a repeat process in the high quality storage mode. In the application process, the memory control unit 420 applies a voltage for storing data to a plurality of bit cells for a predetermined period obtained by dividing the application period. In the check process, the memory control unit 420 checks whether or not Vth is within the Vth variation range after the application process. In the repeat process, the memory control unit 420 repeats the application process and the check process until Vth is within the Vth variation range.

[0087] As a result, the information processing device 1 according to this embodiment divides multiple bit cells into specified periods, applies a voltage to store data, and repeats this while checking Vth, making it possible to perform storage processing in a high-quality storage mode with a narrow Vth variation range using a simple method.

[0088] In addition, in this embodiment, when the information processing device 1 (its own device) becomes EOL, the main control unit 10 sets a permanent partition (specific area) in the SSD memory unit 410, and stores important data that needs to be read at a later date in the permanent partition.

[0089] As a result, the information processing device 1 according to this embodiment sets a permanent partition (specific area) when EOL occurs and stores important data in high quality storage mode, so that the data retention (data retention period) of the important data after EOL can be extended. Therefore, the information processing device 1 according to this embodiment can guarantee reading of important data in the SSD 40 for a certain period of time.

[0090] The control method according to the present embodiment is a control method for an information processing device 1 including an SSD 40 including an electrically rewritable SSD storage unit 410 configured with multi-bit cells that store multiple bits of data in one memory cell, and a main control unit 10 that executes processing based on the data stored in the SSD 40, and includes a memory control step. In the memory control step, a memory control unit 420 of the SSD 40 controls access to the SSD storage unit 410, and executes a storage process that can change the Vth variation width when storing multiple bits of data in the multi-bit cells.

[0091] As a result, the control method according to this embodiment has the same effect as the information processing device 1 described above, and can reduce data corruption in the SSD when power is not being supplied, for example after EOL, and can ensure data reading from SSD 40 for a certain period of time.

[0092] The present invention is not limited to the above-described embodiments, and can be modified without departing from the spirit of the present invention. For example, in the above embodiment, the information processing device 1 is described as being a notebook personal computer (mobile computer) as an example, but is not limited to this and may be other information processing devices such as a desktop personal computer or a tablet terminal device.

[0093] In addition, in the above embodiment, an example has been described in which the information processing device 1 sets a permanent partition (specific area) at the time of EOL, but this is not limited to this, and a permanent partition (specific area) may be set as an area for storing important data during normal use.

[0094] In addition, in the above embodiment, an example has been described in which the information processing device 1 switches between two types of storage processing, a normal storage mode and a high-quality storage mode, but depending on the application, three or more storage modes with Vth variation ranges may be provided and switched between.

[0095] In addition, in the above embodiment, the information processing device 1 has been described as setting a permanent partition as an example of a specific area, but this is not limited to this and may be other areas, such as an area that is not a partition.

[0096] In the above embodiment, a part of the processing of the memory control unit 420 of the SSD 40 may be performed by the information processing device 1 (for example, the main control unit 10 or the embedded controller 31).

[0097] In the above embodiment, the multi-bit cell is any one of MLC, TLC, and QLC, but the present invention is not limited to this and may be another type of multi-bit cell.

[0098] In the above embodiment, the information processing device 1 is described as being based on a personal computer having an embedded controller 31, but the information processing device 1 is not limited to this and may be configured without having an embedded controller 31. The OS of the information processing device 1 is not limited to Windows (registered trademark) and may be other OS such as Android (registered trademark) or iOS (registered trademark).

[0099] Each of the components of the information processing device 1 and SSD 40 described above has a computer system inside. A program for implementing the functions of each of the components of the information processing device 1 and SSD 40 described above may be recorded on a computer-readable recording medium, and the program recorded on the recording medium may be read into a computer system and executed to perform processing in each of the components of the information processing device 1 and SSD 40 described above. Here, "reading a program recorded on a recording medium into a computer system and executing it" includes installing the program into the computer system. The "computer system" referred to here includes hardware such as an OS and peripheral devices.

[0100] Furthermore, a "computer system" may include multiple computer devices connected via a network including the Internet, WAN, LAN, dedicated lines, and other communication lines. Furthermore, a "computer-readable recording medium" refers to portable media such as flexible disks, optical magnetic disks, ROMs, and CD-ROMs, and storage devices such as hard disks built into a computer system. In this way, the recording medium storing the program may be a non-transitory recording medium such as a CD-ROM.

[0101] The recording medium also includes a recording medium installed inside or outside and accessible from a distribution server to distribute the program. The program may be divided into a plurality of parts, downloaded at different times, and then combined by the components of the information processing device 1 and the SSD 40, or each divided program may be distributed by a different distribution server. Furthermore, the "computer-readable recording medium" includes a storage medium that holds a program for a certain period of time, such as a volatile memory (RAM) inside a computer system that becomes a server or a client when a program is transmitted via a network. The program may be a storage medium for implementing part of the above-mentioned functions. Furthermore, the program may be a so-called difference file (difference program) that can realize the above-mentioned functions in combination with a program already recorded in the computer system.

[0102] In addition, some or all of the above-mentioned functions may be realized as an integrated circuit such as LSI (Large Scale Integration). Each of the above-mentioned functions may be individually processed, or some or all of the functions may be integrated into a processor. The integrated circuit method is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. In addition, if an integrated circuit technology that can replace LSI appears due to advances in semiconductor technology, an integrated circuit based on that technology may be used. [Explanation of symbols]

[0103] 1. Information processing device 10 Main control section 11 CPU 12. Main memory 13 Video Subsystem 14 Display section 21 Chipset 22 BIOS memory 31 Embedded Controller (EC) 32 Input section 33 Power supply circuit 40 SSD 41 Flash Memory 42 SSD Controller 50 Storage section 51 Area range memory unit 101 AP Processing Unit 102 SSD device driver part 410 SSD storage 411 Management information storage unit 412 Mode information storage unit 413 Data Storage Unit 420 Memory control unit 421 Area setting processing unit 422 Write processing section 423 Read processing unit

Claims

1. A solid state drive (SSD) including an electrically rewritable non-volatile memory unit configured with a multi-bit cell that stores multiple bits of data in one memory cell; A main control unit that executes processing based on data stored in the SSD; Equipped with The SSD is a storage control unit that controls access to the non-volatile storage unit, the storage control unit executing a storage process that can change a variation width of a threshold voltage when storing the multiple bits of data in the multiple bit cell; the storage control unit stores the multiple bits of data in a specific area set by the main control unit among storage areas of the non-volatile storage unit such that a variation range of the threshold voltage is narrower in the specific area than in other areas; The main control unit is When the device reaches EOL (End Of Life), the specific area is set in the non-volatile storage unit, and important data that needs to be read out at a later date is stored in the specific area. Information processing device.

2. the SSD includes a position information storage unit that stores logical position information of the specific area in the non-volatile storage unit; When storing data at a designated logical location, which is a logical location designated by the main control unit, the storage control unit determines whether the designated logical location is the specific area based on the logical location information stored in the location information storage unit, and if the designated logical location is the specific area, stores data at the designated logical location in a high quality storage mode in which the variation in threshold voltage is narrower than in a normal storage mode. The information processing device according to claim 1 .

3. When the specified logical location is not the specific region, the storage control unit executes the storage process in the normal storage mode in which the variation in the threshold voltage is wider than in the high-quality storage mode and the storage period, which is the period required for storage in the multi-bit cell, is shorter than in the high-quality storage mode. The information processing device according to claim 2 .

4. In the high quality storage mode, the storage control unit an application process for applying a voltage for storing data to the plurality of bit cells for a predetermined period obtained by dividing the application period; a confirmation process for confirming whether or not the threshold voltage is within a variation range of the threshold voltage after the application process; a repeating process of repeating the application process and the confirmation process until the threshold voltage falls within a variation range of the threshold voltage; The information processing apparatus according to claim 2 .

5. A solid state drive (SSD) including an electrically rewritable non-volatile memory unit configured with a multi-bit cell that stores multiple bits of data in one memory cell; A main control unit that executes processing based on data stored in the SSD; A control method for an information processing device comprising: A step in which a storage control unit of the SSD controls access to the non-volatile storage unit, the step including a step of executing a storage process capable of changing a variation width of a threshold voltage when storing the multiple bits of data in the multiple bit cell; In the step, the storage control unit stores the multiple bits of data in a specific area set by the main control unit among the storage areas of the non-volatile storage unit such that a variation range of the threshold voltage is narrower in the specific area than in other areas; When the device itself reaches EOL (End Of Life), the main control unit sets the specific area in the non-volatile storage unit and stores important data that needs to be read out later in the specific area. Control methods.

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