Write leveling circuit applied to memory, and control method and control device thereof

Abstract

The present disclosure provides a write leveling circuit and its control method and control device applied to a memory, the write leveling circuit comprising a write signal generating unit, a delay unit, and a sampling unit, the write signal generating unit being configured to perform delay processing on a first write signal based on a received first clock signal, and output a second write signal, the delay unit being configured to perform delay processing on a received first data strobe signal, and output a second data strobe signal, the sampling unit being connected to the delay unit and the write signal generating unit respectively, and configured to output a first sampling signal based on the received second data strobe signal and second write signal, the sampling unit being further configured to receive the first data strobe signal, and output a second sampling signal based on the first data strobe signal and the second write signal. Furthermore, a controller corresponding to the outside of the memory adjusts a signal sent from the controller to the memory based on the first sampling signal and the second sampling signal output from the write leveling circuit, so that the memory can accurately write data.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on August 16, 2022, bearing application number 202210982417.7 and entitled "Light leveling circuit and control method and control device for memory", the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of memories, and more particularly to a write leveling circuit applied to a memory, and a control method and control device thereof. [Background technology]

[0003] Currently, memory plays a very important role in various electronic devices. When writing data to a memory, the cycle of the clock signal at which the data is written is usually determined based on the data strobe signal (DQS). When the wiring between the DRAM (Dynamic Random Memory) and the memory controller in an electronic device adopts a fly-by topology, there may be a misalignment between the clock signal and the data strobe signal received by each DRAM in the electronic device, so it is necessary to adjust the data strobe signal received by the memory so that the data is written accurately to the memory.

[0004] In order to control the write leveling circuit and adjust the data strobe signal received by the memory, how to design a write leveling circuit has become an issue that needs to be resolved immediately. Summary of the Invention

[0005] The present disclosure provides a write leveling circuit applied to a memory, a control method thereof, and a control device thereof, in order to solve the problem of how to adjust the write leveling of a memory.

[0006] In a first aspect, the present disclosure provides a write leveling circuit applied to a memory, the write leveling circuit comprising: a write signal generating unit, a delaying unit, and a sampling unit; The write signal generating unit is configured to perform a delay process on a first write signal according to a received first clock signal, and output a second write signal; The delay unit is configured to perform a delay process on the received first data strobe signal and output a second data strobe signal; The sampling unit is respectively connected to the delay unit and the write signal generating unit, and is configured to receive the second data strobe signal output from the delay unit and the second write signal output from the write signal generating unit, and output a first sampling signal based on the second data strobe signal and the second write signal, and the sampling unit is further configured to receive the first data strobe signal and the second write signal output from the write signal generating unit, and output a second sampling signal based on the first data strobe signal and the second write signal.

[0007] In a second aspect, the present disclosure provides a method for controlling a write levelling circuit applied to a memory, the method being adapted to a circuit according to the first aspect, the method comprising the steps of: when determining that the first sampling signal indicates that the effective edge of the first clock signal and the effective edge of the first data strobe signal are not aligned, repeating adjusting the delay of the first data strobe signal until determining, based on the first sampling signal output from the sampling unit, that the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned; if determining that the first sampling signal represents an active edge of the first clock signal and an active edge of the first data strobe signal that are aligned, controlling a delay of the first data strobe signal to be decreased by a first predetermined time, and the decreased signal is the first data strobe signal currently received by the sampling unit; and when it is determined that the second sampling signal indicates that the effective edge of the first data strobe signal and the effective edge of the second write signal are not aligned, repeatedly adjusting the delay of the first data strobe signal or the delay of the first write signal based on the second sampling signal output from the sampling unit until it is determined that the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned.

[0008] In a third aspect, the present disclosure provides a control device for a write leveling circuit applied to a memory, the control device being adapted to the circuit according to the first aspect, the control device comprising: a first adjusting unit, a first control unit, and a second adjusting unit; The first adjusting unit is configured to adjust a delay of the first data strobe signal when the first sampling signal determines that an effective edge of the first clock signal and an effective edge of the first data strobe signal are not aligned, and repeatedly execute the first adjusting unit until the first adjusting unit determines, based on the first sampling signal output from the sampling unit, that an effective edge of the first data strobe signal and an effective edge of the first clock signal are aligned; the first control unit is configured to control a delay of the first data strobe signal to be decreased by a first predetermined time when the first sampling signal determines that the first clock signal and the first data strobe signal are aligned, and to set the decreased signal as the first data strobe signal currently received by the sampling unit; The second adjustment unit is configured to adjust a delay of the first data strobe signal or a delay of the first write signal when it determines that the second sampling signal indicates that the effective edge of the first data strobe signal and the effective edge of the second write signal are not aligned, and repeatedly executes the second adjustment unit until the second adjustment unit determines, based on the second sampling signal output from the sampling unit, that the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned.

[0009] In a fourth aspect, the present disclosure provides a memory including a write leveling circuit according to any of the first aspects.

[0010] In a fifth aspect, the present disclosure provides an electronic device comprising: a processor; and a memory communicatively coupled to the processor; The memory stores computer executable instructions; The processor executes computer executable instructions stored in the memory to implement the method of any of the second aspects.

[0011] In a sixth aspect, the present disclosure provides a computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, realises a method according to any of the second aspect.

[0012] In a seventh aspect, the present disclosure provides a computer program product comprising a computer program which, when executed by a processor, implements the method of any of the second aspect.

[0013] The present disclosure provides a write leveling circuit applied to a memory, and a control method and control device thereof, the write leveling circuit comprising a write signal generating unit, a delay unit, and a sampling unit, the write signal generating unit being configured to perform a delay process on a first write signal based on a received first clock signal, and output a second write signal, the delay unit being configured to perform a delay process on a received first data strobe signal, and output a second data strobe signal, the sampling unit being connected to the delay unit and the write signal generating unit respectively, and configured to receive the second data strobe signal output from the delay unit and the second write signal output from the write signal generating unit, and output a first sampling signal based on the second data strobe signal and the second write signal, the sampling unit being further configured to receive the first data strobe signal and the second write signal output from the write signal generating unit, and output a second sampling signal based on the first data strobe signal and the second write signal. Furthermore, a controller corresponding to the outside of the memory adjusts the signal sent from the controller to the memory based on the first sampling signal and the second sampling signal output from the sampling unit in the write leveling circuit, so that the time difference between the valid edge of the data strobe signal received by the memory and the valid edge of the clock signal meets the standard requirements of the memory, thereby enabling the memory to write data accurately. [Brief description of the drawings]

[0014] [Figure 1] FIG. 2 is a schematic diagram of a wiring layout of a memory provided in the present disclosure. [Diagram 2] FIG. 2 is a schematic diagram showing a configuration of a write leveling circuit applied to a memory according to an embodiment of the present disclosure. [Diagram 3] FIG. 13 is a schematic diagram showing another configuration of a write leveling circuit applied to a memory according to an embodiment of the present disclosure. [Figure 4] FIG. 13 is a schematic diagram showing yet another configuration of a write leveling circuit applied to a memory according to an embodiment of the present disclosure. [Diagram 5] FIG. 13 is a schematic diagram showing yet another configuration of a write leveling circuit applied to a memory according to an embodiment of the present disclosure. [Figure 6] FIG. 13 is a schematic diagram showing yet another configuration of a write leveling circuit applied to a memory according to an embodiment of the present disclosure. [Figure 7] 1 is a flowchart of a control method for a write leveling circuit applied to a memory according to an embodiment of the present disclosure. [Figure 8] 11 is a flowchart of another control method for a write leveling circuit applied to a memory according to an embodiment of the present disclosure. [Figure 9] FIG. 13 illustrates signal changes according to an embodiment of the present disclosure. [Figure 10] FIG. 13 illustrates another signal change according to an embodiment of the present disclosure. [Figure 11] 1 is a schematic diagram showing a configuration of a control device of a write leveling circuit applied to a memory provided in the present disclosure; [Figure 12] FIG. 13 is a schematic diagram showing the configuration of another control device of a write leveling circuit applied to a memory provided in the present disclosure. [Figure 13] FIG. 2 is an exemplary structural diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the drawings. Where the following description refers to the drawings, the same numerals in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are only examples of apparatus and methods consistent with certain aspects of the present disclosure.

[0016] At present, in electronic devices, in order to reduce the wiring between the DRAM (Dynamic Random Memory) in the electronic device and the controller of the memory, when the electronic device includes multiple DRAMs, a fly-by wiring topology is usually adopted. As shown in FIG. 1, FIG. 1 is a schematic diagram of the wiring layout of the memory provided in the embodiment of the present disclosure, in which the clock signal output port in the controller corresponding to each DRAM is connected to the first DRAM of the multiple DRAMs connected in series and transmits a clock signal to the first DRAM. The clock signal received by the other DRAMs of the multiple DRAMs connected in series is output from the previous DRAM connected in series. In addition, in order to receive a data strobe signal from the controller, the data terminals of each DRAM of the multiple DRAMs are directly connected to the controller, and the length of the wiring for transmitting the data strobe signal between each DRAM and the controller is the same.

[0017] When the above wiring topology is adopted to connect a controller and multiple DRAMs, the time when the data strobe signal arrives at each DRAM is the same, but there is a difference in the time of the clock signal received by each DRAM, and the difference between the time of the clock signal received by each DRAM and the time of the data strobe signal is different. Therefore, each DRAM needs to adjust the delay of the DQS signal received therein, so that the time difference between the valid edge of the DQS signal received by each DRAM and the valid edge of the clock signal meets the memory standard requirements. For example, if the time difference is between [-0.5tck, 0.5tck], it is considered that the DQS signal sent from the controller meets the standard requirements of the DRAM, and data can be written to the DRAM accurately, where tck is intended to represent the clock period of the clock signal.

[0018] In one example, a write leveling circuit may be provided in the memory to align an effective edge of a data strobe signal received by the memory with an effective edge of a clock signal. The write leveling circuit includes a first receiver and a second receiver, configured to receive a clock signal and a data strobe signal input to a memory pin, respectively. A delay module is further provided following the first receiver, configured to perform a delay process (delay process) on the data strobe signal output from the first receiver, and then output the delayed signal to one end of a flip-flop. The write leveling circuit further includes a write signal generating unit, which generates a write signal based on the clock signal output from the second receiver and outputs the generated write signal to the other end of the flip-flop, so that the flip-flop can compare whether the effective edge of the write signal output from the received write signal generating unit is aligned with the effective edge of the delayed signal output from the delay module, thereby determining whether the effective edge of the clock signal received by the memory is aligned with the effective edge of the data strobe signal.

[0019] If there is a large delay when a signal (such as a data strobe signal or a write signal) is transmitted inside a memory, as the memory read / write speed increases, the power consumption and signal jitter when the signal is transmitted inside the memory also increase.

[0020] Therefore, it is an urgent problem to design a new write leveling circuit and control the write leveling circuit to facilitate adjustment of a data strobe signal received by a memory.

[0021] The write leveling circuit applied to a memory, and the control method and control device thereof provided in the present disclosure aim to solve the above-mentioned technical problems of the prior art.

[0022] The technical solution of the present disclosure and how the technical solution of the present disclosure solves the above technical problems are described in detail below with specific examples. Some of the following specific examples can be combined with each other, and the same or similar concepts or processes may not be repeated in some examples. The following examples of the present disclosure are described with reference to the drawings.

[0023] FIG. 2 is a schematic diagram showing the configuration of a write leveling circuit applied to a memory according to an embodiment of the present disclosure. As shown in FIG. 2, the write leveling circuit includes a write signal generating unit 21, a delaying unit 22, and a sampling unit 23. The write signal generating unit 21 is configured to perform a delay process on the first write signal based on a received first clock signal, and output a second write signal. The delaying unit 22 is configured to perform a delay process on the received first data strobe signal, and output a second data strobe signal. The sampling unit 23 is connected to the delaying unit 22 and the write signal generating unit 21, respectively, and is configured to receive the second data strobe signal output from the delaying unit 22 and the second write signal output from the write signal generating unit 21, and output a first sampling signal based on the second data strobe signal and the second write signal. The sampling unit 23 is further configured to receive the first data strobe signal and the second write signal output from the write signal generating unit 21, and output the second sampling signal based on the first data strobe signal and the second write signal.

[0024] Illustratively, in this embodiment, the write leveling circuit includes a write signal generating unit 21, a delaying unit 22, and a sampling unit 23. Here, the write signal generating unit 21 is configured to perform a delay process on the first write signal generated by the write signal generating unit 21 according to a received first clock signal, obtain a second write signal, and output the obtained second write signal to the sampling unit 23 connected to the write signal generating unit 21.

[0025] In addition, the write leveling circuit is further provided with a delay unit 22, which is configured to perform a delay process on the received first data strobe signal to obtain a second data strobe signal, and transmit the second data strobe signal to a sampling unit 23 connected to the delay unit 22. Here, when the write leveling circuit is provided inside the memory, the first data strobe signal received by the delay unit 22 is considered to be a data strobe signal transmitted inside the memory, and the signal can be obtained by converting the data strobe signal received at the memory pin. The first clock signal received by the write signal generating unit 21 is considered to be a clock signal transmitted inside the memory, and the signal can be obtained by converting the clock signal received at the memory pin. It should be noted that in the present disclosure, the memory standard of the memory is not particularly limited, and may be a memory of DDR5 memory standard, or may be a memory of other memory standards.

[0026] In addition, the sampling unit 23 in this embodiment is configured to generate a first sampling signal according to the second write signal output from the write signal generating unit 21 connected thereto and the second data strobe signal output from the delay unit 22 connected thereto. In addition, the sampling unit 23 is further configured to receive the first data strobe signal, and generate a second sampling signal according to the received first data strobe signal and the second write signal output from the write signal generating unit 21 connected thereto.

[0027] After the sampling unit 23 in the write leveling circuit generates the first sampling signal and the second sampling signal, in some embodiments, the write leveling circuit in the memory simultaneously outputs the first sampling signal and the second sampling signal to the controller corresponding to the memory, so that the controller can adjust the signal sent from the controller to the memory based on the received first sampling signal and second sampling signal, thereby making the time difference between the effective edge of the data strobe signal received by the memory and the effective edge of the clock signal meet the time difference range specified for the memory. Here, when adjusting the signal sent to the memory, the controller may adjust the delay of the data strobe signal sent to the memory, and is not particularly limited here. Also, the effective edge of the signal referred to in this disclosure may be the rising edge of the signal or the falling edge of the signal.

[0028] In this embodiment, a write leveling circuit applicable to a memory is provided, and the write leveling circuit is provided with a sampling unit 23, a delay unit 22 and a write signal generating unit 21, so that the sampling unit 23 can output a first sampling signal according to the second data strobe signal output from the delay unit 22 and the second write signal output from the write signal generating unit 21, and the sampling unit 23 further outputs a second sampling signal according to the first data strobe signal received and the second write signal output from the write signal generating unit 21, so that a corresponding controller outside the memory adjusts the signal sent from the controller to the memory according to the first sampling signal and the second sampling signal output from the sampling unit 23 in the write leveling circuit, so as to make the time difference between the effective edge of the data strobe signal received by the memory and the effective edge of the clock signal meet the specification requirements of the memory, and ensure that the memory can write data accurately.

[0029] In some embodiments, FIG. 3 is a schematic diagram showing another configuration of a write leveling circuit applied to a memory according to an embodiment of the present disclosure. Based on the device configuration shown in FIG. 2, the write signal generation unit in this embodiment includes a decoder 211 and a first delay module 212, where the decoder 211 is configured to decode a received write command and output a first write signal, and the first delay module 212 is connected to the decoder 211 and configured to perform a delay process on the first write signal based on the received first clock signal and output a second write signal.

[0030] 3, the write signal generating unit in this embodiment includes a decoder 211 and a first delay module 212. Here, the write command received by the decoder 211 is a write command sent from a controller corresponding to the outside of the memory having the write signal generating unit therein, i.e., a write command sent from the controller to a memory pin, which is used to instruct the memory to perform a current write operation.

[0031] After receiving a write command, the decoder 211 in the write signal generating unit can decode the write command to obtain a first write signal that can be recognized by the device inside the memory and indicates that a write operation needs to be performed now, and then the decoder 211 sends the obtained first write signal to a first delay module 212 connected to the decoder 211, and the first delay module 212 performs a delay process on the received first write signal based on a first clock signal, thereby obtaining a second write signal, and outputs the second write signal to a sampling unit 23 connected to the first delay module 212.

[0032] It can be understood that in this embodiment, the write signal generating unit 21 is provided with a decoder 211, so that the decoder 211 can decode the received write command, so that the device in the memory can accurately determine that the memory currently needs to perform a write operation, and then when the controller performs signal adjustment based on the write leveling circuit, the controller can more accurately determine the data strobe signal required for the memory, thereby improving the accuracy of data writing to the memory.

[0033] In some embodiments, based on the configuration shown in FIG. 3, the first delay module 212 of the write signal generating unit 21 in this embodiment is specifically configured to perform a delay process on the first write signal based on the received first clock signal, the CAS write latency of the memory and the first indication signal, and output a second write signal, where the first indication signal is used to indicate the shortened time of the CAS write latency of the memory.

[0034] For example, in the process in which the first delay module 212 in this embodiment performs delay processing on the first write signal output from the decoder 211 to obtain a second write signal, specifically, the first delay module 212 can perform delay processing on the first write signal based on the shortened time of the CAS write latency (CWL: Column Address Strobe Write Latency) of the memory indicated by the received first instruction signal, the first clock signal, and the CAS write latency of the memory.

[0035] For example, in one possible embodiment, the first delay module 212 performs a difference process between the CAS write latency of the memory and the shortened time indicated by the first instruction signal, and the delay time indicated by the result after the difference process is set to the time difference between the first write signal and the second write signal during the delay process of the first write signal in the delay unit 22. Here, the clock period of the first clock signal can be used as the time reference for the delay time indicated after the difference process, and for example, if the difference result is 0.5 tck, the delay time between the first write signal and the second write signal obtained is 0.5 x the clock period of the first clock signal.

[0036] It should be noted that the CAS write latency of the memory acquired by the first delay module 212 may be pre-stored in the first delay module 212, or may be determined by the first delay module 212 according to the received third indication signal, where the third indication signal can be used to indicate the CAS write latency currently required for the memory. The CAS write latency of the memory can also be adjusted according to the memory read / write speed desired by the user. For example, the controller finds an indication signal of the CAS write latency corresponding to the read / write speed according to the required memory read / write speed, and sends the indication signal to the first delay module 212 in the memory, so that the first delay module 212 can perform delay processing on the received first write signal.

[0037] In addition, in one possible embodiment, the delay between the first write signal in the write signal generating unit 21 and the second write signal output from the write signal generating unit 21 includes not only the difference between the CAS write latency of the memory and the shortened time indicated in the first instruction signal, but also the signal delay caused by electronic devices such as inverters provided to improve signal transmission quality in the process of transmitting the first write signal to the sampling unit 23 after performing delay processing.

[0038] It can be understood that in this embodiment, when the first delay module 212 performs delay processing on the first write signal output from the decoder 211, the first delay module 212 performs delay processing on the first write signal in consideration of the CAS write latency of the memory and the shortened time of the CAS write latency indicated by the first indication signal, so that when an external controller of the memory including the write leveling circuit determines the data strobe signal to be received by the memory through the write leveling circuit, the effective edge of the first data strobe signal received inside the memory is aligned with the effective edge of the second write signal by adjusting the shortened time indicated by the first indication signal.

[0039] In some embodiments, Fig. 4 is a schematic diagram illustrating another configuration of a write leveling circuit applied to a memory according to an embodiment of the present disclosure. Based on the configuration of the device shown in Fig. 3, in this embodiment, the write signal generating unit 21 further includes a signal converting module 213, the decoder 211 is connected to the first delay module 212 via the signal converting module 213, and the signal converting module 213 is configured to perform pulse stretching on the first write signal output from the decoder 211, and output the stretched write signal to the first delay module 212.

[0040] Illustratively, as shown in FIG. 4, in this embodiment, the write signal generating unit 21 in the write leveling circuit includes a decoder 211, a signal conversion module 213, and a first delay module 212. Here, the decoder 211 is configured to receive a write command, decode the write command, and send the decoded signal to the signal conversion module 213 connected to the decoder 211. The signal conversion module 213 then performs pulse stretching on the decoded signal output from the decoder 211, and outputs the pulse stretched signal as a first write signal to the first delay module 212 connected thereto, so that the first delay module 212 performs delaying on the received first write signal, thereby obtaining a second write signal.

[0041] As can be understood, the signal conversion module 213 of the write signal generation unit 21 in this embodiment satisfies the standard requirements (e.g., SPEC requirements) corresponding to the memory by performing pulse stretching processing on the signal output from the decoder 211 to the signal conversion module 213.

[0042] Based on any of the above embodiments, the sampling unit 23 in the write leveling circuit provided by this embodiment includes a first flip-flop 231, a second flip-flop 232, and a data selector 233, a data terminal of the first flip-flop 231 is connected to the write signal generating unit 21 and configured to receive the second write signal output from the write signal generating unit 21, a clock terminal of the first flip-flop 231 is connected to the output terminal of the delay unit 22 and configured to receive the second data strobe signal output from the delay unit 22, and the first flip-flop 231 selects a sampling signal based on the second write signal and the second data strobe signal. the data terminal of the second flip-flop 232 is connected to the write signal generating unit 21 and configured to receive the second write signal output from the write signal generating unit 21; the clock terminal of the second flip-flop 232 is configured to receive the first data strobe signal; the second flip-flop 232 is configured to output the second sampling signal based on the second write signal and the first data strobe signal; the output terminal of the first flip-flop 231 is connected to a first terminal of the data selector 233, and the output terminal of the second flip-flop 232 is connected to a second terminal of the data selector 233.

[0043] 5, which is a schematic diagram showing yet another configuration of a write leveling circuit applied to a memory according to an embodiment of the present disclosure, based on the configuration shown in FIG. 2, the write leveling circuit in this embodiment includes a first flip-flop 231, a second flip-flop 232, and a data selector 233. Here, the clock terminal and the data terminal of the first flip-flop 231 are respectively connected to the delay unit 22 and the write signal generating unit 21, and the first flip-flop 231 samples the second write signal received at the data terminal of the first flip-flop 231 and output from the write signal generating unit 21 connected thereto based on the effective edge of the second data strobe signal received at its clock terminal and transmitted from the delay unit 22 connected thereto, and outputs the sampling result as a first sampling signal to the data selector 233 connected to the first flip-flop 231.

[0044] In addition, the clock terminal of the second flip-flop 232 is used to receive the first data strobe signal, and the data terminal of the second flip-flop 232 is connected to the write signal generating unit 21 and used to receive the second write signal output from the write signal generating unit 21. Then, the second flip-flop 232 samples the second write signal received by the second flip-flop 232 based on the valid edge of the received first data strobe signal, and outputs the sampling result as a second sampling signal to the data selector 233 connected to the second flip-flop 232.

[0045] The data selector 233 receives a first sampling signal transmitted from a first flip-flop 231 connected to it and a second sampling signal transmitted from a second flip-flop 232 connected to it, and then selects and outputs one of the sampling signals, thereby enabling a controller outside the memory to adjust a signal from the controller to the memory based on the received first sampling signal or second sampling signal.

[0046] It can be understood that in this embodiment, by providing the sampling unit 23 with a first flip-flop 231, a second flip-flop 232 and a data selector 233, compared with simultaneously sending the first sampling signal and the second sampling signal to the controller, the sampling unit 23 device provided in this embodiment can reduce the occupancy rate of the data receiving port on the controller, and when the write leveling circuit is packaged in the memory, the pin occupancy rate on the memory can also be reduced.

[0047] Based on the configuration of the write leveling circuit applied to the memory provided in any of the above embodiments, in this embodiment, the write leveling circuit further includes a first converter 24, which is respectively connected to the delay unit 22 and the sampling unit 23, and is configured to perform logic level conversion processing on the received third data strobe signal to obtain a first data strobe signal, where the level of the third data strobe signal is a current mode logic level, and the level of the first data strobe signal is a complementary metal oxide semiconductor (CMOS) level.

[0048] Exemplarily, the write leveling circuit provided in this embodiment further includes a first converter 24. Here, the third data strobe signal received by the first converter 24 is considered to be a data strobe signal transmitted from a controller outside the memory to a pin of the memory in practical application. When the controller transmits the third data strobe signal to the memory, a Current Model Logic (CML) level transmission format is usually adopted to improve signal transmission efficiency. Meanwhile, inside the memory, a CMOS level transmission format is usually adopted to transmit signals. Therefore, the first converter 24 in the write leveling circuit obtains the third data strobe signal at the pin, and then converts the third data strobe signal transmitted in the CML level transmission format into a first data strobe signal transmitted in the CMOS level transmission format, so that each device in the write leveling circuit in the memory can accurately identify the first data strobe signal.

[0049] Based on the configuration of the write leveling circuit applied to the memory provided in any of the above embodiments, in this embodiment, the write leveling circuit further includes a second converter 25, which is connected to the write signal generating unit 21 and configured to perform logic level conversion processing on the received second clock signal to obtain a first clock signal, where the level of the second clock signal is a current mode logic level, and the level of the first clock signal is a CMOS level.

[0050] Exemplarily, in this embodiment, the write leveling circuit provided in this embodiment further includes a second converter 25. Here, the second clock signal received by the second converter 25 is considered to be a clock signal transmitted to a pin of the memory from a controller outside the memory or a previous memory connected in series to the memory in practical application. Meanwhile, when a controller transmits a clock signal to a memory or transmits a clock signal between memories, a current mode logic (CML) level transmission format is usually adopted to improve signal transmission efficiency. Meanwhile, inside the memory, a CMOS level transmission format is usually adopted to perform signal transmission. Therefore, the second converter 25 in the write leveling circuit obtains the second clock signal at a pin, and then converts the second clock signal transmitted by the CML level transmission format into a first clock signal transmitted by the CMOS level transmission format, so that each device in the write leveling circuit in the memory can accurately identify the first clock signal.

[0051] 6 is a schematic diagram showing another configuration of a write leveling circuit applied to a memory according to an embodiment of the present disclosure. As shown in the figure, in this embodiment, when the write leveling circuit is provided inside the memory and the memory is provided with an upper data strobe signal receiving pin and a lower data strobe signal receiving pin, the first converter 24 in the write leveling circuit can be configured to receive a third data strobe signal from the lower data strobe signal receiving pin of the memory, perform logic level conversion processing on the third data strobe signal, and then transmit the obtained first data strobe signal to the delay unit 22 connected to the first converter 24 and the second flip-flop 232 of the sampling unit 23, respectively.

[0052] After receiving the first data strobe signal, the delay unit 22 performs a delay process on the first data strobe signal, and then transmits the second data strobe signal obtained by the delay process to the first flip-flop 231 of the sampling unit 23 connected to the delay unit 22.

[0053] In addition, the write leveling circuit further includes a second converter 25, in which the second converter 25 is configured to receive a second clock signal input from a memory pin, perform a logic level conversion process on the second clock signal, and then transmit the processed first clock signal to the signal conversion module 213 of the write signal generation unit 21 connected to the second converter 25.

[0054] The decoder 211 of the write signal generating unit 21 is configured to generate a first write signal according to the received write command, and then transmit the generated first write signal to the signal converting module 213 connected to the decoder 211. After receiving the first write signal, the signal converting module 213 performs pulse stretching and transmits the stretched signal to the first delay module 212 connected to the signal converting module 213, which performs delaying on the stretched signal to obtain a second write signal. Then, the first delay module 212 transmits the obtained second write signal to the first flip-flop 231 and the second flip-flop 232 connected to the first delay module 212 respectively.

[0055] In the sampling unit 23, the first flip-flop 231 performs sampling based on the second write signal output from the first delay module 212 received at its data terminal and the second data strobe signal output from the delay unit 22 received at its clock terminal, to generate a first sampling signal, which is output to a data selector 233 connected to the first flip-flop 231. Similarly, the second flip-flop 232 performs sampling based on the second write signal output from the first delay module 212 received at its data terminal and the first data strobe signal output from the first receiver 24 received at its clock terminal, to generate a second sampling signal, which is output to a data selector 233 connected to the second flip-flop 232.

[0056] It can be understood that when the third data strobe signal received by the above first converter 24 is a lower data strobe signal, and the pins of the memory further include an upper data strobe signal receiving pin, the write leveling circuit can also include a third converter 26, in which the third converter 26 is configured to perform logic level conversion on the received upper data strobe signal, and send the logic level converted signal to the upper delay unit 27 connected to the third converter 26 and the fourth flip-flop 282 connected to the third converter 26 respectively. The upper delay unit 27 in this embodiment has the same function as the delay unit 22, and is configured to perform delay processing on the received data strobe signal, and send the delayed signal to the third flip-flop 281 connected to the upper delay unit 27.

[0057] In addition, the write leveling circuit is further provided with a second delay module 214, which is configured to perform delay processing on the pulse stretched signal output from the signal conversion module 213 connected to it, and to transmit the delayed signal to a third flip-flop 281 and a fourth flip-flop 282 connected to the second delay module 214, respectively.

[0058] In the upper sampling unit 28, the third flip-flop 281 performs sampling based on the signal output from the second delay module 214 received at its data terminal and the signal output from the upper delay unit 27 received at its clock terminal, generates a third sampling signal, and outputs it to the upper data selector 283 connected to the third flip-flop 28. Similarly, the fourth flip-flop 282 performs sampling based on the signal output from the second delay module 214 received at its data terminal and the signal output from the third receiver 26 received at its clock terminal, generates a fourth sampling signal, and outputs it to the upper data selector 283 connected to the fourth flip-flop 282.

[0059] It can be understood that when a memory includes a lower data strobe signal receiving pin and an upper data strobe signal receiving pin, the time difference between the effective edge of the received lower data strobe signal and the effective edge of the clock signal needs to meet the standard setting of the memory, and the time difference between the effective edge of the received upper data strobe signal and the effective edge of the clock signal needs to meet the standard setting of the memory. Therefore, the write leveling circuit in the memory may be provided with two converters (i.e., the first converter 24 and the third converter 26 in the figure) that perform logic level conversion processing on the received data strobe signal, two delay units (i.e., the delay units 22 and 27 in the figure), and two sampling units (i.e., the sampling unit 23 and the upper sampling unit 28 in the figure). The above-mentioned write leveling circuit design allows the controller outside the memory to adjust the signal sent to the memory, so that the time difference between the valid edge of the lower data strobe signal received by the memory and the valid edge of the clock signal meets the memory specification setting, and also the time difference between the valid edge of the upper data strobe signal received by the memory and the valid edge of the clock signal meets the memory specification setting, thereby improving the accuracy of data writing in the memory. For example, the controller can adjust the data strobe signal received by the first converter 24 or the delay during the delay process by the first delay module, so that the time difference between the valid edge of the lower data strobe signal received by the memory and the valid edge of the clock signal meets the memory specification setting. In addition, the controller can adjust the data strobe signal received by the third converter 26 or the delay during the delay process by the second delay module, so that the time difference between the valid edge of the upper data strobe signal received by the memory and the valid edge of the clock signal meets the memory specification setting.

[0060] Based on any of the above embodiments, the first sampling signal in this embodiment represents whether the effective edge of the first clock signal and the effective edge of the first data strobe signal are aligned.

[0061] For example, the write leveling process of a memory is usually divided into external write leveling and internal write leveling, where external write leveling is used to align the data strobe signal and the clock signal received at the memory pin. In this embodiment, in order to allow the first sampling signal output from the sampling unit 23 to represent whether the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned, the delay of the delay unit 22 in delaying the first data strobe signal is made equivalent to the delay when the write signal generating unit receives the first clock signal and delays the first write signal to obtain a second write signal, so that the result of whether the effective edge of the received second data strobe signal and the effective edge of the second write signal are aligned, which is represented by the first sampling signal output from the sampling unit 23, is always consistent with the result of whether the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned. With the above-mentioned setting of the delay of the delay unit 22, it is possible to determine whether the purpose of external write leveling of the memory is achieved according to the first sampling signal output from the sampling unit 23.

[0062] In some embodiments based on any of the above embodiments, the first sampling signal is used to indicate that a delay of the first data strobe signal is adjusted specifically when the first sampling signal indicates that an effective edge of the first clock signal and an effective edge of the first data strobe signal are not aligned.

[0063] Exemplarily, in this embodiment, to realize memory-external write leveling, when a controller external to the memory determines that the first sampling signal represents that the effective edge of the first clock signal and the effective edge of the first data strobe signal are not aligned, the controller can continuously adjust a delay of the data strobe signal sent to the memory, i.e., by continuously adjusting the delay of the first data strobe signal, the effective edge of the first clock signal and the effective edge of the first data strobe signal are aligned.

[0064] It should be clarified that in the present disclosure, determining whether the effective edges of two signals are aligned can be determined by determining whether the time difference between the times corresponding to the effective edges of the two signals is within a predetermined difference, where if the time difference is within the predetermined difference, it represents that the effective edges of the two signals are aligned.

[0065] In some embodiments, the second sampling signal indicates whether an active edge of the first data strobe signal and an active edge of the second write signal are aligned.

[0066] Illustratively, the write leveling process of the memory also includes internal write leveling, the main purpose of which is to ensure that the valid edge of the first data strobe signal received inside the memory is aligned with the valid edge of the second write signal in order to reduce the transmission path of the data strobe signal transmitted inside the memory.

[0067] In the external leveling process, the memory is provided with a delay unit 22, which performs delay processing on the received first data strobe signal. The longer the delay corresponding to the delay processing in the delay unit 22, the greater the power consumption and jitter of the write leveling circuit at this time. Therefore, in order to reduce the transmission path of the data strobe signal inside the memory, in the internal write leveling process, the sampling unit 23 directly outputs a second sampling signal based on the first data strobe signal and a second write signal generated from a write signal generating unit connected to the sampling unit, thereby determining whether the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned by the second sampling signal. For example, the sampling unit 23 can determine whether the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned by performing a differential processing between the time corresponding to each effective edge of the first data strobe signal and the time corresponding to each effective edge of the second write signal.

[0068] In some embodiments, the second sampling signal is specifically used to indicate that a delay of the first write signal or a delay of the first data strobe signal is adjusted when the first sampling signal indicates that the effective edge of the first clock signal and the effective edge of the first data strobe signal are aligned and the effective edge of the first data strobe signal and the effective edge of the second write signal are not aligned.

[0069] For example, in the internal write leveling process, in order to avoid the problem of high power consumption during memory internal signal transmission, the following adjustments can be made: In this embodiment, after the external write leveling process is completed, that is, when the first sampling signal indicates that the effective edge of the first clock signal and the effective edge of the first data strobe signal are aligned, and the effective edge of the first data strobe signal and the effective edge of the second write signal are not aligned, the effective edge of the first data strobe signal and the effective edge of the second write signal can be aligned by adjusting the delay of the first write signal or the delay of the first data strobe signal.

[0070] It can be understood that compared with the external write leveling process, which requires a delay unit to perform delay processing before outputting the first data strobe signal, the internal write leveling process does not require delay processing for the first data strobe signal, which corresponds to reducing the delay when the first data strobe signal is transmitted inside the memory, and then the delay of the first write signal can be further adjusted to reduce the power consumption generated when the first write signal is transmitted, and then the delay of the first write signal or the delay of the first data strobe signal can be continuously adjusted to ensure the achievement of the purpose of internal write leveling.

[0071] FIG. 7 is a flowchart of a control method for a write leveling circuit applied to a memory according to an embodiment of the present disclosure. The method provided in this embodiment is applied to the write leveling circuit shown in FIG. 2, and the method includes the following steps:

[0072] If in step S701 it is determined that the first sampling signal indicates that the effective edge of the first clock signal and the effective edge of the first data strobe signal are not aligned, then the delay of the first data strobe signal is adjusted.

[0073] Repeatedly execute step S701 until it is determined based on the first sampling signal output from the sampling unit that the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned.

[0074] For example, the execution subject of the present embodiment may be a controller outside the memory or other electronic devices, and the present disclosure is not particularly limited thereto. In the following, a case where the execution subject of the present disclosure is a controller will be described as an example.

[0075] In the write leveling process of the memory, first, the controller receives a first sampling signal output from the write leveling circuit, and if the controller determines based on the first sampling signal that the effective edge of the first clock signal and the effective edge of the first data strobe signal are not aligned, the controller continuously adjusts the delay of the data strobe signal sent to the memory, i.e., aligns the first data strobe signal and the first clock signal by continuously changing the delay of the first data strobe signal. It should be noted that in this embodiment, the amount by which the controller adjusts the delay of the data strobe signal each time may be the same value or different values, and this embodiment is not particularly limited.

[0076] It should also be explained that in this embodiment, the first sampling signal is generated by the sampling unit in the write leveling circuit by comparing whether or not the valid edge of the second data strobe signal output from the delay unit is aligned with the valid edge of the second write signal, and the delay during the delay process of the first data strobe signal by the delay unit is equivalent to the delay when the write signal generation unit receives the first clock signal and performs delay processing on the first write signal to obtain the second write signal, so the first sampling signal generated by comparing whether or not the valid edge of the second data strobe signal is aligned with the valid edge of the second write signal can represent whether or not the valid edge of the first data strobe signal is aligned with the valid edge of the first clock signal.

[0077] In one example, the first sampling signal may be a time difference between the time the sampling unit receives the valid edge of the second data strobe signal and the time the sampling unit receives the valid edge of the second write signal, and the controller determines whether the valid edges of the two signals are aligned by comparing the time difference with a predetermined time difference range.

[0078] In step S702, if it is determined that the first sampling signal represents that the first clock signal and the first data strobe signal are aligned, then controlling to decrease the delay of the first data strobe signal by a first predetermined time, and the decreased signal is the first data strobe signal currently received by the sampling unit.

[0079] Exemplarily, when the controller determines based on the first sampling signal that the first clock signal and the first data strobe signal are aligned, that is, representing that the external write leveling process in the write leveling process of the memory is completed, the controller then reduces the delay of the first data strobe signal during alignment by a first predetermined time, and then sets the first data strobe signal whose delay is reduced by the first predetermined time as the first data strobe signal that is initially input to the sampling unit in the write leveling circuit during the internal write leveling process of the memory.

[0080] It should be noted that the first predetermined time in this embodiment can be determined based on a write preamble signal and a corresponding relationship between the write preamble signal and the first predetermined time length.

[0081] If in step S703 it is determined that the second sampling signal indicates that the effective edge of the first data strobe signal and the effective edge of the second write signal are not aligned, then the delay of the first data strobe signal or the delay of the first write signal is adjusted.

[0082] Repeatedly execute step S703 until it is determined based on the second sampling signal output from the sampling unit that the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned.

[0083] For example, when performing internal write leveling on a memory, if the controller first determines based on the second sampling signal that the valid edge of the first data strobe signal and the valid edge of the second write signal are not aligned, the controller adjusts delays of the first data strobe signal and the first write signal to align the valid edge of the first data strobe signal and the valid edge of the second write signal, i.e., ensures alignment between the data strobe signal and the write signal received at the memory unit portion inside the memory.

[0084] It can be understood that the present embodiment provides a control method for a write leveling circuit applied to a memory, and the controller can control the write leveling circuit according to the first sampling signal and the second sampling signal output from the write leveling circuit, thereby achieving the purpose of write leveling of the memory. In addition, in the control process, the controller can first perform the external write leveling process of the memory by determining whether to adjust the delay of the first data strobe signal according to whether the effective edges of the signal represented by the first sampling signal are aligned. In addition, in order to reduce the power consumption and delay caused when the data strobe signal and the write signal are transmitted inside the memory, in the internal write leveling process, the controller further continuously adjusts the delay of the first data strobe signal or the delay of the first write signal according to the received second sampling signal, thereby finally completing the write leveling process of the memory, so that the memory can accurately write data.

[0085] In some embodiments, based on the methodology shown in FIG. 7, if it is determined that the valid edge of the first data strobe signal and the valid edge of the second write signal are aligned, the delay of the first data strobe signal is extended by a second predetermined time, and the extended signal is determined to be the data strobe signal received when the memory performs a write operation.

[0086] 7, in order to further ensure that the time difference between the valid edge of the data strobe signal received at the memory pin and the valid edge of the clock signal received at the pin meets the memory standard requirements, in this embodiment, when the second sampling signal determines that the valid edge of the first data strobe signal and the valid edge of the second write signal are aligned, the controller extends the delay of the first data strobe signal when aligned by a second predetermined time, and the extended data strobe signal is the first data strobe signal received when the memory performs a write operation. In addition, the time difference between the valid edge of the first data strobe signal after the second predetermined time extension and the valid edge of the first clock signal received at the memory pin when aligned meets the time difference required by the memory standard (e.g., tDQSoffset of the memory).

[0087] It should be noted that the second predetermined time in the present disclosure may be determined based on a write preamble signal and a corresponding relationship between the write preamble signal and the second predetermined time length.

[0088] It can be seen that in this embodiment, by extending the delay of the first data strobe signal when aligning the valid edge of the first data strobe signal with the valid edge of the second write signal by a second predetermined time, the data strobe signal that should ultimately be received at the memory pin end can be further determined so that the memory can accurately write data.

[0089] In some embodiments, determining that the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned based on the first sampling signal output from the sampling unit includes determining that the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned when a level value of the first sampling signal output from the sampling unit changes from a first level value to a second level value.

[0090] For example, in this embodiment, when determining whether the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned based on the first sampling signal generated by the sampling unit in the write leveling circuit, the determination can be made by detecting the level value of the first sampling signal. Specifically, in this embodiment, if the delay of the delaying process of the first data strobe signal by the delay unit is equivalent to the delay of the write signal generating unit receiving the first clock signal and delaying the first write signal to obtain the second write signal, the result of whether the effective edge of the second data strobe signal and the effective edge of the second write signal are aligned always coincides with the result of whether the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned. At this time, the sampling unit can sample the level value of the second write signal at the effective edge of the second data strobe signal, and output the sampling result as a first sampling signal. When the controller determines that the level value of the output first sampling signal has switched from the first level value to the second level value, it represents that the effective edge of the second data strobe signal and the effective edge of the second write signal are aligned; similarly, at this time, the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned.

[0091] It can be understood that in this embodiment, the first sampling signal output from the sampling unit can represent whether the effective edge of the second data strobe signal and the effective edge of the second write signal are aligned, and when the alignment result is the same as the alignment result of whether the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned, the signal level value output from the first sampling signal can be detected to switch from a first level value to a second level value to determine whether the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned. The method provided by this embodiment is simple, easy to implement, and does not require repeated calculation of the time difference between the signal effective edges.

[0092] In some embodiments, based on the above embodiments, determining that the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned based on the second sampling signal output from the sampling unit includes determining that the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned when the level value of the second sampling signal output from the sampling unit changes from the second level value to the first level value.

[0093] For example, in this embodiment, after the sampling unit receives the first data strobe signal and the second write signal output from the write signal generating unit, it samples the level value of the second write signal at the effective edge of the first data strobe signal to determine whether the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned, and the sampling result is the second sampling signal output from the sampling unit, so that the change in the level value of the second sampling signal can be constantly monitored, and when the level value of the second sampling signal switches from the second level value to the first level value, it represents that the effective edge of the second write signal and the effective edge of the first data strobe signal are aligned.

[0094] It can be understood that in this embodiment, by detecting whether the level value change of the second sampling signal switches from the second level value to the first level value, it can determine whether the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned. The method provided by this embodiment is simple and easy to implement, and does not require repeated calculation of the time difference between the signal effective edges.

[0095] 8 is a flow chart of another control method of a write leveling circuit applied to a memory according to an embodiment of the present disclosure, the method provided in this embodiment is applied to the write leveling circuit shown in FIG. 3, where the write signal generating unit in the write leveling circuit includes a decoder and a first delay module, the decoder is configured to decode the received write command and output a first write signal, the first delay module is connected to the decoder and configured to perform a delay process on the first write signal according to the received first clock signal, and output a second write signal, the first delay module is specifically configured to perform a delay process on the first write signal according to the received first clock signal, the CAS write latency of the memory, and a first indication signal, and output a second write signal, where the first indication signal is used to indicate the shortened time of the CAS write latency of the memory. Based on the above embodiment, the method includes the following steps:

[0096] In step S801, if it is determined that the level value of the first sampling signal output from the sampling unit has not changed from the first level value to the second level value, it is determined that the effective edge of the first clock signal and the effective edge of the first data strobe signal are not aligned, and the delay of the first data strobe signal is adjusted.

[0097] Step S801 is repeatedly executed until the level value of the first sampling signal output from the sampling unit changes from the first level value to the second level value.

[0098] For illustrative purposes, the specific principles of step S801 may refer to the specific principles of step S701 and the above embodiments, and will not be described again here.

[0099] In step S802, if it is determined that the level value of the first sampling signal output from the sampling unit has changed from the first level value to the second level value, it is determined that the effective edge of the first clock signal and the effective edge of the first data strobe signal are aligned, and the delay of the first data strobe signal is controlled to be decreased by a first predetermined time, and the signal after the decrease is the first data strobe signal currently received by the sampling unit.

[0100] For illustrative purposes, the specific principles of step S802 may refer to the specific principles of step S702 and the above embodiments, and will not be described again here.

[0101] In step S803, if it is determined that the level value of the second sampling signal output from the sampling unit is the first level value, the first delay module adjusts the first instruction signal received by the first delay module to increase the reduction time of the CAS write latency of the memory indicated in the first instruction signal, sends a write command to the decoder, and sends the adjusted first instruction signal to the first delay module.

[0102] Step S803 is repeatedly executed until the level value of the second sampling signal output from the sampling unit switches from the first level value to the second level value.

[0103] For example, in this embodiment, after completing the external write leveling of the memory in step S801, in order to reduce the power consumption and delay caused when the data strobe signal and the write signal are transmitted inside the memory, the adjustment process of the internal write leveling of the memory is continued after the external write leveling. First, during the internal write leveling, the delay of the first data strobe signal when the effective edge of the first clock signal and the effective edge of the first data strobe signal are aligned is reduced by a first predetermined time. After the first data strobe signal changes, the delay of the first write signal output from the decoder is continuously shortened by continuously adjusting the first delay module of the write signal generating unit, so that the effective edge of the first data strobe signal and the effective edge of the second write signal output from the write signal generating unit are aligned inside the memory.

[0104] When controlling the shortening of the delay of the first write signal, in this embodiment, the shortening time of the CAS write latency indicated in the first instruction signal sent to the first delay module can be increased, and as the shortening time continuously increases, the difference between the CAS write latency and the shortening time (i.e., the delay during the delay processing of the first write signal by the first delay module) also continuously decreases.

[0105] That is, in the internal write leveling process, first, each time an adjustment is made, a write command is sent to the decoder in the write leveling circuit, and the adjusted first instruction signal is sent to the first delay module. At the same time, a second sampling signal output from the sampling unit is obtained while ensuring that the first data strobe signal is unchanged (the first data strobe signal at this time is the data strobe signal corresponding to the delay of the first data strobe signal when the effective edge of the first clock signal and the effective edge of the first data strobe signal are aligned and the delay is reduced by a first predetermined time). If the level value indicated by the second sampling signal is the first level value, it means that it is necessary to continue shortening the delay of the first write signal at this time.

[0106] It should be noted that, due to the limitations of the registers in the memory, when adjusting the CAS write latency reduction time indicated by the first instruction signal, the CAS write latency reduction time can only be an integer multiple of the value of the time period of the first clock signal, so when adjusting the delay of the first write signal, the change value of the delay each time can only be an integer multiple of the time period. When the sampling value output by the second sampling signal switches from the first level value to the second level value, at this time, the effective edge of the first data strobe signal and the effective edge of the second write signal may not be aligned, resulting in a phenomenon that the time corresponding to the effective edge of the first data strobe signal is slower than the time corresponding to the effective edge of the second write signal, so the delay of the first data strobe signal needs to be adjusted.

[0107] In step S804, reduce the delay of the first data strobe signal received by the sampling unit, send a write command to the decoder, and send a delay signal to the first delay module, where the delay signal is the first instruction signal received by the first delay module when the second sampling signal output from the sampling unit switches from the first level value to the second level value.

[0108] Step S804 is repeatedly executed until the level value of the second sampling signal output from the sampling unit switches from the second level value to the first level value.

[0109] For example, after completing the adjustment in the above step S803, in order to align the valid edge of the first data strobe signal with the valid edge of the second write signal, this step also adjusts the delay of the first data strobe signal. Because the delay of the first data strobe signal is not limited by the memory standard, and the change amount of the delay adjustment does not need to be an integer multiple of the clock period of the first clock signal, this step can align the valid edge of the first data strobe signal with the valid edge of the second data strobe signal by continuously adjusting the delay of the first data strobe signal. In addition, each time an adjustment process is performed, a write command needs to be sent to the decoder and a delay signal needs to be sent to the first delay module, so that the decoder can output a first write signal, and the first delay module can perform a delay process on the first write signal output from the decoder connected to it, and the time length of the delay process is determined by the delay signal received by the first delay module, which is the first instruction signal received by the first delay module when the second sampling signal switches from the first level value to the second level value, i.e., the first instruction signal received by the first delay module when the repetition of step S803 is completed.

[0110] It can be understood that in this embodiment, during the internal adjustment process of the memory, firstly, the delay during the first write signal delay process is reduced to reduce the power consumption and delay during the transmission of the first write signal, and then the delay of the first data strobe signal is adjusted to align the effective edge of the first data strobe signal with the second write signal, so that when the memory performs a write operation, data can be written accurately and the power consumption during the internal signal transmission of the memory during the write operation can also be reduced.

[0111] In some embodiments, the sampling unit in the write leveling circuit comprises a first flip-flop, a second flip-flop, and a data selector, a data terminal of the first flip-flop is connected to the write signal generating unit and used to receive a second write signal output from the write signal generating unit, a clock terminal of the first flip-flop is connected to the output terminal of the delay unit and used to receive a second data strobe signal output from the delay unit, the first flip-flop is configured to output a first sampling signal based on the second write signal and the second data strobe signal, a data terminal of the second flip-flop is connected to the write signal generating unit and used to receive the second write signal output from the write signal generating unit, a clock terminal of the second flip-flop is configured to receive the first data strobe signal, the second flip-flop is used to output a second sampling signal based on the second write signal and the first data strobe signal, an output terminal of the first flip-flop is connected to a first terminal of the data selector, and an output terminal of the second flip-flop is connected to a second terminal of the data selector.

[0112] In this case, when controlling the write leveling circuit, if it is determined that the first sampling signal indicates that the effective edge of the first clock signal and the effective edge of the first data strobe signal are not aligned, before adjusting the delay of the first data strobe signal, the method of controlling the write leveling circuit includes: The method further includes sending a first control signal to the data selector, where the first control signal is used to instruct the data selector to output a first sampling signal, and receiving the first sampling signal output from the data selector.

[0113] After determining that the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned based on the first sampling signal output from the sampling unit, the control method of the write leveling circuit further includes sending a second control signal to the data selector, where the second control signal is used to instruct the data selector to output the second sampling signal.

[0114] For example, the execution subject of the present embodiment may be a controller outside the memory or other electronic devices, and the present disclosure is not particularly limited thereto. In the following, a case where the execution subject of the present disclosure is a controller will be described as an example.

[0115] When the sampling unit in the write leveling circuit includes a first flip-flop, a second flip-flop and a data selector, in the write leveling process, the controller needs to send a control signal to the data selector so that the data selector can select the currently required sampling signal from the first sampling signal output from the first flip-flop and the second sampling signal output from the second flip-flop connected to it.

[0116] First, in the write leveling process, the controller first needs to send a first control signal to the data selector, so that the data selector can output a first sampling signal to the controller until the controller determines based on the first sampling signal that the valid edge of the first clock signal and the valid edge of the first data strobe signal are aligned, at which time the external write leveling process in the write leveling process ends.

[0117] Also, when the controller determines that the valid edge of the first clock signal and the valid edge of the first data strobe signal are aligned, the controller can switch the first control signal sent to the data selector to a second control signal, so that after the data selector receives the second control signal, it outputs a second sampling signal generated by a second flip-flop connected thereto.

[0118] As can be understood, when the sampling unit in the write leveling circuit includes a first flip-flop, a second flip-flop, and a data selector, the controller changes the sampling signal output from the data selector by changing the control signal sent to the data selector, so that the controller can accurately receive the required first sampling signal or second sampling signal whether in external write leveling or internal write leveling.

[0119] 9 is a diagram showing signal changes according to an embodiment of the present disclosure. The diagram showing signal changes shown in FIG. 9 is a schematic diagram showing changes in a data strobe signal and a write signal when a write leveling process is performed by controlling a write leveling circuit. This embodiment will be described with reference to the write leveling circuit shown in FIG.

[0120] Illustratively, in this embodiment, the second clock signal in Fig. 9 is a clock signal received by the second converter 25 in the write leveling circuit. The write command corresponding to the command signal is a write command received by the decoder 211 in the write leveling circuit in Fig. 6. After receiving the write command, the decoder 211 generates a first write signal and sends the first write signal to the signal conversion module 213 connected to the decoder 211, and the signal conversion module 213 performs pulse stretching on the received first write signal, and further obtains a first write signal after pulse stretching (i.e., the first write signal after pulse stretching in Fig. 9). The signal conversion module 213 sends the first write signal after pulse stretching to the first delay module 212 connected to the signal conversion module 213, and the first delay module 212 performs delay processing on the first write signal after pulse stretching, thereby obtaining a second write signal (i.e., the second write signal in the external write leveling stage in the figure), which is input respectively to the first flip-flop 231 and the second flip-flop 232 connected to the first delay module 212. Also, as can be seen from the figure, in the external write leveling process, the delay between the first write signal after pulse stretching and the second write signal is the sum of the CAS write latency and the absolute delay, where the absolute delay is the delay occurring during signal transmission.

[0121] 9 is the data strobe signal received by the first converter 24 in the write leveling circuit at the end of the external write leveling process. The second data strobe signal in the external write leveling process in FIG. 9 is obtained after the first converter 24 performs level conversion on the third data strobe signal in the external write leveling process, outputs it to the delay unit 22 connected to the first converter 24, and the delay unit 22 performs delay processing on the signal input to the delay unit 22 by the first converter 24. Therefore, the delay between the third data strobe signal in the external write leveling process in FIG. 9 and the second data strobe signal in the external write leveling process is the sum of the delay by the delay unit 22 and the delay by the first converter 24. As can also be seen from the figure, after the external write leveling process is completed, the valid edge of the second write signal included in the external write leveling (i.e., the rising edge of the second write signal) and the valid edge of the second data strobe signal (i.e., the rising edge of the second data strobe signal) are aligned.

[0122] After the external write leveling is completed, the delay of the first data strobe signal is shortened by a first predetermined time length, and since the first data strobe signal is obtained by the first converter 24 in the write leveling circuit performing a level conversion process on the received third data strobe signal, the delay between the first data strobe signal and the third data strobe signal is a fixed delay caused by the first converter, and it is necessary to shorten the delay of the first data strobe signal by a first predetermined time length, that is, to shorten the delay of the third data strobe signal by a first predetermined time length. That is, after the third data strobe signal in the external write leveling is shifted forward by a first predetermined time length, the third data strobe signal of the intermediate process in Fig. 9 is obtained, and the third data strobe signal of the intermediate process is the third data strobe signal that the first converter 24 first receives in the internal write leveling in the write leveling process.

[0123] The second write signal in the internal write leveling process in the figure is the signal output from the write signal generating unit 21 in the write leveling circuit at the end of the internal write leveling process. The first data strobe signal in the internal write leveling process is the signal generated after the third data strobe signal of the intermediate process in the figure passes through the first converter 24. As can be seen from the figure, in the internal write leveling process, the second write signal output from the write signal generating unit 21 is shifted forward compared to the second write signal in the external write leveling process, that is, the delay is shortened, and the second write signal can only be shifted forward by an integer multiple of the clock period, so that in the internal write leveling process in the figure, the effective edge of the second write signal (i.e., its rising edge) may be located before the effective edge of the first data strobe signal (i.e., its rising edge) in the internal write leveling process, and therefore, in the internal write leveling process, the first data strobe signal output from the first converter 24 needs to be shifted forward, so that the effective edge of the first data strobe signal and the effective edge of the second write signal can be aligned.

[0124] In Fig. 9, the third data strobe signal in the internal write leveling process is a signal input to the first converter 24 when the valid edge of the first data strobe signal and the valid edge of the second write signal in the internal write leveling process are aligned. Then, the third data strobe signal is shifted backward by a second predetermined time to obtain the final third data strobe signal in Fig. 9. Then, when performing a write operation on the memory, the write leveling process determines the final third data strobe signal as the data strobe signal sent from the controller to the memory pin, so that the memory can accurately write data.

[0125] 10 is a diagram showing another signal change according to an embodiment of the present disclosure. The diagram showing the signal change shown in FIG. 10 is a schematic diagram showing the change of the data strobe signal and the write signal when the write leveling process is performed by controlling the write leveling circuit. This embodiment will be described with reference to the write leveling circuit shown in FIG.

[0126] 10 is a clock signal received by the second converter 25 in the write leveling circuit, and the write command corresponding to the command signal is a write command received by the decoder 211 in the write leveling circuit in FIG.

[0127] The second write signal and the second data strobe signal in the external write leveling process in the figure are respectively the signals output from the write signal generating unit 21 and the delay unit 22 at the end of the external write leveling. The third data strobe signal in the external write leveling process in the figure is the data strobe signal received by the first converter 24 at the end of the external write leveling process. After the external write leveling process is completed, the first data strobe signal output from the first converter 24 needs to be shifted forward by a first predetermined time length. Since the delay between the third data strobe signal input to the first converter 24 and the first data strobe signal output from the first converter 24 is fixed, shifting the first data strobe signal forward by a first predetermined time length is equivalent to shifting the third data strobe signal input to the first converter 24 forward by a first predetermined time length (i.e., 1.25tck in the figure), thereby obtaining the third data strobe signal of the intermediate process.

[0128] In the internal write leveling process, the second write signal output from the write signal generating unit 21 at the end of the external write leveling process (i.e., the initial second write signal in the internal write leveling process in the figure) needs to be shifted forward, and the delay of the third data strobe signal input to the first converter 24 needs to be adjusted, so that the valid edge of the second write signal output from the write signal generating unit 21 can be aligned with the valid edge of the first data strobe signal output from the first converter 24.

[0129] In the figure, if it is determined that after shifting the initial second write signal, the effective edge of the second write signal output from the write signal generating unit 21 is aligned with the effective edge of the first data strobe signal output from the first converter 24, there is no need to adjust the delay of the data strobe signal input to the first converter 24 (i.e., the data strobe signal of the intermediate process in the figure).

[0130] After the internal write leveling process is completed, the third data strobe signal input to the first converter 24 at the end of the process, i.e., the third data strobe signal in the intermediate process in the figure, is shifted backward by a second predetermined time length (i.e., 1.75 tck in the figure), thereby obtaining a final third data strobe signal. In the figure, the final third data strobe signal in the figure has two rising edges of the signal, i.e., the edges of the signal indicated by two dashed arrows in the figure. As can be seen from the figure, the delays between these two rising edges and the effective edge (i.e., the rising edge) of the second clock signal are -0.5 tck and 0.5 tck, respectively, and the delay difference corresponds to the time difference required by the memory standard (for example, the time difference may be a tDQSoffest parameter required for the memory in actual application). Therefore, when transmitting data to be written to the memory subsequently, the data to be written to the memory can be transmitted based on the time corresponding to either of the two rising edges of the final third data strobe signal shown in the figure.

[0131] FIG. 11 is a schematic diagram showing the configuration of a control device of a write leveling circuit applied to a memory provided in the present disclosure, the control device being applied to a circuit provided in any of the embodiments of FIGS. 2 to 6, and the control device comprising a first adjustment unit 1101, a first control unit 1102, and a second adjustment unit 1103.

[0132] The first adjustment unit 1101 is configured to adjust a delay of the first data strobe signal when it determines that the first sampling signal represents that the effective edge of the first clock signal and the effective edge of the first data strobe signal are not aligned, and repeatedly executes the first adjustment unit until the first adjustment unit determines, based on the first sampling signal output from the sampling unit, that the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned.

[0133] the first control unit 1102 is configured to control decreasing a delay of the first data strobe signal by a first predetermined time when the first sampling signal determines that the first clock signal and the first data strobe signal are aligned, and the decreased signal is the first data strobe signal currently received by the sampling unit; The second adjustment unit 1103 is configured to adjust the delay of the first data strobe signal or the delay of the first write signal when it determines that the second sampling signal indicates that the effective edge of the first data strobe signal and the effective edge of the second write signal are not aligned, and repeatedly executes the second adjustment unit until the second adjustment unit determines based on the second sampling signal output from the sampling unit that the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned.

[0134] The device provided in this embodiment is for realizing the technical solution provided by the above method, and the realization principle thereof is the same as the technical effect, which will not be described again.

[0135] FIG. 12 is a schematic diagram showing the configuration of another control device of a write leveling circuit applied to a memory provided in the present disclosure, the device further comprising an extension unit 1104; The extension unit 1104 is configured to extend the delay of the first data strobe signal by a second predetermined time when it determines that the valid edge of the first data strobe signal and the valid edge of the second write signal are aligned, and to determine the extended signal as the data strobe signal received when the memory performs a write operation.

[0136] In some embodiments, the first adjustment unit 1101 is configured to determine that the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned when it is determined based on the first sampling signal output from the sampling unit, specifically, when the level value of the first sampling signal output from the sampling unit changes from a first level value to a second level value.

[0137] In some embodiments, the second adjusting unit 1103 is configured to determine that the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned when it is determined based on the second sampling signal output from the sampling unit that the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned, specifically, when the level value of the second sampling signal output from the sampling unit changes from the second level value to the first level value.

[0138] In some embodiments, the write signal generating unit includes a decoder and a first delay module, where the decoder is configured to decode and process the received write command to output a first write signal; the first delay module is connected to the decoder and configured to perform a delay process on the first write signal based on the received first clock signal, and output a second write signal; the first delay module is specifically configured to perform a delay process on the first write signal based on the received first clock signal, the CAS write latency of the memory, and a first instruction signal, and output the second write signal, where the first instruction signal is used to indicate a shortened time of the CAS write latency of the memory.

[0139] The first adjusting unit 1101 includes a first adjusting module 11011, a first sending module 11012, a second adjusting module 11013, and a second sending module 11014.

[0140] The first adjustment module 11011 is configured to increase the reduction time of the CAS write latency of the memory indicated in the first instruction signal by adjusting the first instruction signal received by the first delay module when it determines that the level value of the second sampling signal output from the sampling unit is the first level value.

[0141] The first sending module 11012 is configured to send a write command to the decoder and send the adjusted first instruction signal to the first delay module.

[0142] The first adjusting module 11011 and the first sending module 11012 are repeatedly executed until the level value of the second sampling signal output from the sampling unit switches from the first level value to the second level value.

[0143] The second adjustment module 11013 is configured to reduce the delay of the first data strobe signal received at the sampling unit.

[0144] The second transmitting module 11014 is configured to send a write command to the decoder and send a delay signal to the first delay module, where the delay signal is the first instruction signal received by the first delay module when the second sampling signal output from the sampling unit switches from the first level value to the second level value.

[0145] The second adjusting module 11013 and the second sending module 11014 are repeatedly executed until the level value of the second sampling signal output from the sampling unit switches from the second level value to the first level value.

[0146] In some embodiments, the sampling unit comprises a first flip-flop, a second flip-flop, and a data selector, where a data terminal of the first flip-flop is connected to the write signal generating unit and used to receive a second write signal output from the write signal generating unit; a clock terminal of the first flip-flop is connected to an output terminal of the delay unit and used to receive a second data strobe signal output from the delay unit; the first flip-flop is configured to output a first sampling signal based on the second write signal and the second data strobe signal; a data terminal of the second flip-flop is connected to the write signal generating unit and used to receive the second write signal output from the write signal generating unit; a clock terminal of the second flip-flop is used to receive the first data strobe signal; the second flip-flop is configured to output a second sampling signal based on the second write signal and the first data strobe signal; an output terminal of the first flip-flop is connected to a first terminal of the data selector; and an output terminal of the second flip-flop is connected to a second terminal of the data selector.

[0147] The control device of the light leveling circuit further includes a first sending unit 1105 and a second sending unit 1106, and the first sending unit 1105 is configured to send a first control signal to the data selector before adjusting the delay of the first data strobe signal when the first adjusting unit 1101 determines that the first sampling signal represents that the effective edge of the first clock signal and the effective edge of the first data strobe signal are not aligned, and the first control signal is used to instruct the data selector to output the first sampling signal; The second transmitting unit 1106 is configured to send a second control signal to the data selector after determining, based on the first sampling signal output from the first adjusting unit 1101 sampling unit, that the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned, and the second control signal is used to instruct the data selector to output the second sampling signal.

[0148] The device provided in this embodiment is for realizing the technical solution provided by the above method, and the realization principle thereof is the same as the technical effect, which will not be described again.

[0149] The present disclosure provides a memory, the memory including a circuit provided in any of the embodiments of FIGS.

[0150] The present disclosure provides an electronic device comprising a processor and a memory communicatively connected to the processor, where the memory stores computer-executable instructions, and where the processor executes the computer-executable instructions stored in the memory to implement a method provided in either of the embodiments of FIG. 7 or FIG. 8.

[0151] FIG. 13 is an exemplary structural diagram of an electronic device according to an embodiment of the present disclosure. As shown in FIG. 13, the electronic device includes: The electronic device includes a processor 291, and may further include a memory 292, and may include a communication interface 293 and a bus 294. Here, the processor 291, the memory 292, and the communication interface 293 can complete communication with each other via the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can call the logic instructions in the memory 292 to execute the method of the above embodiment.

[0152] Furthermore, the logic instructions in the memory 292 described above may be implemented in the form of a software functional unit, and may be stored in a computer-readable storage medium when sold or used as an independent product.

[0153] The memory 292 can be used as a computer-readable storage medium to store software programs, computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present disclosure. The processor 291 executes the software programs, instructions and modules stored in the memory 292 to execute the function applications and data processing, i.e., to realize the methods in the above embodiments.

[0154] The memory 292 may include a storage program area and a storage data area, where the storage program area can store an operating system, an application program necessary for at least one function, etc., and the storage data area can store data created according to the use of the terminal device, etc. The memory 292 may also include a high-speed random access memory, or may include a non-volatile memory.

[0155] The present disclosure provides a computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement the method provided in either of the embodiments of FIG. 7 or FIG.

[0156] The present disclosure provides a computer program product including a computer program which, when executed on a processor, implements the method provided in any of the embodiments of FIG. 7 or FIG.

[0157] Those skilled in the art will readily conceive other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any modifications, applications or adaptations of the present disclosure, which modifications, applications or adaptations follow the general principles of the present disclosure and include common knowledge or conventional technical means in the art that are not disclosed by the present disclosure. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

[0158] It should be understood that the present disclosure is not limited to the exact construction described above and illustrated in the drawings, and various modifications and changes can be made without departing from the scope thereof, which is limited only by the appended claims.

[0159] Those skilled in the art will readily conceive other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any modifications, applications or adaptations of the present disclosure, which modifications, applications or adaptations follow the general principles of the present disclosure and include common knowledge or conventional technical means in the art that are not disclosed by the present disclosure. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

[0160] It should be understood that the present disclosure is not limited to the exact construction described above and illustrated in the drawings, and various modifications and changes can be made without departing from the scope thereof, which is limited only by the appended claims. [Explanation of symbols]

[0161] 21 Write signal generation unit 211 Decoder 212 First Delay Module 213 Signal conversion module 214 Second Delay Module 22 Delay Unit 23 Sampling Unit 231 1st Flip-Flop 232 2nd Flip-Flop 233 Data Selector 24 1st Converter 25 Second Converter 26 3rd Converter 27 Upward Delay Unit 28 Upper Sampling Unit 281 3rd Flip-Flop 282 4th Flip-Flop 283 Upper Data Selector

Claims

1. A write leveling circuit for use in a memory, comprising: a write signal generating unit, a delaying unit, and a sampling unit; The write signal generating unit is configured to perform a delay process on a first write signal based on a received first clock signal, and output a second write signal; The delay unit is configured to perform a delay process on the received first data strobe signal and output a second data strobe signal; the sampling unit is respectively connected to the delay unit and the write signal generating unit, configured to receive the second data strobe signal output from the delay unit and the second write signal output from the write signal generating unit, and output a first sampling signal according to the second data strobe signal and the second write signal; the sampling unit is further configured to receive the first data strobe signal and the second write signal output from the write signal generating unit, and output a second sampling signal according to the first data strobe signal and the second write signal; The write signal generating unit comprises a decoder and a first delay module; The decoder is configured to decode a received write command and output the first write signal; the first delay module is connected to the decoder and configured to perform a delay process on the first write signal based on the received first clock signal, and output the second write signal; Light leveling circuit.

2. The first delay module comprises: The first write signal is delayed based on the received first clock signal, the CAS write latency of the memory, and a first instruction signal, and the second write signal is output, and the first instruction signal is used to indicate a time for reducing the CAS write latency of the memory.

2. The write leveling circuit according to claim 1.

3. The write signal generating unit further includes a signal converting module, and the decoder is connected to the first delay module through the signal converting module; The signal conversion module is configured to perform a pulse stretching process on the first write signal output from the decoder, and output the stretched write signal to the first delay module.

2. The write leveling circuit according to claim 1.

4. the sampling unit includes a first flip-flop, a second flip-flop, and a data selector; a data terminal of the first flip-flop is connected to the write signal generating unit and is used for receiving a second write signal output from the write signal generating unit; a clock terminal of the first flip-flop is connected to an output terminal of the delay unit and is used for receiving a second data strobe signal output from the delay unit; and the first flip-flop is used for outputting a first sampling signal according to the second write signal and the second data strobe signal; a data terminal of the second flip-flop is connected to the write signal generating unit and is used for receiving a second write signal output from the write signal generating unit; a clock terminal of the second flip-flop is used for receiving the first data strobe signal; and the second flip-flop is used for outputting a second sampling signal according to the second write signal and the first data strobe signal; an output terminal of the first flip-flop is connected to a first terminal of the data selector, and an output terminal of the second flip-flop is connected to a second terminal of the data selector; 2. The write leveling circuit according to claim 1.

5. the write leveling circuit further comprises a first converter; The first converter is respectively connected to the delay unit and the sampling unit, and configured to perform logic level conversion on the received third data strobe signal to obtain the first data strobe signal, where the level of the third data strobe signal is a current mode logic level, and the level of the first data strobe signal is a CMOS level; and / or the write leveling circuit further comprises a second converter; The second converter is connected to the write signal generating unit and configured to perform logic level conversion on the received second clock signal to obtain the first clock signal, where the level of the second clock signal is a current mode logic level, and the level of the first clock signal is a CMOS level.

2. The write leveling circuit according to claim 1.

6. the first sampling signal indicates whether an effective edge of the first clock signal and an effective edge of the first data strobe signal are aligned or not, and the first sampling signal is used to indicate that a delay of the first data strobe signal should be adjusted if the first sampling signal indicates that an effective edge of the first clock signal and an effective edge of the first data strobe signal are not aligned; and / or the second sampling signal indicates whether an effective edge of the first data strobe signal and an effective edge of the second write signal are aligned, and the second sampling signal is used to instruct to adjust a delay of the first write signal or a delay of the first data strobe signal when the first sampling signal indicates that an effective edge of the first clock signal and an effective edge of the first data strobe signal are aligned and an effective edge of the first data strobe signal and an effective edge of the second write signal are not aligned.

2. The write leveling circuit according to claim 1.

7. A method for controlling a write leveling circuit applied to a memory, the method being applied to the circuit according to claim 1, comprising the steps of: if it is determined that the first sampling signal indicates that the effective edge of the first clock signal and the effective edge of the first data strobe signal are not aligned, iteratively adjusting the delay of the first data strobe signal until it is determined, based on the first sampling signal output from the sampling unit, that the effective edge of the first data strobe signal and the effective edge of the first clock signal are aligned; if determining that the first sampling signal represents an active edge of the first clock signal and an active edge of the first data strobe signal that are aligned, controlling a delay of the first data strobe signal to be decreased by a first predetermined time, the decreased signal being the first data strobe signal currently received by the sampling unit; and when it is determined that the second sampling signal indicates that the effective edge of the first data strobe signal and the effective edge of the second write signal are not aligned, repeatedly adjusting a delay of the first data strobe signal or a delay of the first write signal based on the second sampling signal output from the sampling unit until it is determined that the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned.

8. The method for controlling the write leveling circuit includes the steps of: and if an effective edge of the first data strobe signal and an effective edge of the second write signal are aligned, extending a delay of the first data strobe signal by a second predetermined time and determining the extended signal as a data strobe signal received when the memory performs a write operation; Determining that an effective edge of a first data strobe signal and an effective edge of a first clock signal are aligned based on a first sampling signal output from the sampling unit, determining that an effective edge of a first data strobe signal and an effective edge of a first clock signal are aligned when a level value of a first sampling signal output from the sampling unit changes from a first level value to a second level value; determining, based on a second sampling signal output from the sampling unit, that an effective edge of the first data strobe signal and an effective edge of the second write signal are aligned; determining that an effective edge of the first data strobe signal and an effective edge of the second write signal are aligned when a level value of a second sampling signal output from the sampling unit changes from the second level value to the first level value; 8. A method for controlling a write leveling circuit according to claim 7.

9. The write signal generating unit includes a decoder and a first delay module, the decoder is configured to decode a received write command and output the first write signal, the first delay module is connected to the decoder and configured to perform a delay process on the first write signal based on the received first clock signal, and output the second write signal, the first delay module is configured to perform a delay process on the first write signal based on the received first clock signal, a CAS write latency of the memory, and a first indication signal, and output the second write signal, the first indication signal is used to indicate a shortened time of the CAS write latency of the memory, when determining that the second sampling signal indicates that the valid edge of the first data strobe signal and the valid edge of the second write signal are not aligned, repeating adjusting the delay of the first data strobe signal or the delay of the first write signal until determining that the valid edge of the first data strobe signal and the valid edge of the second write signal are aligned based on the second sampling signal output from the sampling unit; When it is determined that the level value of the second sampling signal output from the sampling unit is the first level value, adjusting the first indication signal received by the first delay module until the level value of the second sampling signal output from the sampling unit switches from the first level value to the second level value, thereby increasing the reduction time of the CAS write latency of the memory indicated by the first indication signal, sending a write command to the decoder, and repeating the sending of the adjusted first indication signal to the first delay module; and repeatedly decreasing a delay of a first data strobe signal received by the sampling unit, sending a write command to the decoder, and sending a delay signal to the first delay module until a level value of a second sampling signal output from the sampling unit switches from the second level value to the first level value, wherein the delay signal is a first indication signal received by the first delay module when the second sampling signal output from the sampling unit switches from the first level value to the second level value.

9. The method for controlling a write leveling circuit according to claim 8.

10. The sampling unit includes a first flip-flop, a second flip-flop, and a data selector, a data terminal of the first flip-flop is connected to the write signal generating unit and is used to receive a second write signal output from the write signal generating unit, a clock terminal of the first flip-flop is connected to an output terminal of the delay unit and is used to receive a second data strobe signal output from the delay unit, and the first flip-flop is used to output a first sampling signal according to the second write signal and the second data strobe signal. a data terminal of the second flip-flop is connected to the write signal generating unit and is used to receive a second write signal output from the write signal generating unit; a clock terminal of the second flip-flop is used to receive the first data strobe signal; the second flip-flop is used to output a second sampling signal according to the second write signal and the first data strobe signal; an output terminal of the first flip-flop is connected to a first terminal of the data selector; and an output terminal of the second flip-flop is connected to a second terminal of the data selector; If it is determined that the first sampling signal indicates that an effective edge of the first clock signal and an effective edge of the first data strobe signal are not aligned, before adjusting a delay of the first data strobe signal, the method of controlling the write leveling circuit includes: sending a first control signal to the data selector, the first control signal being used to instruct the data selector to output a first sampling signal; After determining that an effective edge of a first data strobe signal and an effective edge of a first clock signal are aligned based on a first sampling signal output from the sampling unit, the method for controlling the write leveling circuit includes: and transmitting a second control signal to the data selector, the second control signal being used to instruct the data selector to output a second sampling signal.

8. A method for controlling a write leveling circuit according to claim 7.

11. A control device for a write leveling circuit applied to a memory, which is applied to the circuit according to claim 1, comprising: a first adjustment unit, a first control unit, and a second adjustment unit; The first adjusting unit is configured to adjust a delay of the first data strobe signal when the first sampling signal determines that an effective edge of the first clock signal and an effective edge of the first data strobe signal are not aligned, and repeatedly execute the first adjusting unit until the first adjusting unit determines, based on the first sampling signal output from the sampling unit, that an effective edge of the first data strobe signal and an effective edge of the first clock signal are aligned; the first control unit is configured to control a delay of the first data strobe signal to be decreased by a first predetermined time when the first sampling signal determines that the first clock signal and the first data strobe signal are aligned, and to make the decreased signal the first data strobe signal currently received by the sampling unit; A control device for a write leveling circuit, wherein the second adjustment unit is configured to adjust a delay of the first data strobe signal or a delay of the first write signal when it determines that the second sampling signal indicates that the effective edge of the first data strobe signal and the effective edge of the second write signal are not aligned, and the second adjustment unit repeatedly executes the second adjustment unit until it determines, based on the second sampling signal output from the sampling unit, that the effective edge of the first data strobe signal and the effective edge of the second write signal are aligned.

12. A memory comprising the write leveling circuit according to any one of claims 1 to 6.

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