Integrated Circuit Interconnect Shape Optimizer

Abstract

Systems, devices, and methods for optimization of conductive interconnects are described. The method includes receiving an integrated circuit layout including a plurality of terminals and interconnects, where the interconnects represent conductive couplings between the plurality of terminals. The method includes receiving terminal information describing operational parameters of the plurality of terminals. The method includes receiving layer information describing material compositions and material property information of the plurality of terminals and the interconnects. The method includes generating a three-dimensional representation of the integrated circuit using the integrated circuit layout and the layer information. The method includes using the three-dimensional representation and the terminal information to determine individual contributions of cells included in the three-dimensional representation to a resistance-capacitance (RC) value of the interconnect. The method also includes generating an updated integrated circuit layout based at least in part on the individual contributions.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63 / 310,750, filed February 16, 2022, which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to integrated circuits, and more particularly, but not exclusively, to first principles electronic design automation for shape optimization and layout generation of integrated circuits. [Background technology]

[0003] Routing is a fundamental problem in electronic design and automation that generates wires for interconnecting pins of common signals while following manufacturing design rules. For very large scale integrated circuit designs, where there may be billions of transistors in a single chip, optimizing routing is especially difficult due to the complexity of the integrated circuits. Routing is usually divided into at least a global routing stage and a detailed routing stage, where the global routing plan generates the routing paths without considering the manufacturing design rules of a given vendor process node, and the detailed routing determines the exact route.

[0004] A typical routing algorithm may be generated using a multi-dimensional grid-based graph search technique (e.g., a two-dimensional grid with a third dimension corresponding to the routing layer), where the routing resources are modeled as a graph whose graph topology can represent the structure of the integrated circuit. A global routing can then partition the graph into tiles and find inter-tile paths to guide a detailed router. The detailed router then finds an exact wiring route by overlaying a grid on the graph, where each unit of the grid is equal to or larger than the sum of the minimum width and spacing of the wires for a given vendor process node. A typical router generates detailed routes sequentially and may have a preferred routing direction (i.e., metal wires arranged horizontally or vertically with respect to different metallization layers of the integrated circuit) and thus be limited in both efficiency and geometry (e.g., limited to the Manhattan routing convention of vertical and horizontal straight lines). Summary of the Invention [Means for solving the problem]

[0005] Non-limiting, non-exhaustive embodiments of the present invention are described with reference to the following figures, in which like reference numerals refer to like parts throughout the various views unless otherwise specified. Where appropriate, not every instance of an element is labeled in order to avoid cluttering the figures. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles being described. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic diagram of an exemplary system for modifying conductive interconnects in an integrated circuit layout in accordance with an embodiment of the present disclosure. [Diagram 2] 1 is a schematic diagram illustrating an exemplary process for generating an updated layout of interconnects of an integrated circuit according to an embodiment of the present disclosure. [Figure 3A]FIG. 1 is a schematic diagram illustrating a toy model of a two-port interconnect according to an embodiment of the present disclosure. [Figure 3B] 1A-1C are schematic diagrams illustrating an exemplary variable width interconnect coupling two terminals according to an embodiment of the present disclosure. [Figure 4A] 1 is a schematic diagram illustrating an example floor plan view of a simplified three-dimensional representation of at least a portion of a layout file describing an interconnect that couples two terminals (e.g., a two-port interconnect) in accordance with an embodiment of the present disclosure. [Figure 4B] 4B is an example floor plan view of an updated layout generated from the example floor plan 500 of FIG. 4A according to a first set of terminal information 220, in accordance with an embodiment of the present disclosure. [Figure 4C] FIG. 4B is another example floor plan view of an updated layout generated from the example floor plan of FIG. 4A using a second set of terminal information in accordance with an embodiment of the present disclosure. [Figure 4D] FIG. 4B is another example floor plan view of an updated layout generated from the example floor plan of FIG. 4A using a third set of terminal information in accordance with an embodiment of the present disclosure. [Figure 5A] 1 is a schematic diagram illustrating an example three-dimensional representation of a layout file according to an embodiment of the present disclosure. [Figure 5B] FIG. 2 is a schematic diagram illustrating an exemplary three-dimensional representation of an updated layout according to an embodiment of the present disclosure. [Figure 6A] FIG. 2 is a schematic diagram illustrating an example floor plan of a layout file according to an embodiment of the present disclosure. [Figure 6B] FIG. 2 is a schematic diagram illustrating an example floor plan view of an updated layout in an intermediate state, according to an embodiment of the present disclosure. [Figure 6C] FIG. 1 is a schematic diagram illustrating an example floor plan of an advanced updated layout according to an embodiment of the present disclosure. [Figure 7] 3 is a block diagram illustrating an example flow of operations applied to a three-dimensional representation as part of the example process 200 of FIG. 2 according to an embodiment of the present disclosure. [Figure 8]FIG. 1 is a schematic diagram illustrating an example three-dimensional representation of an updated layout file including a fan-out configuration, according to an embodiment of the present disclosure. [Figure 9] FIG. 1 is a schematic diagram illustrating an example three-dimensional representation of an updated layout file including a fan-in-out configuration, according to an embodiment of the present disclosure. [Figure 10] FIG. 2 is a block diagram illustrating an example flow for modifying the shape of a fan-in or fan-in-out layout file, according to an embodiment of the present disclosure. [Figure 11] 1 is a schematic diagram illustrating an example three-dimensional representation of a multi-layer layout file including multiple interconnects coupling multiple terminals in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] An embodiment of a system and method for cell-based detailed interconnect routing based on RC simulation is described herein. In the following description, many specific details are described to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein can be implemented without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0008] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0009] Most fundamental properties of integrated circuits are related to resistance and capacitance. The delay in charging and discharging an integrated circuit element with each clock cycle is given directly by the RC time constant. Capacitance is related to the amount of charge flowing into and out of the circuit, so that a current can be drawn and subsequently the power required to operate the integrated circuit. Furthermore, Joule heat generated during operation also results directly from resistance and current. As a result of the increasing miniaturization, phenomena such as electromigration and dielectric breakdown affect the reliability of integrated circuits, which are present in the conductors (e.g. metals such as Au, Ag, Al, Cu, Ti, their combinations to form metal alloys) and between conductors (e.g. SiO2, SiO x It is also related to the electric field strength in a material (such as an oxide or other insulator).

[0010] Described herein are embodiments of an iterative cell-based integrated circuit (IC) optimizer that implements first principles techniques for modifying detailed interconnect geometry of an integrated circuit layout. In this context, an integrated circuit layout describes a graphical and / or numerical representation of at least a portion of an integrated circuit, such as a layer of the integrated circuit, that includes one or more interconnects between one or more terminals. In this context, a terminal is a contact associated with an IC element, also called a port, and an interconnect is a conductive material that electrically couples two or more terminals. An interconnect is also called a "net" or "wire", following technical terminology used in the field of IC layout routing.

[0011] An integrated circuit layout can describe the locations and dimensions of multiple interconnects and multiple types of terminals. For example, an interconnect can electrically couple multiple input terminals to a single output terminal (referred to as a "fan-in" configuration). In another example, an interconnect can electrically couple a single input terminal to multiple output terminals (referred to as a "fan-out" configuration). In yet another example, an interconnect can electrically couple multiple input terminals to multiple output terminals (referred to as a "fan-in-out" configuration). In some embodiments, an interconnect electrically couples one or more drivers to one or more loads, for example as part of powering one or more transistors.

[0012] Analytical solutions for the RC values ​​of interconnects that incorporate physically meaningful terms are virtually unavailable for the dimensions and geometries employed in IC layouts. Therefore, finite volume methods, finite element methods, or other types of 3D full-field numerical simulation methods may be used to determine the RC values. In particular, a three-dimensional representation of an IC layout may be generated to discretize the layout into an array of volumetric elements called cells or voxels. The cells are characterized by uniform material properties that correspond to the location of the cells in the IC layout. As an example, cells at the location of an interconnect in an IC layout may be defined as a conductor (e.g., metal). In another example, cells at the location outside the interconnect may be defined as a dielectric or insulator (e.g., oxide). The materials may include materials used in multi-layer CMOS processes applied to IC manufacturing.

[0013] The three-dimensional representation shows at least a portion of an integrated circuit including interconnects and terminals that can be used for simulation of the contribution of individual cells to the RC time constant of the interconnect. The RC time constant of the interconnect can be simulated from the material properties of the individual cells and the operating parameters of the terminals. Simulation of the capacitive and conductive contributions of each cell to the overall electrical properties (e.g., conductance and capacitance) of the interconnect and / or dielectric can be used to reshape the interconnect, including reallocating the material of the individual cells, as a way to optimize the RC time constant of the interconnect.

[0014] Advantageously, the techniques described herein facilitate a departure from the convention of straight interconnect layout. Currently, vendor process nodes are approaching the optical resolution threshold of semiconductor manufacturing systems. Straight routing and the emphasis on edge-placement error as a figure of merit for manufacturability and process optimization constrain conventional layout designs and introduce inefficiencies into the operation of integrated circuits. Thus, the curvilinear layout shown in the preceding figures represents a major advancement toward improved integrated circuit design in the context of nanometer process nodes. For example, the techniques described herein allow retention of function, rather than edge-placement error, to guide manufacturability decisions, allowing physically meaningful RC values ​​of the IC layout to serve as optimization metrics. Modifications can be made to the interconnect that optimize the RC values ​​and improve the overall performance and robustness of the IC interconnect in ways not available with the current straight routing convention.

[0015] 1 is a schematic diagram of an exemplary system 100 for modifying conductive interconnects of an integrated circuit layout, according to an embodiment of the present disclosure. The exemplary system 100 includes one or more servers 105, one or more client computing devices 110, one or more semiconductor manufacturing systems 115, and a network 120. The server 105 includes a first database 125 of training data 130, a second database 135 of process data 137, a shape optimizer 140, and one or more machine learning models 150 encoded in software 155. As part of the software 155, the server 105 includes instructions for the shape optimizer 140 and / or the models 150 to be trained and / or deployed using a computer circuit 160. In some embodiments, the server 105 further includes a third database 165 that stores a design file 170, also referred to as an integrated circuit layout file, which may be stored in one or more database file formats, including but not limited to GDSII or OASIS.

[0016] The following description focuses on embodiments of the present disclosure that implement a networked system for deploying shape optimizer 140 as part of a detailed routing platform for optimization of integrated circuit layout 170. However, it is contemplated that some embodiments of the present disclosure include some or all of the processes performed on a client computing device 110, such as a laptop or personal computer. For example, training of an untrained model 150 can be performed using server 105, while a trained model 150 can be transferred to client computing device 110 via network 120 and deployed directly onto client computing device 110. Similarly, components of exemplary system 100 can be hosted and / or stored on a distributed computing system (e.g., a cloud system) rather than a single system. For example, the first database 125, the second database 135, the third database 165, and / or the computer circuitry 160 may be implemented in a distributed system such that portions of the training data 130, the process data 137, the software 155, and / or the design files 170 may be stored or executed by distributed computing systems in one or more physical locations.

[0017] In an illustrative example of the operation of the exemplary system 100, a user of a client computing device 110 prepares a layout 170 (with reference to FIG. 2 ) that describes an integrated circuit to be manufactured using the manufacturing system 115. In a typical system, the layout 170 is routed based on design rules, which may be encoded into software that may be stored and / or hosted on the server 105 and / or the client computing device 110. Design rule checking software generates a Boolean result indicating whether the design is manufacturable, and may also provide Boolean values ​​for "required" or "recommended" rules. With the design rule checking software, the layout 170 may be easily identified as compliant or non-compliant, but is manually corrected.

[0018] To that end, the layout 170 may be processed using shape optimizer 140 software 155 stored on the server 105 and / or client computing device 110 to generate an updated layout 270 that is optimized with respect to physically meaningful parameters, including but not limited to RC time constants. In some embodiments, the layout 170 is transferred over the network 120 to the server 105 where the shape optimizer 140 processes the layout 170. In some embodiments, the shape optimizer 140 is implemented as part of an interactive design environment hosted on the client computing device 110 and / or server 105, such as a browser environment or a graphical user interface that presents layout information and one or more tools for designing the layout file 170.

[0019] Optimization criteria may also include targets for power consumption, integrated circuit area, processing power, and design and / or wafer-scale yield, which may be application specific. In this manner, the aggregate effect of multiple detailed routing optimizations may be determined and evaluated against a global optimization goal. Additionally, composite optimization factors may be used to guide the detailed routing. In an illustrative example, for designs used in highly specialized, space- or power-constrained, or defect-intolerant applications, a lower yield may be tolerated in preference to other goals. For high-volume applications where defects are tolerable or size is unlimited, yield may be prioritized at the expense of area or processing power. Similarly, indirect quantities may be adapted for use as optimization goals. For example, the total cost of ownership of application-specific integrated circuits used in data center operations may be applied as an optimization function.

[0020] The manufacturing system 115 is an example of a complex system in the pipeline between layout design and a semiconductor foundry that processes integrated circuit layouts and converts design data into mask data. The mask data is then used to generate photomasks used in the photolithography process of physical semiconductor device manufacturing. In the context of the exemplary system 100, the manufacturing system 115 is represented by a network interface computer (e.g., a server) for ease of visual description. Typically, multiple processes (e.g., inverse lithography, optical proximity correction, process correction code) are completed between "tape-out," which refers to the point at which an integrated circuit design rule compliant design is sent to a foundry, and the fabrication of the compliant integrated circuit on a wafer.

[0021] In some embodiments, the software 155 implements the shape optimizer 140 in a manner that generates one or more updated layouts 270 from the layout 170. In some cases, the updated layouts 270 are merged to generate an updated layout 270 that includes multiple layers, and the updated layout 270 is output for a user, for example, as part of an interactive design environment. Outputting may include, but is not limited to, transfer to the client computing device 110 over the network 120 and / or storing the updated layout 270 and / or optimization data in the third database 165. When the example system 100 operates as part of an interactive design environment, outputting the manufacturability data may include generating and communicating user interface data that causes the client computing device 110 to present the manufacturability parameter data on the display 111.

[0022] In some embodiments, updated and / or new process data 137 is received from the manufacturing system 115. Semiconductor processing technology is constantly improving as new devices and techniques are developed, and thus, the example system 100 is contemplated to support retraining of the shape optimizer 140 and preparation of new models 145-150 upon changes to the process data 137 or when new process data 137 is received.

[0023] In the illustrated embodiment, shape optimizer 140 includes functional subunits described as modules 141-149 that are used to generate an updated integrated circuit layout 270. In some embodiments, shape optimizer 140 includes discretization module 141 configured to ingest layout data 215 (with reference to FIG. 2 ) that is used to generate a three-dimensional representation of layout file 170 that includes a number of cells. Shape optimizer 140 may include physics simulation module 143 configured to solve electromagnetic equations as part of an electromagnetic simulation of integrated circuit layout 170. Physics simulation module 143 may enable exemplary system 100 to determine local contributions of cells to at least some performance metrics of layout 170, which may include, but are not limited to, RC values ​​of interconnects. Shape optimization module 145 may be included that is configured to implement physically meaningful heuristics based on one or more outputs of physics simulation module 143. For example, shape optimization module 145 may include routines in software 155 for modifying the definition of one or more cells of the three-dimensional representation of layout 170 according to relationships between the contributions of individual cells near the boundaries of an interconnect.

[0024] In some embodiments, the operations of the physics simulation module 143 may be supplemented and / or implemented by one or more machine learning models 144 trained to generate at least a portion of the updated layout 270 using the layout file 170 as input. In an illustrative example, the machine learning model 144 may be or include a deep convolutional neural network model trained using the updated layout 270 generated using the physics simulation module 143. For example, a database of training data 146 may be generated by optimizing multiple layout files 170 using physics-based simulation. The training data may include paired layout files 170 with corresponding updated layouts 270 that allow the machine learning model 144 to be trained by supervised learning. In some embodiments, the shape optimizer 140 generates the updated layout 270 by first generating an output layout of the machine learning model 144 that is subsequently optimized by the physics simulation module 143. Advantageously, supplementing the physics simulation module 143 with the machine learning model 144 in this manner may reduce the number of iterations of the physics simulation module 143 used to generate the updated layout 270.

[0025] In some embodiments, the shape optimizer 140 includes a process simulator 147 configured to perform a simulation of the manufacturability of the updated layout 270. In some embodiments, the process simulator 147 can perform a manufacturability analysis based on process node design rules and / or functionality retention criteria. A modification module 149 configured to modify the updated layout 270 in light of an output returned by the process simulator 147 can be provided. For example, if the process simulator 147 indicates that the updated layout 270 is not manufacturable by the semiconductor manufacturing system 115, the modification module 149 can modify the updated layout to satisfy the manufacturability constraints of the semiconductor manufacturing system 115. The techniques described herein can be applied at multiple distinct scales. For example, the routing of the interconnects can be performed at a first scale, while optimization of the shape of the individual interconnects can be performed using smaller scales, each scale can correspond to a distinct size of a cell that makes up the three-dimensional representation.

[0026] It is understood that the techniques described herein can be iterative, with the output of a given iteration serving as input for subsequent iterations. In this manner, the initial layout file 170 can be iteratively modified toward an optimization goal, such as minimizing the RC values ​​of the interconnects. To that end, the exemplary processes described with reference to the preceding figures are understood to represent individual iterations of an optimization technique that can include multiple iterations. An individual iteration can include additional operations, omit one or more operations, or reorder constituent operations.

[0027] 2 is a schematic diagram illustrating an example process 200 for generating an updated layout 270 of interconnects of an integrated circuit according to an embodiment of the disclosure. The example process 200 may be performed by a system (e.g., system 100 of FIG. 1 ) that executes operations for performing iterative optimization of performance metrics to generate a manufacturable integrated circuit layout that may be stored as a layout file 170 (e.g., in database 165 of FIG. 1 ). The example process 200 may be a computer-implemented method encoded in software 155 provided by at least one machine-accessible storage medium (e.g., non-transitory memory) that, when executed by a machine (e.g., server 150 and / or client computing device 110), causes the machine to perform operations for generating the updated layout 270. The updated layout 270 refers to the updated integrated circuit layout in the preceding description as a form of layout file 170 that includes or otherwise incorporates at least a subset of the geometric modifications made to the interconnects and / or terminals.

[0028] It is further understood that the order in which some or all of the process blocks appear in the exemplary process 200 should not be considered limiting. Rather, one of ordinary skill in the art having the benefit of this disclosure will understand that some of the process blocks may be performed in various orders not shown or in parallel. Additionally, while the exemplary process 200 is described as a sequence of operations performed by modules 141-149 of the shape optimizer 140, it is also contemplated that non-modular software 155 may be provided. Alternatively, one or more modules may be segmented into sub-modules as part of a workload optimization, e.g., as part of parallelizing the software 155 or running on a distributed system.

[0029] In operation 201, the exemplary process 200 includes receiving layout data 215. As described in more detail with reference to FIG. 1, the layout file 170 may be or include a numerical description of one or more interconnects between terminals associated with an integrated circuit. The description may correspond to a netlist, layout, schematic, diagram, or any other representation of an integrated circuit in which the location, quantity, and connectivity of the terminals are described. In some embodiments, the layout file 170 includes information regarding wiring route information (e.g., non-optimized or unmanufacturable wiring routes), the number of metallization layers, the physical dimensions of the integrated circuit, wiring routes, etc. It is understood that an integrated circuit can include many components (e.g., resistors, transistors, capacitors, diodes, transistors, or other electronic subcomponents), and the specific or relative spatial arrangement of the components is provided by the description. Thus, the layout file 170 indicates how individual terminals among the multiple terminals are electrically coupled. In some embodiments, the layout file 170 also describes information related to terminals that are not directly located on the integrated circuit (e.g., ground connections).

[0030] At operations 203 and 205, the example process 200 includes receiving terminal information 220 and layer information 225. The terminal information 220 refers to data describing one or more operational parameters of at least a subset of the terminals included in the layout file 170. In an illustrative example, the layout file 170 may include a description of interconnects coupling driver terminals to load terminals, as described in more detail with reference to FIG. 4A. In this example, the terminal information 220 may describe operational parameters for a portion of the layout file 170, including, but not limited to, driver impedance, operating frequency, and / or load capacitance. In some embodiments, the terminal information 220 includes metadata identifying each terminal in relation to the layout file 170, such that the terminals included in the layout file can be properly associated with terminal operational parameters.

[0031] The layer information 225 may include, but is not limited to, material property information for a layer corresponding to the layout file 170. For example, the layout file 170 may describe a via layer, a metal layer, or other layers that may be included in a multi-layer integrated circuit fabricated by a CMOS process. In this manner, the layer information 225 may include material property information including electronic properties, thermal properties, elemental composition, phase / structure information, and the like. Examples of electronic properties include, but are not limited to, conductivity, dielectric constant, and breakdown voltage. Examples of thermal properties include, but are not limited to, conductivity. In an illustrative example, the layer information 225 may define a layer as a metal layer and may define two or more materials for the layer including a dielectric oxide and a conductive metal. The layer information 225 may be associated with the layout file 170 by, for example, spatial coding of the layout file 170, where the interconnects are coded to metal and the areas outside the interconnects are coded to dielectric. In some embodiments, the layout file 170 can include multiple interconnects and / or terminals within a given region, such that multiple regions of the layout are represented as conductive material, as described in more detail with reference to Figures 4A-12.

[0032] At operation 207, the example process 200 includes discretizing the layout file 170 as part of generating a three-dimensional representation 235 of at least a portion of the layout file 170. The three-dimensional representation 235 may include a number of cells, with each cell corresponding to a discrete volume element that describes a portion of the layout file 170. As previously discussed, a cell is a volume element having a particular size, shape, and volume. In some embodiments, the cells share a common size, a common shape, and / or a common volume. In some embodiments, the cells may have a variety of sizes, shapes, and / or volumes such that the layout file 170 may be discretized into a more general set of cells of various sizes and shapes.

[0033] For example, in one embodiment, the plurality of cells may include a first cell having a first volume and a second cell having a second volume different from the first volume. Having cells of different sizes may have certain computational advantages. For example, regions of the simulated environment that are further from the boundary of the interconnect may be generated with a larger size compared to cells on or near the boundary of the interconnect. Advantageously, dynamic cell sizing may reduce the computational resource requirements of the electromagnetic simulation techniques described herein, thereby improving the operation of the exemplary process 200 on the exemplary system 100. It is understood that the individual cells are not necessarily limited to a particular shape, which may include any one or combination of a cube, a rectangular prism, a triangular prism, a sphere, a cylinder, a tetrahedron, a hexagonal prism, a pyramid, or other shapes not expressly enumerated. Rather, it is understood that the cells may be sized, shaped, and / or positioned to facilitate any resolution of the three-dimensional representation 235. For example, a cell may be defined as any volume between arrayed nodes mapped onto layout file 170. The placement of nodes within the arrayed nodes may be guided by geometric aspects of layout file 170. For example, areas of layout file 170 with a high density of corners or other features may correspond to a higher node density, while areas with a low density of features may correspond to a lower node density. In some embodiments, each individual cell is small enough such that a given terminal included in the multiple terminals of an integrated circuit is represented by more than one cell included in the multiple cells.

[0034] In some embodiments, generating the three-dimensional representation 235 may include configuring a coordinate system (e.g., Cartesian, cylindrical, spherical, etc.), size, shape, and / or number of cells. The configuration may include assigning material properties of the cells to match or otherwise represent a description of the integrated circuit (e.g., based on the arrangement and location of multiple terminals associated with the integrated circuit). For example, cells representing terminals of a given net may be assigned material properties corresponding to conductors (e.g., metals such as Au, Ag, Al, Cu, Ti, combinations thereof to form metal alloys, or other suitable materials). Conversely, cells that are outside of interconnects, terminals, or other conductors may be assigned material properties corresponding to insulators or dielectrics (e.g., SiO2, SiO x , oxides such as SiN, high-k dielectrics, low-k dielectrics, etc.

[0035] As part of the shape optimization, an initial three-dimensional representation 235 may be generated from an already-routed layout file 170 that includes interconnects laid out according to a straight-line routing convention (e.g., "Manhattan routing"). In subsequent iterations of the example process 200, operations 201-207 may be omitted and an updated layout 270 may be stored as the three-dimensional representation 235.

[0036] In operation 209, the exemplary process 200 includes generating individual contributions of the cells that make up the three-dimensional representation 235 to one or more electronic properties of the interconnect. The individual contributions may include capacitive contributions 250, conductive contributions 255 to a characteristic index 260. The characteristic index 260 may be based on an objective function that defines one or more parameters of the interconnect. The characteristic index 260 may include any electrical property or parameter that may be derived or otherwise inferred from a first-principles simulation of a given net and / or integrated circuit based on a simulated environment, such as, but not limited to, resistance, capacitance, admittance, admittance density, impedance, or RC time constant. In an illustrative example, the characteristic index 260 may correspond to an RC time constant of the interconnect that may be used as a convergence goal for multiple iterations of the exemplary process 200. The individual contributions 250 and 255 may be used as part of a physically meaningful heuristic or other model approach in shape optimization where the characteristic index 260 may be modified as part of an optimization of the layout file 170. For example, convergence of the physical simulation to an optimal RC value may correspond to about 20 iterations or less, about 19 iterations or less, about 18 iterations or less, about 17 iterations or less, about 16 iterations or less, about 15 iterations or less, about 14 iterations or less, about 13 iterations or less, about 12 iterations or less, about 11 iterations or less, about 10 iterations or less, about 9 iterations or less, about 8 iterations or less, about 7 iterations or less, about 6 iterations or less, about 5 iterations or less, about 4 iterations or less, about 3 iterations or less, about 2 iterations or less, or 1 iteration. However, as the layout 170 becomes more complex, the number of iterations may exceed 20.

[0037] In one or more embodiments, the electromagnetic simulation used to determine the individual contributions 250 and 255 corresponds to a simulation of a given interconnect. The electromagnetic simulation can generate electrostatic and / or electromagnetic field values ​​for at least a subset of the cells included in the three-dimensional representation 235 based at least in part on the layer information 225 and the terminal information 220. In some embodiments, the local contributions to the characteristic index are calculated based on field values ​​obtained via the electromagnetic simulation (e.g., the physical simulation module 143). For example, a current density, an admittance density, or more generally, a flux of a parameter related to the resistance or capacitance of the interconnect may be calculated for each individual cell. In this way, the spatially localized cell-level simulation results can be used to determine how currents flow through the simulated environment in response to a bias signal, which in turn can be used to calculate the local contributions of the individual cells to the characteristic index 260.

[0038] It is further understood that since the field values ​​from the electromagnetic simulation are based on the material properties of the individual cells, the local contributions are calculated at least in part based on the material properties. In some embodiments, an admittance density of at least a subset of the cells is calculated at least in part based on the field values ​​to determine how the cells affect the admittance matrix of the interconnect. In some embodiments, the admittance density corresponds to a scalar field of the simulated environment at the location discretized using the cells. The admittance density may be understood to indicate the local contribution to the overall conductance and capacitance of the interconnect. It is understood that the admittance density may be derived, in part, from the field values ​​of the electromagnetic simulation of the three-dimensional representation 235, as described in more detail with reference to FIGS. 3A-4B.

[0039] In operation 211, the exemplary process includes modifying the three-dimensional representation 235 using the output of the physics simulation module 143 and / or the machine learning model 144. As described in more detail with reference to FIGS. 3A-4B and 7, the local contributions of the cells to a performance metric (e.g., a convergence objective or optimization criterion) may be used to reshape the interconnect by reallocating material property information of one or more cells of the three-dimensional representation 235 or by deforming one or more cells of the three-dimensional representation 235. In an illustrative example, the capacitive and conductive contributions of at least a subset of the cells of the three-dimensional representation 235 to an overall RC value of the interconnect may be determined using the layer information 225 and the terminal information 220. In this example, the material identifiers of one or more cells of the subset of cells may be modified based at least in part on a comparison of the relative magnitudes of each cell's respective contributions. Exemplary embodiments of the three-dimensional representation 235 generated in act 211 are described in more detail with reference to FIGS. 4A-7C, 8-10, and 11. FIG.

[0040] In some embodiments, the example process 200 includes one or more sub-operations to modify the modifications of operation 211. For example, modules 147 and / or 149 can verify the manufacturability of the three-dimensional representation by process simulation to generate a predicted manufactured state of the modified three-dimensional representation 235 on the semiconductor manufacturing system 115, as described in more detail with reference to FIG. 1. If the manufactured state fails to reproduce one or more functional aspects of the modifications to the three-dimensional representation 235, the manufacturability check implemented as module 147 can return a simple Boolean false, or can indicate which modifications are likely to introduce defects into the manufactured layout. Advantageously, completing the manufacturability check using a physically meaningful process can facilitate curvilinear routes, at least in part because heuristic and / or rule-based manufacturability verification tools (e.g., design rule checker algorithms) are generally built for regular straight route runs.

[0041] With the output of the manufacturability analysis, the example process 200 may include modifying modifications to the three-dimensional representation 235 to maintain the functionality of the interconnect in the context of the layout file 170. In some embodiments, the machine learning model 144 may be trained to modify modifications to the three-dimensional representation 235 to maintain manufacturability, for example, by supervised training using a set of paired manufacturable and unmanufacturable layouts 170. In this context, the training data may be generated from a number of layout files 170 that are validated using a physics-based process model. Such physics simulations may include elements configured to identify cells and / or regions of the three-dimensional representation 235 that are likely to be mismanufactured, for example, using a process model developed for an operation that is a component included as part of the manufacture of an integrated circuit using the semiconductor manufacturing system 115. By using functionality retention rather than other figures of merit (e.g., edge placement error) as a standard for determining manufacturability, operation 211 may advantageously generate a physically meaningful manufacturability score that facilitates the transition to curved interconnect shapes. As shown, iterations of the exemplary process 200 may occur over a subset of the constituent operations. For example, an iteration may include operations 209 and 211, with layer information 225 and terminal information 220 maintained for each iteration based on layout data 215 received in operations 201-205. Similarly, modifications may be made to the three-dimensional representation 235 on a cell-by-cell basis rather than a layout file basis (e.g., as a transformation of one or more polygons or vertices of the layout file 170). Thus, encoding the layout file 170 with the three-dimensional representation 235 and the modifications from operation 211 may include one or more image processing techniques applied to the three-dimensional representation 235 to convert quantized regions described by cells into smooth regions with lines. In doing so, a portion of the conductive material of a subset of the cells may be reallocated to a dielectric material, and a portion of the dielectric material of a subset of the cells may be reallocated to a conductive material.However, in some embodiments, if the cells have characteristic dimensions that are less than the lower limit of the resolution of one or more processes of the semiconductor manufacturing system 115, the updated layout may retain quantized boundaries that are smoothed during manufacturing.

[0042] At operation 213, the example process 200 includes outputting an updated layout 270. Outputting the updated layout 270 may include, but is not limited to, generating a layout file 170 using the three-dimensional representation 235 that incorporates the modifications made over one or more iterations of operations 209 and 211. In some embodiments, the updated layout 270 may be encoded as a layout file 170, such as GDSII or OASIS, a mask set, or any other data format used in integrated circuit design. In some embodiments, the updated layout 270 may be encoded as visualization data that may be distributed or otherwise accessed by the client computing device 110 as part of the interactive design environment. In this manner, one or more users of the interactive design environment may simultaneously or concurrently access and / or modify the layout file 170 and / or the updated layout 270.

[0043] Detailed Consideration of Interconnect Shape Modification Once the routes are successfully established between the terminals, the capacitance between the nets can be determined and used to optimize the geometry of the interconnect to improve RC, although other optimization goals are also envisioned, including but not limited to reducing electromigration and avoiding dielectric breakdown. To that end, the admittance density of equation (1), repeated below,

[0044]

number

[0045] can be applied to understand which regions contribute to RC and then formulate heuristics for reshaping the interconnects to improve RC.

[0046]

number

[0047] Here, the fundamental solution f k is the complex Laplace equation with Dirichlet boundary conditions of 1 at terminal k and 0 at all other terminals.

[0048]

number

[0049] Everywhere else, Neumann boundary conditions apply, where the complex material parameters are

[0050]

number

[0051] where the permittivity is ε, the conductivity is σ, and the angular frequency is ω. Then, the admittance matrix of a system with N ports is given by the volume integral over the admittance density:

[0052]

number

[0053] It can be determined as:

[0054] Without being bound to a particular physical mechanism, it is understood that RC depends on the load attached to the output terminal of the interconnect, which represents the transistor gate node of the CMOS logic. When the gate capacitance of the transistor gate is large, optimization of the interconnect geometry may include reducing the interconnect resistance while the interconnect capacitance is negligible or substantially negligible. While such a scenario was typical in older vendor process nodes, in the latest technology nodes such as FinFET technology, the interconnect capacitance is comparable to the gate capacitance of the transistor. Modifying the interconnect geometry may therefore depend on the ratio between the wiring capacitance and the attached load.

[0055] Input Admittance and RC: RC can be calculated from the admittance based at least in part on deriving the effect of the admittance density of a single interconnect on the overall RC of the routed IC layout. As part of generating the overall RC time constant, the admittance matrix

[0056]

number

[0057] can be determined for an N-port fully routed system using the following equation:

[0058]

number

[0059] Furthermore, regions of the three-dimensional representation of the layout file 170 may be allocated to terminals belonging to either transistors or external pins.

[0060]

number

[0061] teeth,

[0062]

number

[0063] and is determined from the underlying system of interconnects and transistors.

[0064] Since the attached load (e.g., a transistor) is a nonlinear component, the resistance and capacitance of the transistor are estimated based on the instantaneous applied voltage signal. As a simplifying assumption, the gate capacitance can be bounded by assuming a maximum capacitance for all operating points of each transistor t as follows:

[0065]

number

[0066] In practice, however, the effective capacitance for a particular voltage ramp or slew may be selected in accordance with embodiments of the present disclosure.

[0067] For the purposes of RC calculations, the low frequency content of the capacitance is important. Since the capacitance is independent of frequency up to near the cutoff frequency, in some embodiments it is assumed that the frequency dependence is negligible. The input admittance at terminal i is

[0068]

number

[0069] To calculate , we also need to assume the load admittance at all other input terminals j ≠ i. For simplicity, we assume an ideal ohmic contact, i.e.

[0070]

number

[0071] Finally, we can assume that the input admittance of terminal i is

[0072]

number

[0073] and considering the loads Y at all terminals except input terminal i, set the currents to their appropriate values. Thus, we have the following linear equation, which can be solved directly:

[0074]

number

[0075] In the formula, δ kl is the Kronecker delta.

[0076] The input admittance defined in equation (6)

[0077]

number

[0078] can be determined from equation (9).

[0079]

number

[0080] The value of can be calculated and used in the upper equation of equation (9), while the lower equation is

[0081]

number

[0082] of

[0083]

number

[0084] It contains that information precisely by expressing it as a function of

[0085] Input Admittance

[0086]

number

[0087] Using RC at terminal i, i But, the formula

[0088]

number

[0089] It can be calculated using:

[0090] RC itakes into account capacitive and resistive effects, as well as other phenomena including, but not limited to, crosstalk and / or coupling efficiency due to loads attached to other wiring. However, equation (10) describes an instantaneous RC time constant. For nonlinear elements such as transistors, the instantaneous RC time constant differs from the RC measured in large signal operation. For this reason, the following discussion assumes worst case gate capacitance for all operating conditions. In this way, it is understood that the objective function for optimizing interconnect geometry in terms of RC value is bounded by the worst case RC.

[0091] RC Improvement Heuristics: Equation (10) shows that optimizing wiring with respect to RC is not trivial. First, the input admittance

[0092]

number

[0093] is an admittance matrix that is understood to have no analytical solution.

[0094]

number

[0095] Second, RC is determined by the quotient of equation (10), which means that its value is determined nonlocally. Thus, an algorithm for optimizing RC cannot easily determine whether a local change to the interconnect structure (e.g., widening and / or narrowing the interconnect at one or more locations in the interconnect) will improve or worsen the output of the objective function. Third, the transistor load that appears in the implicit input admittance system of equation (9) is an important factor in determining how the interconnect structure should be optimized, due to the nature of how RC is calculated. In some embodiments, the magnitude of the load at the terminals can make the interconnect capacitance substantially negligible, resulting in an optimal interconnect that is wide for increased conductivity. While this was the case for older vendor process nodes, for current and future anticipated process nodes, the interconnect capacitance and gate capacitance may be comparable. In such cases, the width of the interconnect may depend on the length of the interconnect. For example, a relatively short interconnect may be relatively wide, while a longer interconnect may be characterized by a capacitance that exhibits an improvement in RC with decreasing width.

[0096] In short, optimizing interconnects is a significant computational challenge. Advantageously, the numerical techniques described herein can be complemented with simple heuristics to improve circuit timing, such as widening interconnects, inserting vias to reduce resistance, and / or increasing the spacing between adjacent wires to reduce cross-coupling capacitance or shortening the parallel run-length of adjacent wires. Thus, the RC-optimization landscape can be understood to allow the algorithm to follow a gradient toward a local optimum. Such a mixed approach, including finite volume methods and simple heuristics, can result in improved IC performance by modifying the layout file 170, while also reducing the computational resource requirements of the optimization process.

[0097] This structure of capacitance is exhibited by algorithms such as FasterCap, which express the interconnect capacitance in terms of the Green's function of Laplace's equation, since the electric field strength between the interconnects is an equivalent measure of capacitance. Similarly, the current density in the interconnect is an equivalent measure of conductance by Ohm's law. Thus, the admittance density in equation (1) can be used to determine a measure of the contribution of local conductance and capacitance to the overall admittance in equation (5). Thus, the admittance density

[0098]

number

[0099] The spatial contribution from can serve as the basis for determining RC in equation (10).

[0100] As a prelude, a heuristic is described for improving the interconnect design without using numerical or analytical methods.

[0101]

number

[0102] The layout file 170 starts with an interconnect and one or more terminals, each described by a material parameter field κ(r) defined using the κ(r) method. In this manner, the layout file 170 may be updated based at least in part on a determination of whether a spatial coordinate r should have the material parameters of the metal of the interconnect or the material parameters of the insulator and / or dielectric.

[0103] Single Load: Attached Load

[0104]

number

[0105] , ∀k ≠ a is RC a As part of optimizing the , it has a significant impact on optimizing the wiring geometry at the input terminal a, which at least in part determines whether the interconnect can be made wider to carry more current or narrower to avoid capacitive cross-coupling. In some cases, a net may be a single load

[0106]

number

[0107] connects two terminals a and b, while all other terminals are

[0108]

number

[0109] , ∀k ≠ a, b can be assumed to be short-circuited. Inserting these loads into equation (9) gives

[0110]

number

[0111] In the equation that is the second component of equation (12), terms of relatively small magnitude other than the load at the shorted terminals, for example, may be neglected.

[0112]

number

[0113] is nonzero, the applied bias of the shorted port k approaches zero as the applied voltage approaches zero.

[0114]

number

[0115] Inserting this into the first two component equations results in the following equation:

[0116]

number

[0117] The second component, the expression

[0118]

number

[0119] and inserting the result into the first component equation allows the following expression for the input admittance to be derived:

[0120]

number

[0121] This equation is understood to be for an interconnect joining two terminals with a single load.

[0122] RC in Eq. (10) a Expanding the equation for into real and imaginary components, equation (14) becomes RC a This can be used to derive the following expression for

[0123]

number

[0124] For a single interconnect joining terminal a to terminal b, the admittance matrix is

[0125]

number

[0126] It can be expressed as:

[0127] For CMOS technology, terminal b can be assumed to correspond to a gate acting as a capacitive load. Thus,

[0128]

number

[0129] is a complex value

[0130]

number

[0131] Therefore, the RC in Eq. (13) can be expressed as a teeth,

[0132]

number

[0133] can be rewritten as:

[0134] In equation (17), the structure of the RC time constant is shown as a ratio of capacitive and conductive contributions. Thus, the conductivity of the interconnect can be compared to the capacitance of the load and the interconnect. From the point of view of the input a, it can be understood that it is physically indistinguishable whether the capacitance at the output is part of the interconnect structure or part of the load, so that the output capacitance C is at least partially the load capacitance C L is combined with.

[0135] Constant-Width Toy Model Optimization: Figure 3A is a schematic diagram illustrating a toy model 300 of a two-port interconnect 310 according to an embodiment of the present disclosure. Figure 3A illustrates the interconnect 310 electrically coupled to two terminals 305 (e.g., "ports") with an equivalent circuit having a physical size, a conductance G, and a capacitance C. In the following procedure, the interconnect 310 is optimized for a load C L 3A shows a toy model 300 in which transmission line effects, such as the effect of capacitance being distributed over the length "L" of the interconnect 310, are ignored. Thus, the following simple analytical model of conductance and capacitance is applied:

[0136]

number

[0137] In the formula, x w , L, W are the dimensions shown in FIG. 3A, and H is the height in the remaining direction. σ and ε are the conductance and permittivity, respectively. Inserting the terms of equation (18) into equation (17) results in the following:

[0138]

number

[0139] Equation (16) indicates that when the capacitance of the interconnect 310 is equal to or larger than the load capacitance, RC is equal to L 2 It will be apparent that a short wire driving a large load may scale with L. Thus, a short wire driving a large load may be understood to scale with L. As described in more detail with reference to FIG. 2, in some embodiments, the local width of the interconnect 310 may be scaled with L (e.g., RC a , which is a variable that is manipulated in an optimization scheme to improve the performance of interconnect 310 (by minimizing w It is understood that depends at least in part on the operating parameters of the load represented by the terminal information 220. w In the two-port scenario shown in FIG. 3A with L The optimal width for

[0140]

number

[0141] It is described by:

[0142] In equation (20), C0 is the capacitance of the interconnect 310 at its total width L, i.e.,

[0143]

number

[0144] The minimum RC is defined as aWhere value is x opt Note that x does not depend on conductivity and can be determined from the ratio of the intrinsic capacitance of the interconnect 310 to the external load capacitance. For small loads, the interconnect 310 primarily drives its own capacitance, and the optimal width x opt ≒ W / 2. However, as the load gets larger, the delay due to charging the load capacitance becomes significant. As a result, x opt becomes large. Note that due to the interdependence of the capacitance of the interconnect 310 with the dielectric width, the intrinsic wiring capacitance can be balanced against the capacitive load. Thus, as the capacitive load approaches infinity (C L →∞), x opt → Gradually approaching the W limit.

[0145] For RC-based shape optimization, the location of one or more interfaces between conductive and dielectric materials may be modified based at least in part on the relative magnitudes of the electric fields built up in the conductor and dielectric. To that end, the admittance density in equation (1) is calculated for both the metal M and (in the example oxide) dielectric OX of the interconnect by:

[0146]

number

[0147] It can be expressed as:

[0148] In contrast, the formula for RC is:

[0149]

number

[0150] It becomes.

[0151] Equation (22) qualitatively reveals a technique for locally optimizing the interconnect 310. If the imaginary part of the admittance density at the metal-oxide interface contributes more to the overall capacitance than the real part of the admittance density contributes to the overall conductance within the conductor, move the interconnect boundary 311 to increase the distance between the capacitor plates (e.g., shrink the interconnect 310). On the other hand, if the real part within the conductor makes a larger contribution, move the interconnect boundary 311 to increase the conductor cross-section.

[0152] For gradient-based optimization, a differentiable function of RC is derived and the optimal value is given by the derivative

[0153]

number

[0154] Solving equation (22) for a stationary point gives an equation that holds for all values ​​of r0.

[0155]

number

[0156] results.

[0157] As revealed by equation (23), in the optimal configuration, the local capacitive and conductive contributions balance each other and are given by

[0158]

number

[0159]

number

[0160] It is defined as:

[0161] Equation (24) describes the local capacitive contribution at location r, and equation (25) describes the local conductive contribution at location r. From these equations, inspired by the qualitative approach shown in equation (22), a heuristic for improving the RC of the interconnect is to reduce the RC at location r on the interface 311 between the interconnect 310 and the dielectric. inter can be constructed as follows:

[0162] C C (r inter ) > C G (r inter ), reduce the interconnect width.

[0163] C C (r inter ) < C G (r inter ), increase the width of the interconnect.

[0164] C C (r inter ) = C G (r inter ), maintain the interconnect width.

[0165] To generalize the previous treatment of RC circuits, we use a voltage generator

[0166]

number

[0167] but the associated generator admittance

[0168]

number

[0169] In digital circuits, the generator is generally a power grid, and the generator admittance

[0170]

number

[0171] is related to the resistance and capacitance of the interconnect 310 and the MOSFET's channel. The real part of the generator admittance can be related to the conductance of the MOSFET's channel in the on-state, and therefore can be interpreted as the drive strength of the interconnect 310. Similar to what has already been shown for the load admittance, different drive strengths can lead to different optimal interconnect 310 designs.

[0172] To determine RC, the input admittance

[0173]

number

[0174] But an ideal voltage source

[0175]

number

[0176] Relationship from

[0177]

number

[0178] It can be found using

[0179] where the generator current

[0180]

number

[0181] is the admittance value of the two-port interconnect 310

[0182]

number

[0183] and

[0184]

number

[0185] To the formula

[0186]

number

[0187] can be associated using

[0188] Equation (27) is combined with equation (26) to give:

[0189]

number

[0190] To obtain an expression for

[0191]

number

[0192] Equation (28) is combined with equation (25) to give the equation for RC:

[0193]

number

[0194] This can result in:

[0195] 3B is a schematic diagram illustrating an exemplary variable width interconnect 310 coupling two terminals 305 according to an embodiment of the present disclosure. To derive the corresponding two-port admittance matrix, an approximation based on the solution of Laplace's equation for the fundamental solution can be used to reduce the complexity of the description using an equivalent circuit. For that purpose, an assumption can be made that the electric potential in the highly conductive interconnect is constant in the x-direction. In FIG. 3B, the x-direction is defined as shown.

[0196] Assuming constant conductivity, the basic solution f a and f b The Laplace equation can be understood as a description of the conservation of current as a function of y position between the terminals 305. More specifically, for the metal domain, the metal fundamental solution

[0197]

number

[0198] In this context, using the Gaussian integration theorem, the integral over a control volume containing two slices of the interconnect 310 at y = 0 and some arbitrary interior point y0 can be expressed as

[0199]

number

[0200] results.

[0201] Since equation (30) is a general equation for any y0, the conservation of current dictates that I0 is constant, and the fundamental metal solution

[0202]

number

[0203] is the formula

[0204]

number

[0205] It can be defined using:

[0206] As previously mentioned, the subscript "a" is assigned to one of the terminals 305 coupled by the interconnect 310. Thus, for terminal "b", the metal fundamental solution is:

[0207]

number

[0208] It can be defined by:

[0209] For equations (31) and (32), the boundary conditions are, respectively,

[0210]

number

[0211] and

[0212]

number

[0213] It is defined as:

[0214] The fundamental equations for dielectrics are their respective values ​​for metals.

[0215]

number

[0216] The dielectric function can be expressed as a simple linear function that decays from x = 0 to zero at the electrode position x = W shown in Figure 3B. The resulting dielectric fundamental function is

[0217]

number

[0218] It can be defined as:

[0219]

number

[0220] Equation (28) can be used with equation (29) to derive a constraint on the admittance density resulting from the stationary point of RC, under the simplifying assumption that . Once found, the stationary point can be defined as a fixpoint for modifying the geometry of interconnect 310 (e.g., by displacing at least a portion of interface 311). Using the general form of the RC equation, including the generator admittance and load admittance, shown in equation (29),

[0221]

number

[0222] It is.

[0223] The stopping point is

[0224]

number

[0225] is given by:

[0226] The functional derivative of the generator input admittance is

[0227]

number

[0228] is given by:

[0229] From this equation, the complete formula for the functional derivative of (35) can be found with respect to the two-terminal 305 interconnect 310:

[0230]

number

[0231] It can be derived as:

[0232]

number

[0233] and

[0234]

number

[0235] It is.

[0236] From equations (37) to (39), for any point r0 on the boundary surface 311, the equation of the fixed point is given by

[0237]

number

[0238] It can be defined as:

[0239] A closer look at arbitrary fan-out The derivation for the variation of RC can be extended to an interconnect coupling a driver (input terminal 305) to multiple output terminals 305, as will be explained in more detail with reference to FIG. 8. In the expression for RC given in equation (34), the output terminals 305 have an input admittance

[0240]

number

[0241] Therefore, RC and its variation for any fan-out may be determined, at least in part, by calculating the input admittance and its derivative with respect to different admittances.

[0242] For this purpose, the N × N admittance matrix

[0243]

number

[0244] The input terminals 305 a∈{1, 2, ..., N} may be characterized by the loads of the terminals 305 for all i = 1, 2, ..., N.

[0245]

number

[0246] To determine the input admittance in this case, we first use Ohm's law

[0247]

number

[0248] Starting from: , which uses a simplified notation, but it being understood that both I and V refer to vectors of complex phasors. To calculate the input admittance for terminal 305 a, the effect of loading on all ports other than a may be determined. For this purpose, a reduced (N - 1) x (N - 1) matrix

[0249]

number

[0250] except that the row and column corresponding to terminal 305 a are deleted.

[0251]

number

[0252] Similarly, the vector

[0253]

number

[0254] and

[0255]

number

[0256] are defined to be equal to I and V, respectively, but without the element a.

[0257]

number

[0258] Regarding, Ohm's law states that

[0259]

number

[0260] It can be expressed as

[0261]

number

[0262] is a diagonal matrix of (N - 1) x (N - 1) with all loads except for the terminal 305a on its diagonal. Furthermore, H has the elements

[0263]

number

[0264] , k∈{1, ..., N}\{a}.

[0265] Equation (41) expresses the voltage ratio (V r ) and H,

[0266]

number

[0267] where Vr = V~ / Va is the voltage ratio relative to the input.

[0268] Equation (42) can be used to determine the input admittance as a function of the voltage ratio and the elements of the admittance matrix.

[0269]

number

[0270] Using these expressions, a system of linear equations can be defined and solved to define the derivative of the input admittance.

[0271]

number

[0272] Detailed consideration of the RC contribution of the cell As described in more detail with reference to FIG. 2, the following discussion details an illustrative example of a computational technique for optimizing the RC of interconnects 310 of a layout file 170 that includes one or more nets, each of which is a T n Starting with a fully routed layout 170 including N interconnects 310 with a set of terminals 305, n ∈ {1, 2, ..., N}. Furthermore, each interconnect 310 n has one or more inputs coming from a pull-up and / or pull-down network, and one or more outputs terminating in a load (e.g., a gate in CMOS technology). The set of inputs to interconnect 310 n is:

[0273]

number

[0274] and the set of outputs is

[0275]

number

[0276] It is written as,

[0277]

number

[0278] denotes a set of terminals 305 (eg, an interconnect 310 can couple an input to an output without a dead or null terminal).

[0279] Optimizing the geometry of the interconnects 310 involves defining the local contribution δRC(r) of each interconnect 310. When RC is at a minimum, RC is stationary and the variation δRC becomes zero, which occurs due to the cancellation of its conductive component inside the interconnect and its capacitive component outside the interconnect, see the two terms in equation (40).

[0280] Detailed consideration of shape modifications Therefore, if the interconnect is not RC optimal, the interconnect interface "r inter " The imbalance of components can be found in the conductive contribution

[0281]

number

[0282] denotes the value of δRC inside the interconnect, and the capacitive contribution

[0283]

number

[0284] Let denote the value of δRC outside the interconnect. Then, a heuristic for improving RC is given by:

[0285]

number

[0286] If so, reduce the interconnect width.

[0287]

number

[0288] If so, increase the interconnect width.

[0289]

number

[0290] If so, maintain the interconnect width.

[0291] In the context of the above heuristics, equality can be understood to be approximate within a range of values. For example,

[0292]

number

[0293] is within a given tolerance

[0294]

number

[0295] If , the interconnect boundary 311 may be maintained.

[0296]

number

[0297] But outside the given tolerance

[0298]

number

[0299] If it is greater, the width of the interconnect 310 may be reduced. In some embodiments, the tolerance is:

[0300]

number

[0301] and

[0302]

number

[0303] For example, the ratio of about 1.5 or less, about 1.4 or less, about 1.3 or less, about 1.2 or less, about 1.1 or less, about 1.05 or less, about 1.01 or less

[0304]

number

[0305] and

[0306]

number

[0307] may be considered equal within a tolerance, including interpolations and portions thereof.

[0308] The implementation of the algorithm is in the boundary region 313 near the interconnect boundary 311.

[0309]

number

[0310] and

[0311]

number

[0312] This is complicated by the geometric dependence of the local modifications to the interconnect boundary 311 on the value of . As will be described in more detail with reference to FIG. 7 , allocating material to cells in the three-dimensional representation 235 may involve determining the differential contribution of a cell in the discretized space and comparing the corresponding contributions of adjacent discretized volumes (e.g., cells) within the boundary region 313.

[0313] In some embodiments, the relative influence of the conductive and dielectric materials in the boundary region 313 on the differential RC contribution at a given position r of the interconnect 310 can be calculated as:

[0314]

number

[0315] and

[0316]

number

[0317] to adjacent cells of the three-dimensional representation 235. In some embodiments, the extrapolation may include applying a three-dimensional smoothing operation to the cells. An example of three-dimensional smoothing is:

[0318]

number

[0319] where σ is the three-dimensional standard deviation vector of the values ​​defined in Cartesian space, σ = (σ x , σ y , σ z) It will be appreciated that σ may be defined in other coordinate spaces to correspond to the coordinate space used to define the three-dimensional representation 235. The value of σ affects the extent of the smoothing, with smaller values ​​resulting in more limited smoothing and larger values ​​resulting in broader smoothing. In some embodiments, the value of σ is determined by multiplying the width X of the interconnect 310 by σ to limit the possibility that the opposing boundaries 311 may affect the field contribution, which is a vector quantity. W (Y). Thus, σ can be a function of position in three-dimensional representation 235, or can be a consistent value for layout 170. In some embodiments, an initial value of σ is selected that is greater than the initial width of interconnect 310 (e.g., for a straight line routing, the width can be a single value).

[0320] For the Gaussian smoothing function of Eq. (45), the smoothed contributions to the conductance and capacitance at a given location r can be expressed as a three-dimensional convolution:

[0321]

number

[0322]

number

[0323] and

[0324]

number

[0325] represent the smoothed capacitive and conductive contributions, respectively, at a location r in the three-dimensional representation 235. Advantageously, extrapolation, such as by the smoothing shown in equations (45) and (46), allows the relative contributions of the cells to the conductance and capacitance of the interconnect 310 (e.g., the real and imaginary components of RC) to be determined with less influence of the location of the cell relative to the interconnect boundary 311. In this way, for a location r within the interconnect 310, the relative contributions of the cells to the conductance and capacitance (e.g., the real and imaginary components of RC) can be determined with less influence of the location of the cell relative to the interconnect boundary 311.

[0326]

number

[0327] If r, then the material may be reallocated from a conductor to a dielectric (e.g., from metal to oxide). Otherwise, the material of the interconnect 310 in the cell corresponding to the location r may be maintained as a conductor. Similarly, for a location r that is outside the interconnect 310, within a given tolerance ε,

[0328]

number

[0329] If , the material may be reallocated from a dielectric to a conductor (e.g., from oxide to metal). Otherwise, the material of the interconnect 310 in the cell corresponding to location r may be maintained as a dielectric.

[0330] In some embodiments, the simulation mesh is unstructured and the walls of the interconnects can be moved by mesh movement operations instead of reallocating material to cells.

[0331] As described in more detail with reference to FIG. 7, in some embodiments, a manufacturability check may be included as part of the operations of the exemplary process 200, including but not limited to generating an updated layout 270. Given a process function P(M, θ) that depends on the mask set M and the fab parameter θ, a material parameter field describing the interconnect 310 may be determined. For an interconnect 310 structure with a given M0 and θ, the material parameters and other quantities of interest of the interconnect 310 structure may be determined using the process function P(M0, θ) = {σ(r), ε(r), ...} =: S0, where the wafer state S0 of the first iteration 0 is defined as the set of physical quantities describing the layout 170. Using the techniques described above, the admittance of the interconnect 310 may be determined, and a smoothed contribution may be determined for the interconnect 310 from the generator admittance and the load admittance.

[0332] Using the updated layout 270, a target design D1 may be defined as the next iteration (e.g., iteration 1 after initial state 0) that includes updated material parameters of the cells that make up the three-dimensional representation 235. Using process data describing the fab parameters θ, a process simulation may be performed to simulate the manufacturing results of D1, which may be used to modify D1 to a new wafer state S1. In some embodiments, D1 is manufacturable based on physical simulations, but at the same time violates Boolean design rules of the process. In this way, the manufacturability checks described herein may target functionality retention rather than meeting manufacturer-provided design rules that may be developed to minimize other figures of merit, such as edge placement error, that are based on straight routing but are less applicable to curved routing.

[0333] In one or more iterations ("i") of the above operations, the wafer state Si The RC value of may converge to an optimal value that is also manufacturable based on physically meaningful process simulation. Advantageously, manufacturability verification based at least in part on process data can provide differentiable manufacturability revisions where small changes in design D lead to small changes in wafer state S. In contrast, Boolean design rules are not smooth or differentiable and do not allow the gradient-based optimization techniques described above to include manufacturability-based revisions of the updated layout 270.

[0334] The mask set M, which will be described in more detail with reference to FIG. IN and process data θ, and a modified mask set M OUT An exemplary algorithm for implementing the above optimization to output {right arrow over (x)} includes the following operations, which can be parallelized or otherwise reordered: 1. Calculate the wafer state S0 using the process model ("P"). 2. Using equation (37), determine the wafer state S i Net contribution of

[0335]

number

[0336] and

[0337]

number

[0338] Calculate. 3. Gaussian smoothing of Eq. (46) for interconnect 310

[0339]

number

[0340] and

[0341]

number

[0342] Calculate. 4. Design a new goal using the heuristics described above. i+1 Generate. 5. At least in part through process simulation P(D i+1 , θ) to D i+1 The mask set M that is closest to and can be produced at the same time i+1 Calculate. 6. Use P(Mi+1, θ) = Si+1 to find the new wafer state S i+1 Calculate. 7. New wafer state S i+1 Calculate the optimization objective (e.g., RC value) using If the optimization objective value does not meet the target value or criterion (e.g., delta or convergence index), increment i and go back to step 2. 8. Once convergence is achieved, the final mask set M F Returns

[0343] 4A-4D are schematic diagrams illustrating two-dimensional plan view projections onto the "xy" plane of a three-dimensional representation 235 of a portion of the layout file 170 and the updated layout 270, according to an embodiment of the present disclosure. The projections represent a two-port interconnect as described in more detail with reference to FIGS. 3A-3B, for which shape optimization, including one or more iterations, may be and / or has been completed as described with reference to FIGS. 2 and 3A-3B. As such, FIGS. 4A-4D are provided to illustrate the influence of the layer information 225 and the terminal information 220 on the shape optimization and updated layout 225. While representing exemplary simulation and optimization results, FIGS. 4A-4D are not intended to be limiting, but rather illustrative. For example, the results of the shape optimization may differ from the examples provided in FIGS. 4B-4D, based at least in part on the layer information 225, terminal information 220, and layout file 170 used to generate the three-dimensional representation 235. Additionally or alternatively, the property metrics used to guide the shape optimization may also affect the outcome of the shape optimization, as may the inclusion of physical effects such as dielectric breakdown or other electric field effects that may be significant at small length scales, on the order of nanometers or less. Thus, optimization using the same layout file 170, the same layer information 225, and the same terminal information 220 may result in a modified layout 270 that differs from the one shown. Advantageously, a realistic interconnect structure may include layer-specific material parameters for each of the multiple layers. Furthermore, physical parameters such as conductivity may vary within a single interconnect 310, for example, as a function of wall-distance. Such variations, while easily captured by the techniques described herein, introduce significant complexity into the rule-based system, which may include adding new rule-based models for each layer and each interconnect 310.

[0344] 4A is a schematic diagram illustrating an example floor plan 400 of a simplified three-dimensional representation 235 of at least a portion of a layout file 170 describing an interconnect 310 (e.g., a two-port interconnect) coupling two terminals 305, according to an embodiment of the disclosure. The example floor plan 400 also includes additional conductive features 415, including but not limited to a conducting backplate, vias, or other terminals that are not coupled to the interconnect 310. As described in more detail with reference to FIG. 2, the three-dimensional representation 235 defines the interconnect 310, the terminals 305, the conductive elements 415, and a cell 401 of dielectric material that surrounds the interconnect 310. As described in more detail with reference to FIGS. 3A-3B, a boundary region 313 near the surface of the interconnect 310 may be modified as part of a shape optimization. The exemplary floor plan 400 omits the cells 401 of dielectric material for visual clarity, but the boundary region 313 is shown in the inset overlaid with the conductive cells 411 of the interconnect 310 and the dielectric cells 413 (e.g., corresponding to oxide or nitride materials) outside the interconnect 310. In conjunction with the layout file 170 used to generate the three-dimensional representation, the layer information 225 is used to identify the conductive cells 411 and the dielectric cells 413 based on spatial information from the layout file 170.

[0345] Although the exemplary floor plan 400 follows a straight-line routing convention, performance metrics including, but not limited to, the RC time constant of the interconnect 310 may indicate that the interconnect 310 may be suboptimal in terms of its shape. For example, electromagnetic interactions between the interconnect 310 and one or more conductive elements 415 may increase the RC time constant for a given set of terminal information 220. As part of reshaping the interconnect 310, the terminal information 220 may be used in conjunction with the three-dimensional representation 235 of the exemplary floor plan 400 to determine the individual contributions of cells 401, such as cells 401 near the boundary region 313, to the RC value of the interconnect under specific operating conditions defined in the terminal information 220. In this manner, different terminal information 220 may result in different updated layouts 270, as described in more detail with reference to FIGS. 4B-4D.

[0346] 4B is an example floor plan 425 of an updated layout 270 generated from the example floor plan 400 of FIG. 4A according to a first set of terminal information 220, in accordance with an embodiment of the present disclosure. Without being bound to a particular set of terminal information 220 and layer information 225, the example floor plan 425 represents the output of one or more iterations of the example process 200 that uses the example floor plan 400 as an input to the physics simulation module 143.

[0347] The exemplary floor plan 425 corresponds to an embodiment of the exemplary process 200 in which the terminal information 220 includes an input frequency, a driver impedance, and a load capacitance. For simplicity, specific values ​​are omitted to focus on the description of the relative influence of the parameters that are components of the terminal information 220. It is understood that in practice, the terminal information may include values ​​of parameters that correspond to values ​​used during operation of the integrated circuit. For example, the driver impedance may be or include values ​​of about 0 ohms or more, about 10 ohms or more, about 100 ohms or more, about 1000 ohms or more, about 5000 ohms or more, about 10,000 ohms or more, about 100,000 ohms or more, about 1,000,000 ohms or more, or about 10,000,000 ohms or more, including portions and interpolations of the following values. Similarly, the input frequency may be or include frequencies in the kHz range, the MHz range, or the GHz range, including portions and interpolations of the following frequencies. Similarly, the load capacitance may be or include values ​​of about 0.0001 fF or greater, about 0.001 fF or greater, about 0.01 fF or greater, about 0.1 fF or greater, about 1.0 fF or greater, about 10 fF or greater, or about 100 fF or greater, including portions and interpolations of the following values. In an illustrative example, the example floor plan 425 may correspond to terminal information specifying a driver impedance of about 1 M Ohm, a load capacitance of about 1 fF, and an input frequency of about 100 GHz.

[0348] 4B, the shape of interconnect 310 is significantly different in example plan view 425 as compared to the rectilinear shape of interconnect 310 in example plan view 400. In particular, interconnect 310 is wider, and a non-uniform width expansion of interconnect 310 has been applied as a function of lateral position relative to terminal 305. As described with reference to FIGS. 2-3B, the position-dependent width ("X W(Y)”) is determined using the contributions of the cells 401 to the capacitive and conductive terms of the RC time constant of the interconnect 310. Without being bound to a particular physical phenomenon, it is understood that the shape of the interconnect 310 in the updated layout 270 shown in the exemplary floor plan 425 exhibits a larger capacitance contribution than the conductance contribution to the RC value of the interconnect 310.

[0349] Advantageously, the techniques described herein enable the example system 100 to generate an updated layout 270 corresponding to the example floorplan 425 through one or more iterations of the example process 200 using physically meaningful information rather than physics-naive heuristics. For example, it may appear that the example floorplan 425 could have been generated by a rules-based model that dictated to increase the width of the interconnects 310 while maintaining a minimum distance between the interconnects 310 and the conductive elements 415. However, such a physically-naive model would not generate an updated layout 270 that results in RC values ​​that are optimized with respect to the terminal information 220 and the layer information 225.

[0350] However, as described in more detail with reference to FIG. 1, the physics simulation module 143 may be augmented by one or more machine learning models 144 trained to reshape at least a portion of the interconnect 310. For example, a convolutional neural network may be trained to accept the layout file 170 or the three-dimensional representation 235 as input along with the terminal information 220 and / or layer information 225 and output the reshaped interconnect 310. The output of the machine learning model 144 may be or include material identifiers of one or more cells 401, portions of the interface 311, etc. Unlike a physically naive rule-based model, the machine learning model 144 may be trained on a particular set of terminal information 220 and / or layer information 225, for example, using a labeled training set of the rectilinear layout file 170 and the updated layout 270 (e.g., as a supervised training approach). In this manner, the machine learning model 144 may approximate the physics simulation described with reference to FIGS. 3A-3B.

[0351] FIG. 4C is another example floor plan 450 of an updated layout 270 generated from the example floor plan 400 of FIG. 4A using a second set of terminal information 220 according to an embodiment of the present disclosure. Similar to the example floor plan 425 of FIG. 4B, the example floor plan 450 is generated by operation of the example process 200 of FIG. 2, as described in more detail with reference to FIGS. 3A-3B. Compared to the example floor plan 425, the example floor plan 450 includes a relatively narrow interconnect and has a wider spacing between the interconnect surface 311 and the conductive element 415. The example floor plan 450 illustrates the effect of different terminal information 220 on modifying the shape of the interconnect 310 based at least in part on the operating parameters of the terminals 305 and the interconnect 310, such as driver impedance, load capacitance, or frequency. In the example of FIG. 4C, the driver impedance is a relatively higher value than the corresponding driver impedance used to generate the example floor plan 425. From this, it can be seen that as impedance increases, the conductive contribution of interconnect cell 401 decreases relative to the capacitive contribution of adjacent cells 401 at boundary region 313, resulting in a relatively narrow interconnect 310. However, it is noted that interconnect 310 in example floorplan 450 has been widened relative to interconnect 310 in example floorplan 400, illustrating that the straight-line "shortest path" route typical of conventional routing algorithms is not optimized with respect to RC time constants. This, in turn, illustrates that imposing a straight-line routing convention can result in performance degradation of an integrated circuit that scales with the number of interconnects.

[0352] FIG. 4D is an example floor plan 460 of an updated layout 270 generated from the example floor plan 400 of FIG. 4A according to the third set of terminal information 220, in accordance with an embodiment of the present disclosure.

[0353] Similar to the example floorplan 425 of FIG. 4B and the example floorplan 450 of FIG. 4C, the example floorplan 460 is generated by operation of the example process 200 of FIG. 2, as described in more detail with reference to FIGS. 3A-3B. In comparison to the example floorplan 425, the example floorplan 460 includes a relatively narrow interconnect and has a wider spacing between the interconnect surface 311 and the conductive element 415. The example floorplan 460 illustrates the effect of different terminal information 220 on modifying the shape of the interconnect 310 based at least in part on the operating parameters of the terminal 305 and the interconnect 310, such as driver impedance, load capacitance, or frequency. In the example of FIG. 4C, the driver impedance is a relatively higher value than the corresponding driver impedance used to generate the example floorplan 425. This shows that as the impedance increases, the conductive contribution of the interconnect cell 401 decreases relative to the capacitive contribution of the adjacent cells 401 in the boundary region 313, resulting in a relatively narrow interconnect 310.

[0354] It is noted that the interconnect 310 in the example floor plan 460 is substantially the same width as the interconnect 310 in the example floor plan 400, except that the positions of the cells 401, and thus the interfaces 311, of the interconnect 310 are relocated relative to the positions of the terminals 305. This illustrates that reshaping the interconnect 310 as part of the example process 200 may include translating, displacing, and / or redirecting the interconnect 310 relative to one or more conductive elements 415 in the layout file 170, as well as widening or narrowing the width of the interconnect 310.

[0355] 5A-5B are schematic diagrams illustrating an example three-dimensional representation 535 of the layout file 170 and the updated layout 270, respectively. As shown, the three-dimensional representation 235, including the example three-dimensional representation 535, includes three-dimensional information that is discretized into cells 401 that are assigned material properties using the layer information 225. The elements of the layout file 170 can be in different three-dimensional locations that are labeled using the Cartesian "x", "y", and "z" axes of FIGS. 5A-5B. In some embodiments, optimization of the interconnect 310 can be limited to the interconnect 310 or can also include the terminals 305. Similarly, one or more interface surfaces 311 can be constrained as part of the operation of the example process 200. In this manner, modifications of the shape of the interconnect 310 can be guided away from a non-physical solution.

[0356] 5A is a schematic diagram illustrating an example three-dimensional representation 235 of a layout file 170 according to an embodiment of the present disclosure. The layout file 170 includes an interconnect 310, a terminal 305, a conductive element 415 at substantially the same "z" position as the interconnect 310, and an additional conductive element 515 at a different "z" position than the interconnect 310. In some embodiments, the conductive element 515 may be or may include a terminal 305. The layout file 170 represents an example input to the example process 200. Thus, the interconnect 310, the conductive element 515, and the conductive element 415 follow a linear routing convention. The three-dimensional representation 235 is discretized into cells 501, and it is understood that the linear routing allows each interface 311 of the interconnect 310 to be represented as a smooth unitary surface as opposed to the quantized curved interface 311 shown in FIG. 5B.

[0357] 5B is a schematic diagram illustrating an example three-dimensional representation 575 of the updated layout file 270 according to an embodiment of the present disclosure. The example three-dimensional representation 575 represents the optimized interconnect 310 reshaped according to the example process 200, as described in more detail with reference to FIG. 2. As previously described, one or more interface surfaces 311 of the interconnect 310 may be constrained such that the interconnect 310 is reshaped while maintaining at least a portion of the electrical contact to the conductive element 515 while improving the RC, as described in more detail with reference to FIGS. 3A-3B. 3A-3B, FIG. 5B illustrates that physics-based shape modification of the interconnect 310 can result in a curvilinear interconnect 310 being widened at one or more locations, narrowed at one or more locations, redirected, translated, displaced, or otherwise deformed based at least in part on an electromagnetic field simulation describing the interaction between the interconnect 310 and the conductive element 415 or conductive element 515. As described in more detail with reference to FIGS. 4A-4D, the final shape of the interconnect 310 is based at least in part on the terminal information 220 and the material information 225, and thus the shape of the interconnect illustrated in FIG. 5B is intended as an example and not a limiting embodiment. In some embodiments, differences in the terminal information 220 and / or layer information 225 can result in different shape modifications in the exemplary three-dimensional representation 575.

[0358] 6A-6C are schematic diagrams illustrating example floor plans of the layout file 170 and the updated layout 270, respectively, of an intermediate and final iteration of the example process 200. Figures 6A-6C are provided to illustrate the progressive shape modification of the interconnect 310 over multiple iterations of the example process 200 described in more detail with reference to Figure 2.

[0359] 6A is a schematic diagram illustrating an example floor plan 600 of a layout file 170 according to an embodiment of the present disclosure. The example floor plan 600 corresponds to the example three-dimensional representation 535 of FIG. 5A projected onto the "xy" plane at a "z" position of the interconnect 310 for ease of visual interpretation. The example floor plan 600 illustrates that the interconnect 315, the conductive element 415, and the conductive element 515 adhere to the straight-line routing convention according to the layout file 170 received after routing but before the first iteration of the example process 200. However, in some embodiments, the layout file 170 is received after at least one iteration of the example process 200. For example, the updated layout 270 may be encoded as the layout file 170 and stored in the third database 165. An example of such a process may include a situation where a first set of one or more iterations of the exemplary process 200 is completed after which the updated layout 270 is stored as a layout file 170 to be accessed for additional iterations of the exemplary process 200, if indicated.

[0360] 6B is a schematic diagram illustrating an example floor plan 630 of an intermediate state updated layout 270 according to an embodiment of the present disclosure. The example floor plan 630 represents an "xy" projection of the three-dimensional representation 235 after one or more iterations of the example process 200 have applied one or more geometric modifications to the interconnects 310 as compared to the example floor plan 600. As shown, the interconnects 310 no longer follow a straight line routing convention, but rather include one or more curvilinear surfaces. The three-dimensional representation 235 is discretized into cells 401, while FIG. 6B includes smoothed boundary surfaces 311 for ease of visual interpretation, although in some embodiments, the three-dimensional representation 235 may be smoothed as part of generating the updated layout 270 (e.g., the smoothed updated layout 270 may be used to generate a mask that is sent to the manufacturing system 115). The shape of interconnect 310 reveals one or more shape constraints in that interconnect 310 is constrained to maintain contact with conductive element 515 at one or more locations corresponding to the contact points with terminal 305. Although interconnect 310 is shown with three contact points, it is understood that interconnect 310 may represent the "two port" configuration described in connection with Figures 3A-3B.

[0361] 6C is a schematic diagram illustrating an example floor plan 650 of an advanced updated layout 270, according to an embodiment of the present disclosure. The example floor plan 650 represents an "xy" projection of the three-dimensional representation 235 after one or more additional iterations of the example process 200 have applied one or more geometric modifications to the interconnects 310, as compared to the example floor plan 630 of FIG. 6B. The example floor plan 650 illustrates the following in response to the local contribution of the cells 401 to the RC time constant based at least in part on the terminal information 220 and the layer information 225: (i) increasing the distance between the interconnects 310 and the conductive elements 415, (ii) constraining the interconnects 310 to maintain contact with the terminals 305, and (iii) reducing the local width "W X6 illustrates multiple shape modifications to interconnect 310 to incorporate variations in "Y" as a function of lateral position on interconnect 310. In some embodiments, exemplary floor plan 650 is a result of iterations applied to updated layout 270. In some embodiments, exemplary floor plan 650 is generated from operations applied to three-dimensional representation 235 prior to generating updated layout 270. In this manner, the heuristics described with reference to FIGS. 3A-3B may be applied to three-dimensional representation 235, for example, by reallocating material property information of one or more cells 401.

[0362] 7 is a block diagram illustrating an example flow 700 of operations applied to a three-dimensional representation as part of the example process 200 of FIG. 2, according to an embodiment of the present disclosure. As with the component operations of the example process 200, the example flow 700 represents operations that may be performed locally and / or distributed by a computer system (e.g., server 105, client computing device 110, etc.). Thus, the component blocks of the example flow 700 may be understood to represent machine-readable instructions encoded in software (e.g., software 155 of FIG. 1) that enable a computer system to modify the shape of interconnects 310, terminals 305, etc., as part of a physics-based optimization of the layout file 170 that may introduce curvilinear features into routed elements of the layout file 170. Although the component blocks of the example flow 700 are depicted as proceeding in sequence, it will be understood that one or more blocks may be omitted, repeated, reordered, or subdivided as part of an iteration of the example process 200 and / or implementation on a particular computer system. For example, in the context of distributed systems, a block may be broken down into multiple component processes to facilitate parallelization. In this way, two or more blocks may be executed in parallel rather than sequentially.

[0363] At block 705, the example flow 700 includes generating the three-dimensional representation 235, which corresponds to operation 207 of the example process 200. Operations 201-205 of the example process 200 have been omitted from the example flow 700 to focus the description on the components of operations 207-211. As described in more detail with reference to FIG. 2, block 705 may include discretizing the layout file 170 or the modified layout 270 to generate the three-dimensional representation 235.

[0364] At blocks 710-715, the example flow 700 includes generating the conductivity contributions of at least a subset of the cells 401 of the three-dimensional representation 235 to the RC time constant of the interconnect 310. As described in more detail with reference to Figures 3A-3B, in some cases, at least some of the contributions for the cells 401 of the three-dimensional representation 235 may be ignored, for example, if that portion of the cells 401 is relatively far from the interface 311 and thus reallocation of material information is unlikely to occur. Individual Contributions

[0365]

number

[0366] and

[0367]

number

[0368] Detailed physical simulation information for determining is discussed above with reference to FIGS. 3A-3B.

[0369] In block 720, one or more smoothing operations are applied on a cell-by-cell basis to the contributions generated in blocks 710-715. The smoothing operations may be or may include a three-dimensional smoothing function, such as a Gaussian smoothing function with a standard deviation parameter σ. As described in more detail with reference to FIG. 3B, the smoothing allows the relative contributions of neighboring cells 401 to be extrapolated, thereby facilitating the heuristics for determining material reallocation described in connection with blocks 721-730, which may be performed on a cell-by-cell basis.

[0370] At decision block 721, for a given cell 401, the location of the given cell 401 within the three-dimensional representation 235 and / or material property metadata of the given cell 401 are used to determine whether the given cell 401 forms part of the interconnect 310 or the surrounding oxide. In some embodiments, cells 401 corresponding to terminals 305 and / or conductive elements 415 and 515 are omitted from the operations of the example flow 700. In some embodiments, at least a subset of cells 401 corresponding to interconnects 310 are similarly omitted, for example, as a way of imposing one or more shape constraints on interconnects 310.

[0371] In decision blocks 723 and 724, an appropriate comparison of the individual contributions generated in blocks 710 and 715, as described in more detail with reference to Figures 3A-3B, is applied to determine whether to reallocate the material information of a given cell 401 in block 725 or to retain the material information of the given cell 401 in block 730. Although block 730 is shown as two blocks, it is understood that the instructions are equivalent regardless of whether the given cell 401 forms part of the interconnect 310 or the surrounding oxide.

[0372] In block 735, the modifications indicated by blocks 721-730 with respect to the subset of cells 501 are encoded into an updated layout 270. As described in more detail with reference to FIG. 2, the updated layout 270 may be generated by applying one or more material reallocations to the three-dimensional representation 235 to generate an updated three-dimensional representation 235 (e.g., the example three-dimensional representation 575 of FIG. 5B), which may then be converted to a layout file 170 (e.g., in OASIS or GDSII format) for use in manufacturing the integrated circuit.

[0373] In some embodiments, the example flow 700 includes a manufacturability determination and resulting modifications to the updated layout 270 at blocks 740 and 745, respectively. As described in more detail with reference to FIGS. 2 and 3A-3B, verifying the manufacturability of the updated layout 270 may include performing a process simulation using process data describing the semiconductor manufacturing system 115, which allows one or more manufacturability criteria to be evaluated. For example, while a typical Boolean design rule checker may return a false value for the updated layout 270, at least in part due to curvilinear routing, a physics-based process simulation may allow functionality preservation to guide the manufacturability verification. In this manner, verifying the manufacturability may include determining whether the updated layout 270 represents a non-physical solution, whether the updated layout 270 functions according to design when manufactured, and / or whether the updated layout 270 violates any Boolean design rules that apply to linear portions of the updated layout 270.

[0374] In some cases, the updated layout 270 may include portions that comply with straight-line routing standards. For example, the interconnect 310 may include curved interfaces 311 in the "xz" and "yz" planes, and may include flat or substantially flat interfaces 311 in the "xy" plane. Similarly, the interconnect 310 may be constrained by a minimum thickness in the "z" axis so that a Boolean design rule check, which may be relatively less computationally intensive than a physics-based process simulation, may verify whether the updated layout 270 is manufacturable. To that end, such a minimum thickness constraint may be encoded as part of an operation of the exemplary process 200. For example, modifying the three-dimensional representation 235 as part of operation 211 of the exemplary process 200 may include a constraint that a minimum number of cells 401 ascribed to the interconnect 310 (e.g., assigned conductive material properties) is maintained in the "z" direction at all locations within the interconnect 310 (e.g., defined by the interfaces 311).

[0375] Advantageously, the operations of the example process 200 and the example flow 700 may be performed for various combinations of input and output terminals 305, as described by the terminal information 220. The so-called "fan-out," "fan-in," and "fan-in-out" layouts 170 include at least one input terminal and at least one output terminal, but may include multiples of either or both.

[0376] 8 is a schematic diagram illustrating an example three-dimensional representation 835 of an updated layout file 270 including a fan-out configuration, according to an embodiment of the present disclosure. The example three-dimensional representation 835 represents a shape-modified interconnect 310 reshaped according to the example process 200, as described in more detail with reference to FIG. 2. As shown, a first one 305-1 of the terminals 305 represents a single input terminal, while a second one 305-2, a third one 305-3, and a fourth one 305-4 represent output terminals, as described in more detail in connection with FIGS. 3A-3B and in particular the detailed discussion of fan-out optimization above, including equations (39)-(42). With the output terminals 305-2 to 305-3 in different quadrants of the three-dimensional representation 835, the interconnect 310 exhibits a tee shape with discretized curvilinear features and non-uniform width as a function of position (r). At that point, the interconnect 310 of the three-dimensional representation 835 narrows at the division point into multiple branches, each coupling an input terminal 305-1 to a different output terminal 305-2, 305-3, or 305-4. The interconnect 310 is also shown to have a substantially uniform thickness in the "z" direction, while each branch has a different width in the "x" or "y" direction. In this manner, the effect of different terminal information 220 describing each terminal 305 is shown as a result of different operating parameters of the different terminals 305.

[0377] 9 is a schematic diagram illustrating an example three-dimensional representation 935 of an updated layout file 270 including a fan-in-out configuration, according to an embodiment of the present disclosure. The example three-dimensional representation 935 represents a modified interconnect 310 reshaped according to the example process 200, as described in more detail with reference to FIG. 2. The example three-dimensional representation 935 can be understood as a modification of the example three-dimensional representation 835, with the addition of a fifth terminal 305-5 representing a second input terminal. Similar to the first terminal 305-1, the fifth terminal 305-5 is conductively coupled to the output terminals 305-2, 305-3, and 305-4 via the interconnect 310. Similar to FIG. 8, the interconnect 310 branches near a split point substantially aligned with the output terminals 305-3 and 305-4. The interconnect 310 of the three-dimensional representation 935 also shows the wider area between the division point and the input terminals 305-1 and 305-5, along with the relative narrowing of the conductive paths after the division. In contrast to the operations described as part of the fan-out optimization, the fan-in optimization may proceed by segmenting the layout file into multiple partial layouts that are modified by the operations of the exemplary process 200. After modification of the shapes of the partial layouts, an updated layout is generated by merging the partial layouts. In this manner, the fan-in-out modification may include parallel instances of the exemplary process 200 and one or more preliminary operations that are applied to the layout file, for example, as part of a discretization operation.

[0378] FIG. 10 is a block diagram illustrating an example flow 1000 for modifying the shape of a fan-in or fan-in-out layout file 170, according to an embodiment of the present disclosure. As with the example process 200 and the example flow 700, the example flow 1000 represents operations that may be performed locally and / or distributed by a computer system (e.g., server 105, client computing device 110, etc.). Thus, the constituent blocks of the example flow 1000 may be understood to represent machine-readable instructions encoded in software (e.g., software 155 of FIG. 1 ) that enable a computer system to modify the shape of interconnects 310, terminals 305, etc., as part of a physics-based optimization of the layout file 170 that may introduce curvilinear features into routed elements of the layout file 170. Although the constituent blocks of the example flow 1000 are depicted as proceeding in sequence, it is understood that one or more blocks may be omitted, repeated, reordered, or subdivided as part of an iteration of the example process 200 and / or implementation on a particular computer system. For example, in the context of distributed systems, a block may be broken down into multiple component processes to facilitate parallelization. In this way, two or more blocks may be executed in parallel rather than sequentially.

[0379] At block 1005, the exemplary flow 1000 includes receiving layout data 215 including terminals 305 and interconnects 310. Similar to the exemplary process 200, the layout data 215 includes terminal information 220 and layer information 225. The terminal information 220 encodes whether the terminal 305 is an input terminal or an output terminal. Thus, block 1010 includes generating a separate conductive path for each input terminal. For example, in the exemplary three-dimensional layout 1035 of FIG. 9, the interconnects 310 couple two input terminals with three output terminals. Thus, block 1010 includes defining a first conductive path between a first input terminal 305-1 and output terminals 305-2, 305-3, and 305-4, and defining a second conductive path between a second input terminal 305-5 and an output terminal. In this manner, the fan-in-out configuration may be modified by operation of the exemplary process 200 by defining a number of separate conductive paths equal to the number of input terminals. Advantageously, implementing the exemplary flow 1000 allows the complex layout file 170 to be segmented into relatively simple configurations for parallel processing. In this manner, physics-based shape modifications may be applied to the layout file 170 that would otherwise not pass design rule-based manufacturability verification. Furthermore, integrated circuit layouts often incorporate many repeated instances of basic layout elements associated with, for example, circuit components (e.g., fin-FETs). Thus, segmentation may allow the layout data 215 to be used to populate a database of partial layouts indexed to layer information 225 and terminal information 220, which may further improve the performance of the exemplary system 100.

[0380] In block 1015, the first conductive path defined from the layout data 215 is iterated using at least a subset of the operations of the exemplary process 200. As described with reference to FIGS. 3A-8, one or more iterations of the exemplary process 200 can generate an updated layout 270. However, in the context of the exemplary flow 1000, the iteration of the first path provides a partial update of the layout file 170. Concurrently, in parallel, sequentially, or otherwise, block 1020 includes iterating the second conductive path using at least a subset of the operations of the exemplary process 200. As previously described, the exemplary flow 1000 is described with respect to the layout file 170 including two input terminals 305. To that end, blocks 1000 and 1015 may entail additional instances of the exemplary process 200 for additional conductive paths corresponding to the third input terminal 305, the fourth input terminal 305, and so on.

[0381] At block 1025, the example flow 1000 includes merging the shape-modified paths to generate an updated three-dimensional representation 235 for the fan-in or fan-in-out configuration. In some embodiments, the flow 1000 includes applying a Boolean function for each cell to determine whether a given cell 401 should be assigned to a conductive material or a dielectric or insulating material. Examples of Boolean functions include AND, OR, INCLUSIVE OR, EXCLUSIVE OR, etc. In an illustrative example, an INCLUSIVE OR function may be defined such that the cell 401 is assigned to a conductive material (e.g., metal) if the cell 401 is assigned as metal in either the first conductive path or the second conductive path to avoid removing both portions of the interconnect 310 that couple to only one of the input terminals 305.

[0382] FIG. 11 is a schematic diagram illustrating an example three-dimensional representation 1175 of a multi-layer layout file 170 including multiple interconnects 310 coupling multiple terminals, according to an embodiment of the present disclosure. The example three-dimensional representation 1175 represents an optimized layout file 170 including a first interconnect 310-1 and a second interconnect 310-2 reshaped according to the example process 200, as described in more detail with reference to FIG. 2. In the example of FIG. 11, both the first interconnect 310-1 and the second interconnect 310-2 are fan-in-out configured to couple multiple input terminals with multiple output terminals on two different "z" layers of an integrated circuit layout. For such a multi-layer layout 170, the example process 200 may include multiple parallel optimization processes incorporating the operations of the example flows 700 and 1000 to subdivide the optimization operations and then merge components of the example three-dimensional representation 1175 into an updated layout 270.

[0383] In the illustrative example shown in the exemplary three-dimensional representation 1175, the first interconnect 310-1 may be modified as described in more detail with reference to FIGS. 8-11. During optimization of the first interconnect 310-1, the second interconnect 310-2 may be kept static. After convergence of the first interconnect 310-1, the second interconnect 310-2 may be optimized as described in more detail with reference to FIGS. 8-11, with the first interconnect 310-1 kept static. By repeating this process, both the first interconnect 310-1 and the second interconnect 310-2 may be modified to optimize their respective RC values ​​or other optimization metrics, as described in more detail with reference to FIG. 2. Additionally or alternatively, the first interconnect 310-1 and the second interconnect 310-2 may be optimized in parallel, such that multiple interconnects 310 are modified together in each iteration of the exemplary process 200. Advantageously, such an approach allows for fewer iterations of the exemplary process 200.

[0384] The processes described above are described in terms of computer software and hardware. The described techniques may comprise machine-executable instructions embodied in a tangible or non-transitory machine (e.g., computer) readable storage medium that, when executed by the machine, causes the machine to perform the described operations. Additionally, the processes may be embodied in hardware, such as an application specific integrated circuit ("ASIC"), or in other ways.

[0385] A tangible machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a non-transitory form accessible by a machine (e.g., a computer, a network device, a personal digital assistant, a manufacturing tool, any device with a set of one or more processors, etc.). For example, machine-readable storage media include recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0386] The above description of illustrated embodiments of the present invention, including what is described in the "Summary", is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific embodiments and examples of the present invention have been described herein for illustrative purposes, various modifications are possible within the scope of the present invention, as those skilled in the art will recognize.

[0387] These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed herein. Rather, the scope of the invention should be determined entirely by the following claims, which should be construed in accordance with established doctrines of claim interpretation. [Explanation of symbols]

[0388] 100 Systems 105 Server 110 Client Computing Device 111 Display 115 Semiconductor Manufacturing Systems 120 Network 125 First Database 130 Training Data 135 Second Database 137 Process Data 140 Shape Optimizer 141 Discretization Module 143 Physical Simulation Module 144 Machine Learning Models 145 Shape optimization module, model 146 Databases 147 Process Simulator 149 Modification Module 150 Machine Learning Models 155 Software 160 Computer Circuits 165 The third database 170 Design files, integrated circuit layout 200 processes 215 Layout Data 220 Terminal Information 225 Layer information, material information 235 3D Expression 250 Capacitive Contribution 255 Conductive Contribution 260 characteristic indicators 270 Updated Layout 300 Toy Model 305 Terminal 305-1 First terminal 305-2 Second Terminal 305-3 Third Terminal 305-4 4th terminal 305-5 Fifth Terminal 310 Interconnect 310-1 First Interconnect 310-2 Second Interconnect 311 Interconnect Boundaries, Boundary Surfaces, Interconnect Surfaces 313 Boundary area 400 Floor Plan 401 Cell 411 Conductive Cell 413 Dielectric Cell 415 Conductive characteristics, conductive elements 425 Floor Plan 450 Floor Plan 460 Floor Plan 501 Cell 515 Additional Conductive Elements 535 3D Expression 575 3D Expression 600 Floor Plan 630 Floor Plan 650 Floor Plan 700 Flow 835 3D Expression 935 3D Expression 1000 Flow 1035 3D Layout 1175 3D Expression

Claims

1. 1. A computer-implemented method for optimization of a conductive interconnect, comprising: receiving an integrated circuit layout including a plurality of terminals and interconnects, the interconnects representing conductive couplings between the plurality of terminals; receiving terminal information describing operational parameters of the plurality of terminals; receiving layer information describing material composition and material property information of the plurality of terminals and the interconnect; generating a three-dimensional representation of the integrated circuit using the integrated circuit layout and the layer information, the three-dimensional representation including cells corresponding to discrete volume elements of the three-dimensional representation, the cells representing at least a portion of the interconnects or at least a portion of non-conductive material outside the interconnects; using the three-dimensional representation and the terminal information to determine individual contributions of the cells to a resistance-capacitance (RC) value of the interconnect; generating an updated integrated circuit layout based at least in part on the individual contributions; A computer-implemented method comprising:

2. generating the individual contributions of the elements to the RC value, determining a generator admittance and a load admittance of the cell based at least in part on the layer information and the terminal information; determining an input admittance using said generator admittance and said load admittance; determining an admittance density of the cell using the input admittance, the admittance density describing the local contribution of the cell to the admittance of the interconnect; generating a differential RC value for the cell based at least in part on the admittance density; 2. The computer-implemented method of claim 1, comprising:

3. the cell is a first cell, the three-dimensional representation further includes a second cell, and generating the updated integrated circuit layout includes: determining a conductive contribution of the first cell and the second cell to a conductance of the interconnect; determining a capacitive contribution of the first cell and the second cell to a capacitance of the interconnect; generating a smoothed conductive contribution and a smoothed capacitive contribution of the first cell using the respective contributions of the first cell and the second cell; and determining a material composition of the first cell based at least in part on the smoothed contribution of the first cell; and 2. The computer-implemented method of claim 1, comprising:

4. determining the material composition reassigning the cell to represent the non-conductive material if the smoothed capacitive contribution of the first cell exceeds the smoothed conductive contribution of the first cell when the cell represents a portion of the interconnect; or reallocating the cell to represent the interconnect if the smoothed conductive contribution of the first cell exceeds the smoothed capacitive contribution of the first cell when the cell represents a portion of the non-conductive material.

4. The computer-implemented method of claim 3, comprising:

5. 5. The computer-implemented method of claim 4, wherein generating the smoothed contribution of the first cell comprises three-dimensional smoothing of the respective contributions of the first cell and the second cell.

6. 5. The computer-implemented method of claim 4, wherein generating the smoothed contribution of the first cell comprises Gaussian smoothing using a standard deviation parameter σ less than a width of the interconnect in the integrated circuit layout.

7. inputting the updated integrated circuit layout into a process model configured to use the updated integrated circuit layout to output a simulated manufactured integrated circuit produced by a semiconductor manufacturing system; generating the simulated manufactured integrated circuit as an output of the process model; determining manufacturability of the updated integrated circuit layout on the semiconductor manufacturing system using the output of the process model; 2. The computer-implemented method of claim 1, further comprising:

8. the manufacturability indicates that the updated integrated circuit layout is not manufacturable by the semiconductor manufacturing system, the method comprising:

8. The computer-implemented method of claim 7, further comprising generating a modified layout using the updated integrated circuit layout and the process model, wherein the modified layout is manufacturable by the semiconductor manufacturing system.

9. 2. The computer-implemented method of claim 1, wherein the plurality of terminals includes an input terminal and two output terminals.

10. the plurality of terminals includes a plurality of input terminals and at least one output terminal, the three-dimensional representation is a first representation, and the method further comprises: generating said first representation when a first input terminal among said input terminals is active and the remaining input terminals are inactive; generating a second representation using the integrated circuit layout and the layer information, the second representation corresponding to when a second input terminal included in the input terminals is active and remaining input terminals are inactive, and both the first representation and the second representation include the cell; generating a first partial update using the first representation; generating a second partial update using the second representation; generating the updated integrated circuit layout using the first partial update and the second partial update; 2. The computer-implemented method of claim 1, further comprising:

11. 11. The computer-implemented method of claim 10, wherein generating the updated integrated circuit layout includes merging the first partial update and the second partial update using an inclusive OR operator.

12. outputting the updated integrated circuit layout, generating an updated integrated circuit layout file using the updated integrated circuit layout; and Storing the updated integrated circuit layout file in a data store.

2. The computer-implemented method of claim 1, further comprising the steps of:

13. A non-transitory computer-readable memory device storing machine-executable instructions, the machine-executable instructions being operable when executed by the machine to cause the machine to: receiving an integrated circuit layout including a plurality of terminals and interconnects, the interconnects representing conductive couplings between the plurality of terminals; receiving terminal information describing operational parameters of the plurality of terminals; receiving layer information describing material composition and material property information of the plurality of terminals and the interconnect; generating a three-dimensional representation of the integrated circuit using the integrated circuit layout and the layer information, the three-dimensional representation including cells corresponding to discrete volume elements of the three-dimensional representation, the cells representing at least a portion of the interconnects or at least a portion of non-conductive material outside the interconnects; using the three-dimensional representation and the terminal information to determine individual contributions of the cells to a resistance-capacitance (RC) value of the interconnect; and generating an updated integrated circuit layout based at least in part on said individual contributions; 4. A non-transitory computer readable memory device for causing a computer to perform operations including:

14. generating the individual contributions of the elements to the RC value, determining a generator admittance and a load admittance of the cell based at least in part on the layer information and the terminal information; determining an input admittance using said generator admittance and said load admittance; determining an admittance density of the cell using the input admittance, the admittance density describing the local contribution of the cell to the admittance of the interconnect; generating a differential RC value for the cell based at least in part on the admittance density; 14. The non-transitory computer readable memory device of claim 13, comprising:

15. the three-dimensional representation further includes a second cell, and generating the updated integrated circuit layout comprises: determining a conductive contribution of a first cell and a second cell to a conductance of the interconnect; determining a capacitive contribution of the first cell and the second cell to a capacitance of the interconnect; generating a smoothed conductive contribution and a smoothed capacitive contribution of the first cell using the respective contributions of the first cell and the second cell; and determining a material composition of the first cell based at least in part on the smoothed contribution of the first cell; and 14. The non-transitory computer readable memory device of claim 13, comprising:

16. determining the material composition reassigning the cell to represent the non-conductive material if the smoothed capacitive contribution of the first cell exceeds the smoothed conductive contribution of the first cell when the cell represents a portion of the interconnect; or reallocating the cell to represent the interconnect if the smoothed conductive contribution of the first cell exceeds the smoothed capacitive contribution of the first cell when the cell represents a portion of the non-conductive material.

16. The non-transitory computer readable memory device of claim 15, comprising:

17. 14. The non-transitory computer-readable memory device of claim 13, wherein generating a smoothed contribution of a first cell comprises Gaussian smoothing using a standard deviation parameter σ that is less than an initial width of the interconnect in the integrated circuit layout.

18. The instructions, when executed by the machine, cause the machine to: inputting the updated integrated circuit layout into a process model configured to output a simulated manufactured integrated circuit produced by a semiconductor manufacturing system using the updated integrated circuit layout; generating the simulated manufactured integrated circuit as an output of the process model; and determining a manufacturability of the updated integrated circuit layout for the semiconductor manufacturing system based at least in part on the output of the process model; and 14. The non-transitory computer readable memory device of claim 13, further comprising:

19. the manufacturability indicates that the updated integrated circuit layout is not manufacturable by the semiconductor manufacturing system, and the instructions, when executed by the machine, cause the machine to: generating a modified layout based at least in part on the updated integrated circuit layout and the process model, the modified layout being manufacturable by the semiconductor manufacturing system.

20. The non-transitory computer readable memory device of claim 18, further comprising:

20. the plurality of terminals includes a plurality of input terminals and at least one output terminal, the three-dimensional representation is a first representation, and the instructions, when executed by the machine, cause the machine to: generating the first representation corresponding to when a first input terminal among the input terminals is active and the remaining input terminals are inactive; generating a second representation using the integrated circuit layout and the layer information, the second representation corresponding to when a second input terminal included in the input terminals is active and remaining input terminals are inactive, both the first representation and the second representation including the cell; generating a first partial update using the first representation; generating a second partial update using the second representation; and generating the updated integrated circuit layout using the first partial update and the second partial update; and 14. The non-transitory computer readable memory device of claim 13, further comprising:

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