Semiconductor integrated circuit wiring design device, semiconductor integrated circuit wiring design method, and semiconductor integrated circuit wiring design program

Abstract

To provide a wiring design device for a semiconductor integrated circuit that can handle an obstacle in a complicated shape.SOLUTION: A wiring design device for a semiconductor integrated circuit comprises: first-time candidate cell acquisition means 35 which acquires a first cell candidate until a starting-point section cell is extended up to a space region forward in a longitudinal direction from the starting-point section cell to the end point of wiring in parallel with a longitudinal segment or a lateral segment; second-time candidate cell acquisition means 36 which acquires a second cell candidate until the cell is extended up to a space region newly forward in the direction of the end point as a lateral direction orthogonal to the longitudinal direction; and similarly fourth-, fifth-, ..., (n)th-time candidate cell acquisition means 38 which acquire necessary fourth, fifth, ..., n-th (integer) cell candidates.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a wiring design device for a semiconductor integrated circuit, a wiring design method for a semiconductor integrated circuit, and a wiring design program for a semiconductor integrated circuit. [Background technology]

[0002] In semiconductor layout design, when there are complex design rules such as multi-spacing rules or obstacles with complex shapes, conventional shape-based automatic routing cannot complete the routing or creates detour routes.

[0003] Patent Document 1 discloses an invention relating to a wiring design method capable of preventing noise errors occurring between clock nets while keeping the consumption of wiring resources small. That is, this invention is a wiring design method for wiring both a clock net and a non-clock net of a semiconductor integrated circuit, characterized in that the clock net is routed under a first condition that specifies the spacing between the wires, that is, that a space is provided between the wires to allow other wiring, and the non-clock net is routed under a second condition that specifies the spacing between the wires narrower than the first condition.

[0004] Patent Document 2 discloses a wiring design method for a semiconductor integrated circuit, in which, when determining wiring paths between input / output terminals of circuit cells or circuit blocks on a semiconductor substrate by automatic wiring processing, the semiconductor substrate is divided into a plurality of circuit regions including the circuit cells or circuit blocks, position information of obstacles present in the circuit regions is detected, wiring paths between the circuit regions are determined according to the position information of the obstacles, and a wiring path within the divided circuit regions is determined using a part of the determined wiring path. In Patent Document 2, a line segment search method is used as a method for determining the wiring paths between the circuit regions.

[0005] Patent Document 3 discloses a layout design technique suitable for a wiring process in the layout design of a semiconductor integrated circuit. The layout design method of Patent Document 3 includes the steps of: storing, in a rectangular area list storage unit, a rectangular area that is a starting point of wiring from a wiring area of ​​a plurality of layers divided into a plurality of areas by a grid, as a starting area, and a rectangular area that is an end area, in a wiring area of ​​a plurality of layers; a wiring cost addition unit adding a wiring cost each time the search for a wiring path from the starting area to the end area is advanced by one rectangular area; a via cost multiplication unit multiplying the wiring cost by the via cost of a multi-cut via to be placed in any of the wiring areas of the plurality of layers; an obstacle cost addition unit adding an obstacle cost based on obstacle information stored in the obstacle list storage unit; a calculation unit storing the calculation results of the wiring cost, the via cost, and the obstacle cost in the rectangular area list; a route search unit searching for the wiring route in the wiring areas of the plurality of layers based on the calculation results; a wiring connection unit connecting the starting area and the end area; and a via placement unit placing the multi-cut via in any of the wiring areas of the plurality of layers.

[0006] Patent Document 4 discloses a method for designing a semiconductor integrated circuit device, which considers an area where a wiring obstacle is placed when placing a target wiring with a plurality of narrow wires. This method includes the steps of generating circuit diagram data representing a plurality of macros and their connections, generating a netlist representing each of the plurality of macros and wiring between nodes connected thereto based on the circuit diagram data, generating division shape data representing a target wiring among the plurality of wires and including the number of narrowest narrow wires based on the netlist, placing the plurality of macros in a coordinate area, determining a wiring route for placing the target wiring in an area of ​​the coordinate area other than the area where the plurality of macros are placed, and changing the number of lines included in the division shape data to the number of lines per layer and the number of stacked layers based on the wiring route. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2006-278886 A [Patent Document 2] Japanese Patent Application Publication No. 3-124045 [Patent Document 3] JP 2006-65403 A [Patent Document 4] JP 2010-211332 A Summary of the Invention [Problem to be solved by the invention]

[0008] As described above, in conventional semiconductor layout design, various efforts have been made to deal with the existence of complex design rules such as multi-spacing rules, and the presence of obstacles with complex shapes, but conventional shape-based automatic wiring has not been able to complete the wiring. The object of the present invention is to provide a wiring design device for semiconductor integrated circuits, a wiring design method for semiconductor integrated circuits, and a wiring design program for semiconductor integrated circuits that can deal with the existence of such complex design rules and the presence of obstacles with complex shapes. [Means for solving the problem]

[0009] The wiring design apparatus for a semiconductor integrated circuit according to this embodiment includes wiring area / non-wiring area information calculation means for calculating wiring area information and non-wiring area information based on size information of existing metal provided in a design target area and size information of wiring to be drawn in, matrix division means for dividing a wiring area into a matrix and generating rectangular cells, division cell generation means for generating vertical and horizontal line segments throughout the design target area based on corners generated in the wiring area by the rectangular cells to generate division cells of existing wiring, space division cells and wiring area division cells, starting point division cell selection means for selecting a starting point division cell based on a starting point of wiring, and a first cell candidate selection means for extending the starting point division cell until it hits a space area, in a direction parallel to the vertical line or the horizontal line segment and with the vertical direction from the starting point division cell to the end point of wiring as the forward direction, the first candidate cell acquisition means for obtaining a complement of the first candidate cell; a second candidate cell acquisition means for obtaining a second cell candidate by taking as a starting point a cell that has hit the space area at the shortest distance from among the first cell candidates, and extending the cell in the new forward direction in a horizontal direction perpendicular to the vertical direction, with the direction of the end point as a new forward direction, up to the space area; a third candidate cell acquisition means for obtaining a third cell candidate by taking as a starting point a cell that has hit the space area at the shortest distance from among the second cell candidates, and extending the cell in the new forward direction in a vertical direction perpendicular to the horizontal direction, with the direction of the end point as a new forward direction, up to the space area; and a 4th, 5th, ..., nth candidate cell acquisition means for obtaining the necessary 4th, 5th, ..., n (integer) cell candidates in the same manner, wherein the nth candidate cell acquisition means obtains the nth cell candidate up to the end point.

[0010] In the wiring design apparatus for a semiconductor integrated circuit according to this embodiment, the starting point partition cell selection means and each-time candidate cell acquisition means select partition cells so that they have a width (design-time cell width) equal to or greater than a predetermined wiring width.

[0011] The wiring design device for a semiconductor integrated circuit according to this embodiment is characterized in that size information of existing metal provided in the design target area is its width and space dimensions, and size information of the wiring to be drawn in is its width and space dimensions.

[0012] The wiring design device for a semiconductor integrated circuit according to this embodiment is characterized by comprising a final wiring region selection means for generating a confirmed cell by connecting cell candidates from a start point to an end point, and selecting a wiring region drawn with an optimal wiring width within the wiring area generated by the confirmed cell as a final wiring region.

[0013] In the wiring design device for a semiconductor integrated circuit according to this embodiment, the final wiring region selection means creates several candidate wiring regions with optimal wiring widths within the wiring area generated by the confirmed cells, and selects the optimal candidate wiring region as the final wiring region by an area edge method.

[0014] The wiring design method for a semiconductor integrated circuit according to this embodiment includes a wiring area / non-wiring area information calculation step of calculating wiring area information and non-wiring area information based on size information of existing metal provided in a design target area and size information of wiring to be drawn in, a matrix division step of dividing the wiring area into a matrix to generate rectangular cells, a partition cell generation step of generating partition cells of existing wiring, space partition cells, and wiring area partition cells by generating vertical and horizontal line segments throughout the design target area based on corners generated in the wiring area by the rectangular cells, an origin partition cell selection step of selecting an origin partition cell based on a starting point of wiring, and a first cell candidate selection step of extending the origin partition cell until it hits the space area, in a direction parallel to the vertical line segment or the horizontal line segment and with the vertical direction from the origin partition cell to the end point of wiring as the forward direction, a second candidate cell acquisition step of obtaining a second cell candidate from among the first cell candidates, starting from a cell that has hit the space area at the shortest distance, with the direction of the end point in a horizontal direction perpendicular to the vertical direction as a new forward direction, and extending the cell in the new forward direction until it hits the space area; a third candidate cell acquisition step of obtaining a third cell candidate from among the second cell candidates, starting from a cell that has hit the space area at the shortest distance, with the direction of the end point in a vertical direction perpendicular to the horizontal direction as a new forward direction, and extending the cell in the new forward direction until it hits the space area; and 4th, 5th, ..., nth candidate cell acquisition steps of obtaining the necessary 4th, 5th, ..., n (integer) cell candidates in the same manner, wherein the nth candidate cell acquisition step is characterized in that it obtains the nth cell candidate up to the end point.

[0015] In the wiring design method for a semiconductor integrated circuit according to this embodiment, the starting point partition cell selection step and each-time candidate cell acquisition step are characterized in that a partition cell is selected so as to have a width (design-time cell width) equal to or greater than a predetermined wiring width.

[0016] The wiring design method for a semiconductor integrated circuit according to this embodiment is characterized in that size information of an existing metal provided in a design target area is its width and space dimensions, and size information of a wiring to be drawn in is its width and space dimensions.

[0017] The wiring design method for a semiconductor integrated circuit according to this embodiment is characterized by including a final wiring region selection step of generating a confirmed cell by connecting cell candidates from a start point to an end point, and selecting a wiring region drawn with an optimal wiring width within the wiring area generated by the confirmed cell as a final wiring region.

[0018] In the wiring design method for a semiconductor integrated circuit according to this embodiment, the final wiring region selection step is characterized in that several candidate wiring regions are created with an optimal wiring width within the wiring area generated by the defined cells, and the optimal candidate wiring region is selected as the final wiring region by an area edge method.

[0019] The wiring program for a semiconductor integrated circuit according to this embodiment includes a wiring area / non-wiring area information calculation means for calculating wiring area information and non-wiring area information based on size information of existing metal provided in a design target area and size information of wiring to be drawn in, a matrix division means for dividing a wiring area into a matrix and generating rectangular cells, a division cell generation means for generating vertical and horizontal line segments throughout the design target area based on corners generated in the wiring area by the rectangular cells to generate division cells of existing wiring, space division cells, and wiring area division cells, a starting point division cell selection means for selecting a starting point division cell based on a starting point of wiring, a first division cell selection means for extending the starting point division cell until it hits a space area, the first division cell selection means for extending the starting point division cell in a direction parallel to the vertical line segments or the horizontal line segments, the vertical direction from the starting point division cell to the end point of wiring being the forward direction, until it hits a space area, The present invention is characterized in that the computer functions as a first candidate cell acquisition means for acquiring a cell candidate, a second candidate cell acquisition means for acquiring a second cell candidate by taking as a starting point a cell that has hit the space area at the shortest distance from among the first cell candidates, and extending the cell in the new forward direction in a horizontal direction perpendicular to the vertical direction, as a new forward direction in the direction of the end point, up to the space area, and a third candidate cell acquisition means for acquiring a third cell candidate by taking as a starting point a cell that has hit the space area at the shortest distance from among the second cell candidates, and extending the cell in the new forward direction in a vertical direction perpendicular to the horizontal direction, as a new forward direction in the direction of the end point, up to the space area, and similarly functioning as a 4th, 5th, ..., nth candidate cell acquisition means for acquiring the necessary 4th, 5th, ..., n (integer) cell candidates, and the computer functions as an nth candidate cell acquisition means to acquire the nth cell candidate up to the end point.

[0020] The wiring program for a semiconductor integrated circuit according to this embodiment is characterized in that it causes the computer to function as the starting point partition cell selection means and each-time candidate cell acquisition means to select partition cells having a width equal to or greater than a predetermined wiring width (design-time cell width).

[0021] The wiring program for semiconductor integrated circuits according to this embodiment is characterized in that size information of existing metal provided in the design target area is its width and space dimensions, and size information of the wiring to be drawn in is its width and space dimensions.

[0022] In the wiring program for a semiconductor integrated circuit according to the present embodiment, the computer further comprises: The method is characterized in that it functions as a final wiring area selection means for generating a confirmed cell by connecting cell candidates from a starting point to an end point, and selecting a wiring area drawn with an optimal wiring width as a final wiring area within the wiring area generated by the confirmed cell.

[0023] In the wiring program for a semiconductor integrated circuit according to this embodiment, the computer is caused to function as the final wiring region selection means to create several candidate wiring regions with optimal wiring widths within the wiring area generated by the defined cells, and to select the optimal candidate wiring region as the final wiring region using an area edge method. [Brief description of the drawings]

[0024] [Figure 1] FIG. 1 is a configuration diagram of a wiring design device for a semiconductor integrated circuit according to an embodiment of the present invention implemented by a computer. [Diagram 2] FIG. 2 is a diagram showing each unit for realizing a wiring design program for a semiconductor integrated circuit according to an embodiment of the present invention. [Diagram 3] 4 is a flowchart showing the operation of the wiring design apparatus for a semiconductor integrated circuit according to the present embodiment. [Figure 4] 1 is a diagram showing an example of the inside of a design target area in which design is performed by the wiring design device for a semiconductor integrated circuit according to the present embodiment; [Diagram 5] 1 is a diagram showing an example of length and width, which is size information relating to a design target area designed by the wiring design device for a semiconductor integrated circuit according to the embodiment, and size information of existing metal provided in the design target area; [Figure 6]1 is a diagram showing a non-wiring area calculated by the wiring design device for a semiconductor integrated circuit according to the embodiment; [Figure 7] 2 is a diagram showing a wiring area calculated by the wiring design device for a semiconductor integrated circuit according to the embodiment; [Figure 8] 1 is a diagram showing a matrix division by the wiring design device for a semiconductor integrated circuit according to the embodiment; [Figure 9] 2 is a diagram showing a wiring area generated by the wiring design device for a semiconductor integrated circuit according to the embodiment; [Figure 10] 4 is a diagram showing a divided area generated by the wiring design device for a semiconductor integrated circuit according to the embodiment; [Figure 11] 1 is a diagram showing the initial state of a wiring area of ​​wiring generated by the wiring design device for a semiconductor integrated circuit according to the embodiment; [Figure 12] 1 is a diagram showing the state of a wiring area when a divided cell is selected so as to have a width equal to or greater than a predetermined wiring width (designed cell width) at the beginning of wiring generated by the wiring design device for a semiconductor integrated circuit according to the present embodiment. FIG. [Figure 13] 1 is a diagram showing the state of the wiring area when a first candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; [Figure 14] 11 is a diagram showing the state of the wiring area when a second candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; FIG. [Figure 15] 11 is a diagram showing the state of the wiring area when a third candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment. FIG. [Figure 16] 13 is a diagram showing the state of the wiring area when a fourth candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment. FIG. [Figure 17] 13 is a diagram showing the state of the wiring area when a fifth candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment. FIG. [Figure 18] 13 is a diagram showing the state of the wiring area when a sixth candidate cell is obtained by the semiconductor integrated circuit wiring design device according to the embodiment. FIG. [Figure 19]13 is a diagram showing the state of the wiring area when a seventh candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment. FIG. [Figure 20] 1 is a diagram showing the state of a wiring area when a confirmed cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; [Figure 21] 1 is a diagram showing the state of the wiring area after a confirmed cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment, until a final wiring area is obtained by the area edge method; [Figure 22] 1 is a diagram showing the state of the wiring area after a confirmed cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment, until a final wiring area is obtained by the area edge method; [Diagram 23] 1 is a diagram showing the state of the wiring area after a confirmed cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment, until a final wiring area is obtained by the area edge method; [Figure 23A] FIG. 1 is a diagram explaining the first stage of the wiring procedure using the area edge method. [Figure 23B] FIG. 1 is a diagram illustrating the second stage of the wiring procedure using the area edge method. [Figure 23C] FIG. 13 is a diagram explaining the third stage of the wiring procedure using the area edge method. [Figure 23D] FIG. 13 is a diagram illustrating the fourth stage of the wiring procedure using the area edge method. [Figure 23E] A diagram explaining the fifth stage of the wiring procedure using the area edge method. [Figure 24] 1 is a diagram showing a transition state of a wiring area for explaining a specific example of the area edge method adopted by the wiring design device for a semiconductor integrated circuit according to the embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, a wiring design device for a semiconductor integrated circuit, a wiring design method for a semiconductor integrated circuit, and a wiring design program for a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings. In each drawing, the same reference numerals are used for overlapping configurations, and overlapping explanations will be omitted. The wiring design device for a semiconductor integrated circuit according to the embodiment of the present invention can be configured by a computer such as a personal computer or a workstation as shown in FIG.

[0026] In this computer, a CPU 10 configures a wiring design device for a semiconductor integrated circuit using programs and data in a main memory 11. An external storage interface 13, an input interface 14, a display interface 15, and a network interface 16 are connected to the CPU 10 via a bus 12.

[0027] An external storage device 23 is connected to the external storage interface 13. The external storage device 23 stores programs and data for the operation of the wiring design device for semiconductor integrated circuits, which can be read out and used by the CPU 10 in the main memory 11 as appropriate. For this reason, the external storage device 23 stores programs for implementing each means of the wiring design device for semiconductor integrated circuits, which will be described later. An input device 24 such as a keyboard or a touch panel and a pointing device 22 such as a mouse are connected to the input interface 14. A display device 25 having a screen such as an LCD is connected to the display interface 15, and the display device 25 realizes the display of images and the like required for the wiring design device for semiconductor integrated circuits. A network is connected to the network interface 16, and the wiring design device for semiconductor integrated circuits can import data and the like to be used for wiring design. An input device 24 such as a keyboard for inputting data and commands and a pointing device 22 such as a mouse are connected to the input interface 14, and the input device 24 and the mouse 22 can be operated to cause the wiring design device for semiconductor integrated circuits to perform the necessary operations and processes.

[0028] The external storage device 23 stores various means for implementing a wiring design program for a semiconductor integrated circuit, as shown in Fig. 2. These means are composed of a wiring area / non-wiring area information calculation means 31, a matrix division means 32, a section cell generation means 33, a starting point section cell selection means 34, a first candidate cell acquisition means 35, a second candidate cell acquisition means 36, a third candidate cell acquisition means 37, ..., an nth candidate cell acquisition means 38, and a final wiring area selection means 39.

[0029] The wiring design device for a semiconductor integrated circuit according to this embodiment operates according to a program corresponding to the flowchart shown in Fig. 3. Therefore, the operation will be described below based on this flowchart. First, size information on the design target area, size information on existing metals (existing wiring) provided in the design target area, size information on wiring to be drawn in, etc. are retrieved from, for example, the external storage device 23, and design is started (S11).

[0030] For example, it is assumed that there is a design target area R as shown in Fig. 4, and that the width and space are determined as size information of the existing metal provided in the design target area R, and the width and space are determined as size information of the wiring to be drawn in. Here, it is assumed that two types of existing metal, "thick" and "thin", are arranged as shown in the filled rectangle within the dashed line in Fig. 4, as shown in Fig. 5. In this case, it is assumed that the length and width dimensions as size information related to the design target area R, the width and space dimensions as size information of the existing metal provided in the design target area, and the width and space dimensions as size information of the wiring to be drawn in are tabulated as shown in Fig. 5 and stored in the external storage device 23.

[0031] Based on the size information of the existing metal provided in the design target area retrieved from the external storage device 23 in the step S11 and the size information of the wiring to be drawn in, wiring area information is calculated and non-wiring area information is also calculated (S12, wiring area / non-wiring area information calculation means 31). NO_PATH_AREAThe non-wiring area described as " " is calculated. At this time, the area is calculated taking into account the MSR (multi-spacing rules) of the existing metal and the wiring to be drawn in. Furthermore, by performing a NOT logical operation on the area in Figure 6, the area shown in Figure 7 is calculated as " PATH_AREA The wiring area described as " is calculated.

[0032] Next, the wiring area is divided into a matrix to generate rectangular cells (S13, matrix division means 32). That is, the wiring area shown in FIG. 7 is originally divided into a matrix, but here, an example is simplified and explained. In the case of a design using the maze method, it is assumed that a matrix of squares that maintains the wiring width is laid out. However, since the method in this embodiment takes MSR into consideration, it is difficult to lay out squares with a regular shape. For this reason, rectangular squares are created based on the corners (vertices) of the wiring area, which is a polygon. As a result, the generated squares are not square, but are rectangular with various shapes. The coordinate extraction method is shown in FIG. 8. That is, the wiring area shown in FIG. 8(a) is divided into several rectangular cells as shown in FIG. 8(b).

[0033] Next, using the corners generated in the wiring area by the rectangular cells as references, vertical and horizontal line segments are generated throughout the design target area to generate partition cells for existing wiring, partition cells for space, and partition cells for the wiring area (S14, partition cell generating means 33). As a result, partition cells as shown in Fig. 10 are generated for the wiring area as shown in Fig. 9. The difference between Fig. 10 and Fig. 8(b) is that in Fig. 10, spare (extra) line segments are generated so that the partition cells have a width (designed cell width) greater than or equal to a predetermined wiring width. For example, one horizontal partition cell is generated between partition cells M and N in Fig. 10.

[0034] Once the section cells have been generated, a start section cell S and an end section cell G are then selected based on the start point of the wiring (S15, start section cell selection means 34). This determines the extension direction shown by the arrow in Fig. 11. Here, the start section cell selection means 34 selects section cells so that they have a width (designed cell width) greater than or equal to a predetermined wiring width. As a result, the start section cell has three times the width in the horizontal direction, as shown in Fig. 12.

[0035] Next, the starting point section cell is extended in a direction parallel to the vertical or horizontal line segment, from the starting point section cell to the end point of the wiring, to obtain a first (i=1) cell candidate up to the space region (S16, first candidate cell obtaining means 35). As a result, a first candidate cell is obtained, as shown by hatching in FIG. 13.

[0036] Next, it is detected whether the wiring has reached the end point (S17). If the result is NO, i is incremented by one (S18), and the process returns to step S16. The cell that hits the space area at the shortest distance among the first cell candidates is taken as the starting point, and the direction of the end point in the horizontal direction perpendicular to the vertical direction is taken as the new forward direction, and the cell is extended in the new forward direction until it hits the space area to obtain a second (i=2) cell candidate (S16, second candidate cell acquisition means 36). Here, the first cell candidate hits the space area at the partition cell G, so it is bent and extended in the horizontal line segment direction here. Here, the each-time candidate cell acquisition means (second candidate cell acquisition means 36) selects a partition cell so that it has a width (designed cell width) equal to or greater than a predetermined wiring width. The horizontal line segment direction is set to be equal to or greater than the width of the two partition cells used in this embodiment. As a result, a second candidate cell is obtained as shown by hatching in FIG. 14. When a second candidate cell is obtained, the previous candidate cell, the first candidate cell, is made a confirmed cell (a cell whose width or length does not change).

[0037] Next, it is detected whether the wiring has reached the end point (S17), and if NO, i is incremented by one (S18), and the process returns to step S16. Next, the third (i=3) cell candidate is obtained by taking the cell that hits the space area at the shortest distance among the second cell candidates as the starting point, and extending the cell in the new forward direction to the end point direction perpendicular to the horizontal direction (S16, third candidate cell acquisition means 37). As a result, the third candidate cells are the three divided cells "11" to "13" that extend in the vertical direction as shown in FIG. 15, which have been extended to "k" and hit the space area.

[0038] Thereafter, similar processing is performed, and the fourth candidate cell is shown in FIG. 16, the fifth candidate cell is shown in FIG. 17, the sixth candidate cell is shown in FIG. 18, and the seventh candidate cell is shown in FIG. 19. In this embodiment, the seventh candidate cell reaches the end point. When the candidate cell reaches the end point, the previous candidate cell is set as a confirmed cell (a cell selected as having an appropriate width or length according to the rules of this embodiment) as shown in FIG. 20. After this, the computer performs processing as a final wiring area selection means 39. Note that when the fourth candidate cell shown in FIG. 16 hits the space area, when changing direction and moving vertically, the hit division cell "19" is not used, and the division cell "18" is set as the fourth candidate cell because the width of the division cell "19" is narrow and one division cell "18" has a sufficient width.

[0039] When the start point and the end point are connected by the defined cells in the above manner, the wiring area drawn by the optimum wiring width is selected as the final wiring area within the wiring area generated by the defined cells. Here, the optimum wiring width refers to a wiring width set based on a concept different from the width (design time cell width) that is equal to or greater than the predetermined wiring width used when the starting point partition cell selection means and each time candidate cell acquisition means obtain and select partition cells at the time of design within the wiring area generated by the defined cells. In general, it can be the smallest wiring width among the possible wiring widths.

[0040] Then, in order to select the final wiring area, several candidate wiring areas are created with the optimum wiring width in the wiring area generated by the above-mentioned confirmed cells, and the optimum candidate wiring area is selected as the final wiring area by the area edge method. For example, in the example of FIG. 20, the wiring area is generated by the confirmed cells. As shown in FIG. 21, a candidate wiring area 10A having the optimum wiring width can be created so as to follow the upper boundary of the wiring area, and as shown in FIG. 22, a candidate wiring area 10B having the optimum wiring width can be created so as to follow the lower boundary of the wiring area. For the candidate wiring area 10A and the candidate wiring area 10B, the one with the shortest wiring length is basically selected as the final wiring area by the area edge method. As a result, as shown in FIG. 23, only the candidate wiring area 10A is selected as the final wiring area.

[0041] Next, the area edge method will be described with reference to Figs. 23A, 23B, 23C, 23D, and 23E. As shown in Figs. 23A to 23E, it is assumed that the non-routable area is obtained as the hatched portion IH. The start point S and the end point E are shown in Figs. 23A to 23E. The area in which wiring is possible, including the start point S and the end point E, is extracted as a polygonal shape as the frame W in Fig. 23B. The vertex coordinates of the figure are listed. Note that the vertex refers to the corner of the figure. Next, the distance of the upper route UR (Fig. 23C) connecting the vertex coordinates from the listed start point S to the end point E is recalculated, and the distance of the lower route DR (Fig. 23D) connecting the vertex coordinates from the listed start point S to the end point E is calculated, and an appropriate route is selected after evaluating the route. Here, the appropriate route is assumed to be a route with a short route, a route with a small number of vertices, or a route with a fixed lower route, which can be appropriately set by the operator in advance. Then, by forming a wiring LL from a starting point S to an end point E as shown in FIG. 23E, taking into consideration the wiring width and the like along the route extracted above, the wiring area can be compacted and connected, so that dead space can be minimized and a large free space can be secured.

[0042] FIG. 24 shows a specific example of wiring performed by the area edge method. In the area edge method of this embodiment, when the wiring-unavailable area is obtained as a black part as shown in FIG. 24(a), a NOT operation area of ​​the wiring-unavailable area is generated as a wiring area in a polygonal shape as shown in FIG. 24(b). For example, a candidate wiring area 20A and a candidate wiring area 20B are obtained along the edge (boundary) of this wiring area (FIG. 24(c)). Of course, a large number of candidate wiring areas may be generated between the candidate wiring area 20A and the candidate wiring area 20B. Among these candidate wiring areas, the most suitable one is selected as the final wiring area. The most suitable one may be one with the shortest wiring length. In addition, when there are multiple ones with the shortest wiring length, the one with the fewest number of vertices (number of bends) can be selected as the final wiring area. In the example of FIG. 24, the candidate wiring area 20B is selected as the final wiring area as shown in FIG. 24(d).

[0043] According to the present embodiment described above, it is possible to connect routes that could not be routed using conventional shape-based automatic routing, leading to improved routing quality and design shrink. [Explanation of symbols]

[0044] 10 CPU 10A Candidate wiring area 10B Candidate wiring area 11 Main Memory 12 Bus 13 External memory interface 14 Input Interface 15 Display Interface 16 Network Interfaces 20A candidate wiring area 20B Candidate wiring area 22 Pointing Device 23 External storage device 24 Input Devices 25 Display device 31 Wiring area / non-wiring area information calculation method 32 Matrix division method 33 Partition cell generation means 34 Starting point division cell selection means 35 First candidate cell acquisition method 36 2nd Candidate Cell Acquisition Method 37 3rd Candidate Cell Acquisition Method 38 nth candidate cell acquisition means 39 Final wiring area selection method

Claims

1. a wiring area / non-wiring area information calculation means for calculating wiring area information and non-wiring area information based on size information of existing metal provided in a design target area and size information of wiring to be drawn in; a matrix division means for dividing a wiring area into a matrix and generating rectangular cells; a partition cell generating means for generating vertical and horizontal line segments throughout a design target area based on corners generated in a wiring area by the rectangular cells, thereby generating partition cells of existing wiring, partition cells of spaces, and partition cells of wiring areas; a starting point cell selection means for selecting a starting point cell based on a starting point of wiring; a first candidate cell acquiring means for acquiring a first candidate cell by extending the starting point section cell in a direction parallel to the vertical line segment or the horizontal line segment, the vertical direction being from the starting point section cell to an end point of the wiring, until the starting point section cell abuts on a space region; a second candidate cell acquisition means for acquiring a second cell candidate from among the first cell candidates, which is determined as a starting point from a cell that abuts on the space region at the shortest distance, and which extends the cells in a horizontal direction perpendicular to the vertical direction and toward the end point as a new forward direction, until the cell abuts on the space region; a third candidate cell acquisition means for acquiring a third cell candidate from among the second cell candidates, starting from a cell that abuts on the space region at the shortest distance, and extending the cell in the new forward direction up to the space region by setting a direction of the end point in a vertical direction perpendicular to the horizontal direction as a new forward direction; Similarly, there are provided fourth, fifth, ..., n-th candidate cell acquisition means for acquiring necessary fourth, fifth, ..., n-th (integer) cell candidates, The n-th candidate cell acquisition means acquires n-th candidate cells up to the end point, in accordance with the wiring design apparatus for a semiconductor integrated circuit.

2. 2. The wiring design apparatus for a semiconductor integrated circuit according to claim 1, wherein said starting point partition cell selection means and said each-time candidate cell acquisition means select partition cells having a width (design time cell width) equal to or greater than a predetermined wiring width.

3. 2. The wiring design device for a semiconductor integrated circuit according to claim 1, wherein the size information of an existing metal provided in a design target area is its width and space dimensions, and the size information of a wiring to be drawn in is its width and space dimensions.

4. 2. The wiring design device for a semiconductor integrated circuit according to claim 1, further comprising a final wiring area selection means for generating a confirmed cell by connecting cell candidates from a start point to an end point, and selecting a wiring area drawn with an optimal wiring width as a final wiring area within a wiring area generated by the confirmed cell.

5. 5. The wiring design device for a semiconductor integrated circuit according to claim 4, wherein said final wiring region selection means creates several candidate wiring regions by optimum wiring widths within the wiring area generated by said confirmed cells, and selects an optimum candidate wiring region by an area edge method as the final wiring region.

6. A method for designing wiring for a semiconductor integrated circuit, which is executed by a CPU constituting a wiring design device for a semiconductor integrated circuit, by appropriately reading out programs and data for the operation of the wiring design device for a semiconductor integrated circuit from an external storage device in which the programs and data are stored, into a main memory, and using the programs and data, The CPU, a wiring area / non-wiring area information calculation step of calculating wiring area information and non-wiring area information based on size information of existing metal provided in the design target area and size information of wiring to be drawn in; a matrix division step of dividing a wiring area into a matrix and generating rectangular cells; a partition cell generating step of generating vertical and horizontal line segments throughout the entire design target area based on corners generated in the wiring area by the rectangular cells, thereby generating partition cells of existing wiring, partition cells of spaces, and partition cells of the wiring area; a starting point cell selection step of selecting a starting point cell based on a starting point of wiring; a first candidate cell acquisition step of acquiring a first cell candidate by extending the starting point section cell in a direction parallel to the vertical line segment or the horizontal line segment, the vertical direction being from the starting point section cell to an end point of the wiring, until the starting point section cell hits a space region; a second candidate cell acquisition step of obtaining a second cell candidate from among the first cell candidates, starting from a cell that abuts on the space region at the shortest distance, and extending the cell in the new forward direction until the cell abuts on the space region in a horizontal direction perpendicular to the vertical direction and the direction of the end point as a new forward direction; a third candidate cell acquisition step of obtaining a third cell candidate by extending the cell in the new forward direction from the second cell candidate that is the shortest distance from the starting point to the end point in a vertical direction perpendicular to the horizontal direction, until the cell reaches the space region; Similarly, a fourth, fifth, ..., n-th candidate cell acquisition step is performed to acquire the fourth, fifth, ..., n-th (integer) cell candidates as required. The n-th candidate cell acquisition step is characterized in that the n-th cell candidate is acquired up to the end point.

7. 7. The method for designing wiring for a semiconductor integrated circuit according to claim 6, wherein the starting point partition cell selecting step and the candidate cell obtaining step are executed by the CPU so as to select partition cells having a width (design time cell width) equal to or greater than a predetermined wiring width.

8. 7. The wiring design method for a semiconductor integrated circuit according to claim 6, wherein the size information of an existing metal provided in a design target area is its width and space dimensions, and the size information of a wiring to be drawn in is its width and space dimensions.

9. 7. The method for designing wiring for a semiconductor integrated circuit according to claim 6, further comprising a final wiring area selection step, executed by the CPU, of generating a confirmed cell by connecting cell candidates from a start point to an end point, and selecting, within a wiring area generated by the confirmed cell, a wiring area drawn with an optimal wiring width as a final wiring area.

10. 10. The wiring design method for a semiconductor integrated circuit according to claim 9, wherein in the final wiring region selection step, several candidate wiring regions are created in the wiring area generated by the confirmed cells using an optimal wiring width, and an optimal candidate wiring region is selected as the final wiring region using an area edge method.

11. A computer constituting a wiring design device for a semiconductor integrated circuit, a wiring area / non-wiring area information calculation means for calculating wiring area information and non-wiring area information based on size information of existing metal provided in a design target area and size information of wiring to be drawn in; A matrix division means for dividing a wiring area into a matrix and generating rectangular cells; a partition cell generating means for generating vertical and horizontal line segments throughout the entire design target area based on corners generated in the wiring area by the rectangular cells, thereby generating partition cells of existing wiring, partition cells of spaces, and partition cells of the wiring area; a starting point cell selection means for selecting a starting point cell based on a starting point of wiring; a first candidate cell acquiring means for acquiring a first candidate cell by extending the starting point section cell in a direction parallel to the vertical line segment or the horizontal line segment, the vertical direction being from the starting point section cell to an end point of the wiring, until the starting point section cell abuts on a space region; a second candidate cell acquisition means for acquiring a second cell candidate from among the first cell candidates, which is determined as a starting point from a cell that abuts on the space region at the shortest distance, and which extends the cells in a horizontal direction perpendicular to the vertical direction and toward the end point as a new forward direction, until the cell abuts on the space region; a third candidate cell acquisition means for acquiring a third cell candidate from among the second cell candidates, starting from a cell that abuts on the space region at the shortest distance, and extending the cells in the new forward direction up to the point where the third cell candidate abuts on the space region, the third candidate cell acquisition means defining a direction of the end point in a vertical direction perpendicular to the horizontal direction as a new forward direction; Similarly, a fourth, fifth, ..., nth candidate cell acquisition means acquires necessary fourth, fifth, ..., nth (integer) cell candidates; Function as a a program for designing wiring for a semiconductor integrated circuit, the program causing the computer to function as n-th candidate cell acquisition means for acquiring an n-th candidate cell up to the end point;

12. 12. The program for wiring design of a semiconductor integrated circuit according to claim 11, wherein the computer is made to function as the starting point partition cell selection means and the each-time candidate cell acquisition means to select partition cells having a width equal to or greater than a predetermined wiring width (design time cell width).

13. 12. The wiring design program for a semiconductor integrated circuit according to claim 11, wherein the size information of an existing metal provided in a design target area is its width and space dimensions, and the size information of a wiring to be drawn in is its width and space dimensions.

14. The computer further comprises:

12. The program for wiring design of a semiconductor integrated circuit according to claim 11, characterized in that the program functions as a final wiring area selection means for generating a confirmed cell by connecting cell candidates from a start point to an end point, and selecting a wiring area drawn with an optimal wiring width as a final wiring area within a wiring area generated by the confirmed cell.

15. 15. The program for wiring design of a semiconductor integrated circuit according to claim 14, characterized in that the computer is made to function as the final wiring region selection means by creating several candidate wiring regions with optimal wiring widths within the wiring area generated by the confirmed cells, and selecting an optimal candidate wiring region as the final wiring region by an area edge method.

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