Self-assembled monolayers formed on quantum devices

Abstract

A device, method, or computer-implemented method, or combination thereof, is provided that can facilitate forming a self-assembled monolayer on a quantum device. According to one embodiment, the device can include qubits formed on a substrate. The device can further include a self-assembled monolayer formed on the qubits.

Description

[Technical field]

[0001] The subject disclosure relates to self assembled monolayers formed on integrated circuits and methods of forming the self assembled monolayers. More particularly, the subject disclosure relates to self assembled monolayers formed on quantum devices and methods of forming the self assembled monolayers. Summary of the Invention

[0002] The following presents a summary in order to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements or to limit the scope of particular embodiments or the claims. Its sole purpose is to present ideas in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, devices and / or methods (e.g., computer-implemented methods) that facilitate forming a self-assembled monolayer on a quantum device are described.

[0003] According to one embodiment, a device can include a qubit formed on a substrate. The device can further include a self-assembled monolayer formed on the qubit. An advantage of such a device is that it can facilitate at least one of improved coherence time and improved lifetime of the qubit.

[0004] In some embodiments, a self-assembled monolayer is formed on at least one of the qubits and the substrate to prevent oxidation of the qubits and / or the substrate. An advantage of such a device is that it can facilitate at least one of improved coherence time and improved lifetime of the qubits.

[0005] According to one embodiment, the method can include removing one or more oxide layers from qubits formed on a substrate. The method can further include depositing a self-assembled monolayer on the qubits. An advantage of such a method is that it can be implemented to facilitate at least one of improving the coherence time and improving the lifetime of the qubits.

[0006] In some embodiments, the method may further include removing at least one oxide layer from at least one of the qubits and the substrate, and depositing a self-assembled monolayer on at least one of the qubits or the substrate to prevent oxidation of at least one of the qubits and the substrate. An advantage of such a method is that it may be implemented to facilitate at least one of improving the coherence time and improving the lifetime of the qubits.

[0007] According to one embodiment, a device can include one or more superconducting components formed on a substrate. The device can further include a self-assembled monolayer formed on the one or more superconducting components. An advantage of such a device is that it can facilitate at least one of an improved coherence time and an improved lifetime of the one or more superconducting components.

[0008] In some embodiments, a self-assembled monolayer is formed on at least one of the superconducting component(s) and the substrate to prevent oxidation of at least one of the superconducting component(s) and the substrate. An advantage of such a device is that it can facilitate at least one of an improved coherence time and an improved lifetime of the superconducting component(s).

[0009] According to one embodiment, the method can include removing one or more oxide layers from one or more superconducting components formed on a substrate. The method can further include depositing a self-assembled monolayer on the one or more superconducting components. An advantage of such a method is that it can be implemented to facilitate at least one of improving the coherence time and improving the lifetime of the one or more superconducting components.

[0010] In some embodiments, the method may further include removing at least one oxide layer from at least one of the one or more superconducting components and the substrate, and depositing a self-assembled monolayer on at least one of the one or more superconducting components and the substrate using at least one of a solution-based self-assembled monolayer deposition process and a vapor-phase-based self-assembled monolayer deposition process. An advantage of such a method is that it may be implemented to facilitate at least one of improving the coherence time and improving the lifetime of the superconducting components.

[0011] According to one embodiment, a device can include qubits formed on a bump-bonded device substrate. The device can further include a self-assembled monolayer formed on the qubits. An advantage of such a device is that it can facilitate at least one of improved coherence time and improved lifetime of the qubits.

[0012] In some embodiments, a self-assembled monolayer is formed on at least one of the qubits and the substrate to prevent oxidation of the qubits and / or the substrate. An advantage of such a device is that it can facilitate at least one of improved coherence time and improved lifetime of the qubits.

[0013] This patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication containing color drawing(s) will be provided by the U.S. Patent and Trademark Office upon request and payment of the necessary fee. [Brief description of the drawings]

[0014] [Figure 1A] FIG. 1 is a cross-sectional side view of an exemplary, non-limiting device that may include one or more oxide layers on a substrate and / or one or more superconducting components formed on the substrate, according to one or more embodiments described herein. [Figure 1B] FIG. 1B is a cross-sectional side view of the exemplary, non-limiting device of FIG. 1A after removal of one or more oxide layers from one or more surfaces according to one or more embodiments described herein. [Figure 1C] FIG. 1C is a cross-sectional side view of the exemplary, non-limiting device of FIG. 1B after forming one or more self-assembled monolayers on one or more surfaces of the substrate and / or one or more superconducting components. [Diagram 2] FIG. 1C is a cross-sectional side view of the exemplary, non-limiting device of FIG. 1B after forming one or more self-assembled monolayers on one or more surfaces of the substrate and / or one or more superconducting components. [Figure 3A] FIG. 1 is a cross-sectional side view of an exemplary, non-limiting device that may include a bump-bonded device having one or more oxide layers on one or more substrates and / or on one or more superconducting components formed on one or more substrates according to one or more embodiments described herein. [Figure 3B] FIG. 3B is a cross-sectional side view of the exemplary, non-limiting device of FIG. 3A after forming one or more self-assembled monolayers on one or more surfaces of one or more substrates and / or one or more superconducting components formed on one or more substrates, according to one or more embodiments described herein. [Figure 4] FIG. 1 illustrates an exemplary, non-limiting method that can facilitate H-termination of a silicon (Si) substrate surface and the formation of one or more self-assembled monolayers on such a surface, according to one or more embodiments described herein. [Diagram 5] 1 is a flow diagram of an exemplary, non-limiting method that can facilitate forming a self-assembled monolayer on a quantum device according to one or more embodiments described herein. [Figure 6A] FIG. 1 illustrates exemplary, non-limiting information that may include experimental data from the implementation of a quantum device including a self-assembled monolayer formed thereon, in accordance with one or more embodiments described herein. [Figure 6B] FIG. 1 illustrates exemplary, non-limiting information that may include experimental data from the implementation of a quantum device including a self-assembled monolayer formed thereon, in accordance with one or more embodiments described herein. [Figure 6C] FIG. 1 illustrates exemplary, non-limiting information that may include experimental data from the implementation of a quantum device including a self-assembled monolayer formed thereon, in accordance with one or more embodiments described herein. [Figure 7A] FIG. 1 illustrates exemplary, non-limiting information that may include experimental data from implementation of a quantum device including an H-terminated surface after removal of an oxide layer, according to one or more embodiments described herein. [Figure 7B] FIG. 1 illustrates exemplary, non-limiting information that may include experimental data from the implementation of a quantum device including a self-assembled monolayer formed thereon, in accordance with one or more embodiments described herein. [Figure 7C] FIG. 1 illustrates exemplary, non-limiting information that may include experimental data from the implementation of a quantum device including a self-assembled monolayer formed thereon, in accordance with one or more embodiments described herein. [Figure 8]1 is a flow chart of an exemplary, non-limiting computer-implemented method that can facilitate forming a self-assembled monolayer on a quantum device, according to one or more embodiments described herein. [Figure 9] 1 is a flow chart of an exemplary, non-limiting computer-implemented method that can facilitate forming a self-assembled monolayer on a quantum device, according to one or more embodiments described herein. [Figure 10] FIG. 1 is a block diagram of an exemplary non-limiting operating environment capable of facilitating one or more embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The following detailed description is for illustrative purposes only, and is not intended to limit the embodiments or the application or uses of the embodiments, or both, nor is it intended to be bound by any express or implied information presented in the Background or Summary or Detailed Description above.

[0016] One or more embodiments will now be described with reference to the drawings. The same reference numerals are used throughout to refer to the same elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more complete understanding of one or more embodiments. However, it will be apparent that in various cases one or more embodiments may be practiced without those specific details. It should be noted that the drawings in this application are provided for illustrative purposes only, and therefore the drawings are not drawn to scale.

[0017] Quantum processors based on superconducting quantum bits (qubits) may consist of Josephson junctions of aluminum (Al), aluminum oxide (Al2O3) and aluminum (Al) stacks (Al / Al2O3 / Al stacks). In some embodiments, these Josephson junctions are connected to one or more superconducting components, e.g., niobium (Nb) resonators, deposited on a highly resistive substrate, e.g., silicon (Si). With appropriate device architecture and design, the wavefunction lifetime in the qubit has been improved in recent years to hundreds of microseconds, but further increases in the wavefunction lifetime have not been realized. The wavefunction itself oscillates at radio frequencies (RF) of about 5 gigahertz (~5 GHz). At this frequency, the absorption of RF photons inside the oxide formed on the substrate and / or one or more superconducting components, both during device fabrication and during extended exposure to air, can have a significant impact on the lifetime of the qubit.

[0018] It has been experimentally shown that silicon dioxide (SiO2) formed on the surface of a silicon (Si) substrate and niobium monoxide (NbO), niobium dioxide (NbO2) or niobium pentoxide (Nb2O5) or combinations thereof formed on niobium (Nb) resonator lines both absorb strongly in the RF regime. Oxides (e.g., silicon dioxide (SiO2)) on silicon (Si) substrates can be removed by treatment with a dilute hydrogen fluoride (HF) etchant (dilute HF etchant) that removes the oxide and H-terminates the surface, while niobium oxides such as niobium pentoxide (Nb2O5), niobium dioxide (NbO2) or niobium monoxide (NbO) or combinations thereof can also be removed by this etch, but niobium oxides rapidly re-grow in ambient air.

[0019] A challenge with existing quantum devices (e.g., quantum processors, quantum chips, superconducting circuits integrated on a substrate, bump-bonded quantum devices, etc.) or manufacturing processes that facilitate the manufacture of such quantum devices, or both, is that they do not remove such oxides from the quantum device or prevent such oxides from reforming on the quantum device (e.g., due to air exposure during manufacture). In view of the above-mentioned challenges with existing technologies (e.g., quantum devices and / or manufacturing processes) that do not remove such oxides from the surface of the quantum device or prevent such oxides from reforming on the quantum device, the present disclosure can be implemented to create a solution to this challenge in the form of a device or method (e.g., a computer-implemented method) or both that can provide one or more self-assembled monolayers formed on one or more superconducting components (e.g., qubits, resonators, capacitors, etc.) of a quantum device (e.g., a quantum chip, a bump-bonded device including qubits, a superconducting circuit including qubits integrated on a substrate, etc.). An advantage of such a device or method or both is that it can facilitate at least one of an improved coherence time and an improved lifetime of one or more superconducting components (e.g., qubits).

[0020] In some embodiments, the one or more self-assembled monolayers may be formed on one or more superconducting components (e.g., qubits, resonators, capacitors, etc.) of a quantum device (e.g., a quantum chip, a bump-bonded device including qubits, a superconducting circuit including qubits integrated on a substrate, etc.) and on a substrate on which the one or more superconducting components are formed (e.g., integrated). An advantage of such devices and / or methods is that they may facilitate at least one of improved coherence time and improved lifetime of the one or more superconducting components (e.g., qubits).

[0021] 1A-5, 8 or 9, or combinations thereof, illustrate exemplary, non-limiting, multi-step fabrication sequences that may be implemented to fabricate one or more embodiments of the subject disclosure described herein or illustrated in the figures, or described herein and illustrated in the figures. For example, the non-limiting multi-step fabrication sequence illustrated in FIGS. 1A-1C may be implemented to fabricate device 100c, which may include a semiconductor superconducting device including one or more components (e.g., a silicon (Si) substrate, a superconducting component, a qubit, a resonator, a capacitor, etc.) having one or more self-assembled monolayers formed thereon. In another example, the non-limiting multi-step fabrication sequence illustrated in FIGS. 1A, 1B, and 2 may be implemented to fabricate device 200, which may include an exemplary, non-limiting alternative embodiment of device 100c. 1A, 1B, 3A, and 3B can be performed to fabricate device 300a and / or device 300b, where device 300a includes an exemplary, non-limiting, alternative embodiment of device 100b, and / or device 300b includes an exemplary, non-limiting, alternative embodiment of device 100c and / or device 200. For example, the non-limiting, multi-step fabrication sequence illustrated in FIGs. 1A, 1B, 3A, and 3B can be performed to fabricate device 300a and / or device 300b, where such devices can include bump-bonded devices that include one or more semiconductor components (e.g., silicon (Si) substrates) and superconducting components (e.g., qubits, resonators, capacitors, etc.) having one or more self-assembled monolayers formed thereon.

[0022] In one example, devices 100c, 200, 300a, or 300b, or combinations thereof, can be implemented in a quantum computing device (e.g., a quantum processor, a quantum computer, etc.), where such devices can include one or more superconducting components that can be implemented in such quantum computing devices. For example, devices 100c, 200, 300a, or 300b, or combinations thereof, can be implemented in a quantum computing device (e.g., a quantum processor, a quantum computer, etc.), where such devices can include one or more qubits or resonators (e.g., bus resonators, transmission resonators, etc.), or both, that can be implemented in such quantum computing devices.

[0023] As described below with reference to Figures 1A-5, 8 or 9, or combinations thereof, fabrication of various embodiments of the subject disclosure described herein or illustrated in the figures, or described herein and illustrated in the figures (e.g., devices 100c, 200, 300a or 300b, or combinations thereof) can include, for example, a multi-step sequence of photolithography steps or chemical processing steps, or a multi-step sequence of photolithography steps and chemical processing steps, that facilitate the progressive formation of an electronics-based system, device, component or circuit, or combinations thereof, in a semiconductor superconducting device (e.g., an integrated circuit). For example, various embodiments of the subject disclosure described herein or illustrated in the figures, or described herein and illustrated in the figures (e.g., devices 100c, 200, 300a, or 300b, or combinations thereof) may be used in a variety of applications, including, but not limited to, photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive photoresist, negative photoresist, hybrid photoresist, etc.), etching techniques (e.g., reactive ion etching (RI E), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), deposition techniques, sputtering techniques, plasma ashing techniques, thermal treatments (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, etc.), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (CMP), backgrinding techniques, or another technique for manufacturing integrated circuits, or a combination thereof.

[0024] As described below with reference to Figures 1A-5, 8 or 9, or combinations thereof, various embodiments of the subject disclosure described herein or illustrated in the figures, or described and illustrated herein (e.g., devices 100c, 200, 300a or 300b, or combinations thereof) can be fabricated using a variety of materials. For example, various embodiments of the subject disclosure described herein or illustrated in the figures, or described and illustrated herein (e.g., devices 100c, 200, 300a or 300b, or combinations thereof) can be fabricated using materials from one or more different material classes, including, but not limited to, conductive materials, semiconductor materials, superconducting materials, dielectric materials, polymeric materials, organic materials, inorganic materials, non-conductive materials or other materials, or combinations thereof, that can be utilized with one or more of the techniques described above to fabricate integrated circuits.

[0025] When an element, such as a layer (also called a film), region, or substrate, or combinations thereof, is described as being "on" or "on" another element, it will be understood that the element can be directly on the other element, or there can be intervening elements. In contrast, when an element is described as being "directly on" or "directly on" another element, there are no intervening elements. When an element is described as being "below" or "under" another element, it will also be understood that the element can be directly below or under the other element, or there can be intervening elements. In contrast, when an element is described as being "directly below" or "directly under" another element, there are no intervening elements. It will also be understood that when an element is described as being "coupled" to another element, the coupling may describe one or more different types of coupling, including, but not limited to, a chemical coupling, a communicative coupling, an electrical coupling, a physical coupling, an operable coupling, an optical coupling, a thermal coupling, or another type of coupling, or a combination thereof.

[0026] 1A illustrates a cross-sectional side view of an exemplary, non-limiting device 100a that may include one or more oxide layers on a substrate and / or one or more superconducting components formed on the substrate, according to one or more embodiments described herein. As described below, such one or more superconducting components may be formed on the substrate of device 100a.

[0027] The device 100a can include a substrate 102. The substrate 102 can include any material having semiconducting properties, including, but not limited to, silicon (Si), sapphire (e.g., aluminum oxide (Al2O3)), silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), silicon carbide (SiC), germanium (Ge) alloy, III / V compound semiconductor, II / VI compound semiconductor, or another material, or a combination thereof. In some embodiments, the substrate 102 can include a layered semiconductor, including, but not limited to, silicon / silicon-germanium (Si / SiGe), silicon / silicon carbide (Si / SiC), silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI), or another layered semiconductor, or a combination thereof. In one example, the substrate 102 can include a silicon (Si) substrate.

[0028] The device 100a may further include one or more superconducting components 104 that may be formed on the substrate 102. Such superconducting components 104 may be formed on the substrate 102 using one or more of the photolithography, patterning, photoresist, or material deposition techniques (e.g., lithography patterning processes, evaporation techniques, sputtering techniques, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), etc.) explicitly described above, or combinations thereof. The superconducting components 104 may be formed on the substrate 102 using a superconducting material, such as, for example, niobium (Nb) or another superconducting material, or both. Superconducting components 104 may be formed on substrate 102 to form, for example, one or more qubits, one or more components of a qubit, or one or more components of a superconducting circuit that can be coupled to such qubits, such as, for example, one or more wires, electrodes, capacitors, resonators (e.g., a bus resonator, a transmission resonator, etc.), tuning gates, or another superconducting component, or a combination thereof.

[0029] In one example, the device 100a can include a qubit device and the substrate 102 can include a silicon (Si) substrate on which a niobium (Nb) superconducting component 104 is formed. In this example, one or more surfaces of the device 100a can be oxidized by air exposure, such as air exposure during processing. For example, the air exposure can form a first oxide layer 106, including, for example, silicon dioxide (SiO2), on one or more surfaces of the substrate 102. In another example, the air exposure can form a second oxide layer 108, including, for example, niobium monoxide (NbO), niobium dioxide (NbO2), or niobium pentoxide (Nb2O5), or combinations thereof, on one or more surfaces of the superconducting component 104. As described below with reference to FIG. 1B, the first oxide layer 106 or the second oxide layer 108, or both, can be removed using an etching process.

[0030] 1B illustrates a cross-sectional side view of the exemplary, non-limiting device 100a of FIG. 1A after removal of one or more oxide layers from one or more surfaces according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0031] Device 100b may include an exemplary, non-limiting alternative embodiment of device 100a after removal of one or more oxide layers from one or more surfaces of device 100a. For example, as shown in FIG. 1B, first oxide layer 106 or second oxide layer 108 or both may be removed from one or more surfaces of substrate 102 or superconducting component 104 or both, respectively. For example, first oxide layer 106 may include silicon dioxide (SiO2), which may be removed from one or more surfaces (e.g., top surface) of substrate 102 including a silicon (Si) substrate. In another example, second oxide layer 108 may include niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5) or other suboxides or combinations thereof, which may be removed from one or more surfaces (e.g., top surface) of superconducting component 104 including a niobium (Nb) superconducting component such as a niobium (Nb) resonator.

[0032] In the examples described above, an etching process may be used to remove the first oxide layer 106 or the second oxide layer 108, or both, from such surfaces of such components. For example, a dilute etchant, such as a dilute hydrofluoric (HF) etchant (dilute HF etchant) including a non-aqueous dilute hydrofluoric etchant with trifluoroacetic acid (CF3CO2H) or another dilute etchant or both, may be used to remove the first oxide layer 106 or the second oxide layer 108, or both, from one or more surfaces of the substrate 102 or the superconducting component 104, or both. In one example, a dilute etchant solution (e.g., an aqueous hydrofluoric (HF) solution) including a dilute etchant ranging from about 1 percent (%) to about 10% aqueous hydrofluoric (HF) may be used to remove the first oxide layer 106 or the second oxide layer 108, or both, from one or more surfaces of the substrate 102 or the superconducting component 104, or both. In another example, a wet etching solution including a buffered etchant including ammonium fluoride (NH4F) may be used to remove the first oxide layer 106 or the second oxide layer 108, or both, from one or more surfaces of the substrate 102 and / or the superconducting component 104. In these examples, the substrate 102 may then be rinsed with deionized water to remove any physically absorbed fluoride.

[0033] A dilute etchant (such as a non-aqueous dilute HF etchant with trifluoroacetic acid (CF3CO2H)) may be used to remove the first oxide layer 106 or the second oxide layer 108, or both, from one or more surfaces of the substrate 102 or the superconducting component 104, or both, respectively, to further hydrogen terminate (H-terminated) the surface of the substrate 102 (e.g., as shown by the representation of three "H" letters on the substrate 102 in FIG. 1B). For example, in an embodiment in which the substrate 102 comprises a silicon (Si) substrate, the first oxide layer 106 may be removed from a surface (e.g., top surface) of the substrate 102 using such a dilute etchant as set forth above to produce an H-terminated silicon (Si) surface, which is a chemically passivated silicon (Si) surface of the substrate 102 having silicon (Si) atoms covalently bonded to hydrogen (H) atoms.

[0034] In one example, a buffered etchant including aqueous hydrogen fluoride (HF) and / or ammonium fluoride (NH4F) at various concentrations as described above may be used to remove the second oxide layer 108 on one or more surfaces of the superconducting component 104. In another example, the second oxide layer 108 on one or more surfaces of the superconducting component 104 may be removed by performing a dry etching process in a vacuum chamber using a fluoride gas including, but not limited to, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6) or another fluoride gas or combinations thereof. In another example, a combination of the wet etching process described above for removing the first oxide layer 106 (e.g., silicon dioxide (SiO2)) from such surface of the substrate 102 and a vacuum chamber annealing process at elevated temperatures for removing the second oxide layer 108 (e.g., niobium dioxide (NbO2), niobium pentoxide (Nb2O5) or other suboxides or combinations thereof) from such surface of the superconducting component 104 may be used to remove the first oxide layer 106 or the second oxide layer 108, or both, of one or more surfaces of the substrate 102 or the superconducting component 104, respectively. For example, the vacuum chamber annealing process may use temperatures ranging from about 250 degrees Celsius (°C) to about 400°C. In some embodiments, the vacuum chamber annealing process may use temperatures of at least 250° C. and / or temperatures greater than 400° C. to remove the second oxide layer 108 (e.g., niobium dioxide (NbO2), niobium pentoxide (Nb2O5) or other suboxides or combinations thereof) from such surfaces of the superconducting component 104.

[0035] The dilute etchants described above (e.g., a non-aqueous dilute HF etchant with trifluoroacetic acid (CF3CO2H) or the like) can be used to remove the first oxide layer 106 and / or the second oxide layer 108 from one or more surfaces of the substrate 102 and / or the superconducting component 104, respectively, while the second oxide layer 108, which may include one or more niobium oxides (e.g., niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5) or other suboxides or combinations thereof), can rapidly regrow in ambient air. For example, the second oxide layer 108 shown in FIG. 1B may include a new oxide layer (e.g., niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5) or other suboxides or combinations thereof) that has grown rapidly on the superconducting component 104 after a similar oxide layer has been removed from the device 100a, e.g., using a dilute etchant as described above. To prevent re-oxidation of one or more surfaces (e.g., H-terminated surfaces) of the substrate 102 and / or one or more surfaces of the superconducting component 104, such surfaces may be reacted with one or more reactive organic compounds to form one or more self-assembled monolayers (also referred to as self-assembled monolayers, self-limiting monolayers, etc.) on such surfaces, as described below with reference to FIG. 1C.

[0036] 1C illustrates a cross-sectional side view of the exemplary, non-limiting device 100b of FIG. 1B after forming one or more self-assembled monolayers on one or more surfaces of the substrate and / or one or more superconducting components. For the sake of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0037] Device 100c may include an exemplary, non-limiting alternative embodiment of device 100b after forming one or more self-assembled monolayers on one or more surfaces of substrate 102 or superconducting component 104, or both. For example, device 100c may include an exemplary, non-limiting alternative embodiment of device 100b after forming one or more self-assembled monolayers on one or more surfaces of substrate 102 or superconducting component 104, or both, using a vapor-phase-based self-assembled monolayer deposition process described below.

[0038] To prevent reoxidation of one or more H-terminated surfaces of the substrate 102 (e.g., hydrogenated silicon (Si) surfaces) and / or one or more surfaces of the superconducting component 104 (e.g., surfaces of one or more niobium (Nb) superconducting components), the surfaces may be reacted with a reactive organic compound to form, by covalent bonding, one or more self-assembled monolayers (also referred to as self-limiting monolayers) on such surfaces. Forming a self-assembled monolayer on such surfaces may further remove any dangling bonds that are vehicles for reoxidation at ambient conditions, and may stabilize or encapsulate (e.g., seal) or stabilize and encapsulate (e.g., seal) such surfaces to prevent regrowth of one or more of the oxides described above. It should be appreciated that such self-assembled monolayers have properties that include, but are not limited to, having strong silicon-carbon (SiC) bonds that do not dissociate at temperatures below about 300 degrees Celsius (° C.), not hydrolyzing or oxidizing under ambient conditions, or being hydrophobic, or a combination thereof.

[0039] As will be described below, in embodiments in which substrate 102 comprises a silicon (Si) substrate and superconducting component 104 comprises a niobium (Nb) superconducting component, such self-assembled monolayers can be applied to one or more surfaces of substrate 102 (e.g., silicon (Si) surfaces) and / or one or more surfaces of superconducting component 104 (e.g., surfaces containing niobium oxide remaining after etching) using a solution-based deposition process or a gas phase deposition process (also referred to as a vapor phase deposition process). Depending on the particular chemistry of each such surface or surfaces (e.g., silicon (Si) or niobium (Nb)), the self-assembled monolayer reacts with the appropriate surface.

[0040] In one example, one or more etched surfaces of the substrate 102 of the device 100b (e.g., surfaces comprising hydrogenated silicon) and / or one or more etched surfaces of the superconducting component 104 (e.g., surfaces comprising niobium oxide) can be reacted with one or more reactive organic compounds at moderate temperatures (e.g., temperatures ranging from about 120° C. to about 200° C.) to form covalently bonded self-assembled monolayers on such surfaces. In another example, one or more etched surfaces of the substrate 102 of the device 100b (e.g., surfaces comprising hydrogenated silicon) and / or one or more etched surfaces of the superconducting component 104 (e.g., surfaces comprising niobium oxide) can be reacted with one or more reactive organic compounds using ultraviolet radiation to form covalently bonded self-assembled monolayers on such surfaces. The one or more reactive organic compounds according to one or more embodiments of the subject disclosure described herein can include, but are not limited to, an alkyne (e.g., a 1-alkyne), an alkene (e.g., a 1-alkene), an alcohol, a thiol, or another reactive organic compound, or a combination thereof.

[0041] The chain length of such reactive organic compounds as specified above can range, for example, from 1 to 18 carbon (C) atoms. Of the reactive organic compounds specified above, only thiols can react with hydrogenated silicon (Si) bearing surfaces (e.g., H-terminated surfaces of substrate 102) and niobium oxide bearing surfaces that may remain after etching (e.g., surfaces of superconducting component 104 having niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5) or other suboxides or combinations thereof). The remaining reactive organic compounds specified above (e.g., alkynes, alkenes and alcohols) can react only with hydrogenated silicon (Si) bearing surfaces to form self-assembled monolayers having silicon-carbon (Si-C) or silicon-oxygen (Si-O) bonds between the surfaces and long-chain hydrocarbons. The solvents specified above can have boiling points higher than the heating temperature used for bond formation and can be inert to both the surfaces and the reactive organic compounds used for self-assembly.

[0042] 1C, in an embodiment in which the substrate 102 comprises a silicon (Si) substrate and the superconducting component 104 comprises a niobium (Nb) superconducting component, the formation of one or more self-assembled monolayers on one or more surfaces of the substrate 102 (e.g., a silicon (Si) surface) or one or more surfaces of the superconducting component 104 (e.g., a surface comprising niobium oxide remaining after etching), or both, can be achieved using a vapor phase deposition process (e.g., a vapor phase-based self-assembled monolayer deposition process). For example, as shown in FIG. 1C, a vapor 110 comprising perfluorodecene (PFD) can be applied to such surfaces of the substrate 102 or superconducting component 104, or both, of device 100b to form a long-chain reactive organic compound (R 2 O 3 in FIG. 1C ) on one or more surfaces of device 100c. fFor example, to form such a self-assembled monolayer, the device 100b having an etched surface of the substrate 102 and / or superconducting component 104 can be quickly transferred (e.g., after etching as described above) to a vacuum chamber and the substrate 102 heated to a moderately high temperature (e.g., a temperature ranging from about 100° C. to about 180° C.) while the device 100b is exposed to a vapor 110 of one or more of the reactive organic materials identified above.

[0043] 2 illustrates a cross-sectional side view of the exemplary, non-limiting device 100b of FIG. 1B after forming one or more self-assembled monolayers on one or more surfaces of the substrate and / or one or more superconducting components. For the sake of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0044] Device 200 may include an exemplary, non-limiting alternative embodiment of device 100b after one or more self-assembled monolayers have been formed on one or more surfaces of substrate 102 or superconducting component 104, or both. For example, device 200 may include an exemplary, non-limiting alternative embodiment of device 100b after one or more self-assembled monolayers have been formed on one or more surfaces of substrate 102 or superconducting component 104, or both, using a solution-based self-assembled monolayer deposition process described below.

[0045] Based on the removal of the first oxide layer 106 and / or the second oxide layer 108 from the device 100b as described above, and then rinsing and drying the device 100b under a stream of nitrogen (N), the device 100b can be immersed in a solution 202 containing one or more of the reactive organic compounds identified above dissolved in a solvent. Based on the immersion of the device 100b in the solution 202, the device 100b can be heated to a moderately high temperature in the range of about 100° C. to about 140° C. under a nitrogen (N) atmosphere to react with the organic compounds (R 2 in FIG. 2 ). f ) to the etched surface of device 100b, thereby forming device 200 as shown in FIG.

[0046] 3A illustrates a cross-sectional side view of an exemplary, non-limiting device 300a that may include a bump-bonded device having one or more oxide layers on one or more substrates and / or on one or more superconducting components formed on one or more substrates according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0047] Device 300a may include exemplary, non-limiting alternative embodiments of device 100a and / or device 100b after further extending device 100a into a bump-bonded device and removing one or more oxide layers from device 300a. For example, device 300a may include exemplary, non-limiting alternative embodiments of device 100a and / or device 100b after further extending device 100a into a bump-bonded device by bonding two substrates 102 with bumps 302 (e.g., solder bumps) using a bump bonding process (e.g., a flip chip process) as shown in FIG. 3A and further applying a steam etchant to device 300a to remove one or more oxide layers (e.g., silicon dioxide (SiO2), niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5), etc.) from device 300a.

[0048] The substrate 102 of the device 300a may include a silicon (Si) substrate having one or more superconducting components 104 (not shown in FIGS. 3A and 3B) formed thereon, such superconducting components 104 may be formed on such substrate 102 as described above with reference to FIG. 1A prior to bonding the substrate 102 with bumps 302 using a bump bonding process. As described above with reference to FIG. 1A, one or more surfaces of the substrate 102 and / or superconducting components 104 may each have a first oxide layer 106 and / or a second oxide layer 108 (not shown in FIGS. 3A and 3B) formed thereon by air exposure of such surfaces. As shown in FIG. 3A, a steam etchant 304 may be applied to the device 300a to remove the first oxide layer 106 and / or the second oxide layer 108. For example, the vapor etchant 304 may include a vapor hydrogen fluoride (HF) etchant that may be applied to the device 300a in a manner to penetrate spaces between the substrates 102 or between the bumps 302 or between the substrate 102 and the bumps 302 that cannot be reached by solution deposition.

[0049] 3B illustrates a cross-sectional side view of the exemplary, non-limiting device 300a of FIG. 3A after forming one or more self-assembled monolayers on one or more surfaces of one or more substrates and / or one or more superconducting components formed on one or more substrates according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0050] Device 300b may include an exemplary, non-limiting alternative embodiment of device 300a after forming one or more self-assembled monolayers (not shown in FIG. 3B) on one or more surfaces of substrate 102 or superconducting component 104 or both. In one example, device 300b may include an exemplary, non-limiting alternative embodiment of device 300a after forming one or more self-assembled monolayers on one or more surfaces of substrate 102 or superconducting component 104 or both using a vapor-phase based self-assembled monolayer deposition process. For example, as shown in FIG. 3B, a vapor 110 including perfluorodecene (PFD) may be applied to such surfaces of substrate 102 or superconducting component 104 or both of device 300b to facilitate self-assembly of long-chain reactive organic compounds on such surfaces of device 300b as described above with reference to FIG. 1C. For example, to form such a self-assembled monolayer, the device 300a having an etched surface of the substrate 102 and / or superconducting component 104 can be quickly transferred (e.g., after etching as described above) to a vacuum chamber and the substrate 102 heated to a moderately high temperature (e.g., a temperature ranging from about 100° C. to about 180° C.) while exposing the device 300a to a vapor 110 of one or more of the reactive organic materials identified above. In these examples, the vapor 110 (e.g., vapor PFD) can be applied to the device 300b in such a manner that it penetrates into spaces between the substrates 102 or between the bumps 302 or between the substrate 102 and the bumps 302 that cannot be reached by solution deposition.

[0051] 4 illustrates an exemplary, non-limiting method 400 that can facilitate H-termination of a silicon (Si) substrate surface and the formation of one or more self-assembled monolayers on such surface, according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0052] 4 may include a method of H-terminating a silicon (Si) surface of a substrate 102 that includes a silicon (Si) substrate. For example, the method 400 may include H-terminating a silicon (Si) surface of a substrate 102 that includes a silicon (Si) substrate using a dilute HF etchant as described above with reference to FIGS. 1A and 1B.

[0053] 4 may further include depositing a self-assembled monolayer (e.g., after etching as described above) on the H-terminated silicon (Si) surface of the substrate 102. For example, the method 400 may include depositing a self-assembled monolayer (e.g., a self-assembled fluorinated alkene, perfluorodecene (PFD), etc.) on the H-terminated silicon (Si) surface of the substrate 102 (e.g., after etching as described above) using a vapor-phase based self-assembled monolayer deposition process (e.g., using vapor 110), as described above with reference to FIGS.

[0054] 5 illustrates a flow diagram of an exemplary, non-limiting method 500 that can facilitate forming a self-assembled monolayer on a quantum device according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0055] At 502, the method 500 may include starting with a qubit substrate having a pattern of oxidized silicon (Si) and niobium (Nb). For example, at 502, the method 500 may include starting with a device, such as device 100a or device 300a, or both, described above with reference to Figures 1A and 3A, respectively, such device may include a substrate 102 (e.g., a silicon (Si) substrate) or a superconducting component 104 (e.g., a niobium (Nb) superconducting component) or both, with a first oxide layer 106 (e.g., silicon dioxide (SiO2)) or a second oxide layer 108 (e.g., niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5) or other suboxides or combinations thereof) or both formed thereon, respectively.

[0056] At 504, the method 500 may include treating with an etchant to remove the oxide, for example using a non-aqueous dilute HF etchant with trifluoroacetic acid (CF3CO2H). For example, as described above with reference to Figures 1A, 1B and 3A, the device 100a or the device 300a or both may be treated with a non-aqueous dilute HF etchant with trifluoroacetic acid (CF3CO2H) to remove the first oxide layer 106 and / or the second oxide layer 108 from one or more surfaces of such devices and / or to H-terminate the silicon (Si) surface of the substrate 102.

[0057] At 506a, the method 500 may include depositing a self-assembled monolayer (SAM) on the H-terminated silicon (Si) surface by solution deposition. For example, as described above with reference to FIG. 2, one or more self-assembled monolayers may be formed (e.g., deposited, assembled, grown, etc.) on one or more surfaces of the device 100b using, for example, a solution-based self-assembled monolayer deposition process (e.g., a solution 202 of one or more of the reactive organic compounds identified above in a solvent).

[0058] At 506b, method 500 can include depositing a self-assembled monolayer (SAM) on the H-terminated silicon (Si) surface by vapor phase deposition. For example, as described above with reference to Figures 1B, 1C, 3A and 3B, one or more self-assembled monolayers can be formed (e.g., deposited, assembled, grown, etc.) on device 100b or device 300a or both using, for example, a vapor-phase-based self-assembled monolayer deposition process (e.g., vapor 110 including, for example, PFD, one or more of the reactive organic materials identified above with respect to Figure 1C, etc.).

[0059] At 508a, the method 500 can include repeating the process at the niobium (Nb) surface using a thiol-based self-assembled monolayer (SAM). For example, with reference to FIG. 2, the method 500 can include repeating the deposition step of 506a at 508a, such as by depositing (e.g., forming, assembling, growing, etc.) a thiol-based self-assembled monolayer on one or more surfaces of the superconducting component 104, including the niobium (Nb) superconducting component, using, for example, a solution-based self-assembled monolayer deposition process (e.g., a solution 202 of one or more of the reactive organic compounds identified above in a solvent).

[0060] At 508b, the method 500 can include repeating the process at the niobium (Nb) surface using a thiol-based self-assembled monolayer (SAM). For example, with reference to Figures 1C and 3B, the method 500 can include repeating the deposition step of 506b at 508b, for example, to deposit (e.g., form, assemble, grow, etc.) a thiol-based self-assembled monolayer on one or more surfaces of the superconducting component 104, including the niobium (Nb) superconducting component, using, for example, a vapor-phase based self-assembled monolayer deposition process (e.g., vapor 110 including one or more reactive organic compounds, such as PFD, reactive organic materials, such as those identified above with reference to Figure 1C).

[0061] At 510, method 500 can include performing final processing of the qubit chip, where a self-assembled monolayer (SAM) coating prevents re-oxidation of silicon (Si) and niobium (Nb) surfaces. For example, at 510, method 500 can include performing final processing, such as packaging of the qubit chip, which can include, for example, devices 100c, 200, or 300b, or combinations thereof, described above with reference to Figures 1C, 2, and 3B.

[0062] 6A, 6B, and 6C illustrate exemplary, non-limiting information 600a, 600b, 600c that may include experimental data from the implementation of a quantum device including a self-assembled monolayer formed thereon, according to one or more embodiments described herein, and for the sake of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0063] The information 600a, 600b, 600c may include X-ray photoelectron spectra indicative of experimental data from the implementation of a quantum device including a self-assembled monolayer formed on the quantum device according to one or more embodiments described herein.

[0064] The information 600a shown in FIG. 6A shows oxidized silicon (Si) as plot 602a and also shows the dramatic reduction in oxygen (O 1s core level) and H-terminated silicon (Si) after etching with dilute HF or trifluoroacetic acid as plot 604a.

[0065] The information 600b shown in FIG. 6B includes spectra showing a reduction in the intensity of the oxygen O1s signal, which indicates the removal of silicon dioxide (SiO2) from a silicon (Si) substrate using various oxide removal processes, as shown by plots 604b, 606b, 608b, and 610b. Plot 602b shown in FIG. 6B shows the intensity of the oxygen O1s signal obtained from an as-inserted silicon (Si) substrate. Plot 604b shown in FIG. 6B shows the reduction in the intensity of the oxygen O1s signal obtained from a silicon (Si) substrate after treatment with trifluoroacetic acid (TFA). Plot 606b shown in FIG. 6B shows the reduction in the intensity of the oxygen O1s signal obtained from a silicon (Si) substrate after treatment with a HF solution containing ten percent (10%) HF in water (H2O). Plot 608b shown in FIG. 6B shows the reduction in the intensity of the oxygen O1s signal obtained from a silicon (Si) substrate after treatment with HF vapor. Plot 610b shown in FIG. 6B illustrates the reduction in intensity of the oxygen O1s signal obtained from a silicon (Si) substrate after treatment with HF vapor and subsequent annealing at 400°C.

[0066] The information 600c shown in FIG. 6C includes a spectrum showing the silicon Si 2p core level of oxidized silicon (Si) as plot 602c, showing the chemically shifted core level component associated with silicon dioxide (SiO2) at 104 electron volts (eV) binding energy, and the same silicon Si 2p core level after etching and perfluorodecene SAM deposition as plot 604c, showing that the oxide has been removed and has not regrown after air exposure.

[0067] 7A illustrates exemplary non-limiting information 700a that may include experimental data from the implementation of a quantum device including an H-terminated surface after oxide layer removal according to one or more embodiments described herein, where repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted for the sake of brevity.

[0068] The information 700a may include as plot 702a an ultraviolet photoelectron spectrum illustrating experimental data from the implementation of a quantum device including an H-terminated silicon (Si) surface formed by removing silicon dioxide (SiO2) using a non-aqueous dilute HF etchant with trifluoroacetic acid (CF3CO2H), according to one or more embodiments described herein.

[0069] 7B illustrates exemplary, non-limiting information 700b that may include experimental data from the implementation of a quantum device including a self-assembled monolayer formed thereon, according to one or more embodiments described herein, and in the interest of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0070] Information 700b may include an ultraviolet photoelectron spectrum showing experimental data from an implementation of a quantum device including a self-assembled monolayer formed on the quantum device according to one or more embodiments described herein. Information 700b may include an ultraviolet photoelectron spectrum of a silicon (Si) surface (e.g., a coated silicon (Si) surface of substrate 102) covered with a perfluorodecene (PFD) self-assembled monolayer. The altered spectrum shows the molecular structure of the PFD. The spectra shown by plots 702b and 704b were collected using light of different polarizations (shown as P-pol and S-Pol in FIG. 7B), and the difference between the spectra reveals the ordering of the self-assembled monolayer (SAM) on the silicon (Si) surface.

[0071] 7C illustrates exemplary, non-limiting information 700c that may include experimental data from the implementation of a quantum device including a self-assembled monolayer formed thereon, according to one or more embodiments described herein, in which repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted for brevity.

[0072] The information 700c may include an X-ray photoelectron spectrum showing experimental data from an implementation of a quantum device including a self-assembled monolayer formed on the quantum device according to one or more embodiments described herein. The information 700c may include an X-ray photoelectron spectrum of a silicon (Si) surface (e.g., a coated silicon (Si) surface of a substrate 102) covered with a perfluorodecene (PFD) self-assembled monolayer. The plot 702c shown in FIG. 7C shows an X-ray photoelectron spectrum of a silicon (Si) surface (e.g., a coated silicon (Si) surface of a substrate 102) covered with a perfluorodecene (PFD) self-assembled monolayer treated with trifluoroacetic acid (TFA) for 3 minutes and then treated with PFD for 60 minutes. Plot 704c shown in Figure 7C shows an X-ray photoelectron spectrum of a silicon (Si) surface covered with a perfluorodecene (PFD) self-assembled monolayer (e.g., the coated silicon (Si) surface of substrate 102) treated with trifluoroacetic acid (TFA) for 8 minutes followed by PFD for 60 minutes. The F 1s core level shown in Figure 7C is a further indication of the PFD self-assembled monolayer.

[0073] 8 illustrates a flow diagram of an exemplary, non-limiting, computer-implemented method 800 that can facilitate forming a self-assembled monolayer on a quantum device according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0074] At 802, the computer-implemented method 800 can include removing one or more oxide layers from the qubits formed on the substrate. For example, with reference to FIGS. 1A, 1B, and 3A, the computer-implemented method 800 can include, at 802, removing the first oxide layer 106 (e.g., silicon dioxide (SiO2)) or the second oxide layer 108 (e.g., niobium dioxide (NbO2), niobium pentoxide (Nb2O5), or other suboxides, or combinations thereof) or both from one or more surfaces of the device 100a or device 300a, or both, using a wet etchant process or a dry etchant process or both (e.g., a non-aqueous dilute HF etchant with trifluoroacetic acid (CF3CO2H), various concentrations of aqueous hydrogen fluoride (HF), buffered etchants including ammonium fluoride (NH4F), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), etc.). In this example, the substrate 102 and / or superconducting component 104 of device 100a and / or device 300a may constitute a qubit.

[0075] At 804, the computer-implemented method 800 may include depositing a self-assembled monolayer on the qubit. For example, with reference to Figures 1C, 2 and 3B, the computer-implemented method 800 may include depositing one or more self-assembled monolayers on one or more surfaces of device 100b or device 300a or both using a solution-based self-assembled monolayer deposition process (e.g., using solution 202) or a vapor-phase based self-assembled monolayer deposition process (e.g., using vapor 110). In this example, substrate 102 or superconducting component 104 or both of device 100b or device 300a may comprise a qubit.

[0076] 9 illustrates a flow diagram of an exemplary, non-limiting, computer-implemented method 900 that can facilitate forming a self-assembled monolayer on a quantum device according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of the same elements and / or processes used in other embodiments described herein are omitted.

[0077] At 902, the computer-implemented method 900 can include removing one or more oxide layers from one or more superconducting components formed on a substrate. For example, with reference to FIGS. 1A, 1B, and 3A, at 902, the computer-implemented method 900 can include removing a first oxide layer 106 (e.g., silicon dioxide (SiO2)) or a second oxide layer 108 (e.g., niobium dioxide (NbO2), niobium pentoxide (Nb2O5), or other suboxides, or combinations thereof) or both from one or more surfaces of a superconducting component 104 formed on a substrate 102 of device 100a or device 300a, or both, using a wet etchant process or a dry etchant process or both (e.g., a non-aqueous dilute HF etchant with trifluoroacetic acid (CF3CO2H), various concentrations of aqueous hydrogen fluoride (HF), a buffered etchant including ammonium fluoride (NH4F), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), etc.).

[0078] At 904, the computer-implemented method 900 can include depositing a self-assembled monolayer on one or more superconducting components. For example, with reference to Figures 1C, 2 and 3B, the computer-implemented method 900 can include, at 904, depositing one or more self-assembled monolayers on one or more surfaces of the superconducting components 104 of device 100b or device 300a, or both, using a solution-based self-assembled monolayer deposition process (e.g., using solution 202) or a vapor-phase-based self-assembled monolayer deposition process (e.g., using vapor 110).

[0079] Device 100c, 200, or 300b, or combinations thereof, may be associated with various technologies, such as semiconductor and / or superconductor device technologies, semiconductor and / or superconductor device fabrication technologies, quantum computing device technologies, quantum computing device fabrication technologies, oxide removal technologies, self-assembled monolayer deposition technologies, Josephson junction transmon device technologies, Josephson junction transmon device fabrication technologies, transmon qubit technologies, transmon qubit fabrication technologies, and / or other technologies.

[0080] Device 100c, 200, or 300b, or combinations thereof, may provide technical improvements over the various techniques listed above. For example, by fabricating device 100c, 200, or 300b, or combinations thereof, utilizing the oxide removal and self-assembled monolayer deposition processes described above with reference to Figures 1A-5, 8, or 9, or combinations thereof, one or more components of such devices (e.g., substrate 102, superconducting component 104, qubits, resonators, capacitors, etc.) may be stabilized or encapsulated (e.g., sealed) or stabilized and encapsulated (e.g., sealed) to prevent re-oxidation of one or more surfaces of such components. In embodiments in which devices 100c, 200 and / or 300b include quantum devices and / or such components include qubits and / or other superconducting components of the quantum devices, by preventing re-oxidation of such surfaces of such qubits or other superconducting components or both, devices 100c, 200 or 300b, or combinations thereof, can facilitate at least one of improved coherence time (e.g., longer coherence time), improved performance or improved lifetime (e.g., longer lifetime) of such qubits or other superconducting components or both, or combinations thereof.

[0081] Device 100c, 200 or 300b or combinations thereof may provide technical improvements to processing units associated with device 100c, 200 or 300b or combinations thereof. For example, based on the examples provided above illustrating the fabrication of such devices using methods and / or materials that prevent elements of device 100c, 200 or 300b or combinations thereof (e.g., substrate 102, superconducting component 104, qubits, resonators, capacitors, etc.) from re-oxidizing, device 100c, 200 or 300b or combinations thereof may facilitate, for example, improved coherence times (e.g., longer coherence times), thereby facilitating improved processing performance of quantum computing devices (e.g., quantum processors) including device 100c, 200 or 300b or combinations thereof.

[0082] A practical application of device 100c, 200 or 300b, or combinations thereof, is that the device may be implemented in a quantum computing device (e.g., a quantum computer) to improve the processing performance of such a device, such that such a device may facilitate fast quantum computing or possibly general-purpose quantum computing or both. Such a practical application may improve the output (e.g., computational and / or processing results) of one or more compilation jobs (e.g., quantum computing jobs) executed on such a device.

[0083] It should be appreciated that devices 100c, 200, or 300b, or combinations thereof, provide new ways of fabricating superconducting devices driven by relatively new quantum computing technologies, such as devices 100c, 200, or 300b, or combinations thereof, that can improve the coherence time, performance, or lifetime, or combinations thereof, of such qubit devices (e.g., quantum processors, quantum computers, quantum circuits, quantum hardware, etc.).

[0084] Device 100c, 200 or 300b or combinations thereof may be combined with hardware or software or both to solve problems that are highly technical in nature and not abstract and cannot be performed as a set of mental acts by a human being. For example, device 100c, 200 or 300b or combinations thereof may be used in semiconductor devices or superconductor devices (e.g., integrated circuits) or both used to implement quantum computing devices that can process information and / or perform calculations that are not abstract and cannot be performed as a set of mental acts by a human being.

[0085] It should be appreciated that device 100c, 200 or 300b or combinations thereof may utilize various combinations of electrical components, mechanical components and circuitry that cannot be replicated by the human intellect or performed by humans. For example, facilitating device 100c, 200 or 300b or combinations thereof in a semiconductor superconducting device that may enable the operation of a quantum computing device (e.g., a quantum processor of a quantum computing device) is an operation beyond the human intellect. For example, the amount of data processed by such a quantum computing device utilizing device 100c, 200 or 300b or combinations thereof in a period of time, the speed at which such data is processed, or the type of data, or combinations thereof, may be greater than the amount, speed at which such data can be processed, or a different type of data than the human intellect can process in the same period of time, or combinations thereof.

[0086] According to some embodiments, device 100c, 200 or 300b or combinations thereof may further be fully operable to perform one or more other functions (e.g., fully powered on, fully running, etc.) while also performing the above-referenced operations. It should also be recognized that such simultaneous multi-operation execution is beyond the capabilities of the human mind. It should also be recognized that device 100c, 200 or 300b or combinations thereof may include information that is not manually obtainable by an entity such as a human user. For example, the type, amount or variety of information included in device 100c, 200 or 300b or combinations thereof, or combinations thereof, may be more complex than information manually obtained by a human user.

[0087] The exemplary, non-limiting, multi-step manufacturing sequences described above with reference to Figures 1A-5, 8 or 9, or combinations thereof, which may be implemented to manufacture one or more embodiments of the subject disclosure described herein or illustrated in the figures, or as described herein and illustrated in the figures, may be implemented by a computing system (e.g., operating environment 1000 shown in Figure 10 and described below) or a computing device (e.g., computer 1012 shown in Figure 10 and described below) or both. In non-limiting, exemplary embodiments, such a computing system (e.g., operating environment 1000) or such a computing device (e.g., computer 1012) may include one or more processors and one or more memory devices that may store thereon executable instructions that, when executed by the one or more processors, may facilitate execution of the exemplary, non-limiting, multi-step manufacturing operations described above with reference to Figures 1A-5, 8 or 9, or combinations thereof. As a non-limiting example, the one or more processors may facilitate execution of the exemplary, non-limiting multi-step manufacturing operations described above with reference to Figures 1A-5, 8 or 9, or combinations thereof, by directing or controlling, or directing and controlling, one or more systems or equipment operable to perform the fabrication of semiconductor devices or superconducting devices or semiconductor superconducting devices.

[0088] For simplicity of explanation, the methodologies (e.g., computer-implemented methods) described herein are depicted and described as a series of operations. It is to be understood and appreciated that the subject innovation is not limited by the operations depicted and / or by the order of operations, e.g., operations can be performed in various orders or simultaneously, or both, and can be performed with other operations not depicted and other operations not described herein. Moreover, not all depicted operations are required to implement the methodologies (e.g., computer-implemented methods) described herein in accordance with the disclosed subject matter. Moreover, those skilled in the art will understand and appreciate that such methods can alternatively be represented as a series of interrelated states, such as by a state diagram or events. It is also to be appreciated that the methodologies (e.g., computer-implemented methods) disclosed below and throughout this specification can be stored on an article of manufacture to facilitate transporting and transferring such methodologies (e.g., computer-implemented methods) to a computer. As used herein, the term article of manufacture is intended to encompass a computer program accessible from a computer-readable device or storage medium.

[0089] To provide background for various aspects of the disclosed subject matter, FIG. 10 and the following discussion are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. FIG. 10 illustrates a block diagram of an exemplary, non-limiting operating environment that may facilitate one or more embodiments described herein. For example, the exemplary, non-limiting multi-step manufacturing operations described herein with respect to FIGS. 1A-5, 8 or 9, or combinations thereof, that may facilitate implementation of one or more embodiments of the subject disclosure described herein, may be implemented using the operating environment 1000. For the sake of brevity, repeated descriptions of the same elements and / or processes used in the respective corresponding embodiments are omitted.

[0090] 10, a suitable operating environment 1000 for implementing various aspects of the present disclosure may further include a computer 1012. The computer 1012 may further include a processing unit 1014, a system memory 1016, and a system bus 1018. The system bus 1018 couples system components including, but not limited to, the system memory 1016 to the processing unit 1014. The processing unit 1014 may be any of a variety of processors available. Dual microprocessors and other multi-processor architectures may also be used as the processing unit 1014. The system bus 1018 may be any of several types of bus structures including a memory bus or memory controller, a peripheral or external bus, and / or a local bus using any of a variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), MicroChannel Architecture (MCA), Enhanced ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI).

[0091] The system memory 1016 may further include a volatile memory 1020 and a non-volatile memory 1022. The non-volatile memory 1022 stores a basic input / output system (BIOS), which includes the basic routines for transferring information between elements within the computer 1012, such as during start-up. The computer 1012 may further include removable / non-removable volatile / non-volatile computer storage media. FIG. 10 illustrates, for example, a disk storage 1024. The disk storage 1024 may further include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. The disk storage 1024 may further include storage media separate from or in combination with other storage media. To facilitate connection of the disk storage 1024 to the system bus 1018, a removable or non-removable interface, such as an interface 1026, is typically used. 10 further illustrates software that acts as an intermediary between users and the basic computer resources described within suitable operating environment 1000. Such software may further include, for example, an operating system 1028. The operating system 1028, which may be stored on disk storage 1024, functions to control and allocate resources of the computer 1012.

[0092] System applications 1030 take advantage of the management of resources by operating system 1028 via program modules 1032 and program data 1034 stored, for example, in system memory 1016 or disk storage 1024. It should be appreciated that the present disclosure may be implemented with various operating systems or combinations of operating systems. A user enters commands or information into computer 1012 through input devices 1036. Input devices 1036 include, but are not limited to, a pointing device such as a mouse, a trackball, a stylus, a touch pad, a keyboard, a microphone, a joystick, a game pad, a satellite dish, a scanner, a TV tuner card, a digital camera, a digital video camera, a web camera, and the like. These and other input devices connect to processing unit 1014 through system bus 1018 via interface ports 1038. Interface ports 1038 include, for example, serial ports, parallel ports, game ports, and a universal serial bus (USB). The output device 1040 uses some of the same types of ports as the input device 1036. Thus, for example, a USB port may be used to provide input to the computer 1012 and to output information from the computer 1012 to the output device 1040. An output adapter 1042 is provided to illustrate that there are some output devices 1040 that require dedicated adapters, such as monitors, speakers, and printers, among others. By way of example, output adapters 1042 include, but are not limited to, video cards and sound cards that provide a means of connection between the output device 1040 and the system bus 1018. It should be noted that other devices and / or device systems, such as a remote computer 1044, provide both input and output capabilities.

[0093] The computer 1012 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1044. The remote computer 1044 can be a computer, a server, a router, a network PC, a workstation, a microprocessor-based device, a peer device or other common network node, and typically further includes many or all of the elements described with respect to the computer 1012. For simplicity, only a memory storage device 1046 is shown in the remote computer 1044. The remote computer 1044 is logically connected to the computer 1012 through a network interface 1048, which is then physically connected through a communication connection 1050. The network interface 1048 encompasses wired and / or wireless communication networks, such as a local area network (LAN), a wide area network (WAN), and a cellular network. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereon, packet-switched networks, and Digital Subscriber Lines (DSL). The communications connection 1050 refers to the hardware / software used to connect the network interface 1048 to the system bus 1018. For ease of illustration, the communications connection 1050 is shown internal to the computer 1012, but the communications connection 1050 can also be external to the computer 1012. For purposes of illustration only, the hardware / software for connecting to the network interface 1048 can further include internal and external technologies such as modems, including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet® cards.

[0094] The present invention may be a system, method, apparatus, or computer program product, or combinations thereof, at any level of technical detail capable of integration. The computer program product may include a computer readable storage medium having computer readable program instructions thereon for causing a processor to execute aspects of the present invention. The computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media may include portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or raised structures in grooves on which instructions are recorded, and suitable combinations of these. As used herein, computer readable storage media should not be construed as being, in itself, a transitory signal, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating in a wave guide or other transmission body (e.g., light pulses traveling in a fiber optic cable), or electrical signals transmitted through electrical wires.

[0095] The computer readable program instructions described herein may be downloaded from a computer readable storage medium into the respective computing / processing device or may be downloaded to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and transfers the computer readable program instructions to a computer readable storage medium in the respective computing / processing device for storage. The computer readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or configuration data for an integrated circuit, or may be source or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the “C” programming language or the like. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or remote server.In the last scenario above, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to carry out aspects of the invention.

[0096] Aspects of the present invention are described herein with reference to flowchart and / or block diagram illustrations of methods, apparatus (systems) and computer program products according to embodiments of the present invention. It will be understood that each block of the flowchart and / or block diagram illustrations, and combinations of blocks in the flowchart and / or block diagram illustrations, can be implemented by computer readable program instructions. These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing device forming a machine such that the instructions, executed by the processor of the computer or other programmable data processing device, generate means for implementing the functions / operations specified in the blocks of the flowchart and / or block diagram illustrations. These computer readable program instructions can further be stored on a computer readable storage medium capable of directing a computer, programmable data processing device, or other device, or combination thereof, to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises a product including instructions for implementing aspects of the functions / operations specified in the blocks of the flowchart and / or block diagram illustrations. These computer readable program instructions can further be loaded onto a computer, other programmable data processing apparatus or other device to cause the computer, other programmable apparatus or other device to perform a series of operational steps to generate a computer-implemented process, in a manner such that the instructions executed on the computer, other programmable apparatus or other device perform the functions / operations specified in the blocks of these flowcharts and / or block diagrams.

[0097] The flowcharts and block diagrams in the accompanying figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing specified logical functions. In some alternative implementations, the functions shown in the blocks may be implemented in an order different from that shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, as well as combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a hardware-based dedicated system that performs the specified functions or operations or implements a combination of dedicated hardware and computer instructions.

[0098] Although the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on one or more computers, or both, those skilled in the art will recognize that the disclosure may also be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Furthermore, those skilled in the art will recognize that the computer-implemented methods of the present invention may also be implemented with other computer system configurations, including single-processor or multi-processor computer systems, minicomputing devices, mainframe computers, computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable home or industrial electronic devices, and the like. The illustrated aspects may also be implemented in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the disclosure may also be implemented on stand-alone computers. In a distributed computing environment, program modules may be located in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components may be executed from a memory that may include or consist of one or more distributed memory units. As used herein, the terms "memory" and "memory unit" are interchangeable. Furthermore, one or more embodiments described herein may execute code of the computer-executable components in a distributed manner, e.g., execute code of the computer-executable components in multiple processors that act in conjunction or cooperation to execute code from one or more distributed memory units.As used herein, the term "memory" may encompass a single memory or memory unit in one location or multiple memories or memory units in one or more locations.

[0099] As used in this application, the terms "component," "system," "platform," "interface," and the like, may refer to or include a computer-related or operational machine-related entity having one or more particular functions, or both. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or combinations thereof. As an example, both an application running on a server and the server may be a component. Within a process or thread of execution, or both, one or more components may be localized on one computer or distributed between two or more computers, or both. In other examples, corresponding respective components may be executed from various computer-readable media having various data structures stored thereon. A component may communicate via local or remote processes or both, e.g., according to a signal having one or more data packets (e.g., data from one component interacting with another component via a signal, whether within a local system, within a distributed system, or across a network such as the Internet, or with other systems, or a combination thereof). As another example, a component may be a device having a particular function provided by mechanical parts operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor may be located within or outside the device and may execute at least a portion of the software or firmware application.As another example, a component may be a device that provides a particular functionality through electronic components that do not include mechanical parts, and those electronic components may include a processor or other means for executing software or firmware that provides at least part of the functionality of the electronic component. In one aspect, a component may emulate an electronic component through a virtual machine, for example, in a cloud computing system.

[0100] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise stated or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, if X uses A, if X uses B, or if X uses both A and B, "X uses A or B" is satisfied under any of the above cases. Furthermore, unless otherwise stated or clear from the context to indicate the singular form, the articles "a" and "an" used in this specification and the accompanying drawings should generally be construed to mean "one or more". As used herein, the terms "example" and / or "exemplary" are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Moreover, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, or to be meant to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0101] As used herein, the term "processor" may refer to substantially any computing processing unit or device, including, but not limited to, a single-core processor, a single-core processor with software multithreaded execution capabilities, a multi-core processor, a multi-core processor with software multithreaded execution capabilities, a multi-core processor with hardware multithreading techniques, a parallel platform, and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit designed to perform the functions described herein, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. Additionally, a processor may utilize nanoscale architectures, such as, but not limited to, molecular-based and quantum dot-based transistors, switches, and gates, to optimize space usage or enhance the performance of a user device. A processor may also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component associated with the operation and functionality of the component are utilized to refer to a "memory component" that is an entity embodied as a "memory" or a component that includes memory. It should be appreciated that the memory and / or memory components described herein can be volatile or non-volatile memory, or can include both volatile and non-volatile memory.By way of example, non-volatile memory may include, but is not limited to, read only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM), such as ferroelectric RAM (FeRAM). Volatile memory may include RAM, which may function, for example, as external cache memory. Many forms of RAM may be used, including, by way of example, but not limited to, static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of the systems or computer-implemented methods herein are intended to include, but are not limited to, these and other suitable types of memory.

[0102] What has been described above includes merely examples of systems and computer-implemented methods. Of course, it is not possible to describe every conceivable combination of components or computer-implemented methods in order to describe the present disclosure, but one of ordinary skill in the art can appreciate that many other combinations and permutations of the present disclosure are possible. Moreover, to the extent that the terms "includes," "has," "possesses," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as the term "comprising" is interpreted when used as a transitional term in the claims.

[0103] The above description of various embodiments is provided for illustrative purposes, and is not intended to be exhaustive or to be limited to only the disclosed embodiments. Many modifications and variations that do not depart from the scope and spirit of the described embodiments will be apparent to those skilled in the art. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technology, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A device, comprising: a qubit formed on a substrate; a self-assembled monolayer formed on the qubit and the substrate; The device that contains

2. The device of claim 1 , wherein the self-assembled monolayer comprises an organic self-assembled monolayer.

3. The device of claim 1 or 2, wherein the self-assembled monolayer is selected from the group consisting of alkynes, alkenes, alcohols and thiols.

4. 4. The device of claim 1, wherein the self-assembled monolayer is formed on the qubit and the substrate to prevent oxidation of the qubit and the substrate, thereby facilitating at least one of improving the coherence time of the qubit and improving the lifetime of the qubit.

5. 1. A method comprising: removing one or more oxide layers from qubits formed on a substrate; removing the second oxide layer or layers from the substrate; and depositing a self-assembled monolayer over said qubit and said substrate; The method includes:

6. 6. The method of claim 5, wherein the self-assembled monolayer comprises an organic self-assembled monolayer selected from the group consisting of alkynes, alkenes, alcohols, and thiols.

7. Depositing the self-assembled monolayer on the qubit and the substrate using at least one of a solution-based self-assembled monolayer deposition process and a vapor-phase-based self-assembled monolayer deposition process. The method of claim 5 or 6, further comprising:

8. Depositing the self-assembled monolayer on the qubit and the substrate to prevent oxidation of the qubit and the substrate, thereby facilitating at least one of improving the coherence time of the qubit and improving the lifetime of the qubit. The method of claim 5 or 6, further comprising:

9. A device, comprising: one or more superconducting components formed on a substrate; a self-assembled monolayer formed on the one or more superconducting components and the substrate; The device that contains

10. The device of claim 9 , wherein the self-assembled monolayer comprises an organic self-assembled monolayer.

11. 11. The device of claim 9 or 10, wherein the self-assembled monolayer is selected from the group consisting of alkynes, alkenes, alcohols and thiols.

12. 12. The device of claim 9, wherein the self-assembled monolayer is formed on the one or more superconducting components and the substrate to prevent oxidation of the one or more superconducting components and the substrate.

13. 1. A method comprising: removing one or more oxide layers from one or more superconducting components formed on the substrate; removing the second oxide layer or layers from the substrate; and depositing a self-assembled monolayer on said one or more superconducting components and said substrate; The method includes:

14. The method of claim 13 , wherein the self-assembled monolayer comprises an organic self-assembled monolayer.

15. 15. The method of claim 13 or 14, wherein the self-assembled monolayer is selected from the group consisting of alkynes, alkenes, alcohols and thiols.

16. Depositing the self-assembled monolayer on the one or more superconducting components and the substrate using at least one of a solution-based self-assembled monolayer deposition process and a vapor-phase-based self-assembled monolayer deposition process.

16. The method of any of claims 13 to 15, further comprising:

17. A device, comprising: a qubit formed on a substrate of the bump-bonded device; a self-assembled monolayer formed on the qubit and the substrate; The device that contains

18. The device of claim 17 , wherein the self-assembled monolayer comprises an organic self-assembled monolayer.

19. 19. The device of claim 17 or 18, wherein the self-assembled monolayer is selected from the group consisting of alkynes, alkenes, alcohols and thiols.

20. 20. The device of any of claims 17 to 19, wherein the self-assembled monolayer is formed on the qubits and the substrate to prevent oxidation of the qubits and the substrate, thereby facilitating at least one of improving the coherence time of the qubits and improving the lifetime of the qubits.

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