Power Amplifier

Abstract

To provide a power amplifier capable of increasing operational reliability.SOLUTION: A power amplifier 1 of an embodiment includes: a first amplifier A1 in which a plurality of voltages are inputted to a plurality of input terminals, for outputting a first output signal OUTP1; a second amplifier A2 in which a plurality of voltages are inputted to a plurality of input terminals, for outputting a second output signal OUTM1; a first circuit LIM1 for outputting a third signal OUTPLIM1 which is the first output signal OUTP1 with the magnitude of the voltage value being limited and a fourth signal OUTMLIM1 which is the second output signal OUTM1 with the magnitude of the voltage value being limited; and a second circuit CMFB1 for transmitting an average value of the voltage value of the third signal OUTPLIM1 and the voltage value of the fourth signal OUTMLIM1 to the first amplifier A1 and the second amplifier A2 as a first feedback voltage VCMFB1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a power amplifier device. [Background technology]

[0002] 2. Description of the Related Art A BTL (Balanced Transformer Less, Bridge-Tied Load, or Bridged Transformer Less) amplifier is known as one type of power amplifier. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-284450 [Patent Document 2] JP 2013-38538 A [Patent Document 3] JP 2013-157664 A Summary of the Invention [Problem to be solved by the invention]

[0004] A power amplifier capable of improving operational reliability is provided. [Means for solving the problem]

[0005] The power amplifier device according to the embodiment includes a first amplifier that receives a plurality of voltages at a plurality of input terminals and outputs a first output signal, a second amplifier that receives a plurality of voltages at a plurality of input terminals and outputs a second output signal, and a voltage value of the first output signal. Based on the third voltage, a first maximum voltage value of the first output signal based on the third voltage, or a first output signal smaller than the first maximum voltage value; 3rd Signal Output as , the magnitude of the voltage value of the second output signal Based on the third voltage, a second maximum voltage value of the second output signal based on the third voltage, or a second output signal smaller than the second maximum voltage value; 4th Signal AsThe input terminal of the first amplifier includes a first circuit for outputting a third signal and a second circuit for transmitting an average value of the voltage values ​​of the third signal and the fourth signal as a first feedback voltage to the first amplifier and the second amplifier. Of the multiple input terminals of the first amplifier, a first voltage corresponding to the first input signal is applied to a first non-inverting input terminal, a second voltage corresponding to the second input signal is applied to a first inverting input terminal, a first reference voltage is applied to a second non-inverting input terminal, and a first feedback voltage is applied to a second inverting input terminal. Of the multiple input terminals of the second amplifier, a first voltage is applied to a third inverting input terminal, a second voltage is applied to a third non-inverting input terminal, a first reference voltage is applied to a fourth non-inverting input terminal, and a first feedback voltage is applied to a fourth inverting input terminal. The number is , based on a third voltage that is greater than the first reference voltage. The voltage value of the first output signal is It is a limited signal. The fourth signal is a signal in which the magnitude of the voltage value of the second output signal is limited based on the third voltage. . [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing an example of a power amplifying device according to a first embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing an example of an operational amplifier included in the power amplifying device according to the first embodiment. [Diagram 3] FIG. 3 is a circuit diagram showing an example of a limiter circuit included in the power amplifying device according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram showing an example of an intermediate voltage generating circuit included in the power amplifying device according to the first embodiment. [Diagram 5] FIG. 5 is a flowchart showing the operation of the power amplifying device according to the first embodiment. [Figure 6] FIG. 6 is a diagram illustrating the effect of the power amplifying device according to the first embodiment. [Figure 7] FIG. 7 is a circuit diagram showing an example of an operational amplifier included in a power amplifying device according to a first modification of the first embodiment. [Figure 8]FIG. 8 is a circuit diagram showing an example of a limiter circuit included in a power amplifying device according to a second modification of the first embodiment. [Figure 9] FIG. 9 is a circuit diagram illustrating an example of a power amplifying device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are given the same reference numerals, and repeated explanations may be omitted. In addition, all descriptions of one embodiment may also be applied to other embodiments, unless expressly or obviously excluded.

[0008] 1. First embodiment A power amplifying device according to a first embodiment will be described below. In this embodiment, a BTL amplifier will be taken as an example of the power amplifying device.

[0009] 1.1 Configuration 1.1.1 Circuit configuration of power amplifier The circuit configuration of the power amplifier device according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an example of a power amplifier device.

[0010] The power amplification device 1 includes a power supply voltage wiring 2, a ground voltage wiring 3, a power supply voltage terminal T1, a ground voltage terminal T2, input terminals Tinp1 and Tinm1, output terminals Toutp1 and Toutm1, resistive elements Rs1 and Rs2, a first operational amplifier A1, a second operational amplifier A2, resistive elements Rf1 and Rf2, a limiter circuit LIM1, and an intermediate voltage generating circuit CMFB1.

[0011] A power supply voltage line 2 is connected to the power supply voltage terminal T1, and a power supply voltage VCC is applied from the outside.

[0012] A ground voltage line 3 is connected to the ground voltage terminal T2, and a ground voltage VSS is applied thereto from the outside.

[0013] An external signal INP1 is input to the input terminal Tinp1.

[0014] An external signal INM1 is input to the input terminal Tinm1. The signal INM1 is a signal obtained by inverting the phase of the signal NP1.

[0015] One end of the resistive element Rs1 is connected to the input terminal Tinp1, and the other end is connected to a node ND1.

[0016] One end of the resistive element Rs2 is connected to the input terminal Tinm1, and the other end is connected to a node ND2.

[0017] The first power supply voltage terminal of the first operational amplifier A1 is connected to a power supply voltage wiring 2, and the second power supply voltage terminal is connected to a ground voltage wiring 3. The first operational amplifier A1 has a first non-inverting input terminal (hereinafter also referred to as "TDFBp1 ​​terminal"), a second non-inverting input terminal (hereinafter also referred to as "TCFBp1 terminal"), a first inverting input terminal (hereinafter also referred to as "TDFBm1 terminal"), and a second inverting input terminal (hereinafter also referred to as "TCFBm1 terminal"). The TDFBp1 ​​terminal of the first operational amplifier A1 is connected to a node ND1, the TCFBp1 terminal is connected to a node ND3, the TDFBm1 terminal is connected to a node ND2, and the TCFBm1 terminal is connected to a node ND4. A reference voltage VCMREF1 is applied to the node ND3. The reference voltage VCMREF1 is, for example, a voltage VCC / 2, but is not limited to the voltage VCC / 2. The output terminal of the first operational amplifier A1 is connected to an output terminal Toutp1.

[0018] The first operational amplifier A1 amplifies a voltage based on the voltage Vinp1 of the node ND1 applied to the TDFBp1 ​​terminal, the voltage Vinm1 of the node ND2 applied to the TDFBm1 terminal, the voltage of the node ND3 (reference voltage VCMREF1) applied to the TCFBp1 terminal, and the voltage of the node ND4 (feedback voltage VCMFB1 described later) applied to the TCFBm1 terminal. The first operational amplifier A1 then outputs the amplified voltage as a signal OUTP1. The signal OUTP1 is output from an output terminal Toutp1. The configuration of the first operational amplifier A1 will be described in detail later.

[0019] The first power supply voltage terminal of the second operational amplifier A2 is connected to the power supply voltage wiring 2, and the second power supply voltage terminal is connected to the ground voltage wiring 3. The second operational amplifier A2 has a first non-inverting input terminal (hereinafter also referred to as "TDFBp2 terminal"), a second non-inverting input terminal (hereinafter also referred to as "TCFBp2 terminal"), a first inverting input terminal (hereinafter also referred to as "TDFBm2 terminal"), and a second inverting input terminal (hereinafter also referred to as "TCFBm2 terminal"). The first non-inverting input terminal of the second operational amplifier A2 is connected to a node ND2, the second non-inverting input terminal is connected to a node ND3, the first inverting input terminal is connected to a node ND1, and the second inverting input terminal is connected to a node ND4. The output terminal of the second operational amplifier A2 is connected to an output terminal Toutm1.

[0020] The second operational amplifier A2 amplifies a voltage based on the voltage Vinm1 of the node ND2 applied to the TDFBp2 terminal, the voltage Vinp1 of the node ND1 applied to the TDFBm2 terminal, the voltage of the node ND3 (reference voltage VCMREF1) applied to the TCFBp2 terminal, and the voltage of the node ND4 (feedback voltage VCMFB1 described later) applied to the TCFBm2 terminal. The second operational amplifier A2 then outputs the amplified voltage as a signal OUTM1. The signal OUTM1 is output from an output terminal Toutm1. The configuration of the second operational amplifier A2 will be described in detail later.

[0021] One end of the resistor Rf1 is connected to the output terminal Toutp1, and the other end is connected to a node ND2. The signal OUTP1 is fed back to the TDFBm1 terminal of the first operational amplifier A1 via the resistor Rf1.

[0022] One end of the resistor Rf2 is connected to the output terminal Toutm1, and the other end is connected to a node ND1. The signal OUTM1 is fed back to the TDFBm2 terminal of the second operational amplifier A2 via the resistor Rf2.

[0023] Hereinafter, the feedback operation via the resistive elements Rf1 and Rf2 will be referred to as a "first feedback operation."

[0024] A voltage VLIM1 is applied to the limiter circuit LIM1. The limiter circuit LIM1 is connected to output terminals Toutp1 and Toutm1. The limiter circuit LIM1 receives a signal OUTP1 from the first operational amplifier A1 and a signal OUTM1 from the second operational amplifier A2. The limiter circuit LIM1 is also connected to the intermediate voltage generating circuit CMFB1. The limiter circuit LIM1 transmits a signal OUTPLIM1 based on the signal OUTP1 and a signal OUTMLIM1 based on the signal OUTM1 to the intermediate voltage generating circuit CMFB1. The limiter circuit LIM1 also limits the magnitude of the voltage values ​​of the signals OUTP1 and OUTM1 (the maximum voltage value or the minimum voltage value of the signals OUTP1 and OUTM1) based on the voltage VLIM1. The voltage VLIM1 is a voltage for determining the maximum voltage value or the minimum voltage value of the signals OUTP1 and OUTM1. The configuration of the limiter circuit LIM1 will be described in detail later.

[0025] For example, when limiting the maximum voltage value of the signals OUTP1 and OUTM1, the limiter circuit LIM1 determines the maximum voltage value Vmax of the signals OUTP1 and OUTM1 based on the voltage VLIM1. When the signals OUTP1 and OUTM1 are smaller than the maximum voltage value Vmax, the limiter circuit LIM1 transmits the signals OUTP1 and OUTM1 to the intermediate voltage generating circuit CMFB1 as the signals OUTPLIM1 and OUTMLIM1. On the other hand, when the signals OUTP1 and OUTM1 are equal to or greater than the maximum voltage value Vmax, the limiter circuit LIM1 transmits the maximum voltage value Vmax to the intermediate voltage generating circuit CMFB1 as the signals OUTPLIM1 and OUTMLIM1.

[0026] When limiting the minimum voltage value of the signals OUTP1 and OUTM1, the limiter circuit LIM1 determines the minimum voltage value Vmin of the signals OUTP1 and OUTM1 based on the voltage VLIM1. When the signals OUTP1 and OUTM1 are greater than the minimum voltage value Vmin, the limiter circuit LIM1 transmits the signals OUTP1 and OUTM1 to the intermediate voltage generating circuit CMFB1 as the signals OUTPLIM1 and OUTMLIM1. On the other hand, when the signals OUTP1 and OUTM1 are equal to or less than the minimum voltage value Vmin, the limiter circuit LIM1 transmits the minimum voltage value Vmin to the intermediate voltage generating circuit CMFB1 as the signals OUTP1 and OUTM1.

[0027] The intermediate voltage generating circuit CMFB1 is connected to a node ND4. The intermediate voltage generating circuit CMFB1 generates an average value of the signals OUTPLIM1 and OUTMLIM1 received from the limiter circuit LIM1. Then, the intermediate voltage generating circuit CMFB1 transmits the generated average value to the node ND4 as a feedback voltage VCMFB1. In other words, the voltage VCMFB1 is fed back from the intermediate voltage generating circuit CMFB1 to the TCFBm1 terminal of the first operational amplifier A1 and the TCFBm2 terminal of the second operational amplifier A2. The configuration of the intermediate voltage generating circuit CMFB1 will be described in detail later.

[0028] Hereinafter, the feedback operation via the limiter circuit LIM1 and the intermediate voltage generating circuit CMFB1 will be referred to as a "second feedback operation."

[0029] 1.1.2 First Op-Amp Configuration The circuit configuration of the first operational amplifier A1 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the first operational amplifier A1. The second operational amplifier A2 has a similar configuration to the first operational amplifier A1. In the following description, when the source and drain of a transistor are not specified, either the source or the drain of the transistor will be referred to as "one end of the transistor," and the other of the source or the drain of the transistor will be referred to as "the other end of the transistor."

[0030] The first operational amplifier A1 includes a first transconductance circuit Gm_DFB, a second transconductance circuit Gm_CFB, a resistive element R1, a driver stage circuit DS, a p-channel Metal Oxide Semiconductor Field Effect Transistor (hereinafter also referred to as the "PMOS transistor") P1, and an n-channel MOSFET (hereinafter also referred to as the "NMOS transistor") N1.

[0031] The non-inverting input terminal of the first transconductance circuit Gm_DFB is connected to the TDFBp1 ​​terminal of the first operational amplifier A1, and the inverting input terminal is connected to the TDFBm1 terminal of the first operational amplifier A1. The output terminal of the first transconductance circuit Gm_DFB is connected to a node ND5. The first transconductance circuit Gm_DFB outputs a current Idfb based on the voltage difference between a voltage Vinp1 applied from the node ND1 to the non-inverting input terminal and a voltage Vinm1 applied from the node ND2 to the inverting input terminal. The transconductance gm of the first transconductance circuit Gm_DFB is set to an arbitrary value. When there is no voltage difference between the voltage Vinp1 and the voltage Vinm1, the current Idfb becomes zero.

[0032] The non-inverting input terminal of the second transconductance circuit Gm_CFB is connected to the TCFBp1 terminal of the first operational amplifier A1, and the inverting input terminal is connected to the TCFBm1 terminal of the first operational amplifier A1. The output terminal of the second transconductance circuit Gm_CFB is connected to a node ND5. The second transconductance circuit Gm_CFB outputs a current Icfb based on the voltage difference between a reference voltage VCMREF1 applied to the non-inverting input terminal from a node ND3 and a feedback voltage VCMFB1 applied to the inverting input terminal from a node ND4. The transconductance gm of the second transconductance circuit Gm_CFB is set to an arbitrary value. When there is no voltage difference between the reference voltage VCMREF1 and the feedback voltage VCMFB1, the current Icfb becomes zero.

[0033] One end of the resistor R1 is connected to the node ND5, and the other end is grounded. A current Ir, which is a combination of the currents Idfb and Icfb, flows through the resistor R1. The current Ir is converted into a voltage Vr.

[0034] A voltage VCC is applied to a first power supply voltage terminal (not shown) of the driver stage circuit DS, and a voltage VSS is applied to a second power supply voltage terminal (not shown). An input terminal of the driver stage circuit DS is connected to a node ND5, and an output terminal is connected to nodes ND6 and ND7. A voltage Vr is applied to the driver stage circuit DS. The driver stage circuit DS amplifies the voltage Vr and outputs the amplified voltage to drive a PMOS transistor P1 and an NMOS transistor N1 in a push-pull configuration.

[0035] A voltage VCC is applied to one end of the PMOS transistor P1, the other end is connected to a node ND8, and the gate is connected to a node ND6. When the voltage difference between the voltage of the node ND6 and the voltage VCC exceeds the threshold voltage of the PMOS transistor P1, the PMOS transistor P1 is turned on and outputs a current according to the voltage difference between the voltage of the node ND6 and the voltage VCC to the node ND8.

[0036] One end of the NMOS transistor N1 is connected to a node ND8, the other end is applied with a voltage VSS, and the gate is connected to a node ND7. When the voltage difference between the node ND7 and the ground voltage VSS exceeds the threshold voltage of the NMOS transistor N1, the NMOS transistor N1 is turned on and outputs a current according to the voltage difference between the voltage of the node ND7 and the voltage VSS to the node ND8.

[0037] When a current is output from the PMOS transistor P1 or the NMOS transistor N1, the voltage of the node ND8 is controlled according to the value of the current output from the PMOS transistor P1 or the NMOS transistor N1, that is, the signal OUTP1 is determined.

[0038] For example, when the voltage Vr is positive, the current of the PMOS transistor P1 increases. At this time, the first operational amplifier A1 outputs a voltage obtained by amplifying the voltage Vr to the positive side as the signal OUTP1.

[0039] On the other hand, when the voltage Vr is negative, the current of the NMOS transistor N1 increases. At this time, the first operational amplifier A1 outputs a voltage obtained by amplifying the voltage Vr to the negative side as the signal OUTP1.

[0040] 1.1.3 Limiter circuit configuration The circuit configuration of the limiter circuit LIM1 will be described with reference to Fig. 3. Fig. 3 is a circuit diagram showing a limiter circuit for a low-side amplifier as an example of the limiter circuit LIM1.

[0041] The limiter circuit LIM1 includes NMOS transistors N2 and N3.

[0042] One end of the NMOS transistor N2 is connected to the output terminal Toutp1, the other end is connected to the intermediate voltage generating circuit CMFB1, and a voltage VLIM1 is applied to the gate. The voltage VLIM1 is, for example, higher than the reference voltage VCMREF1 and is a voltage that turns on the NMOS transistor N2. The maximum voltage value Vmaxp of the signal OUTP1 is determined based on the voltage VLIM1. When the signal OUTP1 is smaller than the maximum voltage value Vmaxp, the voltage value of the signal OUTPLIM1 becomes the voltage value of the signal OUTP1. In other words, the limiter circuit LIM1 transmits the signal OUTP1 as the signal OUTPLIM1 to the intermediate voltage generating circuit CMFB1. On the other hand, when the signal OUTP1 is equal to or greater than the maximum voltage value Vmaxp, the voltage value of the signal OUTPLIM1 becomes the maximum voltage value Vmaxp. In other words, the limiter circuit LIM1 transmits the maximum voltage value Vmaxp as the signal OUTPLIM1 to the intermediate voltage generating circuit CMFB1.

[0043] One end of the NMOS transistor N3 is connected to the output terminal Toutm1, the other end is connected to the intermediate voltage generating circuit CMFB1, and a voltage VLIM1 is applied to the gate. The voltage VLIM1 is, for example, higher than the reference voltage VCMREF1 and is a voltage that turns on the NMOS transistor N3. The maximum voltage value Vmaxm of the signal OUTM1 is determined based on the voltage VLIM1. When the signal OUTM1 is smaller than the maximum voltage value Vmaxm, the voltage value of the signal OUTMLIM1 becomes the voltage value of the signal OUTM1. In other words, the limiter circuit LIM1 transmits the signal OUTM1 as the signal OUTMLIM1 to the intermediate voltage generating circuit CMFB1. On the other hand, when the signal OUTM1 is equal to or greater than the maximum voltage value Vmaxm, the voltage value of the signal OUTMLIM1 becomes the maximum voltage value Vmaxm. In other words, the limiter circuit LIM1 transmits the maximum voltage value Vmaxm to the intermediate voltage generating circuit CMFB1 as the signal OUTMLIM1.

[0044] 1.1.4 Configuration of intermediate voltage generation circuit The circuit configuration of the intermediate voltage generating circuit CMFB1 will be described with reference to Fig. 4. Fig. 4 is a circuit diagram showing an example of the intermediate voltage generating circuit CMFB1.

[0045] The intermediate voltage generating circuit CMFB1 includes resistor elements R2 and R3, which have the same resistance value.

[0046] One end of the resistive element R2 is connected to the limiter circuit LIM1, and the other end is connected to a node ND4.

[0047] One end of the resistive element R3 is connected to the node ND4, and the other end is connected to the limiter circuit LIM1.

[0048] Since the resistance values ​​of the resistor elements R2 and R3 are the same, the intermediate voltage generating circuit CMFB1 transmits the average value of the voltage value of the signal OUTPLIM1 and the voltage value of the signal OUTMLIM1 to the node ND4 as the feedback voltage VCMFB1.

[0049] 1.2 Feedback operation The feedback operation of the power amplifying device 1 according to this embodiment will be described with reference to Fig. 5. Fig. 5 is a flowchart showing the feedback operation of the power amplifying device 1. Of the first feedback operation and the second feedback operation, the second feedback operation will be described below.

[0050] The limiter circuit LIM1 generates a signal OUTPLIM1 based on the voltage VLIM1 and the signal OUTP1, and generates a signal OUTMLIM1 based on the voltage VLIM1 and the signal OUTM1 (S10).

[0051] Next, the intermediate voltage generating circuit CMFB1 generates the average value of the voltage value of the signal OUTPLIM1 and the voltage value of the signal OUTMLIM1 (S11).

[0052] Next, the intermediate voltage generating circuit CMFB1 transmits the average value generated in S11 as a feedback voltage VCMFB1 to the TCFBm1 terminal of the first operational amplifier A1 and the TCFBm2 terminal of the second operational amplifier A2 (S12).

[0053] 1.3 Effects The configuration according to this embodiment can improve the operational reliability of the power amplifier device. The effect of this embodiment will be described below with reference to Fig. 6. Fig. 6 is a diagram for explaining the effect of the power amplifier device 1 according to this embodiment.

[0054] 6 shows waveforms of the signal OUTP1, the signal OUTM1, and the signal difference (OUTP1-OUTM1) between the signals OUTP1 and OUTM1. In the example of FIG. 6, the reference voltage VCMREF1 is set to a voltage lower than the voltage VCC / 2 and higher than the voltage VSS.

[0055] When the amplitudes of the signals OUTP1 and OUTM1 are small (area [1]), the signals OUTP1 and OUTM1 are not clipped (non-clipped). When not clipped, the amplitudes of the signals OUTP1 and OUTM1 swing symmetrically up and down, and the feedback voltage VCMFB1 is maintained at a constant value equal to the reference voltage VCMREF1.

[0056] On the other hand, when the amplitudes of the signals OUTP1 and OUTM1 are large (region [2]), the signals OUTP1 and OUTM1 are clipped on the voltage VSS side. At this time, the first feedback operation increases the amplitude of the unclipped signal OUTP1 or OUTM1, so the signals OUTP1 and OUTM1 are no longer symmetrical up and down.

[0057] In this embodiment, the following operation is performed as the second feedback operation. The limiter circuit LIM1 limits the maximum voltage value Vmax of the signals OUTP1 and OUTM1 based on the voltage VLIM1. Therefore, the voltage values ​​of the signals OUTPLIM1 and OUTMLIM1 are equal to or less than the maximum voltage value Vmax determined based on the voltage VLIM1. The limiter circuit LIM1 transmits the signals OUTPLIM1 and OUTMLIM1 to the intermediate voltage generating circuit CMFB1. The intermediate voltage generating circuit CMFB1 generates an average value of the voltage value of the signal OUTPLIM1 and the voltage value of the signal OUTMLIM1, and transmits the average value as a feedback voltage VCMFB1 to the first operational amplifier A1 and the second operational amplifier A2. Since the voltage values ​​of the signals OUTPLIM1 and OUTMLIM1 are limited to be equal to or less than the maximum voltage value Vmax, the feedback voltage VCMFB1 is maintained at a constant value equal to the reference voltage VCMREF1 even when the amplitude of the signals OUTP1 and OUTM1 is large. That is, according to the configuration of this embodiment, the variation in the midpoint potential of the signals OUTP1 and OUTM1 is reduced.

[0058] In addition, during non-clipping and clipping, the gain of the first operational amplifier A1 is a constant value Rf1 / Rs1, and the gain of the second operational amplifier A2 is a constant value Rf2 / Rs2, which makes it possible to suppress deterioration of the distortion of the signals OUTP1, OUTM1, and OUTP1-OUTM1.

[0059] Therefore, according to this embodiment, the operational reliability of the power amplifier device can be improved.

[0060] 1.4 First variant A power amplifying device 1 according to a first modification of the first embodiment will be described. In the power amplifying device 1 according to this modification, the configurations of the first operational amplifier A1 and the second operational amplifier A2 are different from those of the first embodiment. The following description will focus on the differences from the first embodiment.

[0061] 1.4.1 First Op-Amp Configuration The circuit configuration of the first operational amplifier A1 will be described with reference to Fig. 7. Fig. 7 is a circuit diagram showing an example of the first operational amplifier A1. Note that the second operational amplifier A2 has a similar configuration to the first operational amplifier A1.

[0062] In the first operational amplifier A1, the first transconductance circuit Gm_DFB, the second transconductance circuit Gm_CFB, and the resistive element R1 are omitted. The first operational amplifier A1 further includes a first voltage controlled voltage source A_DFB, and a second voltage controlled voltage source A_CFB.

[0063] The first power supply voltage terminal of the first voltage-controlled voltage source A_DFB is connected to the node ND5, and the second power supply voltage terminal is connected to the node ND9. The non-inverting input terminal of the first voltage-controlled voltage source A_DFB is connected to the TDFBp1 ​​terminal of the first operational amplifier A1, and the inverting input terminal is connected to the TDFBm1 terminal of the first operational amplifier A1. The first voltage-controlled voltage source A_DFB outputs a voltage difference dVdfb between a voltage Vinp1 applied to the non-inverting input terminal from the node ND1 and a voltage Vinm1 applied to the inverting input terminal from the node ND2. The amplification factor of the first voltage-controlled voltage source A_DFB is set to an arbitrary value.

[0064] The first power supply voltage terminal of the second voltage-controlled voltage source A_CFB is connected to the node ND9, and the second power supply voltage terminal is grounded. The second voltage-controlled voltage source A_CFB outputs a voltage difference dVcfb between a reference voltage VCMREF1 applied to the non-inverting input terminal from the node ND3 and a feedback voltage VCMFB1 applied to the inverting input terminal from the node ND4. The amplification factor of the second voltage-controlled voltage source A_CFB is set to an arbitrary value.

[0065] Other configurations of the first operational amplifier A1 are similar to those in FIG. 2 of the first embodiment.

[0066] A voltage Vd obtained by combining the voltage difference dVdfb and the voltage difference dVcfb is applied to the driver stage circuit DS. The driver stage circuit DS amplifies the voltage Vd and outputs the amplified voltage to drive the PMOS transistor P1 and the NMOS transistor N1 in a push-pull configuration.

[0067] 1.4.2 Effects The configuration according to this modification provides the same effects as those of the first embodiment.

[0068] 1.5 Second variant A power amplifying device 1 according to a second modification of the first embodiment will be described. In the power amplifying device 1 according to this modification, the configuration of the limiter circuit LIM1 is different from that of the first embodiment. The following description will focus on the differences from the first embodiment.

[0069] 1.5.1 Limiter circuit configuration The circuit configuration of the limiter circuit LIM1 will be described with reference to Fig. 8. Fig. 8 is a circuit diagram showing a limiter circuit for a high-side amplifier as an example of the limiter circuit LIM1.

[0070] The limiter circuit LIM1 includes PMOS transistors P2 and P3.

[0071] One end of the PMOS transistor P2 is connected to the output terminal Toutp1, the other end is connected to the intermediate voltage generating circuit CMFB1, and a voltage VLIM1 is applied to the gate. The voltage VLIM1 is, for example, lower than the reference voltage VCMREF1 and is a voltage that turns on the PMOS transistor P2. A minimum voltage value Vminp of the signal OUTP1 is determined based on the voltage VLIM1. When the signal OUTP1 is greater than the minimum voltage value Vmin, the voltage value of the signal OUTPLIM1 becomes the voltage value of the signal OUTP1. In other words, the limiter circuit LIM1 transmits the signal OUTP1 as the signal OUTPLIM1 to the intermediate voltage generating circuit CMFB1. On the other hand, when the signal OUTP1 is equal to or lower than the minimum voltage value Vminp, the voltage value of the signal OUTPLIM1 becomes the minimum voltage value Vminp. In other words, the limiter circuit LIM1 transmits the minimum voltage value Vminp as the signal OUTPLIM1 to the intermediate voltage generating circuit CMFB1.

[0072] One end of the PMOS transistor P3 is connected to the output terminal Toutm1, the other end is connected to the intermediate voltage generating circuit CMFB1, and a voltage VLIM1 is applied to the gate. The voltage VLIM1 is, for example, lower than the reference voltage VCMREF1 and is a voltage that turns on the PMOS transistor P3. A minimum voltage value Vminm of the signal OUTM1 is determined based on the voltage VLIM1. When the signal OUTM1 is greater than the minimum voltage value Vminm, the voltage value of the signal OUTMLIM1 becomes the voltage value of the signal OUTM1. In other words, the limiter circuit LIM1 transmits the signal OUTM1 as the signal OUTMLIM1 to the intermediate voltage generating circuit CMFB1. On the other hand, when the signal OUTM1 is equal to or lower than the minimum voltage value Vminm, the voltage value of the signal OUTMLIM1 becomes the minimum voltage value Vminm. In other words, the limiter circuit LIM1 transmits the minimum voltage value Vminm to the intermediate voltage generating circuit CMFB1 as the signal OUTMLIM1.

[0073] 1.5.2 Feedback Action The feedback operation of the power amplifying device 1 according to this modification will be described below. The flowchart showing the second feedback operation of the power amplifying device 1 according to this modification is the same as that of FIG.

[0074] 1.5.3 Effects In this modification, as a second feedback operation, the limiter circuit LIM1 limits the minimum voltage value Vmin of the signals OUTP1 and OUTM1 based on the voltage VLIM1. Therefore, the voltage values ​​of the signals OUTPLIM1 and OUTMLIM1 are equal to or greater than the minimum voltage value Vmin determined based on the voltage VLIM1. For example, when the reference voltage VCMREF1 is set to a voltage higher than the voltage VCC / 2 and lower than the voltage VCC, when the amplitudes of the signals OUTP1 and OUTM1 increase, the signals OUTP1 and OUTM1 are clipped on the voltage VCC side. However, since the voltage values ​​of the signals OUTPLIM1 and OUTMLIM1 are limited to equal to or greater than the minimum voltage value Vmin, the configuration according to this modification reduces the variation in the midpoint potential of the signals OUTP1 and OUTM1, as in the first embodiment.

[0075] Furthermore, according to the configuration of this modification, like the first embodiment, it is possible to suppress deterioration of the distortion of the signals OUTP1, OUTM1, and OUTP1-OUTM1.

[0076] 2. Second embodiment A power amplifying device 1 according to the second embodiment will be described. The power amplifying device 1 according to this embodiment differs from the first embodiment in that it includes a BTL amplifier (hereinafter also referred to as a "high-side amplifier HS") including a third operational amplifier A3 and a fourth operational amplifier A4. The first embodiment is a 1ch (1 channel) power amplifying device, while the second embodiment is a 2ch (2 channel) power amplifying device. Compared to a power amplifying device including two power amplifying devices of the first embodiment, in the second embodiment, the power consumed by the high-side amplifier HS is shared by the low-side amplifier LS, thereby enabling highly efficient operation. The following description will focus on the differences from the first embodiment.

[0077] 2.1 Circuit configuration of power amplifier The circuit configuration of the power amplifying device 1 according to this embodiment will be described with reference to Fig. 9. Fig. 9 is a circuit diagram showing an example of the power amplifying device 1.

[0078] The power amplifying device 1 further includes a buffer circuit BUF, a first voltage line 4, and a first voltage terminal T3.

[0079] The buffer circuit BUF generates a voltage VCC / 2 as a divided voltage between the power supply voltage line 2 and the ground voltage line 3 .

[0080] A first voltage line 4 is connected to the first voltage terminal T3, and a voltage VCC / 2 is supplied from a buffer circuit BUF.

[0081] The BTL amplifier including the first operational amplifier A1 and the second operational amplifier A2 (hereinafter also referred to as a "low-side amplifier LS") further includes switches SW1 and SW2.

[0082] The switch SW1 is connected to the first power supply voltage terminal of the first operational amplifier A1 and switches the connection between the first power supply voltage terminal of the first operational amplifier A1 and the power supply voltage line 2, and the connection between the first power supply voltage terminal of the first operational amplifier A1 and the first voltage line 4.

[0083] The switch SW2 is connected to the first power supply voltage terminal of the second operational amplifier A2 and switches the connection between the first power supply voltage terminal of the second operational amplifier A2 and the power supply voltage line 2, and the connection between the first power supply voltage terminal of the second operational amplifier A2 and the first voltage line 4.

[0084] For example, when the amplitudes of the signals OUTP1 and OUTM1 are small (for example, when the voltage values ​​(voltage values ​​with respect to the voltage VCC) of the signals OUTP1 and OUTM1 are less than the voltage VCC / 2), the switches SW1 and SW2 are connected to the first voltage wiring 4. As a result, the voltages VCC / 2 and VSS are applied to the first operational amplifier A1 and the second operational amplifier A2.

[0085] On the other hand, when the amplitude of the signals OUTP1 and OUTM1 is large (for example, when the voltage value (voltage value with respect to the voltage VCC) of the signal OUTP1 or OUTM1 is equal to or greater than the voltage VCC / 2), the switches SW1 and SW2 are connected to the power supply voltage line 2. As a result, the voltages VCC and VSS are applied to the first operational amplifier A1 and the second operational amplifier A2.

[0086] In the low-side amplifier LS, the reference voltage VCMREF1 is, for example, a voltage VCC / 4.

[0087] The high-side amplifier HS includes input terminals Tinp2 and Tinm2, output terminals Toutp2 and Toutm2, resistor elements Rs3 and Rs4, a third operational amplifier A3, a fourth operational amplifier A4, resistor elements Rf3 and Rf4, switches SW3 and SW4, a limiter circuit LIM2, and an intermediate voltage generating circuit CMFB2.

[0088] The input terminals Tinp2 and Tinm2 correspond to the input terminals Tinp1 and Tinm1 of the low-side amplifier LS, respectively.

[0089] The output terminals Toutp2 and Toutm2 correspond to the output terminals Toutp1 and Toutm1 of the low-side amplifier LS, respectively.

[0090] The resistive elements Rs3 and Rs4 correspond to the resistive elements Rs1 and Rs2 of the low-side amplifier LS, respectively.

[0091] The TDFBp3 terminal, the TCFBp3 terminal, the TDFBm3 terminal, and the TCFBm3 terminal of the third operational amplifier A3 correspond to the TDFBp1 ​​terminal, the TCFBp1 terminal, the TDFBm1 terminal, and the TCFBm1 terminal of the first operational amplifier A1 of the low-side amplifier LS. The third operational amplifier A3 has a similar configuration to the first operational amplifier A1.

[0092] The TDFBp4 terminal, the TCFBp4 terminal, the TDFBm4 terminal, and the TCFBm4 terminal of the fourth operational amplifier A4 correspond to the TDFBp2 terminal, the TCFBp2 terminal, the TDFBm2 terminal, and the TCFBm2 terminal, respectively, of the second operational amplifier A2 of the low-side amplifier LS. The fourth operational amplifier A4 has a similar configuration to the second operational amplifier A2.

[0093] The resistive elements Rf3 and Rf4 correspond to the resistive elements Rf1 and Rf2 of the low-side amplifier LS, respectively.

[0094] The switch SW3 is connected to the second power supply voltage terminal of the third operational amplifier A3 and switches the connection between the second power supply voltage terminal of the third operational amplifier A3 and the ground voltage wiring 3, and the connection between the second power supply voltage terminal of the third operational amplifier A3 and the first voltage wiring 4. The switch SW3 corresponds to the switch SW1 of the low-side amplifier LS.

[0095] The switch SW4 is connected to the second power supply voltage terminal of the fourth operational amplifier A4, and switches the connection between the second power supply voltage terminal of the fourth operational amplifier A4 and the ground voltage wiring 3, and the connection between the second power supply voltage terminal of the fourth operational amplifier A4 and the first voltage wiring 4. The switch SW4 corresponds to the switch SW2 of the low-side amplifier LS.

[0096] For example, when the amplitudes of the signals OUTP2 and OUTM2 are small (for example, when the voltage values ​​of the signals OUTP2 and OUTM2 (voltage values ​​relative to the voltage VSS) are equal to or greater than the voltage VCC / 2), the switches SW3 and SW4 are connected to the first voltage wiring 4. As a result, the voltages VCC and VCC / 2 are applied to the third operational amplifier A3 and the fourth operational amplifier A4.

[0097] On the other hand, when the amplitude of the signals OUTP2 and OUTM2 is large (for example, when the voltage value of the signal OUTP2 or OUTM2 (voltage value with respect to the voltage VSS) is less than the voltage VCC / 2), the switches SW3 and SW4 are connected to the ground voltage wiring 3. As a result, the voltages VCC and VSS are applied to the third operational amplifier A3 and the fourth operational amplifier A4.

[0098] The limiter circuit LIM2 corresponds to the limiter circuit LIM1 of the low-side amplifier LS. The limiter circuit LIM2 has a similar configuration to the limiter circuit LIM1 of the second modification of the first embodiment.

[0099] The intermediate voltage generating circuit CMFB2 corresponds to the intermediate voltage generating circuit CMFB1 of the low-side amplifier LS. The intermediate voltage generating circuit CMFB2 has a similar configuration to that of the intermediate voltage generating circuit CMFB1.

[0100] The signals INP2 and INM2 correspond to the signals INP1 and INM1 of the low-side amplifier LS, respectively.

[0101] The nodes ND11 and ND12 correspond to the nodes ND1 and ND2 of the low-side amplifier LS, respectively.

[0102] The voltages Vinp2 and Vinm2 correspond to the voltages Vinp1 and Vinm1 of the low-side amplifier LS, respectively.

[0103] The reference voltage VCMREF2 and the feedback voltage VCMFB2 correspond to the reference voltage VCMREF1 and the feedback voltage VCMFB1, respectively, of the low-side amplifier LS. The reference voltage VCMREF2 is, for example, a voltage 3VCC / 4.

[0104] The nodes ND13 and ND14 correspond to the nodes ND3 and ND4 of the low-side amplifier LS, respectively.

[0105] The signals OUTP2 and OUTM2 correspond to the signals OUTP1 and OUTM1 of the low-side amplifier LS, respectively.

[0106] The voltage VLIM2 and the signals OUTPLIM2 and OUTMLIM2 correspond to the voltage VLIM1 and the signals OUTPLIM1 and OUTMLIM1 of the low-side amplifier LS, respectively.

[0107] 2.2 Feedback operation The feedback operation of the power amplifying device 1 according to this embodiment will be described below. The flowchart showing the second feedback operation in the low-side amplifier LS and the high-side amplifier HS of the power amplifying device 1 according to this embodiment is similar to that of FIG.

[0108] 2.3 Effects The configuration according to this embodiment provides the same effects as the first embodiment.

[0109] Also, similarly to the first embodiment, the variation in the midpoint potential of the signals OUTP1 and OUTM1 and the variation in the midpoint potential of the signals OUTP2 and OUTM2 are reduced. This maximizes the high efficiency range of the power amplifier 1. Furthermore, because the variation in the midpoint potential is reduced, in a power amplifier including two or more power amplifiers of the second embodiment, even if the output terminals of the low-side amplifiers LS and the output terminals of the high-side amplifiers HS are erroneously connected, the potential difference between the erroneously connected output terminals is small, so that the short-circuit current value that flows is small. This eliminates the need to provide a circuit for protecting against short circuits with other channels.

[0110] Of course, this embodiment can also be applied to the first modified example of the first embodiment.

[0111] 3. Modifications, etc. As described above, the power amplification device (1) according to the embodiment includes a first amplifier (A1) that receives a plurality of voltages at a plurality of input terminals and outputs a first output signal (OUTP1), a second amplifier (A2) that receives a plurality of voltages at a plurality of input terminals and outputs a second output signal (OUTM1), a first circuit (LIM1) that outputs a third signal (OUTPLIM1) that limits the magnitude of the voltage value of the first output signal (OUTP1) and a fourth signal (OUTMLIM1) that limits the magnitude of the voltage value of the second output signal (OUTM1), and a second circuit (CMFB1) that transmits an average value of the voltage value of the third signal (OUTPLIM1) and the voltage value of the fourth signal (OUTMLIM1) as a first feedback voltage (VCMFB1) to the first amplifier (A1) and the second amplifier (A2).

[0112] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0113] In the flowcharts described in the above embodiments, the order of the processes can be changed as much as possible.

[0114] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0115] 1...power amplifier, 2...power supply voltage wiring, 3...ground voltage wiring, A1...first operational amplifier, A2...second operational amplifier, A3...third operational amplifier, A4...fourth operational amplifier, LIM1, LIM2...limiter circuit, CMFB1, CMFB2...intermediate voltage generating circuit, Rs1, Rs2, Rf1, Rf2, R1 to R3...resistance elements, Gm_DFB...first transconductance circuit, Gm_CFB...second transconductance circuit, DS...driver stage circuit, N1 to N3, P1 to P3...transistors, A_DFB...first voltage controlled voltage source, A_CFB...second voltage controlled voltage source

Claims

1. a first amplifier that receives a plurality of voltages on a plurality of input terminals and outputs a first output signal; a second amplifier receiving a plurality of voltages at a plurality of input terminals and outputting a second output signal; a first circuit that outputs, as a third signal, a first maximum voltage value of the first output signal based on a third voltage, or the first output signal smaller than the first maximum voltage value, based on a magnitude of a voltage value of the first output signal, and outputs, as a fourth signal, a second maximum voltage value of the second output signal based on the third voltage, or the second output signal smaller than the second maximum voltage value, based on a magnitude of a voltage value of the second output signal; a second circuit that transmits an average value of a voltage value of the third signal and a voltage value of the fourth signal as a first feedback voltage to the first amplifier and the second amplifier; Equipped with Among the plurality of input terminals of the first amplifier, a first voltage corresponding to a first input signal is applied to the first non-inverting input terminal; a second voltage corresponding to a second input signal is applied to the first inverting input terminal; A first reference voltage is applied to the second non-inverting input terminal; The first feedback voltage is applied to a second inverting input terminal, Among the plurality of input terminals of the second amplifier, The first voltage is applied to a third inverting input terminal, The second voltage is applied to a third non-inverting input terminal, The first reference voltage is applied to a fourth non-inverting input terminal, The first feedback voltage is applied to a fourth inverting input terminal, the third signal is a signal in which the magnitude of a voltage value of the first output signal is limited based on the third voltage that is higher than the first reference voltage, and the fourth signal is a signal in which the magnitude of a voltage value of the second output signal is limited based on the third voltage. Power amplifier.

2. a first amplifier that receives a plurality of voltages on a plurality of input terminals and outputs a first output signal; a second amplifier receiving a plurality of voltages at a plurality of input terminals and outputting a second output signal; a first circuit that outputs, based on a magnitude of a voltage value of the first output signal, a first minimum voltage value of the first output signal based on a third voltage, or the first output signal greater than the first minimum voltage value, as a third signal, and that outputs, based on a magnitude of a voltage value of the second output signal, a second minimum voltage value of the second output signal based on the third voltage, or the second output signal greater than the second minimum voltage value, as a fourth signal; a second circuit that transmits an average value of a voltage value of the third signal and a voltage value of the fourth signal as a first feedback voltage to the first amplifier and the second amplifier; Equipped with Among the plurality of input terminals of the first amplifier, a first voltage corresponding to a first input signal is applied to the first non-inverting input terminal; a second voltage corresponding to a second input signal is applied to the first inverting input terminal; A first reference voltage is applied to the second non-inverting input terminal; The first feedback voltage is applied to a second inverting input terminal, Among the plurality of input terminals of the second amplifier, The first voltage is applied to a third inverting input terminal, The second voltage is applied to a third non-inverting input terminal, The first reference voltage is applied to a fourth non-inverting input terminal, The first feedback voltage is applied to a fourth inverting input terminal, the third signal is a signal in which a voltage value of the first output signal is limited based on the third voltage that is lower than the first reference voltage, and the fourth signal is a signal in which a voltage value of the second output signal is limited based on the third voltage. Power amplifier.

3. the first circuit limits the first maximum voltage value of the first output signal and the second maximum voltage value of the second output signal.

2. The power amplifier according to claim 1.

4. the first amplifier generates the first output signal based on a first current based on the first voltage and the second voltage, and a second current based on the first reference voltage and the first feedback voltage.

4. The power amplifier device according to claim 1.

5. the first amplifier generates the first output signal based on a voltage difference between the first voltage and the second voltage and a voltage difference between the first reference voltage and the first feedback voltage.

4. The power amplifier device according to claim 1.

6. the first circuit includes a first transistor and a second transistor; the first output signal is input to one end of the first transistor, the other end is connected to the second circuit, and the third voltage is applied to a gate of the first transistor; the second output signal is input to one end of the second transistor, the other end is connected to the second circuit, and the third voltage is applied to a gate of the second transistor; 6. The power amplifier device according to claim 1.

7. the second circuit includes a first resistive element and a second resistive element; one end of the first resistor element is connected to the first circuit, and the other end is connected to the first amplifier and the second amplifier; one end of the second resistor element is connected to the first amplifier and the second amplifier, and the other end is connected to the first circuit; 7. The power amplifier device according to claim 1.

8. The resistance value of the first resistor element is equal to the resistance value of the second resistor element.

8. The power amplifier according to claim 7.

9. a third amplifier that receives a plurality of voltages on a plurality of input terminals and outputs a third output signal; a fourth amplifier that receives a plurality of voltages on a plurality of input terminals and outputs a fourth output signal; a third circuit that outputs a fifth signal obtained by limiting the magnitude of a voltage value of the third output signal, and a sixth signal obtained by limiting the magnitude of a voltage value of the fourth output signal; a fourth circuit that transmits an average value of a voltage value of the fifth signal and a voltage value of the sixth signal as a second feedback voltage to the third amplifier and the fourth amplifier; Equipped with 9. The power amplifier device according to claim 1.

10. Among the plurality of input terminals of the third amplifier, a fourth voltage corresponding to the third input signal is applied to the fifth non-inverting input terminal; A fifth voltage corresponding to the fourth input signal is applied to the fifth inverting input terminal; A second reference voltage is applied to the sixth non-inverting input terminal, The second feedback voltage is applied to a sixth inverting input terminal, Among the plurality of input terminals of the fourth amplifier, The fourth voltage is applied to the seventh inverting input terminal, the fifth voltage is applied to the seventh non-inverting input terminal; the second reference voltage is applied to the eighth non-inverting input terminal; The second feedback voltage is applied to an eighth inverting input terminal.

10. The power amplifier according to claim 9.

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