Methods for Amplitude Estimation in NISQ (Noisy Intermediate Scale Quantum) Computers

Abstract

An embodiment relates to a method for estimating the amplitude of a unitary operator U within an error ε by using a quantum processor configurable to implement the unitary operator U on a quantum circuit, which has a maximum depth S and can perform the unitary operator no more than D times in a single execution. A schedule of iterations n=1 to N based on the error ε and the number D is determined. Each iteration n is characterized by a schedule parameter kn, where kn≦D for all n and k n grows at a sub-exponential rate. Iterations n can be performed sequentially. In each iteration, the quantum processor calculates the unitary operator U by k n The quantum circuit is configured to execute the algorithm by sequentially applying it to the quantum circuit, and the non-quantum processor then estimates the amplitude of the unitary operator based on the resulting measured states.

Description

[Technical field]

[0001] The disclosure is made in the field of quantum algorithms, and in particular the disclosure provides methods for implementing basic primitives for amplitude estimation in a manner that reduces the depth of the quantum circuitry required while remaining faster than classical algorithms. [Background technology]

[0002] Amplitude estimation (AE) is a quantum algorithm with many applications, e.g., counting in mathematical finance and approximation in Monte Carlo methods. A general setup for the amplitude amplification algorithm is as follows: We are given a unitary U that transforms U|0>=sin(θ)|0>+cos(θ)|1> (we call this an oracle, and the number of times the circuit runs the algorithm for U is called the oracle call count T). The goal of the amplitude estimation (AE) algorithm is to estimate cos(θ) within an additive error ε.

[0003] The AE literature focuses on minimizing the number of oracle calls required for the above tasks. The number of oracle calls required for AE tasks is O(1 / ε 2 ) whereas in the quantum configuration it is known to be O(1 / ε), which theoretically provides a significant speedup.

[0004] However, this algorithm is unitary U k for k=O(1 / ε), in other words, applying the unitary U sequentially O(1 / ε) times, thus involving highly deep quantum circuits. (In some cases, particularly for real-world applications such as Monte Carlo estimation, the unitary U may itself have considerable depth, with the error ε being as large as 10 -3Note that if we want to stay on the order of , this depth would be multiplied by 1000 in the above algorithm, making the algorithm completely intractable for NISQ quantum computers.)

[0005] As a result of previous research showing some progress in applying AE to NISQ devices, non-patent document 1 can be mentioned. The document provides a template and the algorithm is based on a set of parameters (k1, k2, ... , k t ) and a constant N shot The purpose of this is to execute a schedule of operations defined in the following manner:

[0006] Parameter k i For each of these, shot Over k iterations (depending on the noise of the operation), we iteratively iterate over the unitary U i The test is applied once and the resulting condition is measured.

[0007] After this operation, classical post-processing of the measurement results is performed to provide the required amplitude estimate. i =2 i It is claimed that a quantum algorithm can provide a good estimate of the amplitude if the schedule is defined by the parameters (starting from i=0, up to i=log(1 / ε)). kfor k=O(1 / ε), so the depth of the quantum circuit remains prohibitively large. The main advantage of the algorithm in this paper is that it replaces the computationally expensive quantum phase estimation step that was required in addition to the oracle calls in Brassard et al.'s original AE algorithm with classical post-processing. Thus, although Non-Patent Document 1 reduces the depth of Brassard et al.'s original AE algorithm by avoiding the quantum phase estimation step, the number of sequential oracle calls to be performed remains O(1 / ε), so the algorithm far exceeds the performance of NISQ machines. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Suzuki et al., “Amplitude Estimation Without Phase Estimation”(Quantum Inf Process 19, 75 (2020). https: / / doi.org / 10.1007 / s11128-019-2565-2) Summary of the Invention

[0009] An embodiment relates to a method for estimating the amplitude of a unitary operator U to within an error ε by using a quantum processor configurable to implement the unitary operator U on a quantum circuit having a maximum circuit depth S and capable of performing the unitary operator no more than D times in a single execution. A schedule of iterations n=1 to N based on the error ε and the number of iterations D is determined. Each iteration n is determined by a schedule parameter k n For all n, k n ≦D and k ngrows at a sub-exponential rate. The iterations n may be performed sequentially. In each iteration, the quantum processor is configured to sequentially apply a unitary operator U kn times to the quantum circuit, and the quantum processor executes the quantum circuit. A resulting state of the quantum circuit is measured. And the non-quantum processor estimates the amplitude of the unitary operator based on the measured resulting states.

[0010] Other aspects include components, devices, systems, improvements, methods, processes, applications, computer readable media, and other technology related to any of the above. [Brief description of the drawings]

[0011] [Figure 1] 1 is a flow diagram of a method for estimating the amplitude of a unitary operator, according to an embodiment. [Diagram 2] FIG. 2 is a block diagram illustrating components of an exemplary machine that can read instructions from a machine-readable medium and execute them on a processor (or controller) according to an embodiment.

[0012] The drawings depict various embodiments of the present disclosure for illustrative purposes only. Those skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods shown herein may be employed without departing from the principles of the disclosure described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The following description relates to preferred embodiments for purposes of illustration only. It should be noted from the following discussion that alternative embodiments of the structures and methods disclosed herein are readily recognizable as viable alternatives that may be employed without departing from the principles of the disclosure.

[0014] Embodiments relate to maintaining quantum advantage over classical algorithms while reducing the depth of the AE circuit (e.g., for low-depth Noisy Intermediate-Scale Quantum (NISQ) computers, etc.). NISQ computers may have less than 1000, 500, or 300 qubits. In one aspect, new AE algorithms are provided via different schedules that provide a tradeoff between quantum circuit depth and the acceleration of quantum algorithms achieved compared to classical algorithms. In some embodiments, the schedule parameter α, for example for index α∈(0,2], is reduced.

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[0015] After each iteration, the resulting quantum state is measured and stored. After execution of the schedule, the amplitude of the unitary operator U may be determined by a non-quantum processor based on the measured states. In some embodiments, the iterations need not be performed sequentially from n=1 to N. For example, the iterations may be performed in parallel (e.g., on separate quantum circuits).

[0016] Note that the Suzuki et al. AE algorithm can be implemented when D is O(1 / ε), but our algorithm works better when D is a small constant (e.g., D can even be as small as 5).

[0017] The tradeoff for this schedule is DT=1 / ε 2 where T is the total number of oracle calls.

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[0018] FIG. 1 is a flowchart of a method 100 for estimating the amplitude of a unitary operator U within an error ε according to an embodiment. The method uses a quantum processor configurable to implement the unitary operator U on a quantum circuit. The quantum circuit has a maximum depth of S and can implement the unitary operator within D times in a single execution. The steps of the method can be executed in a different order, and the method can include different, additional, or fewer steps.

[0019] A schedule of iterations from n = 1 to N is determined based on the error ε and the number D (S110). Each iteration n is characterized by a schedule parameter k n All n for k n ≦ D, and k n increases at a rate less than exponential. The iterations n can be executed sequentially. In each iteration n, the quantum processor is configured to sequentially apply the unitary operator U to the quantum circuit kn times (S120), and the quantum processor executes the quantum circuit (S130). The state resulting from the execution of the quantum circuit is measured (S140) (e.g., the state of each qubit in the quantum circuit is recorded). The resulting state is stored. Then, the non-quantum processor estimates the amplitude of the unitary operator based on the stored resulting state (S150). In some embodiments, before the end of the schedule (e.g., after each iteration or after every two or more iterations), the non-quantum processor performs one or more amplitude estimations. In some embodiments, S110, S120, and S150 are performed by the non-quantum processor, and S130 and S140 are performed by the quantum processor. In some embodiments, D < O(1 / ε) and T < O(1 / ε 2 ), where

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[0020] FIG. 2 is a block diagram illustrating components of an exemplary machine that can read instructions from a machine-readable medium and execute them on one or more processors (or controllers), according to some embodiments. Specifically, FIG. 2 illustrates a schematic representation of an exemplary type of machine, computer system 200. Computer system 200 can be used to execute instructions 224 (e.g., program labels or software) that cause the machine to perform any one or more of the methodologies (or processes) described herein. In some embodiments, the machine can operate as a standalone device or as a device connected (e.g., networked) with other machines. In a networked deployment, the machine can operate in the role of a server machine or a client machine in a server-client network environment, or as a peer machine in a P2P (or distributed) network environment. Note that FIG. 2 and its description describe an exemplary device. Other machines with quantum processors may behave differently and may have more, fewer, or different components.

[0021] The machine may be a server computer, a client computer, a personal computer (PC), a tablet PC, a set-top box (STB), a smartphone, an IoT appliance, a network router, switch or bridge, or any machine capable of executing instructions 224 (sequential or otherwise) that specify actions to be performed by the machine. Additionally, although only a single machine is illustrated, the term "machine" shall be deemed to include any collection of machines that individually or collectively execute instructions 224 to perform any one or more of the methodologies discussed herein.

[0022] The exemplary computer system 200 includes one or more processing units, such as processors 201, 202. For example, the processor 202 can be a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a controller, a state machine, one or more application specific integrated circuits (ASICs), one or more radio frequency integrated circuits (RFICs), or any combination thereof.

[0023] Quantum processor 201 may be one or more physical devices that perform operations based specifically on quantum effects, one or more devices with such behavior, or any other device that may be reasonably interpreted as exhibiting quantum processing behavior. Quantum processor 201 exploits the laws of quantum mechanics to perform operations. Quantum processor 201 generally uses qubits (qubits, quantum bits) instead of bits used in classical computers. Classical bits are always either 0 or 1 in value. Roughly speaking, qubits have a nonzero probability of being in a superposition or linear combination of 0 and 1. Because quantum processor 201 can perform operations on qubits, allowing qubits to exist in a superposition of 0 and 1 can result in significantly enhanced performance for certain computational tasks. For example, Shor's algorithm describes how to use a quantum processor to efficiently factor large integers, which has considerable applications and implications in cryptography. Grover's search algorithm describes how to use a quantum processor to efficiently search large sets of information, such as lists or databases.

[0024] Quantum processor 201 may be capable of constructing and executing one or more quantum circuits, which are models of quantum computations that are sequences of quantum gates, which are reversible transformations on one or more qubits.

[0025] The computer system 200 also includes a main memory 205. The computer system may include a storage unit 216. The processors 201, 202, the memory 204, and the storage unit 216 communicate via a bus 208.

[0026] Additionally, computer system 200 may include static memory 206 and a display driver 210 (which may drive a plasma display panel (PDP), liquid crystal display (LCD), or projector that may display UI 105 to a user). Computer system 200 may also include an alphanumeric input device 212 (e.g., a keyboard), a cursor control device 214 (e.g., a mouse, trackball, joystick, motion sensor, or other pointing device), a signal generating device 218 (e.g., a speaker), and a network interface device 220, which are also configured to communicate over bus 208.

[0027] The storage unit 216 includes a machine-readable medium 222 having stored thereon instructions 224 (e.g., software as illustrated in FIG. 2) embodying any one or more of the methodologies or functions described herein. The instructions 224 may also reside, completely or at least partially, within the main memory 205 or within the processors 201 and / or 202 (e.g., within a processor's cache memory) during execution by the computer system 200, and the main memory 205 and the processors 201 and / or 202 may be accompanied by a machine-readable medium. The instructions 224 may be transmitted or received over a network 226 via the network interface device 220.

[0028] While machine-readable medium 222 is shown to be a single medium in the exemplary embodiment, the term "machine-readable medium" should be considered to include a single medium or multiple media capable of storing instructions 224 (e.g., a centralized or distributed database, or associated caches and servers). The term "machine-readable medium" should also be considered to include any medium capable of storing instructions 224 for execution by a machine, causing the machine to perform any one or more of the methodologies disclosed herein. The term "machine-readable medium" includes, but is not limited to, data repositories in the form of solid-state memory, optical media, and magnetic media.

[0029] Although specific embodiments and applications have been illustrated and described, it is to be understood that the invention is not limited to the precise construction and components disclosed herein, and various other modifications, changes and variations, which will be apparent to those skilled in the art, may be made in the arrangement, operation and details of the methods and apparatus disclosed herein without departing from the spirit and scope defined in this disclosure.

[0030] Although the detailed description includes many specific details, these should not be interpreted as limiting the scope of the present invention, but merely as illustrating different examples. It should be noted that the scope of the present disclosure also includes other embodiments not described in detail above. Various other modifications, changes, and variations that will be apparent to those skilled in the art can be made in the arrangement, operation, and details of the methods and apparatus disclosed herein without departing from the spirit and scope defined in the appended claims. Therefore, the scope of the present invention should be determined by the appended claims and their legal equivalents.

Claims

1. 1. A method of estimating an amplitude of a unitary operator U to within an error ε by using a quantum processor configurable to implement the unitary operator U on a quantum circuit, the quantum circuit being capable of performing the unitary operator no more than a number D of times in a single execution, where D<O(1 / ε), the method comprising: determining a schedule of iterations n=1 to N based on the error ε and the number D, each iteration n having a schedule parameter k ｎ and k for all n ｎ ≦D, k ｎ grows at a sub-exponential rate and T<O(1 / ε ２ ) and [0010] and performing said iterations n sequentially, The unitary operator U is k ｎ configuring the quantum processor to sequentially apply a plurality of quantum circuits to the quantum circuit; said quantum processor executing said quantum circuit; measuring a resulting state of the quantum circuit; and and and a non-quantum processor estimating an amplitude of the unitary operator U based on the measured resulting states.

2. 2. The method of claim 1, wherein T<O(1 / ε ２ ) × 50 / 100.

3. 3. The method of claim 2, wherein T<O(1 / ε ２ ) × 20 / 100.

4. 2. The method of claim 1 , Ｎ =D, the method.

5. 10. The method of claim 1 , [0025] That is, the method.

6. 2. The method of claim 1 , ｎ is α where α is a constant and greater than zero.

7. The method of claim 6, wherein α∈(0,2].

8. 7. The method of claim 6, [0030] That is, the method.

9. 7. The method of claim 6, [0045] That is, the method.

10. 7. The method of claim 6, wherein α is T<O(1 / ε ２ )in [0050] It is predetermined that:

11. 7. The method of claim 6, wherein increasing α increases ε and decreases the execution time of the schedule, and decreasing α decreases ε and increases the execution time of the schedule.

12. The method of claim 1 , wherein one or more of the n iterations are performed multiple times.

13. 2. The method of claim 1, wherein for each iteration n, the quantum processor converts the unitary operator U into k ｎ times for the quantum circuit A ｎ , A being the depth of the unitary operator U.

14. 10. The method of claim 1 , wherein the maximum circuit depth of the quantum circuit is less than 50.

15. 10. The method of claim 1, wherein the quantum processor is comprised within a NISQ computer with less than 500 qubits.

16. 2. The method of claim 1, wherein D=5.

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