Pseudorandom number generator, analog-to-digital converter, and electronic device

Abstract

To provide a pseudo random number generator, an analog-to-digital converter, and an electronic apparatus which can prolong the cycle of a pseudo random number with a simple circuit configuration and a small additional power consumption.SOLUTION: The pseudo random number generator includes: a main random number generation unit 10 using a first linear feedback shift register operating at a main clock CLK1; a sub random number generation unit 20 using one or more second linear feedback shift registers operating at a sub clock CLK2 having a period longer than that of the main clock CLK1; and a bit selection switch circuit 30 for replacing a part of the output bit of each register constituting the first linear feedback shift register with a replacement bit as a part of the output bit of each register constituting the second linear feedback shift register, wherein the output bit of the main random number generation unit 10 is output as a pseudo random number.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a pseudorandom number generator, an analog-to-digital converter, and an electronic device that can lengthen the period of pseudorandom numbers with a simple circuit configuration and little additional power consumption. [Background technology]

[0002] Conventionally, there is a method using a linear feedback shift register as an algorithm for generating pseudorandom numbers. This method has the advantage that it requires a small amount of calculation and can be easily implemented in digital circuits. A linear feedback shift register is a shift register that takes as input the exclusive OR of some of the bits that compose it. It is known that the output of a linear feedback shift register is synchronized with a clock and randomly outputs values ​​of 0 and 1 for a certain period. In addition, by selecting the register used for the input of the exclusive OR, a linear feedback shift register can generate pseudorandom numbers of M-sequence, which is a sequence of random numbers with the longest period that can be set.

[0003] An example of the use of pseudorandom numbers is dithering, which is a method for intentionally superimposing random noise on an input signal, to reduce quantization errors that occur during analog-to-digital conversion. A noise generator using pseudorandom numbers is used as the source of this noise.

[0004] Patent Document 1 discloses a random number generator that can obtain random numbers with a period that is the least common multiple of two independent number sequences by taking the exclusive OR of the two sequences. Patent Document 2 discloses a random number generation circuit that can arbitrarily change the tap position of a linear feedback shift register, that is, the position of the register that is used as the input for the exclusive OR. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2001-142682 A [Patent Document 2] JP 2006-215825 A Summary of the Invention [Problem to be solved by the invention]

[0006] Here, since the period of the M sequence is (2^n)-1, for example, in the case of an 8-bit linear feedback shift register, the maximum value of the period of the output sequence is 255. For example, when the reference clock frequency is 1 MHz, this results in a very short period of 0.255 ms. If the period of the random numbers is short, it may cause inconvenience depending on the application. For example, when the random number output is used for dithering to reduce quantization errors that occur during analog-to-digital conversion, if the period of the random numbers is not long enough relative to the sampling time of the analog-to-digital conversion, the two periodic processes may affect each other, resulting in beats in the conversion results and problems such as deterioration of conversion accuracy. For this reason, it is generally desirable for the random numbers to have a long period.

[0007] A common method to increase the period of random numbers generated by a linear feedback shift register is to simply increase the number of registers that make up the shift register from which the random numbers are generated. For example, a 16-bit linear feedback shift register will have a maximum period of 65535, and a 24-bit linear feedback shift register will have a maximum period of 16777215. The period of the random numbers increases as the number of registers increases.

[0008] However, simply increasing the number of registers that make up the shift register has the problem of a large increase in power consumption. Generally, the power consumption of a digital circuit increases in proportion to the number of registers, assuming the operation rate of the registers is the same. For example, a 16-bit shift register consumes twice as much power as an 8-bit shift register, and a 24-bit shift register consumes three times as much power as an 8-bit shift register.

[0009] The present invention has been made in consideration of the above, and aims to provide a pseudo-random number generator, an analog-to-digital converter, and an electronic device that can lengthen the period of pseudo-random numbers with a simple circuit configuration and little additional power consumption. [Means for solving the problem]

[0010] In order to solve the above-mentioned problems and achieve the object, the present invention comprises a main random number generation unit using a first linear feedback shift register that operates on a main clock, a sub-random number generation unit using one or more second linear feedback shift registers that operate on a sub-clock having a longer period than that of the main clock, and a bit selection switching circuit that replaces a portion of the output bits of each register that constitutes the first linear feedback shift register with replacement bits that are a portion of the output bits of each register that constitutes the second linear feedback shift register, and outputs the output bits of the main random number generation unit as pseudo-random numbers.

[0011] Also, in the present invention, in the above-mentioned invention, tap positions of a feedback signal in the first linear feedback shift register correspond to a primitive polynomial, and the first linear feedback shift register generates a pseudo-random number sequence of an M sequence.

[0012] Furthermore, in the present invention, in the above-mentioned invention, tap positions of a feedback signal in the first linear feedback shift register correspond to a primitive polynomial whose degree is the number of registers, and the first linear feedback shift register generates an M-sequence pseudo-random number sequence, and tap positions of a feedback signal in the second linear feedback shift register correspond to a primitive polynomial whose degree is the number of registers, and the second linear feedback shift register generates an M-sequence pseudo-random number sequence.

[0013] In addition, in the above invention, the first linear feedback shift register and the one or more second linear feedback shift registers have different numbers of registers, and the two or more second linear feedback shift registers have different numbers of registers.

[0014] In the present invention, in the above-mentioned invention, the sub-clocks of the two or more second linear feedback shift registers are different from each other.

[0015] In addition, in the above invention, the bit selection switching circuit comprises a bit selector arranged in the first linear feedback shift register between a previous stage register in which an output bit to be replaced is held and a next stage register to which the replacement bit is output, the bit selector selecting the replacement bit and replacing the output bit from the previous stage register with the replacement bit and outputting the replacement bit to the next stage register, a connection line connecting an output tap position of the replacement bit and the bit selector, and a bit selection control unit generating a bit selection signal for switching the output bit from the previous stage register to the replacement bit using the main clock and the sub clock, and outputting the bit selection signal to the bit selector.

[0016] In the present invention, in the above-mentioned invention, the bit selection control section generates the bit selection signal at a constant cycle or at an irregular cycle.

[0017] The present invention also comprises a main random number generation unit using a linear feedback shift register that operates in clock, one or more sub-random number generation units that operate on a sub-clock having a longer period than that of the main clock and output pseudo-random numbers, and a bit selection switching circuit that replaces some of the output bits of each register that constitutes the linear feedback shift register with replacement bits that are some of the output bits of the sub-random number generation units, and outputs the output bits of the main random number generation unit as pseudo-random numbers.

[0018] The present invention also provides an analog-to-digital converter that generates a dither signal using pseudo-random numbers output by the pseudo-random number generator according to any one of the above inventions.

[0019] The present invention also provides an electronic device comprising the pseudorandom number generator according to any one of the above aspects, and a circuit using the pseudorandom numbers output by the pseudorandom number generator. Effect of the Invention

[0020] According to the present invention, it is possible to lengthen the period of pseudo-random numbers with a simple circuit configuration and little additional power consumption. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of a pseudo-random number generator according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a timing chart illustrating generation of a bit selection signal by the bit selection control section. [Diagram 3] FIG. 3 is a circuit diagram showing the configuration of a random number generating unit corresponding to the main random number generating unit. [Figure 4] FIG. 4 is a diagram showing the period of the pseudo-random numbers generated by the random number generator shown in FIG. 3 as a random walk. [Diagram 5] FIG. 5 is a diagram showing the period of the pseudorandom numbers generated by the pseudorandom number generator shown in FIG. 1 as a random walk. [Figure 6] FIG. 6 is a schematic diagram showing a configuration of a pseudo-random number generator according to a modified embodiment of the present invention. [Figure 7] FIG. 7 is a block diagram showing the configuration of an analog-to-digital converter that uses the pseudo-random number generator shown in FIG. 1 to generate a dither signal, and a differential pressure transmission line that is an example of an electronic device that uses this analog-to-digital converter. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

[0023] <Configuration of pseudorandom number generator> FIG. 1 is a circuit diagram showing the configuration of a pseudorandom number generator 1 according to an embodiment of the present invention. As shown in FIG. 1, the pseudorandom number generator 1 includes a main random number generating unit 10, a sub-random number generating unit 20, and a bit selection switching circuit 30. The main random number generating unit 10 is a first linear feedback shift register that operates with a main clock CLK1. The sub-random number generating unit 20 is a second linear feedback shift register that operates with a sub-clock CLK2 having a period longer than that of the main clock CLK1. The bit selection switching circuit 30 performs selection switching to replace some output bits of the registers R1 to R8 constituting the first linear feedback shift register with replacement bits that are some output bits of the registers R01 to R16 constituting the second linear feedback shift register. The pseudorandom number generator 1 outputs the output bits of the main random number generating unit 10 as a pseudorandom number output signal S1.

[0024] As a result, a part of each register value of the first linear feedback shift register is continuously replaced with a part of the register value of the second linear feedback shift register. This is a partial change of the seed signal of the first linear feedback shift register at the time of replacing the register value, and also a sequential change of the phase of the period of the first linear feedback shift register alone. Therefore, the pseudorandom number output signal S1 is output as a pseudorandom number in which the periodicity of the pseudorandom number sequence of the first linear feedback shift register alone is disturbed and the period is lengthened.

[0025] The tap positions of the feedback signal in the first linear feedback shift register correspond to a primitive polynomial. Therefore, the first linear feedback shift register generates a pseudorandom number sequence of an M sequence. Specifically, the first linear feedback shift register is an 8-bit shift register and generates a pseudorandom number sequence of an M sequence according to an 8th degree primitive polynomial X 8 +X 6 +X 5 +X 4Each feedback signal is taken from tap positions P8, P6, P5, and P4 corresponding to +1. Each feedback signal is subjected to an exclusive OR by an exclusive OR circuit 11, and then returned to the register R1 and output as a pseudorandom number output signal S1. This first linear feedback shift register is a Fibonacci linear feedback shift register. An initial seed signal is set in advance. Therefore, this first linear feedback shift register has a maximum period length of 255 by itself.

[0026] On the other hand, the tap positions of the feedback signal in the second linear feedback shift register correspond to the primitive polynomial. Therefore, the first linear feedback shift register generates a pseudorandom number sequence of the M sequence. Specifically, the second linear feedback shift register is a 16-bit shift register and generates a pseudorandom number sequence of the 16th degree primitive polynomial X 16 +X 15 +X 13 +X 4 Each feedback signal is taken from tap positions P16, P15, P13, and P04 corresponding to +1. Each feedback signal is exclusive-ORed by an exclusive-OR circuit 21 and then returned to the register R01. This exclusive-OR signal generates an M-sequence pseudo-random number sequence. This first linear feedback shift register is a Fibonacci linear feedback shift register. An initial seed signal is set in advance. Therefore, this second linear feedback shift register has a maximum period length of 65535 by itself. Note that a Galois linear feedback shift register may be used instead of the above-mentioned Fibonacci linear feedback shift register.

[0027] Here, the bit selection switching circuit 30 has bit selectors 41 and 42, connection lines L1 and L2, and a bit selection control unit 43. The bit selector 41 is disposed between the register R1 and the register R2. The register value of the register R1 is input to the bit selector 41, and the register value of the register R02, which is a replacement bit, is input from the tap position P02 between the register R02 and the register R03 of the sub-random number generator 20 via the connection line L1. The bit selector 41 is connected to the bit selection control unit 43. The bit selection control unit 43 generates a bit selection signal SP as a set trigger pulse that switches the register value of the register R1 to the register value of the register R02 using the main clock CLK1 and the sub-clock CLK2, and outputs the signal to the bit selector 41. The bit selector 41 replaces the register value of the register R1 with the register value of the register R02 according to the bit selection signal SP, and outputs the signal to the register R2.

[0028] Similarly, the bit selector 42 is disposed between the register R6 and the register R7. The bit selector 42 receives the register value of the register R6, and also receives the register value of the register R15, which is a replacement bit, from the tap position P15 between the registers R15 and R16 of the sub-random number generator 20 via the connection line L2. The bit selector 42 is connected to the bit selection control unit 43. The bit selection control unit 43 generates a bit selection signal SP and outputs it to the bit selector 42. The bit selector 42 replaces the register value of the register R6 with the register value of the register R15 in accordance with the bit selection signal SP and outputs it to the register R7.

[0029] 2 is a timing chart explaining the generation of the bit selection signal SP by the bit selection control unit 43. The main clock CLK1 and the sub-clock CLK2 are input to the bit selection control unit 43. As described above, the period of the sub-clock CLK2 is longer than the period of the main clock CLK1 (see FIGS. 2(a) and (b)). Specifically, the period of the sub-clock CLK2 is set to 16 times the period of the main clock CLK1.

[0030] When the bit selection control unit 43 detects the rising edge of the sub-clock CLK2 at time t1, it detects the rising edge of the main clock CLK1 at time t2 immediately after time t1. Then, the bit selection control unit 43 generates a bit selection signal SP that rises at time t2 and has the same pulse width as the main clock CLK1 (see FIG. 2(c)). Then, this bit selection signal SP is sent to the bit selectors 41 and 42.

[0031] 2, the main clock CLK1 and the sub-clock CLK2 are asynchronous, but the main clock CLK1 and the sub-clock CLK2 may be synchronous. In this case, for example, the sub-clock CLK2 is generated by dividing the main clock CLK1.

[0032] In this embodiment, the sub-clock CLK2 is set to have 16 times the period of the main clock CLK1, or 1 / 16 times the frequency. The number of shift registers in the sub-random number generation unit 20 is set to 16 bits, which is twice the number of shift registers in the main random number generation unit 10. Therefore, the power consumption of the sub-random number generation unit 20 is 1 / 8 that of the main random number generation unit 10. This means that the pseudo-random number generator 1 only requires an additional power consumption of 1 / 8 of that of a conventional pseudo-random number generator based only on the main random number generation unit 10. In other words, with an increase in power consumption of 1 / 8, it is possible to obtain pseudo-random numbers with a longer period than that of a conventional pseudo-random number generator based only on the main random number generation unit 10, with a simple configuration.

[0033] <Comparison between the period of the conventional example and the period of this embodiment> Fig. 3 is a circuit diagram showing the configuration of a random number generation unit 10a corresponding to the main random number generation unit 10. Fig. 4 is a diagram showing, by a random walk, the period of the pseudo-random numbers generated by the random number generation unit 10a shown in Fig. 3. Fig. 5 is a diagram showing, by a random walk, the period of the pseudo-random numbers generated by the pseudo-random number generator 1 shown in Fig. 1.

[0034] Conventional random number generator 10a shown in Fig. 3 is the main random number generator 10 without bit selectors 41 and 42, and generates random numbers only by a first linear feedback shift register. In other words, conventional random number generator 10a is a linear feedback shift register that configures an 8-bit M sequence.

[0035] Figure 4 shows the pseudo-random numbers generated by the conventional random number generator 10a shown in Figure 3 as a random walk. The conventional random number generator 10a is operated by the same clock as the main clock CLK1 of the main random number generator 10. Here, the random walk is a continuous addition of +1 if the bit output is 1, or -1 if it is 0.

[0036] As shown in FIG. 4, the conventional random number generator 10a is an M sequence with a period of 255 clocks (bits), and when the main clock CLK1 is 8 MHz, the period is approximately 0.03 ms.

[0037] In contrast, the pseudo-random number generator 1 of this embodiment has a period of about 32,000,000 clocks (bits), which is about 4 seconds when the main clock CLK1 is 8 MHz. Therefore, the pseudo-random number generator 1 can lengthen the period of the conventional random number generation unit 10a corresponding to the main random number generation unit 10 by more than 100,000 times.

[0038] Moreover, in this embodiment, it is possible to achieve a much longer period than that of the conventional random number generating unit 10a with little additional power consumption and with a simple configuration.

[0039] Although the main random number generation unit 10 and the sub random number generation unit 20 each use an M-sequence linear feedback shift register, the present invention is not limited to this and may be a non-M-sequence linear feedback shift register. In other words, the feedback polynomial may be a linear feedback shift register that is not a primitive polynomial.

[0040] <Modification> Fig. 6 is a schematic diagram showing the configuration of a pseudorandom number generator 1a according to a modification of the embodiment of the present invention. As shown in Fig. 6, in this modification, a plurality of sub-random number generating units 20a and 20b corresponding to the sub-random number generating unit 20 are provided, and a portion of the output bits of the first linear feedback shift register of the main random number generating unit 10 is replaced with a portion of the output bits of each linear feedback shift register of the sub-random number generating units 20a and 20b. In this case as well, the timing of bit replacement is controlled by the bit selection control unit 43.

[0041] The sub-clocks CLK2 and CLK3 have longer periods than the main clock CLK1, but may have different periods. In this case, the sub-clock CLK2 is used to generate and output a signal at the rising edge of the bit selection signal SP2 to the bit selector that is the target of bit replacement by the sub-random number generation unit 20a. The sub-clock CLK3 is used to generate and output a signal at the rising edge of the bit selection signal SP3 to the bit selector that is the target of bit replacement by the sub-random number generation unit 20b.

[0042] In addition, the number of registers in the shift registers of the sub random number generation units 20a and 20b may be less than the number of registers in the shift register of the main random number generation unit 10. In Fig. 6, the number of registers in the shift register of the sub random number generation unit 20a is made greater than the number of registers in the shift register of the main random number generation unit 10, and the number of registers in the shift register of the sub random number generation unit 20b is made less than the number of registers in the shift register of the main random number generation unit 10. In other words, the number of registers in the shift registers of the sub random number generation units 20, 20a, and 20b may be the same as the number of registers in the shift register of the main random number generation unit 10, or may be different.

[0043] In the above embodiment and modified example, the tap positions of the connection lines L1 and L2 on the sub-random number generation units 20, 20a, and 20b side correspond one-to-one to the bit selectors of the main random number generation unit 10, but this is not limiting, and the connection lines L1 and L2 may be branched to connect one tap position on the sub-random number generation units 20, 20a, and 20b side to multiple bit selectors. Furthermore, the tap positions on the sub-random number generation unit side, the positions of the bit selectors, or the number of them may be set arbitrarily.

[0044] The sub-random number generators 20, 20a, and 20b do not have to be linear feedback shift registers, but may be any that operate on sub-clocks CLK2 and CLK3 having a longer period than the period of the main clock CLK1 to output pseudo-random numbers. In this case, the pseudo-random numbers generated by the sub-random number generators 20, 20a, and 20b may use, for example, a sequence of numbers stored in advance in a memory.

[0045] The bit selection control unit 43 may generate the bit selection signals SP, SP2, and SP3 at a fixed period or at an irregular period based on an irregular pattern, etc. When the bit selection signals SP, SP2, and SP3 are generated at an irregular period, the irregular period is added to the period of the sub-random number generation units 20, 20a, and 20b, and the period of the pseudo-random numbers can be further extended.

[0046] Furthermore, the bit selection control section 43 sends the bit selection signal SP that converts only one bit to the bit selectors 41 and 42, but the bit selection signal SP may be a signal that replaces two or more consecutive bits with substitution bits. Also, the bit selection signal SP may be a pulse group with an irregular pattern.

[0047] <Application Examples> 7 is a block diagram showing the configuration of an analog-to-digital converter 110 that uses the pseudo-random number generator 1 shown in FIG. 1 to generate a dither signal, and a differential pressure transmission line 100 that is an example of an electronic device that uses this analog-to-digital converter 110. As shown in FIG. 7, the differential pressure transmission line 100 has a sensor unit 101, an analog-to-digital converter 110, a digital signal processing circuit 105, and a communication unit 106.

[0048] The sensor unit 101 detects pressure guiding pipes connected to different positions of a pipe through which a fluid flows, and detects the pressure difference between the pressures in the pressure guiding pipes and the static pressure, and may also include a temperature sensor.

[0049] The analog-to-digital converter 110 has a dither signal generator 102, an adder 103, and an analog-to-digital conversion circuit 104. The dither signal generator 102 outputs an analog dither signal to the adder 103 using the long-period pseudo-random numbers generated by the pseudo-random number generator 1. The adder 103 adds the dither signal to the analog sensor signal output from the sensor unit 101.

[0050] The analog-to-digital converter 104 converts the analog input signal onto which the dither signal is superimposed into a digital signal. Since the analog input signal has the dither signal superimposed, it is possible to reduce quantization errors. In particular, since the period of the pseudorandom number of the dither signal is sufficiently long relative to the sampling time of the analog-to-digital conversion, there is no problem of deteriorating conversion accuracy.

[0051] The digital signal processing circuit 105 calculates the pressure value detected by the sensor unit 101 based on the input digital signal. Then, the communication unit 106 sequentially transmits the pressure value to the outside. At this time, information such as the pressure value may be encrypted.

[0052] The differential pressure transmission line 100 is an example of an electronic device using the pseudo-random number generator 1. The electronic device is not limited to using the pseudo-random numbers generated by the pseudo-random number generator 1 for generating a dither signal, and may use pseudo-random numbers in other circuits or units.

[0053] Furthermore, many of the recent IoT devices use analog sensors and analog-to-digital converters, and the pseudo-random number generator 1 can be applied to electronic devices including these IoT devices.

[0054] In addition, each configuration illustrated in the above-mentioned embodiment is a functional schematic, and does not necessarily have to be physically configured as illustrated. In other words, the form of distribution and integration of each device and component is not limited to that illustrated, and all or part of them can be functionally or physically distributed and integrated in any unit according to various usage conditions, etc. [Explanation of symbols]

[0055] 1,1a Pseudorandom number generator 10 Main Random Number Generator 10a Random number generator 11,21 Exclusive OR circuit 20, 20a, 20b Sub-random number generator 30-bit selection switch circuit 41,42 bit selector 43-bit selection control section 100 Differential pressure transmission line 101 Sensor section 102 Dither Signal Generator 103 Adder 104 Analog-to-digital conversion circuit 105 Digital signal processing circuit 106 Communications Department 110 Analog-to-Digital Converter CLK1 Main clock CLK2, CLK3 sub clock L1,L2 connection wire P4, P5, P6, P8, P02, P04, P13, P15, P16 Tap position R1, R2, R6, R7, R01, R02, R03, R15 registers S1 Pseudorandom output signal SP, SP2, SP3 bit selection signal At time t1 and t2

Claims

1. A main random number generator using a first linear feedback shift register that operates on a main clock; a sub-random number generator using one or more second linear feedback shift registers that operate on a sub-clock having a period longer than that of the main clock; a bit selection / switching circuit for replacing a part of output bits of each register constituting the first linear feedback shift register with a replacement bit which is a part of output bits of each register constituting the second linear feedback shift register; and outputs output bits of the main random number generating unit as pseudo-random numbers.

2. a tap position of a feedback signal in the first linear feedback shift register corresponds to a primitive polynomial, and the first linear feedback shift register generates an M-sequence pseudo-random number sequence.

2. The pseudorandom number generator of claim 1.

3. a tap position of a feedback signal in the first linear feedback shift register corresponds to a primitive polynomial whose degree is the number of registers, and the first linear feedback shift register generates an M-sequence pseudorandom number sequence; a tap position of a feedback signal in the second linear feedback shift register corresponds to a primitive polynomial whose degree is the number of registers, and the second linear feedback shift register generates a pseudo-random number sequence of an M sequence.

2. The pseudorandom number generator of claim 1.

4. The number of registers of the first linear feedback shift register and the one or more second linear feedback shift registers are different, and the number of registers of the two or more second linear feedback shift registers may be different. A pseudorandom number generator according to any one of claims 1 to 3.

5. The sub-clocks of the two or more second linear feedback shift registers are different. A pseudorandom number generator according to any one of claims 1 to 3.

6. The bit selection switching circuit includes: a bit selector disposed in the first linear feedback shift register between a previous stage register in which an output bit to be replaced is held and a next stage register to which the replacement bit is output, the bit selector selecting the replacement bit, replacing the output bit from the previous stage register with the replacement bit, and outputting the resultant to the next stage register; a connection line connecting between the output tap position of the permutation bit and the bit selector; a bit selection control unit that generates a bit selection signal for switching an output bit from the previous stage register to the replacement bit by using the main clock and the sub clock, and outputs the bit selection signal to the bit selector; A pseudorandom number generator according to any one of claims 1 to 3, comprising:

7. The bit selection control unit generates the bit selection signal at a constant cycle or an irregular cycle.

7. The pseudorandom number generator of claim 6.

8. A dither signal is generated using the pseudorandom numbers output by the pseudorandom number generator according to any one of claims 1 to 7. Analog to digital converter.

9. A pseudorandom number generator according to any one of claims 1 to 7, comprising a circuit using pseudorandom numbers output by the pseudorandom number generator. electronic equipment.

Images