Switched capacitor converter, controller circuit and control method thereof, and electronic device using same

Abstract

To provide a switched capacitor converter with improved efficiency.SOLUTION: A first drive unit 210 alternately switches a state φ1 in which odd-numbered switches are on, and even-numbered switches are off among m switches SW1 to SWm and a state φ1B in which the odd-numbered switches are off, and the even-numbered switches are on among the m switches SW1 to SWm according to a first clock CLK1. A second drive unit 220 alternately switches a state φ2 in which (m-1) switching circuits 110_1 to 110_(m-1) output output voltage VOUT and a state φ2B in which the (m-1) switching circuits 110_1 to 110_(m-1) output ground voltage 0 V according to a second clock CLK2. A phase difference controller 230 controls a phase difference between the first clock CLK1 and the second clock CLK2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to switched capacitor converters. [Background technology]

[0002] DC / DC converters and charge pumps are used to generate voltages higher or lower than the power supply voltage. DC / DC converters that use inductors as an element to store energy can control the output voltage by using the inductor, but they have a problem of reduced efficiency due to switching operations.

[0003] In applications that require high efficiency, switched capacitor converters (charge pumps) that do not require inductors as energy storage elements are used. One type of switched capacitor converter known is one that operates in resonance by adding a resonant inductor in series with the flying capacitor (called a resonant switched capacitor converter). A resonant switched capacitor converter enables zero current switching (soft switching), enabling highly efficient operation.

[0004] As one form of resonant switched capacitor converter, a configuration in which an inductor is added to a Dickson type charge pump (switched tank converter) is also known. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 9917517 Summary of the Invention [Problem to be solved by the invention]

[0006] It is in this context that the present disclosure has been made, and one of its exemplary objectives is to provide a switched capacitor converter with improved efficiency. [Means for solving the problem]

[0007] An embodiment of the present disclosure relates to a controller circuit for a switched capacitor converter, the switched capacitor converter including: an input line, an output line, a ground line, m (m≧3) switches connected in series between the input line and the output line, n (n≧2) LC circuits each including a capacitor and an inductor connected in series, a first end of each of the n LC circuits connected to an odd-numbered corresponding one of the connection nodes of the m switches, k (k≧1, k+n=m−1) capacitors each having a first end connected to an even-numbered corresponding one of the connection nodes of the m switches, a first switching circuit that applies an output voltage of the output line or a ground voltage of the ground line to a second end of each of the k capacitors, and a second switching circuit that applies an output voltage or a ground voltage of the ground line to a second end of each of the n LC circuits. The controller circuit includes a first drive unit that alternates between (i) a state in which odd-numbered switches among the m switches are on and even-numbered switches are off, and the first switching circuit applies a ground voltage, and (ii) a state in which odd-numbered switches among the m switches are off and even-numbered switches are on, and the first switching circuit applies an output voltage, in response to a first clock; a second drive unit that alternates between a state in which the second switching circuit applies an output voltage and a state in which it applies a ground voltage, in response to a second clock; and a phase difference controller that controls the phase difference between the first clock and the second clock.

[0008] Another aspect of the present disclosure relates to a switched capacitor converter, comprising an input line, an output line, a ground line, a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series between the input line and the output line, a first capacitor and a first inductor connected in series between a connection node of the first transistor and the second transistor and a first switching node, a second capacitor connected between the connection node of the second transistor and the third transistor and the second switching node, a third capacitor and a second inductor connected in series between the connection node of the third transistor and the fourth transistor and the third switching node, a fifth transistor connected between the output line and the first switching node, and a fifth transistor connected between the first switching node and the ground line. a sixth transistor connected between the output line and the second switching node, a seventh transistor connected between the output line and the second switching node, an eighth transistor connected between the second switching node and a ground line, a ninth transistor connected between the output line and a third switching node, and a tenth transistor connected between the third switching node and a ground line, a first drive unit that switches in opposite phases the set of the first and third transistors and the set of the second and fourth transistors, a second drive unit that switches in opposite phases the set of the fifth, seventh, and ninth transistors and the set of the sixth, eighth, and tenth transistors, and a phase difference controller that controls a phase difference between the switching of the first drive unit and the second drive unit.

[0009] Yet another embodiment of the present disclosure relates to a control method for a switched capacitor converter, the switched capacitor converter including an input line, an output line, a ground line, m (m≧3) switches connected in series between the input line and the output line, n (n≧2) LC circuits each including a capacitor and an inductor connected in series, a first end of each of the n LC circuits connected to an odd-numbered corresponding one of the connection nodes of the m switches, k (k≧1, k+n=m−1) capacitors each having a first end connected to an even-numbered corresponding one of the connection nodes of the m switches, a first switching circuit that applies an output voltage of the output line or a ground voltage of the ground line to a second end of each of the k capacitors, and a second switching circuit that applies an output voltage or a ground voltage of the ground line to a second end of each of the n LC circuits. The control method includes the steps of: (i) alternating between a state in which odd-numbered switches among the m switches are on and even-numbered switches are off, and the first switching circuit applies a ground voltage, and (ii) a state in which odd-numbered switches among the m switches are off and even-numbered switches are on, and the first switching circuit applies an output voltage, in accordance with a first clock; (ii) alternating between a state in which the second switching circuit applies an output voltage and a state in which it applies a ground voltage, in accordance with a second clock; and controlling a phase difference between the first clock and the second clock.

[0010] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc. are also valid aspects of the present invention. Effect of the Invention

[0011] According to certain aspects of the present disclosure, the efficiency of a switched capacitor converter can be improved. [Brief description of the drawings]

[0012] [Figure 1]FIG. 1 is a circuit diagram of a switched capacitor converter according to an embodiment. [Diagram 2] FIG. 2 is a time chart illustrating the operation of the switched capacitor converter of FIG. [Diagram 3] FIG. 3 is a circuit diagram of a switched capacitor converter according to an embodiment. [Figure 4] FIG. 4 is a waveform diagram of the coil current IL flowing through the inductor in the first state I to the fourth state IV. [Diagram 5] FIG. 5 shows the first state I of the switched capacitor converter of FIG. [Figure 6] FIG. 6 shows the second state II of the switched capacitor converter of FIG. [Figure 7] FIG. 7 illustrates the third state III of the switched capacitor converter of FIG. [Figure 8] FIG. 8 illustrates the fourth state IV of the switched capacitor converter of FIG. [Figure 9] FIG. 9 is a circuit diagram of a switched capacitor converter according to an embodiment. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a controller IC. [Figure 11] FIG. 11 is a time chart showing the operation of the controller IC of FIG. [Figure 12] FIG. 12 is a diagram illustrating an example of an electronic device including a switched capacitor converter. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0014] A controller circuit according to an embodiment controls a switched capacitor converter. The switched capacitor converter to be controlled includes an input line, an output line, a ground line, m (m≧3) switches connected in series between the input line and the output line, n (n≧2) LC circuits each including a capacitor and an inductor connected in series, the first terminal of each of the n LC circuits being connected to an odd-numbered corresponding one of the connection nodes of the m switches, k (k≧1, k+n=m−1) capacitors each having a first terminal connected to an even-numbered corresponding one of the connection nodes of the m switches, a first switching circuit that applies an output voltage of the output line or a ground voltage of the ground line to a second terminal of each of the k capacitors, and a second switching circuit that applies an output voltage or a ground voltage of the ground line to a second terminal of each of the n LC circuits. The controller circuit includes a first drive unit that alternates between (i) a state in which odd-numbered switches among the m switches are on and even-numbered switches are off, and the first switching circuit applies a ground voltage, and (ii) a state in which odd-numbered switches among the m switches are off and even-numbered switches are on, and the first switching circuit applies an output voltage, in response to a first clock; a second drive unit that alternates between a state in which the second switching circuit applies an output voltage and a state in which it applies a ground voltage, in response to a second clock; and a phase difference controller that controls the phase difference between the first clock and the second clock.

[0015] According to this configuration, it is possible to achieve high efficiency by satisfying the zero voltage switching (ZVS) condition instead of the resonance condition.

[0016] In one embodiment, the phase difference controller may feedback control the phase difference so that an error between a feedback signal corresponding to the output of the switched capacitor converter and a reference signal approaches zero. This allows the output of the switched capacitor converter to be maintained in a target state when the input voltage or load fluctuates. The output may be an output voltage, an output current, or another state.

[0017] In one embodiment, the phase difference controller may include a pulse width modulator that generates a pulse width modulated signal whose pulse width varies so that an error between a feedback signal corresponding to an output of the switched capacitor converter and a reference signal approaches zero, and a phase shift logic circuit that generates a first clock and a second clock having a phase difference corresponding to the pulse width of the pulse width modulated signal.

[0018] In one embodiment, M=4. In this case, the input voltage V IN It can generate an output voltage that is 1 / 4 of the input.

[0019] In one embodiment, the first switching circuit may include k first inverter circuits, each of which may include an output node connected to a second end of a corresponding one of the k capacitors, a high-side transistor connected between the output node and an output line, and a low-side transistor connected between the output node and a ground line.

[0020] In one embodiment, the second switching circuit may include n second inverter circuits, each of which may include an output node connected to the second end of a corresponding one of the n LC circuits, a high-side transistor connected between the output node and an output line, and a low-side transistor connected between the output node and a ground line.

[0021] In one embodiment, the m switches may be N-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

[0022] In one embodiment, the controller circuit may be monolithically integrated on a single semiconductor substrate. "Monolithic integration" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are monolithically integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate for adjusting the circuit constants. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0023] A switched capacitor converter according to one embodiment includes an input line, an output line, a ground line, a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series between the input line and the output line, a first capacitor and a first inductor connected in series between a connection node of the first transistor and the second transistor and a first switching node, a second capacitor connected between the connection node of the second transistor and the third transistor and a second switching node, a third capacitor and a second inductor connected in series between the connection node of the third transistor and the fourth transistor and the third switching node, a fifth transistor connected between the output line and the first switching node, and a fifth transistor connected between the first switching node and the ground line. a sixth transistor connected between the output line and the second switching node, a seventh transistor connected between the output line and the second switching node, an eighth transistor connected between the second switching node and a ground line, a ninth transistor connected between the output line and a third switching node, and a tenth transistor connected between the third switching node and a ground line, a first drive unit that switches in opposite phases the set of the first and third transistors and the set of the second and fourth transistors, a second drive unit that switches in opposite phases the set of the fifth, seventh, and ninth transistors and the set of the sixth, eighth, and tenth transistors, and a phase difference controller that controls a phase difference between the switching of the first drive unit and the second drive unit.

[0024] According to this configuration, it is possible to achieve high efficiency by satisfying the zero voltage switching (ZVS) condition instead of the resonance condition.

[0025] In one embodiment, the phase difference controller may feedback control the phase difference so that the error between the output of the switched capacitor converter and a target state of the output approaches zero.

[0026] In one embodiment, the phase difference controller may include a pulse width modulator that generates a pulse width modulated signal whose pulse width varies so that an error between an output of the switched capacitor converter and a target state of the output approaches zero, and may control the phase difference according to the pulse width of the pulse width modulated signal.

[0027] (Embodiment) The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions are omitted as appropriate. In addition, the embodiments are not intended to limit the invention, but are merely examples, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0028] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0029] Similarly, "a state in which component C is provided between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0030] Furthermore, "signal A (voltage, current) corresponds to signal B (voltage, current)" means that signal A has a correlation with signal B, specifically meaning (i) when signal A is signal B, (ii) when signal A is proportional to signal B, (iii) when signal A is obtained by level-shifting signal B, (iv) when signal A is obtained by amplifying signal B, (v) when signal A is obtained by inverting signal B, (vi) or any combination thereof. Those skilled in the art will understand that the scope of "corresponding to" is determined according to the types and applications of signals A and B.

[0031] The vertical and horizontal axes of the waveform diagrams and time charts referred to in this specification have been appropriately enlarged or reduced to facilitate understanding, and each waveform shown has been simplified or exaggerated or emphasized to facilitate understanding.

[0032] (Embodiment) 1 is a circuit diagram of a switched capacitor converter 100 according to an embodiment. The switched capacitor converter 100 converts an input voltage V IN The output voltage V OUT on output line 104.

[0033] The switched capacitor converter 100 includes an input line 102, an output line 104, a ground line 106, m (m≧3) switches SW1 to SWm, n (n≧2) LC circuits (also called LC resonant circuits or LC tank circuits) LC1 to LCn, k (k≧1, k+n=m−1) capacitors C2, C4, ..., a first switching circuit 110, a second switching circuit 120, and a controller IC (Integrated Circuit) 200.

[0034] The m switches SW1 to SWm are connected in series between the input line 102 and the output line 104. Although not limited thereto, the m switches SW1 to SWm may be configured with transistors such as MOSFETs. The m switches SW1 to SWm may be integrated into the controller IC 200. Two adjacent connection nodes of the multiple switches SW1 to SWm are denoted as N1, N2, ..., Nm-1 in order from the node closest to the input line 102.

[0035] Each of the n (n≧2) LC circuits LC1, LC2, ... LCn includes a capacitor and an inductor connected in series. Specifically, the i-th (1≦i≦n) LC circuit LCi includes a capacitor C(2×i-1) and an inductor Li. A first end of the i-th LC circuit LCi is connected to an odd-numbered corresponding one N(2×i-1) of the connection nodes N1 to Nm-1.

[0036] Of k capacitors C2, C4, ..., C(2×k), a first end of the j-th (1≦j≦k) capacitor C(2×j) is connected to an even-numbered corresponding one N(2×j) of the multiple connection nodes N1 to Nm-1.

[0037] The first switching circuit 110 couples the output voltage V OUT Alternatively, the ground voltage (0 V) of the ground line 106 is applied.

[0038] The second switching circuit 120 outputs an output voltage V OUT Or apply ground voltage 0V.

[0039] The controller IC 200 includes a first driver 210, a second driver 220, and a phase difference controller 230.

[0040] The first driver 210, in response to a first clock CLK1, switches between (i) a state φ1 in which the odd-numbered switches SW1, SW3... of the m switches SW1 to SWm are on and the even-numbered switches SW2, SW4... are off, and the first switching circuit 110 applies a ground voltage (0 V); and (ii) a state φ2 in which the odd-numbered switches SW1, SW3... are off and the even-numbered switches SW2, SW4... are on, and the first switching circuit 110 applies an output voltage V OUT The state φ1B in which the input is applied is alternately switched. B indicates a logical inversion and is indicated by a bar in the drawing.

[0041] The second driver 220 controls the second switching circuit 120 to generate the output voltage V OUT The state φ2 of applying a ground voltage and the state φ2B of applying a ground voltage are alternately switched.

[0042] The phase difference controller 230 controls the phase difference φd between the first clock CLK1 and the second clock CLK2.

[0043] Fig. 2 is a time chart illustrating the operation of the switched capacitor converter 100 of Fig. 1. The switched capacitor converter 100 transitions among four states I to IV. First state I The first drive unit 210 is in the state φ1, and the second drive unit 220 is in the state φ2B. Second State II The first drive unit 210 is in a state φ1, and the second drive unit 220 is in a state φ2. Third State III The first drive unit 210 is in the state φ1B, and the second drive unit 220 is in the state φ2 IV The first drive unit 210 is in the state φ1B, and the second drive unit 220 is in the state φ2B. When the phase difference φd is changed, the ratio of the time in the first state I and the third state III to the time in the second state II and the fourth state IV changes.

[0044] The above is the basic configuration of the switched capacitor converter 100. Next, the operation of the switched capacitor converter 100 will be explained, but it will be easier to understand if the number m of transistors is specified. Therefore, the configuration and operation for m=4, n=2, k=1 will be explained below.

[0045] 3 is a circuit diagram of a switched capacitor converter 100A according to an embodiment, omitting the controller IC 200. The first transistor M1 to the fourth transistor M4 correspond to the first switch SW1 to the fourth switch SWm in FIG.

[0046] The LC circuit LC1 includes a capacitor C1 and an inductor L1. The LC circuit LC2 includes a capacitor C3 and an inductor L2.

[0047] The first switching circuit 110 includes k (one) inverters INV2 corresponding to the k (one) capacitors C2. The inverter INV2 includes a seventh transistor M7 which is a high-side transistor and an eighth transistor M8 which is a low-side transistor.

[0048] The second switching circuit 120 includes n (two) inverters INV1, INV3 corresponding to n (two) LC circuits LC1, LC2. The output node of the inverter INV1 is connected to the second end of the corresponding LC circuit LC1, and includes a fifth transistor M5 which is a high-side transistor and a sixth transistor M6 which is a low-side transistor. The output node of the inverter INV3 is connected to the second end of the corresponding LC circuit LC2, and includes a ninth transistor M9 which is a high-side transistor and a tenth transistor M10 which is a low-side transistor.

[0049] The first transistor M1, the third transistor M3, and the eighth transistor M8 are on in state φ1 and off in state φ1B. The second transistor M2, the fourth transistor M4, and the seventh transistor M7 are off in state φ1 and on in state φ1B.

[0050] The fifth transistor M5 and the ninth transistor M9 are on in state φ2 and off in state φ2B. The sixth transistor M6 and the tenth transistor M10 are off in state φ2 and on in state φ2B.

[0051] Next, the operation of the switched capacitor converter 100A in FIG. 3 will be described.

[0052] Figure 4 shows the coil current I flowing through the inductor in states I to IV. L It should be noted that the currents flowing through the inductors L1 and L2 are similar. In the first state I, the coil current I L increases, and in the third state III, the coil current I L In the second state II and the fourth state IV, the voltage across the inductor is close to zero, so the coil current I L The coil current I L As can be seen from the waveforms in FIG. 1, the switched capacitor converter 100 is not operating at resonance.

[0053] The first state I to the fourth state IV will now be described in detail.

[0054] 5 is a diagram showing the first state I of the switched capacitor converter 100A of FIG. 3. The coil current I L1 flows through path X, and the coil current I L2 flows along path Y.

[0055] Looking at the first inductor L1, the voltage across it, ΔV L1 teeth ΔV L1 =V IN -V C1 It is.

[0056] When C1=C2=C3, the following relationship holds in the steady state: V C1 =VIN ×3 / 4 V C2 =V IN ×2 / 4 V C3 =V IN ×1 / 4 V OUT =V IN ×1 / 4

[0057] Then, in the first state I, the voltage ΔV across the first inductor L1 L1 teeth ΔV L1 =V IN -V C1 =V IN / 4 The coil current I L teeth, ΔV L1 / L=V IN It increases at a slope of / (4×L).

[0058] Looking at the second inductor L2, the voltage across it is ΔV L2 teeth ΔV L2 =V C2 -V C3 =V IN / 4 Therefore, the coil current I L2 too, ΔV L2 / L=V IN It increases at a slope of / (4×L).

[0059] Coil current I L1 and I L2 is negative immediately after the transition to the first state I, increases with time, and then becomes positive.

[0060] Current I flows in the first state I L1 , I L2 is not delivered to the load.

[0061] FIG. 6 is a diagram showing the second state II of the switched capacitor converter 100A of FIG.

[0062] Looking at the first inductor L1, the voltage across it, ΔV L1 teeth ΔV L1 =(V IN -V C1 )-V OUT ≒0V Therefore, the coil current I L1 does not change.

[0063] Looking at the second inductor L2, the voltage across it is ΔV L2 teeth ΔV L2 =(V C2 -V C3 )-V OUT ≒0V Therefore, the coil current I L2 does not change either.

[0064] Current I flows in the second state II L1 , I L2 is supplied to the load.

[0065] 7 is a diagram showing a third state III of the switched capacitor converter 100A of FIG. 3. In the third state III, the voltage ΔV across the first inductor L1 L1 teeth ΔV L1 =V C2 -V C1 =-V IN / 4 The coil current I L teeth, ΔV L1 / L=V IN It decreases at a slope of / (4×L).

[0066] Looking at the second inductor L2, the voltage across it is ΔV L2 teeth ΔV L2 =-V C3 =-V IN / 4 Therefore, the coil current I L2 too, ΔV L2 / L=V IN It decreases at a slope of / (4×L).

[0067] In the third state III, the coil current I L1 flows through loop X, and current I L2 flows in loop Y. Neither current is delivered to the load.

[0068] FIG. 8 illustrates a fourth state IV of the switched capacitor converter 100A of FIG.

[0069] Looking at the first inductor L1, the voltage across it, ΔV L1 teeth ΔV L1 =(V OUT +V C2 -V C1 )≒0 Therefore, the coil current I L1 does not change.

[0070] Looking at the second inductor L2, the voltage across it is ΔV L2 teeth ΔV L2 =(V OUT -V C3 )≒0V Therefore, the coil current I L2 does not change either.

[0071] In the fourth state IV, the current I L1 , I L2 is supplied to the load.

[0072] Referring to FIG. 4, the coil current I flows in the second state II and the fourth state IV. L1 ,I L2 , that is, the hatched area is supplied as power to the load.

[0073] The above is the operation of the switched capacitor converter 100 A. According to this switched capacitor converter 100 A, zero voltage switching can be realized, and efficiency can be improved.

[0074] 9 is a circuit diagram of a switched capacitor converter 100B according to an embodiment. In this embodiment, m=5, n=2, and k=2, and the switched capacitor converter 100B includes a first switch SW1 to a fifth switch SW5, LC circuits LC1 and LC2, capacitors C2 and C4, a first switching circuit 110, and a second switching circuit 120.

[0075] The LC circuit LC1 includes a capacitor C1 and an inductor L1. The LC circuit LC2 includes a capacitor C3 and an inductor L2.

[0076] The first switching circuit 110 may include k (2) inverters corresponding to the k (2) capacitors C2, C4, similar to the embodiment of Fig. 3. Similarly, the second switching circuit 120 may include n (2) inverters corresponding to the n (2) LC circuits LC1, LC2.

[0077] 10 is a circuit diagram showing a configuration example of the controller IC 200. The phase difference controller 230 feedback controls the phase difference φd so that the error between the output of the switched capacitor converter 100 and the target state of the output approaches zero. In this example, the controller IC 200 controls the output voltage V OUT to the target voltage V OUT(REF) The constant voltage control is performed to stabilize the output voltage.

[0078] The feedback pin FB of the controller IC200 has an output voltage V OUT The feedback signal V FB For example, the feedback signal V FB is the output voltage V OUT This is the voltage divided by resistors R1 and R2. If we omit resistors R1 and R2, the output voltage V OUT directly, the feedback signal V FB may be input to the feedback pin FB.

[0079] The phase difference controller 230 controls the output voltage V OUTThe feedback signal V FB and the reference voltage V REF The phase difference φd is feedback controlled so that the error approaches zero.

[0080] The phase difference controller 230 includes a pulse width modulator 232, an oscillator 234, and a phase shift logic circuit 236. The oscillator 234 generates a clock signal CKL having a predetermined frequency. The oscillator 234 also generates a ramp signal RAMP (a triangular wave or a sawtooth wave) having the same frequency as the clock signal CLK.

[0081] The pulse width modulator 232 receives the feedback signal V FB and the reference voltage V REF The pulse width modulator 232 generates a pulse width modulation signal (PWM signal) whose pulse width changes so that the error between the feedback signal V approaches zero. The pulse width modulator 232 includes, for example, an error amplifier EA1 and a PWM comparator COMP1. The error amplifier EA1 generates a pulse width modulation signal (PWM signal) whose pulse width changes so that the error between the feedback signal V approaches zero. FB and the reference voltage V REF The output of the error amplifier EA1 is connected to a resistor Rc and a capacitor Cc for phase compensation.

[0082] The PWM comparator COMP1 is the output of the error amplifier EA1 (error signal V ERR ) is compared with the ramp signal RAMP to generate a PWM signal.

[0083] The phase shift logic circuit 236 receives the PWM signal and the clock signal CLK, and generates a first clock CLK1 and a second clock CLK2 having a phase difference according to the pulse width of the PWM signal.

[0084] Fig. 11 is a time chart showing the operation of the controller IC200 of Fig. 10. For example, the first clock CLK1 makes a level transition from low to high and from high to low in response to the positive edge of the PWM signal, and the second clock CLK2 makes a level transition from high to low and from low to high in response to the negative edge of the PWM signal. In other words, the frequency of the first clock CLK1 and the second clock CLK2 is half the frequency of the clock CLK generated by the oscillator 234.

[0085] (Application) 12 is a diagram showing an example of an electronic device 700 including a switched capacitor converter 100. A suitable example of the electronic device 700 is a server. Originally, a 12V power line was connected to the server, so the internal circuit 710 is designed to operate at 12V. The internal circuit 710 can include a CPU (Central Processing Unit), a memory, a LAN (Local Area Network) interface circuit, a DC / DC converter that steps down the voltage of 12V, and the like.

[0086] In recent years, there has been a trend to replace the bus voltage from 12 V to 48 V in order to reduce the current flowing through the electric wires. In this case, a power supply circuit 720 is required that steps down the power supply voltage of 48 V to 12 V. The switched capacitor converter 100 with a gain of 1 / 4 described above can be suitably used for such a power supply circuit 720.

[0087] The electronic device 700 is not limited to a server, and may be an in-vehicle device. Conventional automobile batteries are mainly 12V or 24V, but hybrid vehicles may adopt a 48V system, and in this case, a power supply circuit is required to convert the 48V battery voltage to 12V or 24V. In such a case, the 1 / 2 or 1 / 4 switched capacitor converter 100 can be suitably used.

[0088] Alternatively, the electronic device 700 may be industrial equipment, office automation equipment, or consumer equipment such as audio equipment.

[0089] The embodiments are merely examples, and it will be understood by those skilled in the art that there are various variations in the combination of each component and each processing process, and that such variations are also included in the present disclosure and may constitute the scope of the present invention. [Explanation of symbols]

[0090] 100 Switched Capacitor Converter 102 input lines 104 Output Line 106 Ground Line C1 First capacitor C2 Second capacitor C3 Third capacitor Co Output Capacitor L1 First inductor L2 Second inductor SW1, SWm Switch L1, Ln inductor 110 First switching circuit 120 Second switching circuit M1 First transistor M2 Second transistor M3 Third transistor M4 4th transistor M5 Fifth transistor M6 6th transistor M7 Seventh transistor M8 8th transistor M9 9th transistor M10 10th transistor 200 Controller IC 210 First Drive Unit 220 Second Drive Unit 230 Phase difference controller 232 Pulse Width Modulator 234 Oscillator 236 Phase Shift Logic Circuit

Claims

1. 1. A controller circuit for a switched capacitor converter, comprising: The switched capacitor converter comprises: An input line; An output line; A ground line, m (m≧3) switches connected in series between the input line and the output line; n (n≧2) LC circuits, each including a capacitor and an inductor connected in series, a first end of each of the n LC circuits being connected to a corresponding odd-numbered one of the connection nodes of the m switches; k (k≧1, k+n=m−1) capacitors, each having a first end connected to a corresponding even-numbered one of the connection nodes of the m switches; a first switching circuit that applies an output voltage of the output line or a ground voltage of the ground line to a second end of each of the k capacitors; a second switching circuit that applies the output voltage or the ground voltage of the ground line to a second end of each of the n LC circuits; Equipped with The controller circuit includes: (i) a first drive unit that alternately switches between a state in which odd-numbered switches among the m switches are on and even-numbered switches are off, and the first switching circuit applies the ground voltage, and (ii) a state in which odd-numbered switches among the m switches are off and even-numbered switches are on, and the first switching circuit applies the output voltage, in response to a first clock; a second driving section that alternately switches the second switching circuit between a state in which the second switching circuit applies the output voltage and a state in which the second switching circuit applies the ground voltage in response to a second clock; a phase difference controller for controlling a phase difference between the first clock and the second clock; A controller circuit comprising:

2. The controller circuit according to claim 1 , wherein the phase difference controller feedback controls the phase difference so that an error between a feedback signal corresponding to an output of the switched capacitor converter and a reference signal approaches zero.

3. The phase difference controller includes: a pulse width modulator for generating a pulse width modulated signal having a pulse width that varies so that the error between the feedback signal and the reference signal approaches zero; a phase shift logic circuit that generates a first clock and a second clock having a phase difference corresponding to a pulse width of the pulse width modulated signal; The controller circuit of claim 2 , comprising:

4. 4. A controller circuit as claimed in claim 1, wherein M=4.

5. the first switching circuit includes k first inverter circuits; Each of the k first inverter circuits is an output node connected to the second end of each of the k capacitors; a high-side transistor connected between the output node and the output line; a low-side transistor connected between the output node and the ground line; Including, the second switching circuit includes n second inverter circuits; Each of the n second inverter circuits is an output node connected to the second end of a corresponding one of the n LC circuits; a high-side transistor connected between the output node and the output line; a low-side transistor connected between the output node and the ground line; A controller circuit as claimed in any preceding claim, comprising:

6. 6. The controller circuit according to claim 1, wherein the m switches are N-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

7. The controller circuit according to claim 1 , which is monolithically integrated on a single semiconductor substrate.

8. A switched-capacitor converter comprising a controller circuit according to any one of claims 1 to 7.

9. An input line; An output line; A ground line, a first transistor, a second transistor, a third transistor and a fourth transistor connected in series between the input line and the output line; a first capacitor and a first inductor connected in series between a connection node of the first transistor and the second transistor and a first switching node; a second capacitor connected between a connection node of the second transistor and the third transistor and a second switching node; a third capacitor and a second inductor connected in series between a connection node of the third transistor and the fourth transistor and a third switching node; a fifth transistor connected between the output line and the first switching node; a sixth transistor connected between the first switching node and the ground line; a seventh transistor connected between the output line and the second switching node; an eighth transistor connected between the second switching node and the ground line; a ninth transistor connected between the output line and the third switching node; a tenth transistor connected between the third switching node and the ground line; a first driving section that switches the set of the first transistor and the third transistor and the set of the second transistor and the fourth transistor in opposite phases; a second driving unit that switches the set of the fifth transistor, the seventh transistor, and the ninth transistor and the set of the sixth transistor, the eighth transistor, and the tenth transistor in opposite phases; a phase difference controller for controlling a phase difference between the switching of the first drive unit and the second drive unit; A switched capacitor converter comprising:

10. 10. The switched capacitor converter according to claim 9, wherein the phase difference controller feedback controls the phase difference so that an error between an output of the switched capacitor converter and a target state of the output approaches zero.

11. 11. The switched capacitor converter according to claim 10, wherein the phase difference controller includes a pulse width modulator that generates a pulse width modulated signal whose pulse width changes so that the error between an output of the switched capacitor converter and a target state of the output approaches zero, and controls the phase difference according to the pulse width of the pulse width modulated signal.

12. An electronic device comprising the switched capacitor converter according to any one of claims 8 to 11.

13. 1. A method for controlling a switched capacitor converter, comprising: The switched capacitor converter comprises: An input line; An output line; A ground line, m (m≧3) switches connected in series between the input line and the output line; n (n≧2) LC circuits, each including a capacitor and an inductor connected in series, a first end of each of the n LC circuits being connected to a corresponding odd-numbered one of the connection nodes of the m switches; k (k≧1, k+n=m−1) capacitors, each having a first end connected to a corresponding even-numbered one of the connection nodes of the m switches; a first switching circuit that applies an output voltage of the output line or a ground voltage of the ground line to a second end of each of the k capacitors; a second switching circuit that applies the output voltage or the ground voltage of the ground line to a second end of each of the n LC circuits; Equipped with The control method includes: a step of alternately switching, in response to a first clock, between a state in which odd-numbered switches among the m switches are on and even-numbered switches are off, and the first switching circuit applies the ground voltage, and (ii) a state in which odd-numbered switches among the m switches are off and even-numbered switches are on, and the first switching circuit applies the output voltage; a step of switching the second switching circuit alternately between a state in which the second switching circuit applies the output voltage and a state in which the second switching circuit applies the ground voltage in response to a second clock; controlling a phase difference between the first clock and the second clock; A control method comprising:

14. 14. The control method according to claim 13, wherein the step of controlling the phase difference comprises feedback controlling the phase difference so that an error between an output of the switched capacitor converter and a target state of the output approaches zero.

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