Variable Logic-in-Memory Cell

Abstract

The present invention relates to a variable logic-in memory cell composed of a triple-gate feedback memory element, and a variable logic-in memory cell according to one embodiment of the present invention includes a plurality of triple-gate feedback memory elements including a drain region, a channel region, a source region, and a gate region on which first and second programming gate electrodes and a control gate electrode are formed on the channel region.

Description

[Technical field]

[0001] The present invention relates to a programmable logic-in memory cell composed of a triple-gate feedback memory element, and more particularly, to a technology for implementing a programmable logic-in memory cell that provides a logic operation function and a memory function using a triple-gate feedback memory element operated in a positive feedback loop. [Background technology]

[0002] In a conventional von Neumann-based computer system, the processor and memory are separated, and data is transmitted via a bus.

[0003] However, as computing performance increases, bottlenecks occur due to the difference in data processing speed between the processor and memory, and processing of large volumes of data is beginning to show its limits.

[0004] In other words, von Neumann-based systems, a revolutionary development in the semiconductor industry, have increased the integration density and performance of modern computers, but the physical separation between the processor and memory hierarchy has the drawback of consuming a lot of energy and lengthening data transmission and waiting times.

[0005] In the wake of the Fourth Industrial Revolution, and considering the rise in data-intensive applications such as 5G communication standards, the Internet of Things (IoT), and Artificial Intelligence (AI), a new computing paradigm is a must for large-scale data processing requirements.

[0006] In order to solve the above problems, research into logic in memory (LIM) technology that combines computation and storage functions is being intensively and accelerated.

[0007] Logic-in-memory technology performs the processor's calculation function and memory's storage function in the same space, reducing delays and power consumption that occur during data transmission and significantly improving the system integration.

[0008] Conventional logic-in-memory technology has been actively researched based on volatile memory elements such as static random access memory (SRAM) and dynamic RAM (DRAM), and non-volatile memory elements such as resistive RAM (ReRAM), magnetoresistive RAM (MRAM), and phase-change RAM (PCRAM).

[0009] In the case of logic-in-memory technology based on volatile memory elements, a large number of transistors are required for stable operation, which limits the overall area and power consumption.

[0010] Furthermore, in the case of logic-in-memory technology based on non-volatile memory devices, complex process steps are required due to the use of non-silicon materials, and it is difficult to put the technology into practical use due to low device uniformity and stability.

[0011] In addition, logic-in-memory technologies that have been developed so far have a low degree of integration because they cannot implement all basic CMOS logic operations in one cell and each logic operation requires separate circuits and wiring.

[0012] For this reason, there is a need to develop a variable logic-in-memory cell technology that can be fabricated using silicon-based CMOS processes, performs all basic logic operations within a single cell, and stores the values. Summary of the Invention [Problem to be solved by the invention]

[0013] The present invention aims to realize a programmable logic-in memory cell that provides a logic operation function and a memory function using a triple-gate feedback memory device driven by a positive feedback loop.

[0014] The present invention aims to realize a programmable logic-in memory cell by using a triple-gate feedback memory device, which is a silicon-based feedback memory device using an existing CMOS process.

[0015] The present invention aims to realize a configurable logic-in memory cell that performs all basic logic operations using a triple-gate feedback memory element having a channel-type tunable characteristic and stores the results of the performed logic operations.

[0016] The present invention aims to improve the limits of processing speed and integration caused by the data bottleneck phenomenon through the fusion of logical operation and storage functions.

[0017] The present invention aims to improve standby power efficiency with excellent memory characteristics that maintain logic operation values ​​without structural changes and external biases using variable characteristics of channel types. [Means for solving the problem]

[0018] According to an embodiment of the present invention, a variable logic-in memory cell includes a plurality of triple-gate feedback memory elements including a drain region, a channel region, and a source region, and including a gate region on which first and second programming gate electrodes and a control gate electrode are formed on the channel region, and each of the plurality of triple-gate feedback memory elements is programmed to operate in response to a program voltage V applied via the first and second programming gate electrodes. PGIn response to the level of a control voltage V applied via the control gate electrode, the channel region under the first and second programming gate electrodes performs one of a first channel operation and a second channel operation. CG Based on the level of the output voltage V, the output voltage V changes depending on the one of the states in the one of the channel operations. OUT Based on the level of

[0019] The drain region is p-doped, the source region is n-doped, and the channel region is intrinsic. The channel region under the first and second programming gate electrodes is coupled to the programming voltage V PG When the level of the program voltage V PG When the level of the second channel is low, the second channel can operate as a p-channel corresponding to the second channel operation.

[0020] Each of the plurality of triple-gate feedback memory elements is configured such that when the channel region under the first and second programming gate electrodes in the channel region performs the first channel operation, the applied control voltage V CG is determined to be in an on state when the level of the applied control voltage V CG When the level of the signal is at a low level, the signal can be determined to be in the off state.

[0021] Each of the plurality of triple-gate feedback memory elements is configured such that when the channel region under the first and second programming gate electrodes in the channel region performs the first channel operation, the applied control voltage V CGWhen the level of the control gate electrode increases from a zero level to a high level, the height of a potential barrier between the channel region under the control gate electrode and the channel region under the second programming gate electrode adjacent to the source region in the channel region is lowered, and a first positive feedback loop is generated in which electrons are injected from the source region due to the lowered potential barrier, resulting in the on-state in which a current flows.

[0022] Each of the plurality of triple-gate feedback memory elements is configured such that when the channel region under the first and second programming gate electrodes in the channel region performs the second channel operation, the applied control voltage V CG When the level of the applied control voltage V CG When the level of the signal is low, the signal can be determined to be in the on state.

[0023] Each of the plurality of triple-gate feedback memory elements is configured such that when the channel region under the first and second programming gate electrodes in the channel region performs the second channel operation, the applied control voltage V CG When the level of the control gate electrode decreases from the zero level to the low level, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the first programming gate electrode adjacent to the drain region is lowered in the channel region, and a second positive feedback loop is generated in which holes are injected from the drain region due to the lowered potential barrier, resulting in the on-state in which a current flows.

[0024] The variable logic-in memory cell may be configured with one of a first circuit structure including a plurality of first parallel connection parts in which the drain regions and source regions of two triple-gate feedback memory elements among the plurality of triple-gate feedback memory elements are connected to each other, and a second circuit structure including a plurality of second parallel connection parts in which a common drain region and a common source region are connected between a first series connection part in which the drain regions and source regions of two triple-gate feedback memory elements among four triple-gate feedback memory elements among the plurality of triple-gate feedback memory elements are connected in series, and a second series connection part in which the drain regions and source regions of the remaining two triple-gate feedback memory elements are connected in series.

[0025] When the variable logic-in memory cell is configured with the first circuit structure, a drain voltage V DD and a source voltage V is applied to the source terminal of the last first parallel connection unit among the plurality of first parallel connection units. SS When the second circuit structure is configured, a drain voltage V is applied to the drain terminal of the first second parallel connection unit among the plurality of second parallel connection units. DD and applying a source voltage V to the source terminal of the last second parallel connection unit among the plurality of second parallel connection units. SS can be applied.

[0026] The variable logic-in memory cell is configured with the second circuit structure, a triple-gate feedback memory element constituting a first second parallel connection part among the plurality of second parallel connection parts performs the second channel operation, a triple-gate feedback memory element constituting a last second parallel connection part performs the first channel operation, and the control voltage V CG When the level of the output voltage V OUT is at a high level, and the control voltage V CG When the level of the output voltage V OUTWhen the level of the logical operation is low, the logical operation function can be performed.

[0027] The variable logic-in memory cell is configured with the second circuit structure, a triple-gate feedback memory element constituting a first second parallel connection part among the plurality of second parallel connection parts performs the first channel operation, a triple-gate feedback memory element constituting a last second parallel connection part performs the second channel operation, and the control voltage V CG When the level of the output voltage V OUT is at a low level, and the control voltage V CG When the level of the output voltage V OUT When the level of the logical operation is high, the logical operation function can be performed.

[0028] The variable logic-in memory cell is configured with the second circuit structure, a triple-gate feedback memory element constituting a first second parallel connection part among the plurality of second parallel connection parts performs the second channel operation, a triple-gate feedback memory element constituting a last second parallel connection part performs the first channel operation, and the control voltage V CG The first control voltage V A is applied to the left side of the first second parallel connection part and to the upper side of the last second parallel connection part, and the control voltage V CG The second control voltage V B is applied to the right side of the first second parallel connection part and the lower side of the last second parallel connection part, and the first control voltage V A and the second control voltage V B When only one of the levels is high or both are low, the output voltage V OUT is at a high level, and the first control voltage V A and the second control voltage V B When both of the levels of the output voltage V OUTWhen the level of the logical operation is low, the logical operation function can be performed.

[0029] The variable logic-in memory cell is configured with the second circuit structure, a triple-gate feedback memory element constituting a first second parallel connection part among the plurality of second parallel connection parts performs the second channel operation, a triple-gate feedback memory element constituting a last second parallel connection part performs the first channel operation, and the control voltage V CG The first control voltage V A is applied to the upper side of the first second parallel connection part and to the left side of the last second parallel connection part, and the control voltage V CG The second control voltage V B is applied to the lower side of the first second parallel connection unit and to the right side of the last second parallel connection unit, and the first control voltage V A and the second control voltage V B When only one of the levels is low or both are high, the output voltage V OUT is at a low level, and the first control voltage V A and the second control voltage V B When both of the levels of the output voltage V OUT When the level of the logical operation is high, the logical operation function can be performed.

[0030] The variable logic-in memory cell is configured with the second circuit structure, a triple-gate feedback memory element constituting a first second parallel connection part among the plurality of second parallel connection parts performs the first channel operation, a triple-gate feedback memory element constituting a last second parallel connection part performs the second channel operation, and the control voltage V CG The first control voltage V A is applied to the upper side of the first second parallel connection part and to the left side of the last second parallel connection part, and the control voltage V CG The second control voltage V Bis applied to the lower side of the first second parallel connection unit and to the right side of the last second parallel connection unit, and the first control voltage V A and the second control voltage V B When either one of the levels is a low level, the output voltage V OUT is at a low level, and the first control voltage V A and the second control voltage V B When both of the levels of the output voltage V OUT When the level of the logical operation is high, the logical operation function can be performed.

[0031] The variable logic-in memory cell is configured with the second circuit structure, a triple-gate feedback memory element constituting a first second parallel connection part among the plurality of second parallel connection parts performs the first channel operation, a triple-gate feedback memory element constituting a last second parallel connection part performs the second channel operation, and the control voltage V CG The first control voltage V A is applied to the left side of the first second parallel connection part and to the upper side of the last second parallel connection part, and the control voltage V CG The second control voltage V B is applied to the right side of the first second parallel connection part and the lower side of the last second parallel connection part, and the first control voltage V A and the second control voltage V B When either one of the levels is a high level, the output voltage V OUT is at a high level, and the first control voltage V A and the second control voltage V B When both of the levels of the output voltage V OUT When the level of the logical operation is low, the logical operation function can be performed.

[0032] The variable logic-in memory cell is configured with the second circuit structure, and among the triple-gate feedback memory elements constituting a first second parallel connection part of the plurality of second parallel connection parts, the left side performs the first channel operation and the right side performs the second channel operation, and among the triple-gate feedback memory elements constituting the last second parallel connection part, the upper left side performs the second channel operation, the upper right side performs the first channel operation, the lower left side performs the first channel operation, and the lower right side performs the second channel operation, and the control voltage V CG The first control voltage V A is applied to the upper sides of the first second parallel connection part and the last second parallel connection part, and the control voltage V CG The second control voltage V B is applied to the lower sides of the first second parallel connection part and the last second parallel connection part, and the first control voltage V A and the second control voltage V B When the levels of the output voltage V OUT is at a high level, and the first control voltage V A and the second control voltage V B When the levels of the output voltage V OUT When the level of the logical operation is low, the logical operation function can be performed.

[0033] The variable logic-in memory cell is configured with the second circuit structure, and among the triple-gate feedback memory elements constituting a first second parallel connection part of the plurality of second parallel connection parts, the upper left side performs the second channel operation, the upper right side performs the first channel operation, the lower left side performs the first channel operation, and the lower right side performs the second channel operation, and among the triple-gate feedback memory elements constituting the last second parallel connection part, the left side performs the first channel operation, and the right side performs the second channel operation, CG The first control voltage V Ais applied to the upper sides of the first second parallel connection part and the last second parallel connection part, and the control voltage V CG The second control voltage V B is applied to the lower sides of the first second parallel connection part and the last second parallel connection part, and the first control voltage V A and the second control voltage V B When the levels of the output voltage V OUT is at a low level, and the first control voltage V A and the second control voltage V B When the levels of the output voltage V OUT When the level of the logical operation is high, the logical operation function can be performed.

[0034] The variable logic-in memory cell is configured to have the drain voltage V DD , the source voltage V SS , the program voltage V PG and the control voltage V CG When the voltage V is applied at zero level, OUT The memory function can be performed by maintaining the level of Effect of the Invention

[0035] The present invention may provide a programmable logic-in memory cell that provides a logic operation function and a memory function using a triple-gate feedback memory device driven by a positive feedback loop.

[0036] The present invention can implement a programmable logic-in memory cell by using a triple-gate feedback memory device, which is a silicon-based feedback memory device using an existing CMOS process.

[0037] The present invention may be embodied as a configurable logic-in memory cell that performs all basic logic operations and stores the results of the performed logic operations using a triple-gate feedback memory element having a channel-type tunable characteristic.

[0038] The present invention can improve the processing speed and integration limitations caused by the data bottleneck phenomenon through the fusion of logical operation and storage functions.

[0039] The present invention utilizes the variable characteristics of the channel type to improve standby power efficiency with excellent memory characteristics that maintain logic values ​​without structural changes and external bias. [Brief description of the drawings]

[0040] [Figure 1A] 1 is a diagram illustrating a triple-gate feedback memory device constituting a programmable logic-in memory cell according to an embodiment of the present invention; [Figure 1B] 1 is a diagram illustrating a triple-gate feedback memory device constituting a programmable logic-in memory cell according to an embodiment of the present invention; [Figure 2A] FIG. 2 is a diagram illustrating a circuit symbol of a triple-gate feedback memory device according to an embodiment of the present invention. [Figure 2B] FIG. 2 is a diagram illustrating a circuit symbol of a triple-gate feedback memory device according to an embodiment of the present invention. [Figure 3A] 2A and 2B are diagrams illustrating an operation principle of a triple-gate feedback memory device according to an embodiment of the present invention; [Figure 3B] 2A and 2B are diagrams illustrating an operation principle of a triple-gate feedback memory device according to an embodiment of the present invention; [Figure 3C] 2A and 2B are diagrams illustrating an operation principle of a triple-gate feedback memory device according to an embodiment of the present invention; [Figure 3D] 2A and 2B are diagrams illustrating an operation principle of a triple-gate feedback memory device according to an embodiment of the present invention; [Figure 3E]2A and 2B are diagrams illustrating an operation principle of a triple-gate feedback memory device according to an embodiment of the present invention; [Figure 3F] 2A and 2B are diagrams illustrating an operation principle of a triple-gate feedback memory device according to an embodiment of the present invention; [Figure 4A] FIG. 2 is a diagram illustrating a circuit diagram of a variable logic-in memory cell according to an embodiment of the present invention. [Figure 4B] FIG. 2 is a diagram illustrating a circuit diagram of a variable logic-in memory cell according to an embodiment of the present invention. [Figure 5A] 1 is a diagram illustrating the operation of a NOT gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 5B] 1 is a diagram illustrating the operation of a NOT gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 6A] 11A and 11B are diagrams illustrating the operation of a YES gate of the variable logic-in memory cell according to an embodiment of the present invention. [Figure 6B] 11A and 11B are diagrams illustrating the operation of a YES gate of the variable logic-in memory cell according to an embodiment of the present invention. [Figure 7A] 1 is a diagram illustrating the operation of a NAND gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 7B] 1 is a diagram illustrating the operation of a NAND gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 8A] 1 is a diagram illustrating the operation of a NOR gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 8B] 1 is a diagram illustrating the operation of a NOR gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 9A] 10A and 10B are diagrams illustrating the operation of an AND gate of a variable logic-in memory cell according to an embodiment of the present invention. [Figure 9B] 10A and 10B are diagrams illustrating the operation of an AND gate of a variable logic-in memory cell according to an embodiment of the present invention. [Figure 10A]1 is a diagram illustrating an operation of an OR gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 10B] 1 is a diagram illustrating an operation of an OR gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 11A] 1 is a diagram illustrating an operation of an XNOR gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 11B] 1 is a diagram illustrating an operation of an XNOR gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 12A] 1 is a diagram illustrating the operation of an XOR gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. [Figure 12B] 1 is a diagram illustrating the operation of an XOR gate of a variable logic-in memory cell according to an embodiment of the present invention. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] Various embodiments of the present document will now be described with reference to the accompanying drawings.

[0042] The examples and the terms used therein are not intended to limit the technology described in this document to a particular embodiment, but should be understood to include various modifications, equivalents, and / or alternatives of the examples.

[0043] In describing various embodiments below, if it is determined that a detailed description of related publicly known functions or configurations may obscure the gist of the invention, the detailed description will be omitted.

[0044] The terms described below are defined in consideration of functions in various embodiments, and may vary depending on the intention or practice of a user or operator. Therefore, the definitions should be based on the contents of this specification.

[0045] In connection with the description of the drawings, like reference numbers may be used for like components.

[0046] A singular expression can include a plural expression unless the context clearly indicates otherwise.

[0047] In this document, phrases such as "A or B" or "at least one of A and / or B" may include all possible combinations of the items listed together.

[0048] Expressions such as "first," "second," "initial," or "second" may modify the components in question regardless of order or importance, and are used only to distinguish one component from other components, and do not limit the components in question.

[0049] When a (e.g., first) component is referred to as being "(functionally or communicatively) coupled" or "connected" to another (e.g., second) component, the one component may be directly coupled to the other component or may be coupled through another component (e.g., a third component).

[0050] As used herein, "configured to" may be used interchangeably with, for example, hardware or software terms such as "suitable for," "capable of," "modified to," "made to," "capable of," or "designed to," depending on the context.

[0051] In some contexts, an "apparatus configured to" can mean that the apparatus is "capable of" in conjunction with other devices or components.

[0052] For example, a "processor configured (or set up) to perform A, B, and C" may refer to a dedicated processor for performing those operations (e.g., an embedded processor), or a general-purpose processor (e.g., a CPU or application processor) that can perform those operations by executing one or more software programs stored in a memory device.

[0053] Additionally, the term "or" means an inclusive or rather than an exclusive or.

[0054] That is, unless otherwise stated or clear from the context, the phrase "x uses a or b" means any one of the natural inclusive permutations.

[0055] As used below, terms such as "module" and "device" refer to a unit that processes at least one function or operation, which may be embodied in hardware or software, or a combination of hardware and software.

[0056] 1A and 1B are diagrams illustrating a triple-gate feedback memory device constituting a programmable logic-in memory cell according to an embodiment of the present invention.

[0057] FIG. 1A illustrates a cross-sectional view of a triple-gate feedback memory device constituting a programmable logic-in memory cell according to an embodiment of the present invention, and FIG. 1B illustrates a three-dimensional view of the triple-gate feedback memory device.

[0058] Referring to FIG. 1A, a triple-gate feedback memory device 100 according to one embodiment of the present invention includes a drain region 101, a channel region 102, a source region 103 and a gate region, and the gate region includes first and second programming gate electrodes 108 and a control gate electrode 107 formed on a gate insulating film 104.

[0059] As an example, a drain electrode 105 may be formed on the drain region 101 and a source electrode 106 may be formed on the source region 103 .

[0060] According to one embodiment of the present invention, a triple-gate feedback memory device 100 includes a drain region 101, a channel region 102 and a source region 103 which are pin nanostructures.

[0061] As an example, the drain region 101 may be p-doped, the source region 103 may be n-doped, and the channel region 102 may be intrinsic.

[0062] The channel region 102 under the first and second programming gate electrodes 108 is biased by a programming voltage V PG When the level of V is high, it operates as n-channel corresponding to the first channel operation, and the program voltage V PG When the level of the first channel is low, the second channel can operate as a p-channel, which corresponds to the second channel operation.

[0063] A plurality of triple-gate feedback memory devices 100 may be configured to form a programmable logic-in memory cell.

[0064] The triple-gate feedback memory element 100 is configured to receive a program voltage V V applied via first and second programming gate electrodes 108. PG Depending on the level of the potential difference, the channel region under the first and second programming gate electrodes in the channel region can perform one of a first channel operation and a second channel operation.

[0065] In addition, the triple-gate feedback memory element 100 is connected to a control gate electrode 107 via a control voltage V CG Based on the level of the signal, the state can be determined to be either an on state or an off state.

[0066] Therefore, the variable logic-in memory cell has an output voltage V that changes depending on one of the states of one of the channels that has already been operated. OUT Based on the level of

[0067] Referring to FIG. 1B, a triple-gate feedback memory device 110 according to one embodiment of the present invention includes a drain region 111, a channel region 112, a source region 113 and a gate region, and the gate region includes first and second programming gate electrodes 118 and a control gate electrode 117 formed on a gate insulating film 114.

[0068] According to one embodiment of the present invention, the triple-gate feedback memory element 110 includes a drain region 111, a channel region 112 and a source region 113 which are pin nanostructures.

[0069] As an example, the drain region 111 may be p-doped, the source region 113 may be n-doped, and the channel region 112 may be intrinsic.

[0070] The channel region 112 under the first and second programming gate electrodes 118 is biased by a programming voltage V PG When the level of V is high, it operates as n-channel corresponding to the first channel operation, and the program voltage V PG When the level of the first channel is low, the second channel can operate as a p-channel, which corresponds to the second channel operation.

[0071] A plurality of triple-gate feedback memory devices 110 may be configured to form a programmable logic-in memory cell.

[0072] 2A and 2B are diagrams illustrating a circuit symbol of a triple-gate feedback memory device according to an embodiment of the present invention.

[0073] FIG. 2A illustrates a circuit symbol when a channel region of a triple-gate feedback memory device according to an embodiment of the present invention performs a first channel operation and operates as an n-channel.

[0074] Meanwhile, FIG. 2B illustrates a circuit symbol when the channel region of the triple-gate feedback memory device according to an embodiment of the present invention performs a second channel operation and operates as a p-channel.

[0075] Referring to FIG. 2A, a triple-gate feedback memory element 200 according to one embodiment of the present invention includes a nanostructure 201 including a drain region, a channel region, a source region and a gate region, in which first and second programming gate electrodes and a control gate electrode are formed in the gate region to which a programming gate terminal PG and a control gate terminal CG are connected, a drain electrode is formed in the drain region to which a drain terminal D is connected, and a source electrode is formed in the source region to which a source terminal S is connected.

[0076] Additionally, the symbol for the triple-gate feedback memory device 200 indicates, via the channel operating state field 202, that the triple-gate feedback memory device 200 is in a first channel operating state.

[0077] In other words, the symbol for the triple-gate feedback memory device 200 may show the channel operating state region 202 in solid form to indicate that the triple-gate feedback memory device 200 is operating as an n-channel.

[0078] Referring to FIG. 2B, a triple-gate feedback memory element 210 according to one embodiment of the present invention includes a nanostructure 211 including a drain region, a channel region, a source region and a gate region, in which first and second programming gate electrodes and a control gate electrode are formed in the gate region to which a programming gate terminal PG and a control gate terminal CG are connected, a drain electrode is formed in the drain region to which a drain terminal D is connected, and a source electrode is formed in the source region to which a source terminal S is connected.

[0079] Additionally, the symbol of the triple-gate feedback memory device 210 indicates, via the channel operating state field 212, that the triple-gate feedback memory device 210 is in a second channel operating state.

[0080] In other words, the symbol for the triple-gate feedback memory element 210 may show the channel operating state region 212 in an empty configuration to indicate that the triple-gate feedback memory element 200 is operating as a p-channel.

[0081] 3A to 3F are diagrams illustrating the operation principle of a triple-gate feedback memory device according to an embodiment of the present invention.

[0082] 3A to 3C illustrate the operation principle of a triple-gate feedback memory device according to an embodiment of the present invention when it operates as a p-channel.

[0083] Referring to FIG. 3A, in a triple-gate feedback memory device 300 according to an embodiment of the present invention, when a positive voltage is applied through drain terminal 301 and a negative voltage corresponding to a low level of the program voltage is applied from programming gate terminal 302, the channel region under programming gate electrode PG in channel region 303 is programmed to a p-channel and operates as a p-channel.

[0084] As an example, the triple-gate feedback memory element 300 is determined to be in an on or off state based on the level of a control voltage applied via the control gate terminal 304 .

[0085] The on and off operating states of the triple-gate feedback memory device 300 will now be described with reference to FIGS. 3B and 3C.

[0086] Referring to FIG. 3B, when the triple-gate feedback memory device according to an embodiment of the present invention operates as a p-channel, the operating state 310 is determined to be an on state when the level of the control voltage applied via the control gate terminal is a low level, and an off state when the level is a high level.

[0087] Referring to FIG. 3C, when the triple-gate feedback memory device according to one embodiment of the present invention operates as a p-channel, an energy band 320 is illustrated in an off state based on the level of the control voltage, and an energy band 321 is illustrated in an on state.

[0088] Referring to the energy band 320 and the energy band 321, when the channel region under the first and second programming gate electrodes performs a second channel operation corresponding to a p-channel operation, the control voltage V CG When the level of decreases from the zero level to the low level, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the first programming gate electrode adjacent to the drain region is lowered in the channel region, and a second positive feedback loop is generated in which holes are injected from the drain region due to the lowered potential barrier, resulting in an on-state in which a current flows.

[0089] That is, the triple-gate feedback memory element switches from energy band 320 to energy band 321 as a second positive feedback loop occurs.

[0090] For example, the second positive feedback loop may be a positive feedback loop in which holes are the majority carriers in the channel region.

[0091] 3D to 3F illustrate the operation principle of a triple-gate feedback memory device according to an embodiment of the present invention when it operates as an n-channel.

[0092] Referring to FIG. 3D, in a triple-gate feedback memory device 330 according to one embodiment of the present invention, when a negative voltage is applied through source terminal 331 and a positive voltage corresponding to a high level of the program voltage is applied from programming gate terminal 332, the channel region under the programming gate electrode in channel region 333 is programmed to an n-channel and operates as an n-channel.

[0093] As an example, the triple-gate feedback memory element 330 is determined to be in an on or off state based on the level of a control voltage applied via the control gate terminal 334 .

[0094] The on and off operating states of the triple-gate feedback memory device 330 are illustrated in FIGS. 3E and 3F.

[0095] Referring to FIG. 3E, when the triple-gate feedback memory device according to an embodiment of the present invention operates as an n-channel, the operating state 340 is determined to be an on state when the level of the control voltage applied via the control gate terminal is a high level, and an off state when the level is a low level.

[0096] Referring to FIG. 3F, when a triple-gate feedback memory device according to an embodiment of the present invention operates as an n-channel, an energy band 350 is illustrated in an off state based on a control voltage level, and an energy band 351 is illustrated in an on state.

[0097] Referring to the energy band 350 and the energy band 351, when the channel region under the first and second programming gate electrodes performs a first channel operation corresponding to an n-channel operation, the control voltage V CG When the level of increases from the zero level to the high level, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the second programming gate electrode adjacent to the source region in the channel region is lowered, and a first positive feedback loop is generated in which electrons are injected from the source region due to the lowered potential barrier, resulting in an on-state in which current flows.

[0098] That is, the triple-gate feedback memory element switches from energy band 350 to energy band 351 as a first positive feedback loop occurs.

[0099] For example, the first positive feedback loop may be a positive feedback loop in which electrons are the majority carriers in the channel region.

[0100] According to one embodiment of the present invention, a triple-gate feedback memory device may be a device in which a first positive feedback loop or a second positive feedback loop is formed depending on the level of a control voltage applied to a gate region, and an on or off state is variably controlled in a first channel operation and a second channel operation.

[0101] In addition, the triple-gate feedback memory device is turned on by forming a positive feedback loop as charge carriers accumulate in the potential well of the channel region, which can be utilized as a memory function for storing data in the channel region.

[0102] 4A and 4B are diagrams illustrating a circuit diagram of a programmable logic-in memory cell according to an embodiment of the present invention.

[0103] 4A and 4B illustrate circuit diagrams of a programmable logic-in memory cell constructed using a plurality of triple-gate feedback memory elements according to one embodiment of the present invention.

[0104] 4A and 4B, the programmable logic-in memory cell can be realized in two types of circuits.

[0105] Referring to FIG. 4A, a variable logic-in memory cell 400 according to one embodiment of the present invention is configured based on parallel connection parts in which two triple-gate feedback memory elements 401 are connected to each other at their drain regions and at their source regions, and four parallel connection parts are connected to each other at their sources and drains in sequence.

[0106] In other words, the variable logic-in memory cell 400 according to one embodiment of the present invention exhibits a first circuit structure composed of a plurality of first parallel connection parts in which the drain regions of two triple-gate feedback memory elements among a plurality of triple-gate feedback memory elements are connected to each other and the source regions of the two triple-gate feedback memory elements are connected to each other.

[0107] As an example, when the variable logic-in memory cell 400 is configured with a first circuit structure, a drain voltage V DD is applied to the source terminal of the last first parallel connection unit among the plurality of first parallel connection units, and a source voltage V SSA supply voltage is applied by applying a voltage to each triple-gate feedback memory element 401, and logic operation functions and memory functions can be performed based on the level of the output voltage at the output terminal 402 according to the input voltage applied to each triple-gate feedback memory element 401 via the control gate terminal.

[0108] Referring to FIG. 4B, the variable logic-in memory cell 410 according to one embodiment of the present invention has a second circuit structure including a first series connection part in which the drain regions and source regions of two triple-gate feedback memory elements of the four triple-gate feedback memory elements 411 are connected in series, and a plurality of second parallel connection parts in which a common drain region and a common source region are connected between a second series connection part in which the drain regions and source regions of the remaining two triple-gate feedback memory elements are connected in series.

[0109] As an example, when the variable logic-in memory cell 410 is configured with the second circuit structure, a drain voltage V DD and a source voltage V is applied to the source terminal of the last second parallel connection unit among the plurality of second parallel connection units. SS A supply voltage is applied by applying a voltage to each triple-gate feedback memory element 411, and logic operation functions and memory functions can be performed based on the level of the output voltage at the output terminal 412 according to the input voltage applied to each triple-gate feedback memory element 411 via the control gate terminal.

[0110] 5A and 5B are diagrams illustrating the operation of a NOT gate of a variable logic-in memory cell according to an embodiment of the present invention.

[0111] FIG. 5A illustrates a circuit diagram of an operation of a NOT gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0112] Referring to FIG. 5A, a programmable logic-in memory cell 500 according to an embodiment of the present invention is configured with the second circuit structure illustrated in FIG. 4B.

[0113] In addition, in the variable logic-in memory cell 500, based on a programming voltage applied via the programming gate terminal PG, the triple-gate feedback memory element constituting the first second parallel connection section 501 among the multiple second parallel connection sections performs a second channel operation, and the triple-gate feedback memory element constituting the last second parallel connection section 502 performs a first channel operation.

[0114] At this time, the variable logic-in memory cell 500 receives the control voltage V CG When the level of is low, the output voltage V OUT The level of the control voltage V CG When the level of is high, the output voltage V OUT When the level of is low, a logical operation function corresponding to the operation of a NOT gate can be performed.

[0115] FIG. 5B illustrates a timing diagram for the operation of a NOT gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0116] Referring to FIG. 5B, a timing diagram 510 shows a low-level input voltage V A When applied, the high-level output voltage V corresponds to '1'. OUT is calculated, and the high-level input voltage V A When the voltage is applied, the low-level output voltage V OUT This indicates that the following is calculated:

[0117] Also, the supply voltage V SUP , program voltage V PG , input voltage V A This indicates that the memory function is performed to hold the calculated logical value even when the input is removed.

[0118] 6A and 6B are diagrams illustrating the operation of the YES gate of the variable logic-in memory cell according to one embodiment of the present invention.

[0119] FIG. 6A illustrates a circuit diagram of the operation of a YES gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0120] Referring to FIG. 6A, a programmable logic-in memory cell 600 according to an embodiment of the present invention is constructed with the second circuit structure illustrated in FIG. 4B.

[0121] In addition, in the variable logic-in memory cell 600, based on a programming voltage applied via the programming gate terminal PG, the triple-gate feedback memory element constituting the first second parallel connection section 601 among the multiple second parallel connection sections performs a first channel operation, and the triple-gate feedback memory element constituting the last second parallel connection section 602 performs a second channel operation.

[0122] At this time, the variable logic-in memory cell 600 receives the control voltage V CG When the level of is high, the output voltage V OUT The level of the control voltage V CG When the level of is low, the output voltage V OUT When the level of the gate is low, a logical operation function corresponding to the operation of the YES gate can be performed.

[0123] FIG. 6B illustrates a timing diagram for the operation of the YES gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0124] Referring to FIG. 6B, a timing diagram 610 shows a low-level input voltage V A When the voltage is applied, the low-level output voltage V OUT is calculated, and the high-level input voltage V AWhen applied, the high-level output voltage V corresponds to '1'. OUT This indicates that the following is calculated:

[0125] Also, the supply voltage V SUP , program voltage V PG , input voltage V A This indicates that the memory function is performed to hold the calculated logical value even when the input is removed.

[0126] 7A and 7B are diagrams illustrating the operation of a NAND gate of a programmable logic-in memory cell according to an embodiment of the present invention.

[0127] FIG. 7A illustrates a circuit diagram of a NAND gate of a programmable logic-in memory cell in accordance with one embodiment of the present invention.

[0128] Referring to FIG. 7A, a programmable logic-in memory cell 700 according to an embodiment of the present invention is constructed with the second circuit structure illustrated in FIG. 4B.

[0129] As an example, in the variable logic-in memory cell 700, based on a programming voltage applied via the programming gate terminal PG, a triple-gate feedback memory element constituting a first of the plurality of second parallel connection parts performs a second channel operation, and a triple-gate feedback memory element constituting the last second parallel connection part performs a first channel operation.

[0130] In addition, the variable logic-in memory cell 700 is configured to have a control voltage V CG The first control voltage V A is applied to the left side 701 of the first second parallel connection and the top side 703 of the last second parallel connection, and a control voltage V CG The second control voltage V B is applied to the right side 702 of the first second parallel connection and to the bottom side 704 of the last second parallel connection.

[0131] As a result, the variable logic-in memory cell 700 is driven by the first control voltage V A and the second control voltage V B When only one of the levels is high or both are low, the output voltage V OUT is at a high level, and the first control voltage V A and the second control voltage V B When both of the levels are high, the output voltage V OUT The logic operation function of the NAND gate can be performed when the level of

[0132] FIG. 7B illustrates a timing diagram for the operation of a NAND gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0133] Referring to FIG. 7B, a timing diagram 710 illustrates a timing diagram for two input voltages (V A ,V B When the input corresponding to '00', '01', '10', or '11' is applied to OUT This indicates that the values ​​corresponding to '1', '1', '1', and '0' are calculated.

[0134] Also, the supply voltage V SUP , program voltage V PG , input voltage V A This indicates that the memory function is performed to hold the calculated logical value even when the input is removed.

[0135] 8A and 8B are diagrams illustrating the operation of a NOR gate of a programmable logic-in memory cell according to an embodiment of the present invention.

[0136] FIG. 8A illustrates a circuit diagram of an operation of a NOR gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0137] Referring to FIG. 8A, a programmable logic-in memory cell 800 according to an embodiment of the present invention is configured with the second circuit structure illustrated in FIG. 4B.

[0138] As an example, in the variable logic-in memory cell 800, based on a programming voltage applied via the programming gate terminal PG, a triple-gate feedback memory element constituting a first second parallel connection part among the plurality of second parallel connection parts performs a second channel operation, and a triple-gate feedback memory element constituting the last second parallel connection part performs a first channel operation.

[0139] In addition, the variable logic-in memory cell 800 is configured to have a control voltage V CG The first control voltage V A is applied to the upper side 801 of the first second parallel connection and the left side 803 of the last second parallel connection, and a control voltage V CG The second control voltage V B is applied to the bottom 802 of the first second parallel connection and to the right 804 of the last second parallel connection.

[0140] As a result, the variable logic-in memory cell 800 is driven by the first control voltage V A and the second control voltage V B When only one of the levels is low or both are high, the output voltage V OUT is at a low level, and the first control voltage V A and the second control voltage V B When both of the levels of OUT The logic operation function of the NOR gate can be performed when the level of

[0141] FIG. 8B illustrates a timing diagram for the operation of a NOR gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0142] Referring to FIG. 8B, a timing diagram 810 illustrates a timing diagram for two input voltages (V A ,V BWhen the input corresponding to '00', '01', '10', or '11' is applied to OUT This indicates that the values ​​corresponding to '1', '0', '0', and '0' are calculated.

[0143] Also, the supply voltage V SUP , program voltage V PG , input voltage V A This indicates that the memory function is performed to hold the calculated logical value even when the input is removed.

[0144] 9A and 9B are diagrams illustrating the operation of an AND gate of a variable logic-in memory cell according to an embodiment of the present invention.

[0145] FIG. 9A illustrates a circuit diagram of an AND gate of a programmable logic-in memory cell in accordance with one embodiment of the present invention.

[0146] Referring to FIG. 9A, a programmable logic-in memory cell 900 according to an embodiment of the present invention is configured with the second circuit structure illustrated in FIG. 4B.

[0147] As an example, in the variable logic-in memory cell 900, based on a programming voltage applied via the programming gate terminal PG, a triple-gate feedback memory element constituting a first second parallel connection part among the plurality of second parallel connection parts performs a first channel operation, and a triple-gate feedback memory element constituting the last second parallel connection part performs a second channel operation.

[0148] In addition, the variable logic-in memory cell 900 is connected to a control voltage V CG The first control voltage V A is applied to the upper side 901 of the first second parallel connection and the left side 903 of the last second parallel connection, and a control voltage V CG The second control voltage V B is applied to the bottom 902 of the first second parallel connection and to the right 904 of the last second parallel connection.

[0149] As a result, the variable logic-in memory cell 900 is driven by the first control voltage V A and the second control voltage V B When either of the levels is low, the output voltage V OUT is at a low level, and the first control voltage V A and the second control voltage V B When both of the levels are high, the output voltage V OUT The logic operation function of the AND gate can be performed when the level of

[0150] FIG. 9B illustrates a timing diagram for the operation of a NAND gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0151] Referring to FIG. 9B, a timing diagram 910 illustrates a timing diagram for two input voltages (V A ,V B When the input corresponding to '00', '01', '10', or '11' is applied to OUT This indicates that the values ​​corresponding to '0', '0', '0', and '1' are calculated.

[0152] Also, the supply voltage V SUP , program voltage V PG , input voltage V A This indicates that the memory function is performed to hold the calculated logical value even when the input is removed.

[0153] 10A and 10B are diagrams illustrating the operation of an OR gate of a variable logic-in memory cell according to an embodiment of the present invention.

[0154] FIG. 10A illustrates a circuit diagram of an operation of an OR gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0155] Referring to FIG. 10A, a programmable logic-in memory cell 1000 according to an embodiment of the present invention is configured with the second circuit structure illustrated in FIG. 4B.

[0156] As an example, in the variable logic-in memory cell 1000, based on a programming voltage applied via the programming gate terminal PG, a triple-gate feedback memory element constituting a first second parallel connection part among a plurality of second parallel connection parts performs a first channel operation, and a triple-gate feedback memory element constituting the last second parallel connection part performs a second channel operation.

[0157] In addition, the variable logic-in memory cell 1000 is configured to have a control voltage V CG The first control voltage V A is applied to the left side 1001 of the first second parallel connection section and the upper side 1003 of the last second parallel connection section, and a control voltage V CG The second control voltage V B is applied to the right side 1002 of the first second parallel connection and to the bottom side 1004 of the last second parallel connection.

[0158] As a result, the variable logic-in memory cell 1000 is driven by the first control voltage V A and the second control voltage V B When either of the levels is high, the output voltage V OUT is at a high level, and the first control voltage V A and the second control voltage V B When both of the levels of OUT The logic operation function of the OR gate can be performed when the level of

[0159] FIG. 10B illustrates a timing diagram for the operation of an OR gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0160] Referring to FIG. 10B, a timing diagram 1010 illustrates a timing diagram for two input voltages (V A ,V B When the input corresponding to '00', '01', '10', or '11' is applied to OUTThis indicates that the values ​​corresponding to '0', '1', '1', and '1' are calculated.

[0161] Also, the supply voltage V SUP , program voltage V PG , input voltage V A This indicates that the memory function is performed to hold the calculated logical value even when the input is removed.

[0162] 11A and 11B are diagrams illustrating the operation of the XNOR gate of the variable logic-in memory cell according to one embodiment of the present invention.

[0163] FIG. 11A illustrates a circuit diagram of an operation of an XNOR gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0164] Referring to FIG. 11A, a programmable logic-in memory cell 1100 according to an embodiment of the present invention is configured with the second circuit structure illustrated in FIG. 4B.

[0165] In the variable logic-in memory cell 1100, the left side of the triple-gate feedback memory elements constituting the first of the multiple second parallel connection parts performs a first channel operation, and the right side performs a second channel operation, and the upper left side of the triple-gate feedback memory elements constituting the last second parallel connection part performs a second channel operation, the upper right side performs a first channel operation, the lower left side performs a first channel operation, and the lower right side performs a second channel operation.

[0166] The first second parallel connection portion includes a first triple gate feedback memory element 1101 and a second triple gate feedback memory element 1102, and the first triple gate feedback memory element 1101 and the second triple gate feedback memory element 1102 may be included on the left side of the triple gate feedback memory elements constituting the first second parallel connection portion.

[0167] In addition, the first second parallel connection unit may include a third triple-gate feedback memory element 1103 and a fourth triple-gate feedback memory element 1104, and may be included on the right side of the triple-gate feedback memory elements constituting the first second parallel connection unit.

[0168] In addition, the variable logic-in memory cell 1100 is connected to a control voltage V CG The first control voltage V A is applied to the upper side of the first second parallel connection and the upper side of the last second parallel connection, and a control voltage V CG The second control voltage V B is applied to the underside of the first second parallel connection and the last second parallel connection.

[0169] The last second parallel connection section includes a fifth triple gate feedback memory element 1105 and a sixth triple gate feedback memory element 1106, which may be included on the left side of the triple gate feedback memory elements constituting the last second parallel connection section.

[0170] In addition, the last second parallel connection unit may include a seventh triple-gate feedback memory element 1107 and an eighth triple-gate feedback memory element 1108, which may be included on the right side of the triple-gate feedback memory elements constituting the last second parallel connection unit.

[0171] The programmable logic-in memory cell 1100 according to an embodiment of the present invention is configured to receive a first control voltage V A and the second control voltage V B When the levels of V and V are the same, the output voltage V OUT is at a high level, and the first control voltage V A and the second control voltage V B When the levels of V are different, the output voltage V OUTThe logic operation function of the XNOR gate can be performed when the level of

[0172] FIG. 11B illustrates a timing diagram for the operation of an XNOR gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0173] Referring to FIG. 11B, a timing diagram 1110 illustrates a timing diagram for two input voltages (V A ,V B When the input corresponding to '00', '01', '10', or '11' is applied to OUT This indicates that the values ​​corresponding to '1', '0', '0', and '1' are calculated.

[0174] Also, the supply voltage V SUP , program voltage V PG , input voltage V A This indicates that the memory function is performed to hold the calculated logical value even when the input is removed.

[0175] 12A and 12B are diagrams illustrating the operation of the XOR gate of the variable logic-in memory cell according to one embodiment of the present invention.

[0176] FIG. 12A illustrates a circuit diagram of an operation of an XOR gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0177] Referring to FIG. 12A, a programmable logic-in memory cell 1200 according to an embodiment of the present invention is configured with the second circuit structure illustrated in FIG. 4B.

[0178] In the variable logic-in memory cell 1200, the upper left side of the triple-gate feedback memory elements constituting the first of the multiple second parallel connection parts performs the second channel operation, the upper right side performs the first channel operation, the lower left side performs the first channel operation and the lower right side performs the second channel operation, and the left side of the triple-gate feedback memory elements constituting the last second parallel connection part performs the first channel operation and the right side performs the second channel operation.

[0179] The first second parallel connection portion includes a first triple gate feedback memory element 1201 and a second triple gate feedback memory element 1202, and the first triple gate feedback memory element 1201 and the second triple gate feedback memory element 1202 may be included on the left side of the triple gate feedback memory elements constituting the first second parallel connection portion.

[0180] In addition, the first second parallel connection unit may include a third triple-gate feedback memory element 1203 and a fourth triple-gate feedback memory element 1204, and may be included on the right side of the triple-gate feedback memory elements constituting the first second parallel connection unit.

[0181] In addition, the variable logic-in memory cell 1200 is connected to a control voltage V CG The first control voltage V A may be applied to the top of the first second parallel connection and the top of the last second parallel connection.

[0182] In addition, the variable logic-in memory cell 1200 is connected to a control voltage V CG The second control voltage V B may be applied to the underside of the first second parallel connection and the last second parallel connection.

[0183] The last second parallel connection includes a fifth triple gate feedback memory element 1205 and a sixth triple gate feedback memory element 1206, which may be included on the left side of the triple gate feedback memory elements constituting the last second parallel connection.

[0184] In addition, the last second parallel connection unit may include a seventh triple-gate feedback memory element 1207 and an eighth triple-gate feedback memory element 1208, which may be included on the right side of the triple-gate feedback memory elements constituting the last second parallel connection unit.

[0185] The programmable logic-in memory cell 1200 according to an embodiment of the present invention is configured to receive a first control voltage V A and the second control voltage V B When the levels of V and V are the same, the output voltage V OUT is at a low level, and the first control voltage V A and the second control voltage V B When the levels of V are different, the output voltage V OUT The logic operation function of the XOR gate can be performed when the level of

[0186] FIG. 12B illustrates a timing diagram for the operation of an XOR gate of a programmable logic-in memory cell according to one embodiment of the present invention.

[0187] Referring to FIG. 12B, a timing diagram 1210 illustrates a timing diagram for two input voltages (V A ,V B When the input corresponding to '00', '01', '10', or '11' is applied to OUT This indicates that the values ​​corresponding to '0', '1', '1', and '0' are calculated.

[0188] Also, the supply voltage V SUP , program voltage V PG , input voltage V A This indicates that the memory function is performed to hold the calculated logical value even when the input is removed.

[0189] In the above-mentioned specific embodiments, the elements included in the invention are expressed as singular or plural by the presented specific embodiments.

[0190] However, the expressions singular or plural have been selected to suit the circumstances presented for the convenience of explanation, and the above-described embodiments are not limited to singular or plural components, and components expressed in the plural may be composed of a singular number, and components expressed in the singular may be composed of a plural number.

[0191] Meanwhile, although specific embodiments have been described in the description of the invention, it goes without saying that various modifications are possible without departing from the scope of the technical ideas contained in the various embodiments.

[0192] Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the following claims, as well as equivalents thereto.

Claims

1. a plurality of triple-gate feedback memory elements including a gate region including a drain region, a channel region, and a source region, and having first and second programming gate electrodes and a control gate electrode formed on the channel region; Each of the triple-gate feedback memory elements is configured to receive a program voltage (V ＰＧ In response to the level of a control voltage (V ＣＧ ) is determined to be one of an on state and an off state, and an output voltage (V ＯＵＴ A variable logic-in memory cell that performs a logic operation function and a memory function based on the level of The variable logic-in memory cell includes a first circuit structure including a plurality of first parallel connection parts in which drain regions of two triple-gate feedback memory elements among the plurality of triple-gate feedback memory elements are connected to each other and source regions of the two triple-gate feedback memory elements are connected to each other; and a first series connection part in which drain regions and source regions of two triple-gate feedback memory elements among four triple-gate feedback memory elements among the plurality of triple-gate feedback memory elements are connected in series, and a second circuit structure in which a common drain region and a common source region between a second series connection part in which drain regions and source regions of the remaining two triple-gate feedback memory elements are connected in series is connected.

2. the drain region is p-doped; the source region is n-doped; the channel region is in an intrinsic state; The channel region under the first and second programming gate electrodes is biased to the program voltage (V ＰＧ ) is at a high level, the transistor operates as an n-channel corresponding to the first channel operation, and the program voltage (V ＰＧ 2. The variable logic-in memory cell of claim 1, wherein when a level of the first channel is a low level, the variable logic-in memory cell operates as a p-channel corresponding to the second channel operation.

3. Each of the plurality of triple-gate feedback memory elements is configured to have a first channel operation when the channel region under the first and second programming gate electrodes in the channel region is subjected to the first channel operation by applying the applied control voltage (V ＣＧ ) is at a high level, the transistor is determined to be in an on state, and the applied control voltage (V ＣＧ 2. The variable logic-in memory cell according to claim 1, wherein the variable logic-in memory cell is determined to be in an off state when the level of the first gate electrode is a low level.

4. Each of the plurality of triple-gate feedback memory elements is configured to have a first channel operation when the channel region under the first and second programming gate electrodes in the channel region is subjected to the first channel operation by applying the applied control voltage (V ＣＧ 4. The variable logic-in memory cell according to claim 3, wherein when a level of the first programming gate electrode increases from a zero level to a high level, a height of a potential barrier between a channel region under the control gate electrode and a channel region under the second programming gate electrode adjacent to the source region is lowered in the channel region, and a first positive feedback loop is generated in which electrons are injected from the source region due to the lowered potential barrier, thereby entering the on-state in which a current flows.

5. Each of the plurality of triple-gate feedback memory elements is configured to have a channel region under the first and second programming gate electrodes performing the second channel operation when the applied control voltage (V ＣＧ ) is at a high level, the transistor is determined to be in an off state. ＣＧ 2. The variable logic-in memory cell according to claim 1, wherein the variable logic-in memory cell is determined to be in an on state when the level of the first gate electrode is a low level.

6. Each of the plurality of triple-gate feedback memory elements is configured to have a channel region under the first and second programming gate electrodes performing the second channel operation when the applied control voltage (V ＣＧ 6. The variable logic-in memory cell according to claim 5, wherein when the level of the first programming gate electrode decreases from a zero level to a low level, a height of a potential barrier between the channel region under the control gate electrode and the channel region under the first programming gate electrode adjacent to the drain region is lowered in the channel region, and a second positive feedback loop is generated in which holes are injected from the drain region due to the lowered potential barrier, thereby entering the on-state in which a current flows.

7. The variable logic-in memory cell includes: When configured with the first circuit structure, a drain voltage (V ＤＤ ) is applied to the source terminal of the last first parallel connection unit among the plurality of first parallel connection units, and a source voltage (V ＳＳ ) is applied, When configured with the second circuit structure, a drain voltage (V ＤＤ ) is applied to the source terminal of the last second parallel connection unit among the plurality of second parallel connection units, and a source voltage (V ＳＳ 2. The variable logic-in memory cell according to claim 1, wherein a voltage of 0.1 V to 0.5 V is applied to the variable logic-in memory cell.

8. The variable logic-in memory cell includes: The triple-gate feedback memory element constituting the first second parallel connection unit among the plurality of second parallel connection units performs the second channel operation, and the triple-gate feedback memory element constituting the last second parallel connection unit performs the first channel operation, and the control voltage (V ＣＧ ) is at a low level, the output voltage (V ＯＵＴ ) is at a high level, and the control voltage (V ＣＧ ) is at a high level, the output voltage (V ＯＵＴ 8. The variable logic-in memory cell according to claim 7, wherein the logic operation function is performed when the level of the first transistor is a low level.

9. The variable logic-in memory cell includes: The triple-gate feedback memory element constituting the first second parallel connection unit among the plurality of second parallel connection units performs the first channel operation, and the triple-gate feedback memory element constituting the last second parallel connection unit performs the second channel operation, and the control voltage (V ＣＧ ) is at a low level, the output voltage (V ＯＵＴ ) is at a low level, and the control voltage (V ＣＧ ) is at a high level, the output voltage (V ＯＵＴ 8. The variable logic-in memory cell according to claim 7, wherein said logic operation function is performed when the level of said first transistor is a high level.

10. The variable logic-in memory cell includes: The triple-gate feedback memory element constituting the first second parallel connection unit among the plurality of second parallel connection units performs the second channel operation, and the triple-gate feedback memory element constituting the last second parallel connection unit performs the first channel operation, and the control voltage (V ＣＧ ) the first control voltage (V Ａ ) is applied to the left side of the first second parallel connection and to the top side of the last second parallel connection, and the control voltage (V ＣＧ ) the second control voltage (V Ｂ ) is applied to the right side of the first second parallel connection part and the bottom side of the last second parallel connection part, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) is at a high level or both are at a low level, ＯＵＴ ) is at a high level, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) are both at a high level, the output voltage (V ＯＵＴ 8. The variable logic-in memory cell according to claim 7, wherein the logic operation function is performed when the level of the first transistor is a low level.

11. The variable logic-in memory cell includes: The triple-gate feedback memory element constituting the first second parallel connection unit among the plurality of second parallel connection units performs the second channel operation, and the triple-gate feedback memory element constituting the last second parallel connection unit performs the first channel operation, and the control voltage (V ＣＧ ) the first control voltage (V Ａ ) is applied to the upper side of the first second parallel connection and to the left side of the last second parallel connection, and the control voltage (V ＣＧ ) the second control voltage (V Ｂ ) is applied to the lower side of the first second parallel connection and to the right side of the last second parallel connection, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) is at a low level or both are at a high level, ＯＵＴ ) is at a low level, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) are at a low level, the output voltage (V ＯＵＴ 8. The variable logic-in memory cell according to claim 7, wherein said logic operation function is performed when the level of said first transistor is a high level.

12. The variable logic-in memory cell includes: The triple-gate feedback memory element constituting the first second parallel connection unit among the plurality of second parallel connection units performs the first channel operation, and the triple-gate feedback memory element constituting the last second parallel connection unit performs the second channel operation, and the control voltage (V ＣＧ ) the first control voltage (V Ａ ) is applied to the upper side of the first second parallel connection and to the left side of the last second parallel connection, and the control voltage (V ＣＧ ) the second control voltage (V Ｂ ) is applied to the lower side of the first second parallel connection and to the right side of the last second parallel connection, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) is at a low level, the output voltage (V ＯＵＴ ) is at a low level, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) are both at a high level, the output voltage (V ＯＵＴ 8. The variable logic-in memory cell according to claim 7, wherein said logic operation function is performed when the level of said first transistor is a high level.

13. The variable logic-in memory cell includes: The triple-gate feedback memory element constituting the first second parallel connection unit among the plurality of second parallel connection units performs the first channel operation, and the triple-gate feedback memory element constituting the last second parallel connection unit performs the second channel operation, and the control voltage (V ＣＧ ) the first control voltage (V Ａ ) is applied to the left side of the first second parallel connection and to the top side of the last second parallel connection, and the control voltage (V ＣＧ ) the second control voltage (V Ｂ ) is applied to the right side of the first second parallel connection part and the bottom side of the last second parallel connection part, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) is at a high level, the output voltage (V ＯＵＴ ) is at a high level, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) are at a low level, the output voltage (V ＯＵＴ 8. The variable logic-in memory cell according to claim 7, wherein the logic operation function is performed when the level of the first transistor is a low level.

14. The variable logic-in memory cell includes: The triple-gate feedback memory elements constituting the first second parallel connection unit of the plurality of second parallel connection units are configured with the second circuit structure, and the left side of the triple-gate feedback memory elements constituting the first second parallel connection unit of the plurality of second parallel connection units performs the first channel operation, and the right side of the triple-gate feedback memory elements constituting the last second parallel connection unit performs the second channel operation, the upper left side of the triple-gate feedback memory elements constituting the last second parallel connection unit performs the second channel operation, the upper right side of the triple-gate feedback memory elements constituting the first channel operation, the lower left side of the triple-gate feedback memory elements constituting the first channel operation, and the lower right side of the triple-gate feedback memory elements constituting the last second parallel connection unit; ＣＧ ) the first control voltage (V Ａ ) is applied to the upper sides of the first second parallel connection and the last second parallel connection, and the control voltage (V ＣＧ ) the second control voltage (V Ｂ ) is applied to the lower sides of the first second parallel connection part and the last second parallel connection part, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) are at the same level, the output voltage (V ＯＵＴ ) is at a high level, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) are at different levels, the output voltage (V ＯＵＴ 8. The variable logic-in memory cell according to claim 7, wherein the logic operation function is performed when the level of the first transistor is a low level.

15. The variable logic-in memory cell includes: The triple-gate feedback memory elements constituting the first second parallel connection unit of the plurality of second parallel connection units are configured with the second circuit structure, and the upper left side of the triple-gate feedback memory elements constituting the first second parallel connection unit performs the second channel operation, the upper right side of the triple-gate feedback memory elements constituting the first channel operation, the lower left side of the triple-gate feedback memory elements constituting the last second parallel connection unit performs the first channel operation, and the right side of the triple-gate feedback memory elements constituting the last second parallel connection unit performs the first channel operation, and the control voltage (V ＣＧ ) the first control voltage (V Ａ ) is applied to the upper sides of the first second parallel connection and the last second parallel connection, and the control voltage (V ＣＧ ) the second control voltage (V Ｂ ) is applied to the lower sides of the first second parallel connection part and the last second parallel connection part, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) are at the same level, the output voltage (V ＯＵＴ ) is at a low level, and the first control voltage (V Ａ ) and the second control voltage (V Ｂ ) are at different levels, the output voltage (V ＯＵＴ 8. The variable logic-in memory cell according to claim 7, wherein said logic operation function is performed when the level of said first transistor is a high level.

16. The variable logic-in memory cell includes: The drain voltage (V ＤＤ ), the source voltage (V ＳＳ ), the program voltage (V ＰＧ ) and the control voltage (V ＣＧ ) is applied at a zero level, the output voltage (V ＯＵＴ 8. The variable logic-in memory cell according to claim 7, wherein the memory function is performed by maintaining a level of the first charge-discharge potential.

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