NAND flash memory device control device and method thereof

Abstract

A control device for a NAND flash memory device according to an embodiment includes a NAND flash memory, a controller that generates command signals for writing, reading, and deleting data to the NAND flash memory, and an auxiliary power circuit that maintains power for operating the memory and the controller for a first time period from a first time point when the voltage of a power supply becomes lower than a predetermined voltage, wherein the controller cuts off the command signal during the first time period, and power is cut off from the memory for at least a second time period from a second time point after the first time period.

Description

[Technical field]

[0001] The embodiments relate to a control device for a NAND flash memory device, and more particularly to a control device and method for a NAND flash memory device capable of preventing data corruption that occurs in an unstable power supply environment such as a power interruption. [Background technology]

[0002] Recently, there has been an increasing demand for non-volatile memory devices that can be electrically programmed and erased and do not require a refresh function to periodically recreate data. In order to develop large-capacity memory devices that can store a large amount of data, research into high-integration technologies for memory devices is being actively conducted. Here, "program" refers to the action of writing data to a memory cell, and "erase" refers to the action of deleting data written in a memory cell.

[0003] As a result, a NAND flash memory device has been proposed in which multiple memory cells are connected in series (i.e., adjacent cells share a drain or source) to form one string in order to achieve high integration of non-volatile memory devices. Unlike NOR type flash memory devices, NAND flash memory devices are memory devices that read information sequentially, and perform program and erase operations by controlling the threshold voltage of the memory cell while injecting or discharging electrons into the floating gate using the Fowler-Nordheim (FN) tunneling method.

[0004] Therefore, an erased cell has a negative threshold voltage because electrons are discharged from the floating gate, and the erased cell state is called an on-cell. A programmed cell has a positive threshold voltage because electrons are injected into the floating gate, and the programmed cell state is called an off-cell.

[0005] Meanwhile, in recent years, wireless communication and GPS (Global Positioning System) technology have been combined to apply telemetics to automobiles to provide various mobile communication services such as location information, safe driving, entertainment, financial services, reservations, and product purchases. The telemetics includes the above-mentioned NAND flash memory device, and thereby programs data generated during driving in real time.

[0006] In addition, the eCall function, which is related to telematics and safety, automatically attempts to connect the call to 112, Europe's single emergency number, when a serious accident occurs. If the driver loses consciousness or is unable to make a call directly, the eCall function automatically provides the vehicle's location, type, color, and number of passengers to the emergency service center. Most countries have established emergency service systems similar to eCall that operate in the event of a vehicle accident, and such functions require high reliability as they involve human lives.

[0007] However, the NAND flash memory devices used in telematics as described above have a problem in that data corruption such as charge gain occurs when the power supply is unstable. That is, due to charge gain, which is a structural weakness of the NAND flash memory devices used in telematics products, data corruption occurs intermittently when the power supply is interrupted, resulting in a fundamental weakness in reliability and the problem that the eCall function cannot be performed normally. Summary of the Invention [Problem to be solved by the invention]

[0008] In the embodiment, a control device and a control method for a NAND flash memory device are provided, which can fundamentally solve data corruption caused by charge gain that occurs when a power supply is interrupted.

[0009] Also, the embodiments provide a control device and a control method for a NAND flash memory device, which can block memory access when a power interruption is detected, thereby solving problems that may occur when the memory is operating at the time of the power interruption.

[0010] In addition, the embodiments provide a control device and a control method for a NAND flash memory device, which can solve data corruption due to charge gain caused by power interruption during a program operation or erase operation of the NAND flash by supplying auxiliary power until the ongoing operation is completed when a power interruption is detected.

[0011] In addition, the embodiments provide a control device and a control method for a NAND flash memory device, which performs a power-off sequence of a flash memory when a momentary power interruption is detected, and performs a power-on sequence when a normal power supply is detected, so that the flash memory can operate normally when the power supply is restored.

[0012] The technical problems to be solved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the present invention pertains from the following description. [Means for solving the problem]

[0013] A control device for a NAND flash memory device according to an embodiment includes a NAND flash memory, a controller that generates command signals for writing, reading, and deleting data in the NAND flash memory, and an auxiliary power circuit that maintains power for operating the memory and the controller for a first time period from a first point in time when the voltage of a power supply becomes lower than a pre-set voltage, wherein the controller cuts off the command signal during the first time period, and the power supply to the memory is cut off for at least a second time period from a second point in time after the first time period.

[0014] Also, when the first point in time is a program operation time tPROG or an erase operation time tBERS of the memory, the auxiliary power circuit supplies auxiliary power for completing the program operation or erase operation of the memory.

[0015] The first time is a time until a program operation or an erase operation being performed in the memory before the first time point is completed.

[0016] The control device for the NAND flash memory device also includes a Power Management IC (PMIC) connected to the power supply to supply power to the memory and the controller.

[0017] In addition, the auxiliary power supply circuit is disposed between the PMIC and the memory.

[0018] The controller also controls the PMIC to supply power to the memory after the power supply is interrupted for at least the second period of time.

[0019] The auxiliary power supply circuit further includes an input voltage detector for detecting a voltage level of the power supply, the auxiliary power supply circuit being connected to a power input terminal of the PMIC.

[0020] Moreover, the input voltage detection unit detects the voltage level at the input terminal of the auxiliary power supply circuit. Effect of the Invention

[0021] According to the embodiment, an unstable state of the input power supply is detected and the operation of the NAND flash memory device is controlled based on the detected unstable state, thereby preventing defects such as data corruption that may occur when the NAND flash memory device operates in an unstable input power supply state. Specifically, according to the embodiment, when the input power supply is unstable, flash access is blocked, thereby preventing malfunction of the NAND flash memory device in an unstable input power supply environment.

[0022] In addition, according to the embodiment, if an operation of the NAND flash memory device is in progress when a power interruption is detected, auxiliary power is supplied until the ongoing operation is completed, thereby preventing data corruption due to charge gain that occurs when power is interrupted during a program operation or erase operation of the NAND flash memory device, thereby improving the operational reliability of the NAND flash memory device.

[0023] In addition, according to the embodiment, a power-off sequence of a NAND flash memory device is performed when a momentary power interruption is detected, and a power-on sequence is performed when a normal power supply is detected, thereby improving operational reliability and user satisfaction by allowing the flash memory to operate normally when the input power supply is restored. [Brief description of the drawings]

[0024] [Figure 1] FIG. 2 is a diagram illustrating the structure of a memory cell of a NAND flash memory element. [Diagram 2] 2 is an equivalent circuit diagram showing the memory cell array of FIG. 1. [Diagram 3] FIG. 2 is a diagram for explaining a program and erase operation of a NAND flash memory device. [Figure 4] FIG. 2 illustrates an erase operation of a NAND flash memory device. [Diagram 5] FIG. 1 is a diagram illustrating charge gain in a NAND flash memory element. [Figure 6] 1 is a block diagram showing a configuration of a NAND flash memory system in accordance with a first embodiment; [Figure 7] 7 is a diagram illustrating a modification of the NAND flash memory system shown in FIG. 6. [Figure 8] 7 is a diagram illustrating a modification of the NAND flash memory system shown in FIG. 6. [Figure 9] 4A to 4C are diagrams illustrating steps of an operation method of a NAND flash memory system according to an embodiment. [Figure 10] FIG. 13 is a diagram showing a power sequence according to a change in input voltage. [Figure 11] FIG. 13 is a diagram showing a power sequence according to a change in input voltage. [Figure 12] 1 is a flowchart illustrating a method for controlling a NAND flash memory system according to an embodiment. [Figure 13] 1 is a flowchart illustrating a method for controlling a NAND flash memory system according to an embodiment. [Figure 14] FIG. 4 is a diagram showing a change in input voltage when the vehicle is started. [Figure 15] 1 is a flowchart illustrating a step-by-step method for activating a memory protection function according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0026] However, the technical concept of the present invention is not limited to the embodiments described, but may be realized in various different forms, and one or more of the components between the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0027] Furthermore, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning commonly understood by a person of ordinary skill in the art to which the present invention belongs, unless otherwise clearly and specifically defined and described, and commonly used terms such as predefined terms may have their meaning interpreted taking into account the contextual meaning of the relevant art.

[0028] In addition, the terms used in the examples of the present invention are intended to describe the examples and are not intended to limit the present invention. In the present specification, the singular form may include the plural form unless otherwise specified in the phrase, and when it is described as "A and (and) at least one (or more) of B and C," it may include one or more of all combinations that can be combined with A, B, and C.

[0029] In addition, in describing components of the present invention, terms such as first, second, A, B, (a), (b), etc. are used. Such terms are merely used to distinguish the components from other components, and are not limited to the essence, order, or sequence of the components. Furthermore, when a component is described as being "coupled," "bonded," or "connected" to another component, it includes not only the case where the component is directly coupled, coupled, or connected to the other component, but also the case where the component is "coupled," "bonded," or "connected" by another component between the component and the other component.

[0030] In addition, when it is described that something is formed or placed "above or below" each component, "above" or "below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or placed between the two components. In addition, when it is expressed as "above or below," it can include not only the upward direction based on one component, but also the downward direction.

[0031] FIG. 1 is a diagram illustrating the structure of a memory cell of a NAND flash memory element.

[0032] Referring to FIG. 1, the operation of a NAND flash memory device consists of three operations: erase, program, and read.

[0033] A program operation of a NAND flash memory device is performed in units of a page.

[0034] In the program operation, a constant voltage (e.g., 19V) is applied to the control gate (CG) of the memory cell, causing electrons to move toward the floating gate (FG) 10. At this time, the state of the memory cell becomes an OFF TR or OFF cell state, and the threshold voltage becomes positive (+) Vt. At this time, the program operation of the flash memory device is not completed in one go, but may be performed over multiple steps, and the voltage applied to the control gate can be increased to program desired data.

[0035] In addition, the erase operation of a NAND flash memory device is performed in units of blocks and can mean changing a cell from 0 to 1.

[0036] At this time, to perform an erase operation of the NAND flash memory device, a constant voltage (e.g., 20V) is applied to the P substrate, and electrons in the floating gate 10 of the memory cell move downward due to the FN tunneling effect. Then, the erased memory cell can have a negative (-) threshold voltage Vt as electrons in the floating gate 10 are discharged. At this time, the state of the erased memory cell can be called an ON TR or ON cell state.

[0037] Also, the read operation of a NAND flash memory device means an operation of checking whether the state of a memory cell is an On TR or Off TR state and outputting data as 1 or 0.

[0038] FIG. 2 is an equivalent circuit diagram showing the memory cell array of FIG.

[0039] 2, a memory cell array of a NAND flash memory device is made up of a plurality of blocks, and a plurality of bit lines BL0 to BLn are arranged in parallel in each block.

[0040] Also, in each block, a plurality of strings are arranged corresponding to a plurality of bit lines BL0 to BLn, respectively. Each string may include a drain select transistor (DST) and a source select transistor (SST) for selecting a corresponding string. Also, each string includes a plurality of memory cells MC0 to MCn (where n may be 15, 31, or 63) connected in series between the drain select transistor DST and the source select transistor SST. Also, the sources of the source select transistors SST of each string are commonly connected to a common source line (CSL).

[0041] The gates of the drain select transistors DST configured in each of the strings are connected to a drain select line (DSL), and the gates of the source select transistors SST are connected to a source select line (SSL). Also, the control gates (CG) of the memory cells MC0 to MCn are connected to word lines WL0 to WLn.

[0042] A NAND flash memory device having such a memory cell array performs read and program operations in units of pages and erase operations in units of blocks, where a page unit includes all memory cells having control gates commonly connected to one word line.

[0043] FIG. 3 is a diagram for explaining a schematic diagram of program and erase operations of a NAND flash memory device.

[0044] Referring to FIG. 3, the program and erase operations of a NAND flash memory device refer to changing the state of a memory cell from "0" to "1" or from "1" to "0."

[0045] As shown in FIG. 2, the floating gate FG is located between the control gate CG and the P substrate. Here, since the floating gate FG is insulated from the control gate CG and the P substrate by an oxide layer, electrons located therein are trapped. At this time, when electrons are present in the floating gate FG, they affect the electric field emerging from the control gate CG, and the threshold voltage Vt of the memory cell can be changed. That is, the threshold voltage Vt of the memory cell can be changed to a positive (+) value (+Vt) or a negative (-) value (-Vt) based on 0V according to the number of electrons present in the floating gate FG.

[0046] In this way, when a certain voltage is applied to the control gate CG to read the information of the memory cell, the threshold voltage Vt varies depending on the number of electrons in the floating gate FG, which allows or prevents current from flowing. The presence or absence of such current flow is read and interpreted as data "1" or "0." In addition, in MLC (Multi-level cell) devices in which one memory cell stores one or more bits of information, the amount of current is read rather than simply determining the flow of current to measure the number of electrons stored in the floating gate (FG).

[0047] 3(a), the program operation of the NAND flash memory device applies a constant voltage (e.g., 19V) to the control gate of a memory cell, causing electrons to move toward the floating gate 10. At this time, the state of the memory cell becomes the OFF TR state, and has a positive (+) threshold voltage Vt.

[0048] 3(a), by applying a constant voltage to the control gate CG, electrons move to the floating gate 10, and as the number of the moving electrons increases, the threshold voltage Vt of the corresponding memory cell may increase to or above the reference threshold voltage RV. When the threshold voltage Vt of the memory cell increases to or above the reference threshold voltage RV, the state of the corresponding memory cell may change from "1" to "0." Here, the reference threshold voltage RV may be set to various values ​​according to the memory specifications, for example, to a specific value greater than 0V.

[0049] Also, referring to FIG. 3(b), in the erase operation of the NAND flash memory device, a constant voltage (e.g., 20V) is applied to the P substrate, and electrons in the floating gate 10 of the memory cell move downward due to the FN tunneling effect.

[0050] That is, as shown in FIG 3(b), the erase operation reduces the number of electrons in the floating gate, which may reduce the threshold voltage Vt of the corresponding memory cell. When the threshold voltage Vt of the memory cell decreases below the reference threshold voltage RV, the state of the corresponding memory cell may change from "0" to "1".

[0051] As described above, the program operation and erase operation of the NAND flash memory device can be distinguished based on the reference threshold voltage RV of the memory cell, which changes depending on the amount of charge present in the floating gate 10, as shown in Figures 3(a) and 3(b). That is, when the threshold voltage Vt of the memory cell is equal to or higher than the reference threshold voltage RV, the NAND flash memory device recognizes it as "0" and performs a program operation. Also, when the threshold voltage Vt of the memory cell is lower than the reference threshold voltage RV, the NAND flash memory device recognizes it as "1" and performs an erase operation.

[0052] However, in such a NAND flash memory device, data corruption occurs if an unstable condition of the power supply (e.g., a momentary interruption of the power supply) occurs during the process of moving electrons by the above-mentioned program or erase operation. That is, when the power supply is interrupted momentarily while the threshold voltage Vt of the memory cell is increasing from a negative (-) value to a positive (+) value or while the threshold voltage Vt of the memory cell is decreasing from a positive (+) value to a negative (-) value due to the movement of electrons as shown in Fig. 3(a), the NAND flash memory device may not be able to accurately determine whether the device was performing a program operation or an erase operation before the power interruption.

[0053] FIG. 4 is a diagram showing an embodiment of an erase operation of a NAND flash memory device in chronological order.

[0054] 4, the NAND flash memory device may perform an erase operation according to a control signal input from a controller (described later). The control signal may include a command signal and an address signal. In addition, VCC in FIG. 4 may represent a power supply voltage, and VSS may represent a ground voltage.

[0055] 4 indicates whether the command input in each cycle is a command or an address. For example, if the cycle type is a command, it indicates that the data input through the current data bus is a command, and if the cycle type is an address, it indicates that the data input through the current data bus is an address. I / O[7:0] indicates a data bus, and a ready (RDY) signal is a signal that informs the controller that the NAND flash memory device is ready or in use (e.g., during an erase operation), and at tBERS when this signal becomes a low level, the NAND flash memory device informs the controller that an erase operation is currently in progress. That is, the NAND flash memory device can maintain the state of a pin that transmits the red (RDY) signal among a plurality of pins connected to the controller in a high state until it becomes a busy state for performing a specific operation, and can change it to a low state at the time when it becomes a busy state.

[0056] At this time, the erase operation of the NAND flash memory device can be roughly divided into three sections: the first section is the time required to transmit a command and an address into the NAND flash memory device, the second section is the time tWB required for the NAND flash memory device to enter a busy state for performing a specific operation, and the third section is the time tBERS required to erase memory cells in units of blocks.

[0057] The NAND flash memory device operates based on a power supply voltage (e.g., VCC). If the power supply voltage decreases to a level at which the NAND flash memory device does not operate normally, intermittent data corruption may occur.

[0058] That is, if the input voltage drops below a certain level while the NAND flash memory device is performing a program or erase operation, the NAND flash memory device stops the operation and then resumes the program or erase operation when a normal voltage is input.

[0059] Unlike volatile memories such as RAM, non-volatile memories such as the NAND flash memory device experience charge gain when a power reset (or power interruption) occurs during the above program or erase operation. Here, charge gain refers to a state in which the cell threshold voltage Vt is located within a marginal region where "0" and "1" cannot be distinguished. Here, the marginal region refers to a region in which the cell threshold voltage Vt is between 0V and the reference threshold voltage RV. At this time, the memory may malfunction, significantly reducing the reliability of the product.

[0060] 5 illustrates the charge gain in a NAND flash memory device. Referring to FIG 5, a NAND flash memory device includes a charge gain that occurs during a program operation and a charge gain that occurs during an erase operation.

[0061] As shown in FIG. 5(a), a NAND flash memory device can perform a program operation according to an instruction from a control unit. If power is cut off during the movement of electrons by the program operation, the movement of electrons is stopped at the point where power is cut off. Here, the threshold voltage Vt of the memory cell at the point where the program operation is stopped may be located in a marginal region where "0" and "1" cannot be distinguished. If the threshold voltage Vt of the memory cell is located in the marginal region as described above, the control unit (described later) cannot clearly determine whether the threshold voltage Vt of the memory cell is "0" or "1". This may cause a system failure.

[0062] As shown in FIG. 5(b), the NAND flash memory device can perform an erase operation according to a command from a control unit. If power is cut off during the movement of electrons by the erase operation, the movement of electrons is stopped at the point where power is cut off. Here, the threshold voltage Vt of the memory cell at the point where the erase operation is stopped may be located within a marginal region where "0" and "1" cannot be distinguished. When the threshold voltage Vt of the memory cell is located within the marginal region as described above, the control unit (described later) cannot clearly determine whether the threshold voltage Vt of the memory cell is "0" or "1". This may cause a system failure.

[0063] A NAND flash memory system according to an embodiment will be described below.

[0064] FIG. 6 is a block diagram showing the configuration of a NAND flash memory system according to the first embodiment.

[0065] 6, a system 100 includes a power supply device and control device 200. The power supply device may include a conversion unit 110, an input voltage detection unit 120, and a detection signal transmission unit .

[0066] The conversion unit 110 of the power supply device receives an input voltage corresponding to a main power, converts the input voltage into a voltage required by each component of the control device 200, and outputs the voltage.

[0067] Furthermore, the input voltage detection section 120 of the power supply device can detect the voltage of the main power supply and output a detected signal.

[0068] Furthermore, the detection signal transmission unit 130 of the power supply device can transmit the output signal of the input voltage detection unit 120 to the control device 200 .

[0069] The control device 200 may include a storage device. The control device 200 may operate using a voltage input from a power supply device as a driving voltage. The control device 200 may communicate with the vehicle control unit 300 and store data transmitted from the vehicle control unit 300. For example, the control device 200 may be installed in a vehicle and support an eCall function of the vehicle. That is, the control device 200 may communicate with the vehicle control unit 300 and store information for reporting an emergency and requesting assistance. For example, the information may include accident location information, vehicle type information, driving direction information, the number of seat belts activated at the time of the accident, etc.

[0070] The control device 200 may include a memory 210, a power supply unit 220, an auxiliary power supply unit 230, and a control unit 240. The control unit 240 of the control device 200 may control the memory 210. Preferably, the control unit 240 may receive an operation signal (e.g., a ready and busy output signal) from the memory 210 and access the memory 210 based on the received operation signal. The operation signal may correspond to a timing of a NAND flash memory device constituting the memory 210. Here, the timing may be converted into different time periods according to the operation type of the device. For example, the different time periods according to each operation type may include a time tR (read operation) for loading data from a memory cell (not shown) to a page register (not shown), a time tPROG (program operation) for loading data from the page register to a memory cell, a time tBERS (delete operation) for deleting memory cells in units of blocks, etc.

[0071] In addition, the control unit 240 of the control device 200 can control access to the memory 210 based on an output signal corresponding to the input voltage operation transferred from the power supply devices 110, 120, and 130.

[0072] Specifically, the control unit 240 of the control device 200 can halt the operation of the memory 210 under an unstable input voltage condition or a data protection condition of the memory 210 based on the output signal of the input voltage detection unit 120 of the power supply devices transferred from the power supply devices 110, 120, 130. Here, halting the operation of the memory 210 can mean halting access to the memory 210 and further means blocking output of commands for controlling the operation of the memory 210. That is, the control unit 240 of the control device 200 can detect the unstable input voltage condition or the data protection condition when the protection function of the memory 210 is turned on, and halt the operation of the memory 210 based on the detected unstable input voltage condition or the data protection condition.

[0073] The control device 200 and the power supply devices 110, 120, 130 will be described in detail below.

[0074] The power supply device may include a conversion unit 110, an input voltage detection unit 120, and a detection signal transmission unit 130. In the drawings, each component of the power supply devices 110, 120, and 130 is shown as being configured separately from the control device 200, but is not limited thereto. That is, some of the components of the power supply devices 110, 120, and 130 may be included in the control device 200.

[0075] The converter 110 can receive an input voltage and convert it to generate an output voltage.

[0076] The conversion unit 110 may be realized as a regulator. That is, the regulator may receive an input voltage through an input terminal and output an output voltage obtained by converting the input voltage through an output terminal. The voltage supplied to the control device 200 through the regulator may be a driving voltage for each component constituting the control device 200. For example, the voltage supplied to the control device 200 through the regulator may be a driving voltage for the memory 210. The regulator stabilizes and outputs the input voltage, thereby supplying a stable driving voltage to the control device 200 and enabling the memory 210 constituting the control device 200 to operate stably.

[0077] Meanwhile, the input voltage input to the converter 110 may be supplied from a power supply unit (not shown) For example, the power supply unit may be a battery of a vehicle in which the NAND flash memory system is installed.

[0078] The input voltage detection unit 120 detects the magnitude of the input voltage input via the power supply unit, and can output a voltage detection signal corresponding to the magnitude.

[0079] At this time, under normal conditions, the input voltage may have a first level V1.

[0080] The input voltage detection unit 120 may output a first voltage detection signal when the input voltage has a level in a range between the first level V1 and a second level V2 lower than the first level V1. The input voltage detection unit 120 may output a second voltage detection signal when the level of the input voltage is lower than the second level V2 lower than the first level V2. Here, the first voltage detection signal may be a low-level detection signal, and the second voltage detection signal may be a high-level detection signal, but is not limited thereto.

[0081] To this end, the input voltage detection unit 120 may include a comparator (not shown) that receives a reference signal corresponding to the second level V2 through a positive terminal and an input voltage through a negative terminal and outputs a voltage detection signal of a high level or a low level according to a comparison result between the input voltage and the reference signal.

[0082] Meanwhile, the input voltage detection unit 120 can adjust the detection voltage through a voltage dividing resistor, etc. The voltage dividing resistor can divide the input voltage at a preset voltage dividing ratio and transmit the divided voltage to the comparator.

[0083] The detection signal transmission unit 130 is connected to the control device 200, and can thereby transmit a voltage detection signal detected via the input voltage detection unit 120 to the control device 200. Specifically, the detection signal transmission unit 130 is connected to the control unit 240 of the control device 200, and can transmit a high signal or a low signal to the control unit 240 based on the voltage detection signal.

[0084] To this end, the detection signal transfer unit 130 may include first to third resistors R1, R2, and R3 and a transistor S1. The first to third resistors R1, R2, and R3 and the transistor S1 may be a logic circuit that converts a high voltage of the voltage detection signal into a low voltage that can be received by the control unit 240 of the control device 200 and outputs the low voltage. The specific connection structure and operation are as follows.

[0085] The first resistor R1 may have one end connected to the output terminal of the input voltage detection unit 120 and the other end connected to one end of the third resistor R3 and the base of the transistor S1.

[0086] The second resistor R2 may have one end connected to a power terminal of the power supply unit 220 of the control device 200, and the other end connected to the collector of the transistor S1 and the signal input terminal GPIO of the control unit 240.

[0087] The third resistor R3 may have one end connected to the other end of the first resistor R1 and the base of the transistor S1, and the other end connected to the emitter of the transistor S1 and a ground terminal.

[0088] The transistor S1 may have a base connected to an output terminal of the input voltage detection unit 120 via a first resistor R1, a collector connected to a signal input terminal GPIO of the control unit 240, and an emitter connected to a ground terminal.

[0089] The transistor S1 can receive a voltage detection signal from the input voltage detection unit 120 via its base.

[0090] Specifically, the transistor S1 may be turned on or off according to a voltage detection signal of the input voltage detection unit 120 input to the base. For example, the voltage detection signal may be a high signal or a low signal as described above. The transistor S1 may be switched to an on state when a high signal is applied to the base, thereby outputting a second detection signal indicating a voltage abnormality to the collector. The transistor S1 may be switched to an off state when a low signal is applied to the base, thereby outputting a first detection signal, which is a high signal indicating a normal voltage, to the collector. Meanwhile, in the embodiment, the transistor S1 is turned on by a high signal and turned off by a low signal, but this is not limited thereto, and the operations may be interchangeable.

[0091] The memory 210 may be a non-volatile memory that allows data to be programmed, erased, and read. For example, the memory 210 may be a non-volatile memory device that allows data to be electrically programmed and erased and does not require a refresh function that periodically recreates data. Specifically, the memory 210 may be a NAND type flash memory device.

[0092] The memory 210 has been specifically described with reference to FIGS. 1 to 5, so a detailed description thereof will be omitted here.

[0093] The power supply unit 220 is connected to the output terminal out of the conversion unit 110, receives an output voltage of the conversion unit 110, stabilizes the received output voltage, and supplies a driving voltage to the memory 210. That is, the power supply unit 220 may be a PMIC (Power Management IC) that supplies a driving voltage to the memory 210. The PMIC constituting the power supply unit 220 may be a power control module composed of a discrete power element module for power, a high-voltage power circuit, a low-voltage digital circuit, and high-voltage and low-voltage analog circuits, and thus can play a role in converting, distributing, charging, and controlling an input voltage input to the control device 200 according to the memory 210.

[0094] An auxiliary power supply unit 230 may be disposed between the power supply unit 220 and the memory 210. The auxiliary power supply unit 230 may be a capacitor that performs a charging operation under a first condition and a discharging operation under a second condition. Here, the first condition may be a condition in which an input voltage within a normal range is input to an input terminal of the system, and the second condition may be a condition in which a low voltage outside the normal range is input to the input terminal.

[0095] The auxiliary power supply unit 230 may discharge and supply a driving voltage to the memory 210 when the output voltage of the power supply unit 220 is lower than a preset second level V2 under a system power-on condition. At this time, a discharge time of the auxiliary power supply unit 230 is determined in proportion to a capacitance of a capacitor constituting the auxiliary power supply unit 230. Thus, in the embodiment, the capacitance of the capacitor constituting the auxiliary power supply unit 230 may be determined in consideration of a time required to load data from a memory cell of the memory 210 to a page register, a time required to load data from the page register to a memory cell, and a time required to erase a memory cell in a block unit.

[0096] The control unit 240 can control the operation of the memory 210 .

[0097] Specifically, the control unit 240 can access the memory 210 and control the program, erase, and read operations of the memory 210 .

[0098] To this end, the controller 240 may be connected to the memory 210 via a bus, and the controller 240 may transmit commands and addresses to the memory 210 and transmit and receive data thereto via the bus.

[0099] Meanwhile, the control unit 240 can monitor the output signal of the detection signal transmission unit 130. That is, the control unit 240 can monitor a change in the input voltage input to the system.

[0100] When the first detection signal indicating that the input voltage is normal is received through the detection signal transmission unit 130, the control unit 240 can access the memory 210 and perform a program operation or an erase operation according to the first detection signal.

[0101] At this time, when a second detection signal notifying an abnormality in the input voltage is input through the detection signal transmission unit 130, the control unit 240 blocks the output of commands to the memory 210 from the point in time when the second detection signal is input.

[0102] In other words, when the second detection signal is input through the detection signal transmission unit 130, the control unit 240 blocks the output of the command and stops accessing the memory 210.

[0103] The control unit 240 ignores all commands related to the operation of the memory 210 from the time the second detection signal is input, and blocks any commands from being output to the memory 210 from the time the second detection signal is input.

[0104] The control unit 240 and the memory 210 may be powered off after a certain time from when the second detection signal is input. Here, the certain time may refer to the time until the memory 210 normally completes an operation (program operation or erase operation) that was previously performed by the memory 210 using the auxiliary power supplied through the auxiliary power unit 230.

[0105] The memory 210 may be powered off when the input voltage of the main power supply to the system decreases to a third level V3 corresponding to a power-off voltage of the memory 210. That is, when the input voltage of the main power supply decreases to the third level V3, the memory 210 may be naturally powered off due to a power shortage.

[0106] In addition, even if the input voltage of the main power source does not decrease to the third level V3 but returns to the first level V1 again, the memory 210 may be powered off. To this end, the vehicle control unit 300 can turn off the power supply unit 220 of the control device 200 to power off the control device 200. Thereafter, the vehicle control unit 300 can turn on the power supply unit 220 again to power on the control device 200.

[0107] However, the memory 210 in the embodiment may be a NAND flash memory device corresponding to a non-volatile memory. At this time, unlike a RAM which is a volatile memory, the NAND flash memory device does not lose data stored therein even if the input power is cut off. Therefore, the NAND flash memory device does not need to be supplied with auxiliary power even if the power is suddenly cut off because there is no need to worry about the internal data being lost even if the input power is cut off. However, unlike the RAM, the NAND flash memory device distinguishes between "0" and "1" by comparing a boundary region set based on a reference threshold voltage RV with a threshold voltage Vt of a memory cell as described in FIG. 1 to FIG. 5.

[0108] Therefore, if the memory 210 is in the middle of a program or erase operation when the second detection signal is input, if a power-off sequence is performed without completing the program or erase operation, the program or erase operation will be continued when power is restored later.

[0109] However, as described above, if the memory cell has a threshold voltage Vt within a boundary region (0V to reference threshold voltage RV) when the power is restored, it cannot determine whether the value of the memory 210 is "0" or "1", which may cause the control unit 240 to malfunction. Therefore, the control unit 240 can delay the power-off sequence until the program operation or erase operation is completed in case the second detection signal is input at a program operation time tPROG or erase operation time tBERS of the memory 210. In other words, the control unit 240 can supply auxiliary power so that the memory 210 is not powered off until the program operation or erase operation currently being performed by the memory 210 is completed.

[0110] The memory 210 may complete the program or erase operation by being driven by the discharge voltage of the auxiliary power supply unit 230 under the above-described data protection condition of the memory 210. Furthermore, the memory 210 may transmit a completion signal to the control unit 240 when the program or erase operation is completed.

[0111] The control unit 240 recognizes that the operation of the memory 210 is completed, and can proceed with a power-off sequence of the memory 210.

[0112] According to the embodiment, an unstable state of the input power supply is detected and the operation of the NAND flash memory device is controlled based on the detected unstable state, thereby preventing defects such as data corruption that may occur when the NAND flash memory device operates in an unstable input power supply state. Specifically, according to the embodiment, by blocking flash access when the input power supply is unstable, it is possible to prevent malfunction of the NAND flash memory device in an unstable input power supply environment.

[0113] In addition, according to the embodiment, if an operation of the NAND flash memory device is in progress when a power interruption is detected, auxiliary power is supplied until the ongoing operation is completed, thereby preventing data corruption due to charge gain that occurs when power is interrupted during a program operation or erase operation of the NAND flash memory device, thereby improving the operational reliability of the NAND flash memory device.

[0114] In addition, according to the embodiment, when a momentary power interruption is detected, a power-off sequence of the NAND flash memory device is performed, and when a normal power supply is detected, a power-on sequence is performed, so that when the input power supply is restored, the flash memory operates normally, thereby improving operational reliability and user satisfaction.

[0115] Meanwhile, in FIG. 6, it is described that the auxiliary power supply unit 230 is provided within the control device 200, but the auxiliary power supply unit 230 may be disposed at a location other than between the power supply unit 220 and the memory 210 within the control device 200.

[0116] 7 and 8 illustrate a modification of the NAND flash memory system shown in FIG.

[0117] 7 and 8 differ only in the location of the auxiliary power supply unit that supplies auxiliary power to the memory 210 when an abnormality occurs in the input voltage, and the rest of the components may be the same as those in Fig. 6. Therefore, the following description will be limited to the auxiliary power supply unit.

[0118] 7, the NAND flash memory system may include a converter 110, an input voltage detector 120, a detection signal transmitter 130, a memory 210, a power supply 220, and a controller 240. An auxiliary power supply 140 is disposed between an output terminal of the converter 110 and an input terminal of the power supply 220. The auxiliary power supply 140 may provide a discharge voltage to the power supply 220 when an abnormality occurs in the input voltage to the system, so that a driving voltage based on the discharge voltage may be transmitted to the memory 210.

[0119] 8, the NAND flash memory system may include a converter 110, an input voltage detector 120, a detection signal transmitter 130, a memory 210, a power supply 220, and a controller 240. An auxiliary power supply 150 is disposed at an input terminal of the converter 110. The auxiliary power supply 150 may provide a discharge voltage to the converter 110 when an abnormality occurs in an input voltage to the system, so that a driving voltage based on the discharge voltage may be transmitted to the memory 210.

[0120] FIG. 9 is a diagram illustrating a step-by-step operation of a NAND flash memory system according to an embodiment.

[0121] 9, under a condition where an input voltage in a normal range is input, the control unit 240 can access the memory 210 and transmit a command and an address to the memory 210. That is, the control unit 240 can transmit a command to the memory 210 under a normal condition, thereby causing at least one of a program operation, an erase operation (or a read operation) and a read operation of the memory 210 to be performed (S100).

[0122] Thereafter, the control unit 240 may check the voltage detection signal inputted through the signal input terminal GPIO in a polling or interrupt manner, and may determine whether a second detection signal notifying that an input voltage lower than the second level V2 has been detected has been received through the signal input terminal GPIO (S110).

[0123] When the control unit 240 receives a second detection signal indicating that an input voltage lower than the second level V2 has been detected, the control unit 240 may stop accessing the memory 210 and block the output of commands provided to the memory 210 (S120).

[0124] 10 and 11 are diagrams showing power sequences according to changes in input voltage.

[0125] 10, under a normal condition, the input voltage may have a first level V1, and the input voltage detector 120 and the detection signal transmitter 130 may output a voltage abnormality detection signal when the input voltage decreases to the second level V2.

[0126] Thus, the control unit 240 can stop access to the memory 210 (ACCESS STOP) at the first time point T1 when the voltage abnormality detection signal is received.

[0127] Thereafter, the level of the input voltage may continue to decrease until it reaches a third level V3, at which point the memory 210 may be powered off due to lack of power.

[0128] Meanwhile, the power input to the system may be suddenly cut off as shown in FIG. 10, causing the input voltage level to drop to 0V.

[0129] However, in contrast, the power input to the system can be restored to its original voltage level after being momentarily interrupted.

[0130] 11, under normal conditions, the input voltage may have a first level V1, and the input voltage detector 120 and the detection signal transmitter 130 may output a voltage abnormality detection signal when the input voltage decreases to the second level V2.

[0131] Thus, the control unit 240 can stop access to the memory 210 (ACCESS STOP) at the first time point T1 when the voltage abnormality detection signal is received.

[0132] The input voltage can then rise again to its original level at a second time T2.

[0133] At this time, even if the input voltage is restored to the first level V1, the control unit 240 cannot normally control the memory 210 because the access interruption operation has already been performed as described above. As a result, the vehicle control unit 300 turns off the power supply unit 220 to power off the control device 200. To this end, the vehicle control unit 300 may include an input voltage detection unit that detects the input voltage of the main power source (see FIG. 6). Alternatively, the vehicle control unit 300 may be connected to the input voltage detection unit 120 to monitor the input state of the main power source. Then, the vehicle control unit 300 may turn off the power supply unit 220 based on the input state of the main power source.

[0134] Then, if the input voltage maintains the first level V1 from the third point in time T3 to a fourth point in time T4, which is a certain time period after the third point in time T3, the vehicle control unit 300 can power on the power supply unit 220 and power on the control device 200.

[0135] 12 and 13 are flow charts illustrating steps of a method for controlling a NAND flash memory system according to an embodiment.

[0136] 12, in the power sequence of the NAND flash memory system according to the embodiment, the controller 240 can access the memory 210 under a condition that an input voltage within a normal range is input, and can transfer a command and an address to the memory 210. That is, the controller 240 can transfer a command (COMMAND) to the memory 210 under a normal condition, and can cause at least one of a program operation, an erase operation, and a read operation of the memory 210 to be performed accordingly (S200).

[0137] Thereafter, the control unit 240 determines whether the input voltage is lower than the second level V2 based on the voltage detection signal (S210).

[0138] Then, when the input voltage falls below the second level V2, the control unit 240 stops accessing the memory 210 (S220).

[0139] Thereafter, the input voltage may decrease to below a third level V3 that is less than the second level V2, and alternatively may recover from the second level V2 to the first level V1 again (S230, S250).

[0140] And if the input voltage decreases to the third level V3, the memory 210 may be powered off due to lack of power.

[0141] Also, when the input voltage recovers from the second level V2 to the first level V1, the control device 200 may perform a reset operation (S260, S270). Specifically, for the reset operation of the control device 200, the vehicle control unit 300 may turn off the power supply unit 220 of the control device 200 to power off the control device 200 (S260). Thereafter, the vehicle control unit 300 may turn on the power supply unit 220 again to power on the control device 200 (S270).

[0142] 13, in the power sequence of the NAND flash memory system according to the embodiment, the controller 240 can access the memory 210 under a condition that an input voltage within a normal range is input, and can transfer a command and an address to the memory 210. That is, the controller 240 can transfer a command (COMMAND) to the memory 210 under a normal condition, and can cause at least one of a program operation, an erase operation, and a read operation of the memory 210 to be performed accordingly (S300).

[0143] Thereafter, the control unit 240 determines whether a data protection condition of the memory 210 is detected (S310). That is, the control unit 240 can determine whether the input voltage has decreased to below a second level V2 that is lower than the first level V1.

[0144] If the input voltage falls below a second level V2 that is lower than the first level V1, the control unit 240 ignores the input command and accordingly blocks the transfer of the command to the memory 210 (S320).

[0145] Then, the auxiliary power unit 230 supplies auxiliary power to the memory 210 so that the operation (program operation or erase operation) performed in the memory 210 before the protection condition was detected can be completed normally (S330).

[0146] Thereafter, the control device 200 may be powered off (S340). That is, if the input voltage continues to decrease and decreases to the third level V3, the control device 200 may be powered off naturally due to a lack of power. On the other hand, if the input voltage returns to the first level V1, the vehicle control unit 300 may reset the control device 200 by turning off the power supply unit 210 of the control device 200 and then turning it on again.

[0147] As described above, in the embodiment, the control unit 240 performs the memory protection function when a momentary power interruption is detected. Here, the momentary power interruption may occur due to battery separation. In the embodiment, the memory protection function can be performed when a change in input voltage occurs due to battery separation as described above. However, a momentary change in input voltage also occurs when the vehicle is started on. In the embodiment, if the memory protection function is performed by recognizing the vehicle start on condition as an unstable input voltage condition or a data protection condition for the memory 210, the life of the memory 210 may be shortened.

[0148] That is, the lifespan of the memory 210 may decrease in proportion to the number of program operations and read operations. For example, the performance of the memory 210 may deteriorate in proportion to the number of program operations and read operations. Generally, program operations or read operations are most frequently performed when the memory is on or off. In this case, if the memory protection function operates when the vehicle is started on, the frequency of turning the memory on or off increases, which may cause a problem of deterioration in the performance of the memory.

[0149] Therefore, in the embodiment, the memory protection function as described above is not operated when the vehicle is started. In other words, the input voltage unstable condition or memory data protection condition does not include the input change condition that occurs when the vehicle is started. In the embodiment, the memory protection function as described above is not performed when the vehicle is started, thereby minimizing the risk of memory deterioration due to this.

[0150] Generally, in the ACC ON state, the battery is not separated or replaced. In the embodiment, the input voltage unstable condition or memory data protection condition may be detected when the battery is separated or replaced. In this case, the vehicle is generally started and turned on in the ACC ON state. Therefore, in the embodiment, the battery protection function is turned off in the ACC ON state.

[0151] FIG. 14 is a diagram showing a change in input voltage when the vehicle is started.

[0152] Referring to FIG. 14, when starting a vehicle, ACC ON is performed at a first time point T1. The input voltage at this time may be the first level V1 described above. Then, in the ACC ON state, a start-on operation may be performed at a second time point T2. At this time, the input voltage may decrease based on the second point T2, and may decrease to a second level V2 lower than the first level V1 at a third point T3. At this time, the memory protection function in the embodiment operates when the input voltage decreases to the second level V2. However, as described above, the change in the input voltage when the ACC is ON is for start-on. Therefore, in the embodiment, the change in the input voltage when the ACC is ON is ignored. For example, the memory protection function in the embodiment may operate in the ACC OFF state.

[0153] FIG. 15 is a flow chart for explaining a step-by-step method of activating the memory protection function according to the embodiment. Referring to FIG. 15, the control unit 240 according to the embodiment can detect the power supply state of the vehicle. That is, the control unit 240 can detect whether the power supply state of the vehicle is the ACC ON state or the ACC OFF state. Then, when the power supply state of the vehicle is the ACC ON state (S410), the control unit 240 turns off the memory protection function (S420). In other words, the control unit 240 according to the embodiment turns off the memory protection function when the power supply state of the vehicle is the ACC ON state (or the start-on state). As a result, the control unit 240 ignores a change in the input voltage caused by the start-on operation being performed in the ACC ON state.

[0154] Next, the control unit 240 may determine whether the power supply state of the vehicle has been changed to the ACC OFF state (S430). That is, the control unit 240 may determine whether the start of the vehicle is OFF.

[0155] In addition, when the power supply state of the vehicle is changed to the ACC OFF state, the control unit 240 determines whether a certain time has elapsed since the ACC was changed to OFF (S440). For example, the control unit 240 may determine whether one second has elapsed since the power supply state of the vehicle was changed to ACC OFF.

[0156] If the certain period of time has not elapsed, the control unit 240 may wait for a certain period of time (S450).

[0157] Furthermore, when a certain period of time has elapsed, the control unit 240 can turn on the memory protection function and operate the memory protection function in response to a change in the input voltage (S460).

[0158] In other words, the memory protection function described in the embodiments with reference to FIGS. 9, 12, and 13 can be selectively operated only when the power supply state of the vehicle is in the ACC OFF state.

[0159] Therefore, in the embodiment, it is possible to prevent the memory from being turned on or off even when there is a change in the input voltage that occurs when the vehicle is started, thereby improving the life of the memory.

[0160] Meanwhile, in order to test the reliability of the function of this embodiment, NAND flash memory elements of the same product were selected and tested for the presence or absence of data corruption before the function of this embodiment was applied and for the presence or absence of malfunction after the function of this embodiment was applied.

[0161] This was done by (1) cutting off the main power supply during a program or delete operation of a product before the function of this embodiment was applied, and testing whether any malfunctions occurred as a result, and (2) applying the function of this embodiment to the same product and then conducting the same test to verify the effectiveness of the function of this embodiment.

[0162] As a result, in the case of sample 1, it was confirmed that before the function of this embodiment was applied, two malfunctions occurred when the power on / off operation was performed about 1500 times and when it was performed 2900 times. However, after the function of this embodiment was applied to sample 1, it was confirmed that no malfunction occurred even after the power on / off operation was repeated more than 60,000 times.

[0163] In the case of sample 2, before the function of this embodiment was applied, three malfunctions occurred at the time when the power on / off operation was performed about 90 times, when it was performed about 250 times, and when it was performed 1110 times. However, after the function of this embodiment was applied to sample 2, it was confirmed that no malfunction occurred even after the power on / off operation was repeated more than 60,000 times.

[0164] In addition, in the case of sample 3, before the function of this embodiment was applied, a malfunction occurred once after about 370 power-on / off operations. However, after the function of this embodiment was applied to sample 3, it was confirmed that no malfunction occurred even after 60,000 or more power-on / off operations were repeated.

[0165] According to the embodiment, by detecting an unstable state of the input power and controlling the operation of the NAND flash memory device based on the detected unstable state, it is possible to prevent defects such as data corruption that may occur due to the operation of the NAND flash memory device in an unstable input power state. Specifically, according to the embodiment, by blocking flash access when the input power is unstable, it is possible to prevent malfunction of the NAND flash memory device in an environment where the input power is unstable.

[0166] In addition, according to the embodiment, if an operation of the NAND flash memory device is in progress when a power interruption is detected, auxiliary power is supplied until the ongoing operation is completed, thereby preventing data corruption due to charge gain that occurs when power is interrupted during a program operation or erase operation of the NAND flash memory device, thereby improving the operational reliability of the NAND flash memory device.

[0167] In addition, according to the embodiment, a power-off sequence of the NAND flash memory device is performed when a momentary power interruption is detected, and a power-on sequence is performed when a normal power supply is detected, thereby improving operational reliability and user satisfaction by allowing the flash memory to operate normally when the input power supply is restored.

Claims

1. A NAND flash memory; a controller that generates command signals for writing, reading, and deleting data in the NAND flash memory; an auxiliary power supply circuit that maintains power for operating the NAND flash memory for a first time period that is a time period from a first time point when a voltage of a power supply becomes lower than a previously set voltage to a time point when a program operation or an erase operation being performed in the NAND flash memory is completed from before the first time point; the controller interrupts the command signal for the first period of time; The controller executes a power-off sequence for the NAND flash memory based on completion of an operation of the NAND flash memory.

2. 2. The control device of claim 1, wherein if a program operation or an erase operation is being performed in the NAND flash memory at the first time point, the auxiliary power circuit supplies auxiliary power for completing the program operation or the erase operation of the NAND flash memory.

3. 3. The control device for a NAND flash memory device of claim 2, wherein when electrons are moving based on a program operation or erase operation being performed in the NAND flash memory at the first time, the auxiliary power circuit supplies auxiliary power for completing the program operation or erase operation of the NAND flash memory.

4. 2. The apparatus of claim 1, further comprising a power management IC (PMIC) coupled to the power supply and supplying power to the NAND flash memory and a controller.

5. 5. The control device for a NAND flash memory device according to claim 4, wherein the auxiliary power supply circuit is disposed between the PMIC and the NAND flash memory.

6. an input voltage detection unit for detecting a voltage level of the power supply; 5. The apparatus of claim 4, wherein the auxiliary power circuit is coupled to a power input terminal of the PMIC.

7. 7. The control device for a NAND flash memory device of claim 6, further comprising a detection signal transfer unit transferring the voltage level detected by the input voltage detection unit to the controller.

8. 8. The apparatus of claim 7, wherein the detection signal transfer unit includes a first resistor, a second resistor, a third resistor, and a transistor.

9. one end of the first resistor is connected to an output end of the input voltage detection unit, the other end of the first resistor is connected to one end of the third resistor and to the base of the transistor; one end of the second resistor is connected to a power supply terminal of the PMIC, the other end of the second resistor is connected to the collector of the transistor and to the signal input terminal of the controller; one end of the third resistor is connected to one end of the first resistor and to a base of the transistor; 9. The control device of a NAND flash memory device of claim 8, wherein the other end of the third resistor is coupled to an emitter of the transistor and a ground terminal.

10. a regulator disposed between the power supply and the PMIC; The control device for a NAND flash memory device according to claim 4 , wherein the auxiliary power supply circuit is disposed between the regulator and the PMIC.

11. The control device for a NAND flash memory device according to claim 1 , wherein the controller ignores voltage changes of the power supply in an ACC ON state.

12. The control device for a NAND flash memory element as described in claim 1, wherein the NAND flash memory is reset when the voltage of the power supply recovers to a previously set voltage while the power is maintained.

13. 2 . The control device for a NAND flash memory device of claim 1 , wherein the controller controls an operation of the NAND flash memory based on a voltage change of the power supply when a certain time has elapsed since ACC OFF was detected.

14. detecting a voltage of a power supply; if the detected voltage is less than a preset voltage, stopping access to the memory; supplying auxiliary power to the memory for a first time period from a first time point when the detected voltage becomes lower than a previously set voltage to a time point when a program operation or an erase operation being performed on the memory from before the first time point is completed; and executing a power-off sequence of the memory based on the operation of the memory being completed; The method for controlling a NAND flash memory device, wherein the step of stopping access to the memory includes the step of cutting off output of a command signal for controlling an operation of the memory.

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