DC / DC Converter

Abstract

To maintain an average value of coil current constant without depending on an input / output condition.SOLUTION: A DC / DC converter includes a comparator that generates a control signal for a switch output stage by comparing an analog signal and a first lamp signal, a current detection unit that generates a current sense signal by sampling a coil current of the switch output stage at a timing corresponding to a timing control signal, and a timing control unit that generates the timing control signal so as to perform sampling of the coil current at the central timing of an on period or an off period of the switch output stage by using a second lamp signal which has a slew rate twice higher than the first lamp signal. Output feedback control of a current mode control manner using the current sense signal is performed, whereby a desired output voltage is generated from an input voltage.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The invention disclosed herein relates to a DC / DC converter. [Background technology]

[0002] 2. Description of the Related Art Conventionally, DC / DC converters (so-called switching power supplies) that generate a desired output voltage from an input voltage by turning an output transistor on and off have been used as power supply means for various applications.

[0003] As examples of related art, Patent Documents 1 and 2 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2004-304871 A [Patent Document 2] JP 2013-121174 A Summary of the Invention [Problem to be solved by the invention]

[0005] By the way, the current mode control method, which detects both the output voltage and the coil current to perform output feedback control, is widely known as an output feedback control method for DC / DC converters. However, in conventional current mode control methods (peak value detection type or bottom value detection type), the average coil current fluctuates depending on the input / output conditions, which may adversely affect various operations of the DC / DC converter (such as overcurrent protection operation and light load detection operation).

[0006] In view of the above-mentioned problems discovered by the present inventors, the invention disclosed in this specification has an object to provide a DC / DC converter that can maintain a constant average value of coil current regardless of input / output conditions. [Means for solving the problem]

[0007] The DC / DC converter disclosed in this specification is configured to generate a desired output voltage from an input voltage by sampling the coil current of a switch output stage at the center timing of an on-period or off-period of the switch output stage and performing output feedback control of a current mode control type using a current sense signal corresponding to the sampled value.

[0008] The DC / DC converter disclosed in this specification has a comparator that compares an analog signal with a first ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal using a second ramp signal having a slew rate twice that of the first ramp signal so that the coil current is sampled at the center timing of the on-period or off-period of the switch output stage, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control type using the current sense signal.

[0009] The DC / DC converter disclosed in this specification includes a comparator that compares a first analog signal with a ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, an average value generation unit that generates a second analog signal having a simple average value of the signal value of the first analog signal and a start point value or an end point value of the ramp signal, and a timing control unit that generates the timing control signal using the ramp signal and the second analog signal so that the coil current is sampled at the center timing of an on period or an off period of the switch output stage, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control type using the current sense signal.

[0010] The DC / DC converter disclosed in this specification includes a comparator that compares a first analog signal with a first ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, an average value generation unit that generates a second analog signal having a weighted average value of the signal value of the first analog signal and a start value or an end value of the first ramp signal, and a timing control unit that generates the timing control signal using the second ramp signal and the second analog signal, the second ramp signal having a different slew rate from the first ramp signal, so that the coil current is sampled at the center timing of an on period or an off period of the switch output stage, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control type using the current sense signal.

[0011] The DC / DC converter disclosed in this specification also has an oscillator that generates a triangular waveform ramp signal with equal up / down slew rates, a comparator that compares an analog signal with the ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at a timing when the ramp signal takes its peak value or bottom value, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control method using the current sense signal.

[0012] The DC / DC converter disclosed in this specification includes an oscillator that generates a sawtooth ramp signal and an inverted ramp signal that have opposite polarities to each other and repeatedly rise or fall and reset in a common switching period, a first comparator and a second comparator that compare an analog signal with the ramp signal and the inverted ramp signal, respectively, to generate a first comparison signal and a second comparison signal, a logic operation unit that generates a control signal for a switch output stage by logical operation using the first comparison signal and the second comparison signal, a current detection unit that generates a current sense signal by sampling a coil current in the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the reset timing of the ramp signal and the inverted ramp signal, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control method using the current sense signal.

[0013] The DC / DC converter disclosed in this specification has a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal using first and second internal signals generated by itself in synchronization with the on / off control of the switch output stage so that the coil current is sampled at the center timing of the off period of the switch output stage, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control method using the current sense signal.

[0014] Other features, elements, steps, advantages, and characteristics of the present invention will become more apparent from the following detailed description of the best mode and the accompanying drawings related thereto. Effect of the Invention

[0015] According to the invention disclosed in this specification, it is possible to provide a DC / DC converter that can maintain a constant average value of the coil current regardless of input / output conditions. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 shows a first embodiment of a DC / DC converter. [Diagram 2] A diagram showing a first operation example (peak value detection type) of the timing control section. [Diagram 3] FIG. 2 shows a second operation example (bottom value detection type) of the timing control section. [Figure 4] A diagram showing a third operation example of the timing control section (ON period center value detection type) [Diagram 5] FIG. 4 shows a fourth operation example of the timing control section (off period center value detection type). [Figure 6] FIG. 2 shows a second embodiment of a DC / DC converter. [Figure 7] FIG. 1 shows a third embodiment of a DC / DC converter. [Figure 8] FIG. 13 shows a fourth embodiment of a DC / DC converter. [Figure 9] FIG. 13 is a diagram showing a first operation example of the timing control section in the fourth embodiment; [Figure 10] FIG. 13 is a diagram showing a second operation example of the timing control section in the fourth embodiment; [Figure 11] FIG. 23 is a diagram showing a third operation example of the timing control section in the fourth embodiment; [Figure 12] FIG. 13 is a diagram showing a fourth operation example of the timing control section in the fourth embodiment; [Figure 13] FIG. 13 is a diagram showing a fifth operation example of the timing control section in the fourth embodiment; [Figure 14] FIG. 5 illustrates a fifth embodiment of a DC / DC converter. [Figure 15] FIG. 13 is a diagram showing a first operation example of the timing control section in the fifth embodiment; [Figure 16] FIG. 23 is a diagram showing a second operation example of the timing control section in the fifth embodiment; [Figure 17]FIG. 23 is a diagram showing a third operation example of the timing control section in the fifth embodiment; [Figure 18] FIG. 6 shows a sixth embodiment of a DC / DC converter. [Figure 19] FIG. 13 is a diagram showing a configuration example of an oscillator according to a sixth embodiment; [Figure 20] FIG. 23 is a diagram showing an example of an oscillation operation of an oscillator in the sixth embodiment; [Figure 21] FIG. 23 is a diagram showing a first operation example of the timing control section in the sixth embodiment; [Figure 22] FIG. 23 is a diagram showing a second operation example of the timing control section in the sixth embodiment; [Diagram 23] FIG. 7 shows a seventh embodiment of a DC / DC converter. [Figure 24] FIG. 23 is a diagram showing a configuration example of an oscillator according to a seventh embodiment; [Diagram 25] FIG. 23 is a diagram showing an example of an oscillation operation of an oscillator in the seventh embodiment; [Figure 26] FIG. 23 is a diagram showing an example of an operation of a timing control unit in the seventh embodiment; [Figure 27] FIG. 13 shows an eighth embodiment of a DC / DC converter. [Figure 28] FIG. 23 is a diagram showing an operation example of a timing control unit in the eighth embodiment; [Figure 29] FIG. 13 shows a ninth embodiment of a DC / DC converter. [Diagram 30] 1 is a timing chart showing a generation operation of a step-down drive signal; [Diagram 31] 1 is a timing chart showing a generation operation of a boost drive signal; [Diagram 32] FIG. 23 is a diagram showing a first operation example (when stepping down) of the timing control section in the ninth embodiment; [Diagram 33] FIG. 23 is a diagram showing a second operation example (at the time of boosting) of the timing control section in the ninth embodiment; [Diagram 34] FIG. 23 is a diagram showing a configuration example of an oscillator according to a tenth embodiment; [Diagram 35] FIG. 23 is a diagram showing an example of the configuration of a timing control unit in a tenth embodiment; [Diagram 36]FIG. 23 is a diagram showing an operation example of a timing control unit in the tenth embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] First Embodiment 1 is a circuit diagram showing a first embodiment of a DC / DC converter. The DC / DC converter 1 of this embodiment is a step-down switching power supply that generates a desired output voltage Vo from an input voltage Vi and supplies it to a load (such as a CPU [central processing unit]) (not shown), and includes a switch output stage 10, a feedback voltage generating section 20, an error amplifier 30, a phase compensation section 40, a current detection section 50, a differential amplifier 60, an oscillator 70, a PWM [pulse width modulation] comparator 80, a driver 90, a clamper 100, a light load detection comparator 110, and a timing control section 120.

[0018] In addition to the circuit elements described above, the DC / DC converter 1 may incorporate other protection circuits (such as an undervoltage protection circuit, an overvoltage protection circuit, and a temperature protection circuit) as appropriate.

[0019] The switch output stage 10 is a step-down type that steps down an input voltage Vi to generate a desired output voltage Vo, and includes an output transistor 11 (a PMOSFET [P channel type metal oxide semiconductor field effect transistor] in this figure), a synchronous rectifier transistor 12 (an NMOSFET [N channel type MOSFET] in this figure), a coil 13, and a capacitor 14.

[0020] The source of the output transistor 11 is connected to a terminal to which the input voltage Vi is applied. The drain of the output transistor 11 is connected to a first terminal of the coil 13. The gate of the output transistor 11 is connected to a terminal to which a gate signal G1 is applied. The output transistor 11 is turned off when the gate signal G1 is at a high level, and turned on when the gate signal G1 is at a low level.

[0021] The source of the synchronous rectifier transistor 12 is connected to a ground terminal (= a terminal to which a ground voltage GND is applied). The drain of the synchronous rectifier transistor 12 is connected to a first terminal of the coil 13. The gate of the synchronous rectifier transistor 12 is connected to a terminal to which a gate signal G2 is applied. The synchronous rectifier transistor 12 is turned on when the gate signal G2 is at a high level, and turned off when the gate signal G2 is at a low level.

[0022] When a high voltage is applied to the switch output stage 10, it is preferable to use high-voltage elements such as a power MOSFET, an IGBT (insulated gate bipolar transistor), or a SiC transistor as the output transistor 11 and the synchronous rectifier transistor 12, respectively.

[0023] The output transistor 11 and the synchronous rectifier transistor 12 are complementarily turned on / off in response to gate signals G1 and G2. This on / off operation generates a square-wave switch voltage Vsw at the first end of the coil 13, which is pulse-driven between the input voltage Vi and the ground voltage GND. Note that the term "complementary" above includes not only the case where the on / off states of the output transistor 11 and the synchronous rectifier transistor 12 are completely reversed, but also the case where a period (dead time) during which both transistors are simultaneously off is provided.

[0024] Furthermore, when the components of the DC / DC converter 1 are integrated into an IC, the output transistor 11 and the synchronous rectifier transistor 12 may be built into the IC or may be attached externally. The output transistor 11 may also be replaced with an NMOSFET. In that case, however, it is necessary to use a bootstrap circuit or the like to make the high level of the gate signal G1 higher than the input voltage Vi. Also, a rectifier diode may be used in place of the synchronous rectifier transistor 12.

[0025] The coil 13 and the capacitor 14 form an LC filter that rectifies and smoothes the switch voltage Vsw to generate the output voltage Vo. As described above, the first terminal of the coil 13 is connected to the drains (=the application terminal of the switch voltage Vsw) of the output transistor 11 and the synchronous rectification transistor 12. The second terminal of the coil 13 and the first terminal of the capacitor 14 are both connected to the application terminal of the output voltage Vo. The second terminal of the capacitor 14 is connected to the ground terminal.

[0026] The feedback voltage generating unit 20 includes resistors 21 and 22 connected in series between the application terminal of the output voltage Vo and the ground terminal, and outputs a feedback voltage FB (a divided voltage of the output voltage Vo) according to the output voltage Vo from a connection node between the two resistors. Note that if the output voltage Vo is within the input dynamic range of the error amplifier 30, the feedback voltage generating unit 20 may be omitted and the output voltage Vo may be directly input to the error amplifier 30.

[0027] The error amplifier 30 is a current output type transconductance amplifier (so-called gm amplifier) ​​that generates an error current signal I30 according to the difference between a feedback voltage FB input to the inverting input terminal (-) and a first reference voltage REF1 (corresponding to the target set value of the output voltage Vo) input to the non-inverting input terminal (+). The error current signal I30 flows in the positive direction (=direction from the error amplifier 30 toward the phase compensation unit 40) when the feedback voltage FB is lower than the first reference voltage REF1, and flows in the negative direction (=direction from the phase compensation unit 40 toward the error amplifier 30) when the feedback voltage FB is higher than the first reference voltage REF1.

[0028] The phase compensation unit 40 includes a resistor 41 and a capacitor 42 connected in series between the output terminal of the error amplifier 30 and the ground terminal, and receives the error current signal I30 to generate an error voltage signal COMP. By appropriately setting the resistance value of the resistor 41 and the capacitance value of the capacitor 42, it is possible to compensate the phase of the error voltage signal COMP and prevent oscillation of the output feedback loop.

[0029] The current detection unit 50 samples the coil current IL flowing through the coil 13 at a timing according to the timing control signal ST, and generates a current sense signal ISNS according to the sampled value. The current sense signal ISNS may be, for example, a voltage signal that increases as the sampled value of the coil current IL increases, and conversely, decreases as the sampled value of the coil current IL decreases.

[0030] The differential amplifier 60 generates a first analog signal VC1 according to the difference between the error voltage signal COMP input to the non-inverting input terminal (+) and the current sense signal ISNS input to the inverting input terminal (-). The first analog signal VC1 decreases as the current sense signal ISNS increases, and increases as the current sense signal ISNS decreases. In other words, the first analog signal VC1 decreases as the coil current IL increases, and increases as the coil current IL decreases. In this way, the DC / DC converter 1 of this embodiment employs a current mode control method that detects both the output voltage Vo and the coil current IL to perform output feedback control.

[0031] The oscillator 70 generates a first ramp signal VR1 having a ramp waveform (a sawtooth waveform in this embodiment) that is pulse-driven with a predetermined switching period T (and thus a predetermined switching frequency fsw (=1 / T)).

[0032] The PWM comparator 80 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the first ramp signal VR1 input to the inverting input terminal (-) to generate a first comparison signal CMP1 (corresponding to a control signal for the switch output stage 10). The first comparison signal CMP1 is at a high level when the first analog signal VC1 is higher than the first ramp signal VR1, and is at a low level when the first analog signal VC1 is lower than the first ramp signal VR1. That is, the on-duty Don (= ton / T, i.e., the ratio of the on-period ton to the switching period T) of the switch output stage 10 increases as the first analog signal VC1 increases, and conversely decreases as the first analog signal VC1 decreases.

[0033] The driver 90 includes a NAND gate 91 and an AND gate 92, and generates gate signals G1 and G2 (corresponding to drive signals for the switch output stage 10) in response to the first comparison signal CMP1. Specifically, the NAND gate 91 outputs a NAND signal of the sleep control signal XSLP and the first comparison signal CMP1 as the gate signal G1. Moreover, the AND gate 92 outputs a AND signal of the sleep control signal XSLP and the inverted first comparison signal CMP1 as the gate signal G2.

[0034] Therefore, when the sleep control signal XSLP is at a high level (=logical level at wake-up), the gate signals G1 and G2 are basically logically inverted signals of the first comparison signal CMP1. More specifically, when the first comparison signal CMP1 is at a high level, the gate signals G1 and G2 are both at a low level, so that the output transistor 11 is turned on and the synchronous rectification transistor 12 is turned off. Conversely, when the first comparison signal CMP1 is at a low level, the gate signals G1 and G2 are both at a high level, so that the output transistor 11 is turned off and the synchronous rectification transistor 12 is turned on.

[0035] On the other hand, when the sleep control signal XSLP is at a low level (=logical level during sleep), the gate signal G1 becomes a high level regardless of the first comparison signal CMP1, and the gate signal G2 becomes a low level regardless of the first comparison signal CMP1, so that both the output transistor 11 and the synchronous rectification transistor 12 are turned off.

[0036] In this manner, the DC / DC converter 1 of this embodiment has the function of transitioning to sleep mode (=output stopped state) by turning off both the output transistor 11 and the synchronous rectifier transistor 12 when the sleep control signal XSLP is at a low level.

[0037] The clamper 100 applies overcurrent protection (OCP) or reverse current protection (NCP) to the coil current IL (and thus the load current flowing through the load) by limiting the error voltage signal COMP to below a predetermined upper limit value or above a predetermined lower limit value.

[0038] As described above, in the DC / DC converter 1 of this embodiment, the current sense signal ISNS corresponding to the coil current IL is fed back to the differential amplifier 60. Therefore, when the error voltage signal COMP rises, the coil current IL increases, and when the error voltage signal COMP falls, the coil current IL decreases. In this way, the magnitude of the coil current IL can be controlled according to the error voltage signal COMP.

[0039] Conversely, when the coil current IL increases, the on-duty Don decreases, so the output voltage Vo decreases and the error voltage signal COMP increases, and when the coil current IL decreases, the on-duty Don increases, so the output voltage Vo increases and the error voltage signal COMP decreases. In other words, it can be said that the error voltage signal COMP contains information about the magnitude (current value) of the coil current IL. Therefore, by limiting the error voltage signal COMP using the clamper 100, it is possible to indirectly limit the coil current IL.

[0040] The light-load detection comparator 110 compares the error voltage signal COMP input to the non-inverting input terminal (+) with a second reference voltage REF2 (corresponding to the light-load detection threshold) input to the inverting input terminal (-) to generate a sleep control signal XSLP. The sleep control signal XSLP goes to a high level (=logical level during wake-up) when the error voltage signal COMP is higher than the second reference voltage REF2, and goes to a low level (=logical level during sleep) when the error voltage signal COMP is lower than the second reference voltage REF2.

[0041] In this way, the sleep control signal XSLP goes to low level when the coil current IL (and therefore the load current) decreases to the point where the error voltage signal COMP falls below the second reference voltage REF2. Therefore, when the DC / DC converter 1 is under a light load, the switching operation of the switch output stage 10 is stopped, making it possible to significantly improve efficiency under a light load.

[0042] The timing control section 120 generates a timing control signal ST for determining the sampling timing of the coil current IL in the current detection section 50. Next, an example of the operation of the timing control section 120 (a method for generating the timing control signal ST) will be described in detail.

[0043] <Timing control section> 2 is a waveform diagram showing a first operation example (peak value detection type) of the timing control section 120, depicting, from the top, the input voltage Vi, the coil current IL, and the timing control signal ST. In the first operation example in this diagram, the timing control signal ST is generated so as to sample the peak value Ip (maximum value) of the coil current IL. Therefore, in the DC / DC converter 1, output feedback control is applied so as to maintain the peak value Ip of the coil current IL constant.

[0044] Fig. 3 is a waveform diagram showing a second operation example (bottom value detection type) of the timing control section 120, which, like Fig. 2, depicts from top to bottom the input voltage Vi, the coil current IL, and the timing control signal ST. In the second operation example in this figure, the timing control signal ST is generated so as to sample the bottom value Ib (minimum value) of the coil current IL. Therefore, in the DC / DC converter 1, output feedback control is applied so as to maintain the bottom value Ib of the coil current IL constant.

[0045] Thus, typical current mode control methods are classified into peak value detection type (Fig. 2) and bottom value detection type (Fig. 3) according to the sampling timing of the coil current IL. However, with these control methods, for example, if the ripple component of the coil current IL changes with fluctuations in the input voltage Vi, the average coil current Idc (corresponding to the DC component of the coil current Idc) changes when the error voltage signal COMP is maintained at a constant value. As a result, the thresholds for overcurrent protection operation and light load detection operation change depending on the input / output conditions, making application design difficult. Countermeasures against this problem are explained below.

[0046] 4 is a waveform diagram showing a third operation example (on-period center value detection type) of the timing control section 120, depicting, from the top, the input voltage Vi, the coil current IL, the switch voltage Vsw, and the timing control signal ST. In the third operation example in this figure, the timing control signal ST is generated so as to sample the center value Ic of the coil current IL at the center timing of the on-period ton of the switch output stage 10 (= the period during which the output transistor 11 is on and the synchronous rectifier transistor 12 is off, i.e., corresponding to the high-level period of the switch voltage Vsw). Therefore, in the DC / DC converter 1, output feedback control is applied so as to maintain the center value Ic of the coil current IL constant.

[0047] Here, the center value Ic of the coil current IL is equal to the average coil current Idc (and therefore the load current) described above. Therefore, by limiting the error voltage signal COMP to a predetermined upper limit or lower limit, or a predetermined lower limit or higher, it is possible to apply overcurrent protection or reverse current protection at a constant load current regardless of the input / output conditions. In addition, by stopping the switching operation of the switch output stage 10 when the error voltage signal COMP falls below a predetermined threshold, it is possible to transition to a sleep mode at a constant load current regardless of the input / output conditions.

[0048] 5 is a waveform diagram showing a fourth operation example (off-period center value detection type) of the timing control section 120, which depicts, from top to bottom, the input voltage Vi, the coil current IL, the switch voltage Vsw, and the timing control signal ST, as in the previous Fig. 4. In the fourth operation example in this figure, the timing control signal ST is generated so as to sample the center value Ic of the coil current IL at the center timing of the off-period toff of the switch output stage 10 (= the period during which the output transistor 11 is off and the synchronous rectifier transistor 12 is on, i.e., corresponding to the low-level period of the switch voltage Vsw). Therefore, as in the case of employing the previous third operation example, in the DC / DC converter 1, output feedback control is applied so as to maintain the center value Ic of the coil current IL constant.

[0049] In addition, if the on-period ton is short, it is difficult to complete sampling of the coil current IL during that period, so it is desirable to set the sampling timing to the off-period Toff. Conversely, if the off-period toff is short, sampling of the coil current IL can be performed during the on-period Ton.

[0050] <Second embodiment> Fig. 6 is a circuit diagram showing a DC / DC converter according to a third embodiment. The DC / DC converter 1 according to this embodiment is based on the first embodiment (Fig. 1), but has a calculator 130 instead of the differential amplifier 60, and is characterized in that the current sense signal ISNS is fed back and input to the calculator 130 instead of the differential amplifier 60. Therefore, the same components as those in the first embodiment are given the same reference numerals as those in Fig. 1 to avoid redundant explanations, and the following description will focus on the characteristic features of the second embodiment.

[0051] The calculator 130 performs a calculation process on the error voltage signal COMP and the current sense signal ISNS (for example, a subtraction process of subtracting the current sense signal ISNS from the error voltage signal COMP) to generate a first analog signal VC (=COMP-ISNS).

[0052] In this way, when performing output feedback control of the current mode control method, the current sense signal ISNS can be subtracted from the error voltage signal COMP input to the non-inverting input terminal (+) of the PWM comparator 80.

[0053] <Third embodiment> Fig. 7 is a circuit diagram showing a DC / DC converter according to a third embodiment. The DC / DC converter 1 according to this embodiment is based on the second embodiment (Fig. 6), but is characterized in that it uses a calculator 140 instead of the calculator 130. Therefore, the same components as those in the second embodiment are given the same reference numerals as those in Fig. 6 to avoid redundant explanations, and the following description will focus on the characteristic features of the third embodiment.

[0054] The calculator 140 performs a calculation process on the first ramp signal VR1 and the current sense signal ISNS (for example, an addition process on the first ramp signal VR1 and the current sense signal ISNS) to generate an offset first ramp signal VR1' (=VR1+ISNS).

[0055] In accordance with the above changes, the PWM comparator 80 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the offset first ramp signal VR1' input to the inverting input terminal (-) to generate a first comparison signal CMP1.

[0056] In this way, when performing output feedback control of the current mode control method, the current sense signal ISNS may be added to the first ramp signal VR1 input to the inverting input terminal (−) of the PWM comparator 80.

[0057] Although there are various other possible methods for realizing the current mode control method, and due to space limitations, we will refrain from listing all of them as examples, for example, output feedback control of the current mode control method may be performed by adding or subtracting the current sense signal and a signal having error information of the output voltage and inputting the result to an amplifier or comparator. Alternatively, output feedback control of the current mode control method may be performed by inputting the current sense signal or a signal obtained by performing a predetermined arithmetic process (addition, subtraction, multiplication, or division) on the current sense signal and a signal having error information of the output voltage to an amplifier or comparator.

[0058] In each of the above embodiments, the advantages of adopting a center value detection type (FIGS. 4 and 5) current mode control method have been described. In each of the following embodiments, a timing control method for correctly detecting the center value Ic of the coil current IL will be described in detail with specific examples.

[0059] <Fourth embodiment> Fig. 8 is a diagram showing a DC / DC converter according to a fourth embodiment. The DC / DC converter 1 according to this embodiment is based on the first embodiment (Fig. 1), and is characterized in that a timing control signal ST is generated using a first analog signal VC1 and a second ramp signal VR2. Therefore, the same components as those in the first embodiment are given the same reference numerals as those in Fig. 1 to avoid redundant explanations, and the following description will focus on the characteristic features of the fourth embodiment.

[0060] In the DC / DC converter 1 of this embodiment, the oscillator 70 generates a first ramp signal VR1 and supplies it to the inverting input terminal (-) of the PWM comparator 80, while generating a second ramp signal VR2 synchronized with the first ramp signal VR1 and supplies it to the timing control unit 120. The second ramp signal VR2 is a sawtooth waveform signal having a slew rate twice that of the first ramp signal VR1.

[0061] The timing control section 120 generates the timing control signal ST by using both the first analog signal VC1 and the second ramp signal VR2 so that sampling of the coil current IL is performed at the center timing of the on-period ton or the off-period toff of the switch output stage 10. A specific operation example of the timing control section 120 will be described in detail below.

[0062] FIG. 9 is a waveform diagram showing a first operation example of the timing control unit 120 in the fourth embodiment, and depicts, from the top, a first analog signal VC1 (dotted line), a first ramp signal VR1 (solid line), a second ramp signal VR2 (dashed line), a coil current IL, and a timing control signal ST.

[0063] As shown in this figure, the first ramp signal VR1 and the second ramp signal VR2 both repeat rising and resetting in a common switching period T.

[0064] When the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 is in an on-period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 is in an off-period toff, and the coil current IL decreases.

[0065] That is, the higher the first analog signal VC1, the larger the on-duty Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty Don of the switch output stage 10 becomes.

[0066] Here, the timing control unit 120 generates the timing control signal ST by comparing the first analog signal VC1 with the second ramp signal VR2. More specifically, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the timing when the second ramp signal VR2 rises and crosses the first analog signal VC1.

[0067] As shown in the figure, the timing at which the second ramp signal VR2 and the first analog signal VC1 intersect coincides with the center timing of the on-period ton (=the timing when ton / 2 has elapsed since the coil current IL started to increase).

[0068] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the on-period ton.

[0069] Figure 10 is a waveform diagram showing a second operation example of the timing control unit 120 in the fourth embodiment, and like Figure 9, depicts, from top to bottom, the first analog signal VC1 (dotted line), the first ramp signal VR1 (solid line), the second ramp signal VR2 (dashed line), the coil current IL, and the timing control signal ST.

[0070] In the second operation example in this figure, both the first ramp signal VR1 and the second ramp signal VR2 repeatedly rise and reset in a common switching period T. However, the relationship between the first analog signal VC1 and the on-duty Don is opposite to that in the first operation example (FIG. 9).

[0071] Specifically, when the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 is in an off period toff, and the coil current IL decreases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 is in an on period ton, and the coil current IL increases.

[0072] That is, the higher the first analog signal VC1, the smaller the on-duty Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the larger the on-duty Don of the switch output stage 10 becomes.

[0073] In order to realize such an operation, for example, the input polarity of the error amplifier 30 and the input polarity of the PWM comparator 80 may be inverted from that in FIG.

[0074] Here, like the first operation example (FIG. 9), the timing control section 120 compares the first analog signal VC1 with the second ramp signal VR2 to generate the timing control signal ST. More specifically, the timing control section 120 generates a one-shot pulse in the timing control signal ST at the timing when the second ramp signal VR2 rises and crosses the first analog signal VC1.

[0075] As shown in the figure, the timing at which the second ramp signal VR2 and the first analog signal VC1 intersect coincides with the center timing of the off period toff (=the timing when toff / 2 has elapsed since the coil current IL started to decrease).

[0076] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the off period toff.

[0077] Figure 11 is a waveform diagram showing a third operation example of the timing control unit 120 in the fourth embodiment, and similarly to Figures 9 and 10, depicts, from top to bottom, a first analog signal VC1 (dotted line), a first ramp signal VR1 (solid line), a second ramp signal VR2 (dashed line), a coil current IL, and a timing control signal ST.

[0078] In the third operation example of the figure, the polarities of the first ramp signal VR1 and the second ramp signal VR2 are inverted from those in the first operation example (FIG. 9). That is, the first ramp signal VR1 and the second ramp signal VR2 both repeat a decrease and a reset in a common switching period T.

[0079] When the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 is in an on-period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 is in an off-period toff, and the coil current IL decreases.

[0080] That is, the higher the first analog signal VC1, the larger the on-duty Don (=ton / T) of the switch output stage 10, and conversely, the lower the first analog signal VC1, the smaller the on-duty Don of the switch output stage 10. This is the same as in the first operation example (FIG. 9).

[0081] Here, like the first operation example (FIG. 9), the timing control section 120 compares the first analog signal VC1 with the second ramp signal VR2 to generate the timing control signal ST. More specifically, the timing control section 120 generates a one-shot pulse in the timing control signal ST at the timing when the second ramp signal VR2 falls and crosses the first analog signal VC1.

[0082] As shown in the figure, the timing at which the second ramp signal VR2 and the first analog signal VC1 intersect coincides with the center timing of the off period toff (=the timing when toff / 2 has elapsed since the coil current IL started to decrease).

[0083] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the off period toff.

[0084] In this way, in the third operation example of the present figure, unlike the previous second operation example (Figure 10), it is possible to sample the center value Ic of the coil current IL during the off period toff while maintaining the relationship between the first analog signal VC1 and the on-duty Don as before.

[0085] Figure 12 is a waveform diagram showing a fourth operation example of the timing control unit 120 in the fourth embodiment, and like Figures 9 to 11, from top to bottom, the diagram depicts a first analog signal VC1 (dotted line), a first ramp signal VR1 (solid line), a second ramp signal VR2 (dashed line), a coil current IL, and a timing control signal ST.

[0086] In the fourth operation example in the figure, as in the previous first operation example (FIG. 9), both the first ramp signal VR1 and the second ramp signal VR2 repeatedly rise and reset in a common switching period T. However, the second ramp signal VR2 starts to rise with a delay of 1 / 2 the switching period T from the point at which the first ramp signal VR1 starts to rise.

[0087] When the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 is in an on-period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 is in an off-period toff, and the coil current IL decreases.

[0088] That is, the higher the first analog signal VC1, the larger the on-duty Don (=ton / T) of the switch output stage 10, and conversely, the lower the first analog signal VC1, the smaller the on-duty Don of the switch output stage 10. This is the same as in the first operation example (FIG. 9).

[0089] Here, like the first operation example (FIG. 9), the timing control section 120 compares the first analog signal VC1 with the second ramp signal VR2 to generate the timing control signal ST. More specifically, the timing control section 120 generates a one-shot pulse in the timing control signal ST at the timing when the second ramp signal VR2 rises and crosses the first analog signal VC1.

[0090] As shown in the figure, the timing at which the second ramp signal VR2 and the first analog signal VC1 intersect coincides with the center timing of the off period toff (=the timing when toff / 2 has elapsed since the coil current IL started to decrease).

[0091] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the off period toff.

[0092] In this way, in the fourth operation example of the present figure, unlike the previous third operation example (Figure 11), it is possible to sample the center value Ic of the coil current IL during the off period toff without inverting the polarity of the first ramp signal VR1 and the second ramp signal VR2, while maintaining the relationship between the first analog signal VC1 and the on-duty Don as before.

[0093] FIG. 13 is a waveform diagram showing a fifth operation example of the timing control unit 120 in the fourth embodiment, which depicts, from top to bottom, the first analog signal VC1 (dashed line), the equivalent analog signal VC1' (dashed line), the first ramp signal VR1 (solid line), the second ramp signal VR2 (dashed line), the coil current IL, and the timing control signal ST.

[0094] The fifth operation example in this figure is basically the same as the first operation example (FIG. 9), except that the timing control section 120 generates the timing control signal ST by comparing an equivalent analog signal VC1' having information equivalent to that of the first analog signal VC1 with the second ramp signal VR2, instead of the first analog signal VC1.

[0095] In a configuration in which the first analog signal VC1 is compared with multiple ramp signals (= the first ramp signal VR1 and the second ramp signal VR2), there is a higher risk that the first analog signal VC1 will fluctuate due to noise (= the risk that PWM control will become unstable) compared to a configuration in which the first analog signal VC1 is compared with a single ramp signal (= only the first ramp signal VR1).

[0096] Therefore, in consideration of improving the stability of PWM control, it is desirable to compare an equivalent analog signal VC1' having information equivalent to that of the first analog signal VC1 with the second ramp signal VR2, rather than comparing the first analog signal VC1 itself with the second ramp signal VR2.

[0097] A simple method for generating the equivalent analog signal VC1' is to simply buffer the first analog signal VC1, for example.

[0098] Another possible method is to calculate the theoretical value of the first analog signal VC1 (=α×(Vo / Vi)×T, where α is the slew rate of the first ramp signal VR1) from the actual value of the input voltage Vi and the target value of the output voltage Vo, and generate an equivalent analog signal VC1' having that value.

[0099] In the latter method, when the first analog signal VC1 varies transiently as shown in the figure, it becomes impossible to correctly sample the center value Ic of the coil current IL. However, the deviation in the sampling timing is only temporary, and does not cause any particular problems in the overcurrent protection operation or the light load detection operation.

[0100] In the fifth operation example in this figure, an example based on the first operation example (FIG. 9) is given, but in the second to fourth operation examples (FIGS. 10 to 12), it is of course also possible to perform a comparison process between the equivalent analog signal VC1' and the second ramp signal VR2.

[0101] <Fifth embodiment> Fig. 14 is a diagram showing a fifth embodiment of a DC / DC converter. The DC / DC converter 1 of this embodiment is based on the first embodiment (Fig. 1), and is characterized in that a timing control signal ST is generated using a first ramp signal VR1 and a second analog signal VC2. Therefore, the same components as those in the first embodiment are given the same reference numerals as in Fig. 1 to avoid redundant explanations, and the following description will focus on the characteristic parts of the fifth embodiment.

[0102] The DC / DC converter 1 of this embodiment has an average value generating unit 150 as a generating means for the second analog signal VC2. The average value generating unit 150 generates the second analog signal VC2 having a simple average value of the signal value of the first analog signal VC1 and the start point value or the end point value of the first ramp signal VR1.

[0103] The timing control section 120 generates the timing control signal ST by using both the first ramp signal VR1 and the second analog signal VC2 so that sampling of the coil current IL is performed at the center timing of the on-period ton or the off-period toff of the switch output stage 10. A specific operation example of the timing control section 120 will be described in detail below.

[0104] FIG. 15 is a waveform diagram showing a first operation example of the timing control unit 120 in the fifth embodiment, and depicts, from top to bottom, a first analog signal VC1 (dashed line), a second analog signal VC2 (dashed line), a first ramp signal VR1 (solid line), a coil current IL, and a timing control signal ST.

[0105] As shown in this figure, the first ramp signal VR1 is a sawtooth waveform signal that repeatedly rises and resets at a predetermined switching period T.

[0106] When the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 is in an on-period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 is in an off-period toff, and the coil current IL decreases.

[0107] That is, the higher the first analog signal VC1, the larger the on-duty Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty Don of the switch output stage 10 becomes.

[0108] Here, the average value generating unit 150 generates a second analog signal VC2 (=(VC1+VR1L) / 2) having the simple average value of the signal value of the first analog signal VC1 and the starting value of the first ramp signal VR1 (=the bottom value VR1L of the first ramp signal VR1 in this figure).

[0109] In addition, the timing control unit 120 generates the timing control signal ST by comparing the first ramp signal VR1 with the second analog signal VC2. More specifically, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the timing when the first ramp signal VR1 rises and crosses the second analog signal VC2.

[0110] As shown in the figure, the timing at which the first ramp signal VR1 and the second analog signal VC2 intersect coincides with the center timing of the on-period ton (=the timing when ton / 2 has elapsed since the coil current IL started to increase).

[0111] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the on-period ton.

[0112] In the fourth embodiment (FIGS. 8 to 13), the second ramp signal VR2 must be generated with a slew rate twice as fast as that of the first ramp signal VR1, which has a rapidly changing voltage value, but the second ramp signal VR2 is not required in this embodiment. Therefore, when it is difficult to generate the second ramp signal VR2, it is desirable to employ this embodiment.

[0113] Figure 16 is a waveform diagram showing a second operation example of the timing control unit 120 in the fifth embodiment, and similarly to Figure 15 above, depicts, from top to bottom, the first analog signal VC1 (dashed line), the second analog signal VC2 (dashed line), the first ramp signal VR1 (solid line), the coil current IL, and the timing control signal ST.

[0114] The second operation example in this figure is basically similar to the first operation example (Figure 15) described above, but differs in that the average value generation unit 150 generates a second analog signal VC2 (=(VC1+VR1H) / 2) having the simple average value of the signal value of the first analog signal VC1 and the end value of the first ramp signal VR1 (=the peak value VR1H of the first ramp signal VR1 in this figure).

[0115] In this case, the timing at which the first ramp signal VR1 and the second analog signal VC2 intersect coincides with the center timing of the off period toff (=the timing at which toff / 2 has elapsed since the coil current IL started to decrease).

[0116] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the off period toff.

[0117] FIG. 17 is a waveform diagram showing a third operation example of the timing control unit 120 in the fifth embodiment, and depicts, from top to bottom, a first analog signal VC1 (dashed line), a second analog signal VC2 (dashed line), a first ramp signal VR1 (solid line), a second ramp signal VR2 (dashed line), a coil current IL, and a timing control signal ST.

[0118] The operational example in this figure is basically similar to the first operational example (Figure 15) described above, except that the average value generating unit 150 generates a second analog signal VC2 having a weighted average value of the signal value of the first analog signal VC1 and the start point value or end point value of the first ramp signal VR1.

[0119] In accordance with the above changes, the timing control section 120 uses a second ramp signal VR2 having a slew rate different from that of the first ramp signal VR1 and a second analog signal VC2 to generate a timing control signal ST so that sampling of the coil current IL is performed at the center timing of the on-period ton or the off-period toff of the switch output stage 10. Unlike the previous fourth embodiment (FIGS. 8 to 13), the second ramp signal VR2 does not necessarily have a slew rate twice that of the first ramp signal VR1.

[0120] For example, to be more specific with reference to this figure, the second analog signal VC2 has a weighted average value (=mVC1+nVR1L) of the signal value (weight m) of the first analog signal VC1 and the bottom value VR1L (weight n) of the first ramp signal VR1. The second ramp signal VR2 has a slew rate 2m / (m+n) times that of the first ramp signal VR1.

[0121] With this configuration, the timing at which the second ramp signal VR2 and the second analog signal VC2 intersect coincides with the center timing of the on-period ton (=the timing when ton / 2 has elapsed since the coil current IL started to increase).

[0122] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the on-period ton.

[0123] Sixth embodiment Fig. 18 is a diagram showing a sixth embodiment of a DC / DC converter. The DC / DC converter 1 of this embodiment is based on the first embodiment (Fig. 1), but is characterized in that it performs PWM control using a third ramp signal VR3 having a triangular waveform instead of the first ramp signal VR1 having a sawtooth waveform, and detects the timing (=peak timing or bottom timing) at which the third ramp signal VR3 has a peak value VR3H or a bottom value VR3L to generate a timing control signal ST. Therefore, the same components as those in the first embodiment are given the same reference numerals as those in Fig. 1 to avoid redundant explanations, and the following description will focus on the characteristic parts of the sixth embodiment.

[0124] In the DC / DC converter 1 of this embodiment, the oscillator 70 generates a third ramp signal VR3 of a triangular waveform with equal up- and down-slew rates, and supplies the signal to the inverting input terminal (-) of the PWM comparator 80. The oscillator 70 also generates a first clock signal CLK1 whose logic level switches at the peak timings and bottom timings of the third ramp signal VR3, and supplies the signal to the timing control unit 120.

[0125] 19 is a circuit diagram showing a configuration example of an oscillator 70 according to the sixth embodiment. The oscillator 70 of this configuration example includes current sources 71a and 71b, switches 72a and 72b, a capacitor 73a, a comparator 74a, resistors 75a, 75b, and 75c, and a selector 76.

[0126] A first terminal of the current source 71a is connected to an application terminal of the power supply voltage VDD. A second terminal of the current source 71a is connected to a first terminal of the switch 72a. A second terminal of the switch 72a, a first terminal of the switch 72b, a first terminal of the capacitor 73a, and a non-inverting input terminal (+) of the comparator 74a are all connected to an output terminal of the third ramp signal VR3. A second terminal of the switch 72b is connected to a first terminal of the current source 71b. A second terminal of the current source 71b and a second terminal of the capacitor 73a are connected to a ground terminal.

[0127] The resistors 75a, 75b, and 75c are connected in series in the illustrated order between the application terminal of the reference voltage VREF and the ground terminal. The connection node between the resistors 75a and 75b is connected to the first input terminal of the selector 76 as an output terminal of the first divided voltage (corresponding to the peak value VR3H of the third ramp signal VR3). The connection node between the resistors 75b and 75c is connected to the second input terminal of the selector 76 as an output terminal of the second divided voltage (corresponding to the bottom value VR3L of the third ramp signal VR3) lower than the first divided voltage. The output terminal of the selector 76 is connected to the inverting input terminal (-) of the comparator 74 as an output terminal of the threshold voltage VTH. The switches 72a and 72b and the control terminals of the selector 76 are all connected to the output terminal of the comparator 74a (=the output terminal of the first clock signal CLK1).

[0128] In the oscillator 70 having the above configuration, the current source 71a generates a predetermined charging current I71a, and the current source 71b generates a discharging current I71b equal to the charging current I71a.

[0129] Moreover, the switches 72a and 72b are turned on / off in response to the first clock signal CLK1 so as to switch between charging the capacitor 73a with the charging current I71a and discharging the capacitor 73a with the discharging current I71b.

[0130] Specifically, when the first clock signal CLK1 is at a low level, the switch 72a is turned on and the switch 72b is turned off, so that the capacitor 73a is charged by the charging current I71a. Therefore, the third ramp signal VR3 monotonically rises at a predetermined upward slew rate (see times t1 to t2 in FIG. 20).

[0131] On the other hand, when the first clock signal CLK1 is at a high level, the switch 72a is turned off and the switch 72b is turned on, thereby discharging the capacitor 73a with the discharge current I71b. Therefore, the third ramp signal VR3 monotonically decreases at a downward slew rate equal to the upward slew rate (but with opposite polarity) (see times t2 to t3 in FIG. 20).

[0132] The comparator 74a compares the third ramp signal VR3 with a threshold voltage VTH (=peak value VR3H or bottom value VR3L) to generate the first clock signal CLK1. When the first clock signal CLK1 is at a low level, the selector 76 selects the peak value VR3H as the threshold voltage VTH (see times t1 to t2 in FIG. 20), and conversely, when the first clock signal CLK1 is at a high level, the selector 76 selects the bottom value VR3L as the threshold voltage VTH (see times t2 to t3 in FIG. 20).

[0133] Therefore, when the first clock signal CLK1 is at a low level, the first clock signal CLK1 is maintained at a low level until the third ramp signal VR3 exceeds the peak value VR3H, at which point the first clock signal CLK1 is raised from a low level to a high level (see times t1 to t2 in Figure 20).

[0134] On the other hand, when the first clock signal CLK1 is at a high level, the first clock signal CLK1 is maintained at a high level until the third ramp signal VR3 falls below the bottom value VR3L, and at the point in time when the third ramp signal VR3 falls below the bottom value VR3L, the first clock signal CLK1 is dropped from a high level to a low level (see times t2 to t3 in Figure 20).

[0135] In this way, the comparator 74a, the resistors 75a to 75c, and the selector 76 function as a clock signal generating section that compares the third ramp signal VR3 with the peak value VR3H and the bottom value VR3L to generate the first clock signal CLK1.

[0136] The timing control unit 120 receives the input of the first clock signal CLK1 described above, and generates a timing control signal ST so that the coil current IL is sampled at the timing when the logic level of the first clock signal CLK1 switches (=the peak timing or bottom timing of the third ramp signal VR3). A specific operation example of the timing control unit 120 will be described in detail below.

[0137] FIG. 21 is a waveform diagram showing a first operation example of the timing control unit 120 in the sixth embodiment, which depicts, from top to bottom, the first analog signal VC1 (dashed line), the third ramp signal VR3 (solid line), the coil current IL, and the timing control signal ST.

[0138] As shown in this figure, the third ramp signal VR3 has a predetermined switching period T, and repeatedly rises and falls between the peak value VR3H and the bottom value VR3L, rising to a peak value VR3H, then decreasing, and then falling to the bottom value VR3L, then increasing again.

[0139] When the first analog signal VC1 is higher than the third ramp signal VR3, the switch output stage 10 is in an on-period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the third ramp signal VR3, the switch output stage 10 is in an off-period toff, and the coil current IL decreases.

[0140] That is, the higher the first analog signal VC1, the larger the on-duty Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty Don of the switch output stage 10 becomes.

[0141] Here, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the bottom timing when the third ramp signal VR3 takes the bottom value VR3L (corresponding to the timing when the first clock signal CLK1 falls from high level to low level).

[0142] As shown in the figure, the bottom timing of the third ramp signal VR3 coincides with the center timing of the on-period ton (=the timing when ton / 2 has elapsed since the coil current IL started to increase).

[0143] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the on-period ton.

[0144] In this way, if PWM control is performed using the third ramp signal VR3 having a triangular waveform instead of the first ramp signal VR1 having a sawtooth waveform, it is possible to easily sample the center value Ic of the coil current IL by simply detecting the peak timing or bottom timing of the third ramp signal VR3.

[0145] Figure 22 is a waveform diagram showing a second operation example of the timing control unit 120 in the sixth embodiment, and similarly to Figure 21 above, depicts, from top to bottom, the first analog signal VC1 (dotted line), the third ramp signal VR3 (solid line), the coil current IL, and the timing control signal ST.

[0146] The second operation example in this figure is basically the same as the first operation example (FIG. 21) above, except that the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the peak timing when the third ramp signal VR3 has a peak value VR3H (corresponding to the timing when the first clock signal CLK1 rises from a low level to a high level).

[0147] As shown in the figure, the peak timing of the third ramp signal VR3 coincides with the center timing of the off period toff (=the timing when toff / 2 has elapsed since the coil current IL started to decrease).

[0148] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the off period toff.

[0149] Seventh embodiment Fig. 23 is a diagram showing a seventh embodiment of a DC / DC converter. The DC / DC converter 1 of this embodiment is based on the first embodiment (Fig. 1), but a PWM comparator 160 and an OR gate 170 are newly added, and the DC / DC converter 1 performs PWM control using the first ramp signal VR1 and an inverted first ramp signal VR1B obtained by inverting the first ramp signal VR1, and is characterized in that it detects the reset timing of each signal to generate a timing control signal ST. Therefore, the same components as those in the first embodiment are given the same reference numerals as those in Fig. 1 to omit redundant explanations, and the following description will focus on the characteristic parts of the seventh embodiment.

[0150] In the DC / DC converter 1 of this embodiment, the oscillator 70 generates a first ramp signal VR1 and an inverted first ramp signal VR1B of a sawtooth waveform that repeatedly rises or falls and is reset in a common switching period T while having mutually opposite polarities, and supplies these to the inverting input terminals (-) of the PWM comparators 80 and 160. In addition, the oscillator 70 generates a second clock signal CLK2 in which a one-shot pulse is generated at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B, and supplies this to the timing control unit 120.

[0151] As described above, the PWM comparator 80 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the first ramp signal VR1 input to the inverting input terminal (-) to generate the first comparison signal CMP1. The first comparison signal CMP1 goes to a high level when the first analog signal VC1 is higher than the first ramp signal VR1, and goes to a low level when the first analog signal VC1 is lower than the first ramp signal VR1.

[0152] On the other hand, the PWM comparator 160 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the inverted first ramp signal VR1B input to the inverting input terminal (-) to generate a second comparison signal CMP2. The second comparison signal CMP2 goes to a high level when the first analog signal VC1 is higher than the inverted first ramp signal VR1B, and goes to a low level when the first analog signal VC1 is lower than the inverted first ramp signal VR1B.

[0153] The OR gate 170 generates a logical sum signal SX (corresponding to a control signal for the switch output stage 10) of the first comparison signal CMP1 and the second comparison signal CMP2, and outputs it to the driver 90. The logical sum signal SX becomes high level when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is at a high level, and becomes low level when both the first comparison signal CMP1 and the second comparison signal CMP2 are at a low level.

[0154] 24 is a circuit diagram showing an example of the configuration of the oscillator 70 in the seventh embodiment. The oscillator 70 of this example includes a current source 71c, switches 72c and 72d, capacitors 73b and 73c, a comparator 74b, and a delay unit 77.

[0155] The first terminal of the current source 71c is connected to the application terminal of the power supply voltage VDD. The second terminal of the current source 71c, the first terminal of the switch 73b, the first terminal of the capacitor 73b, and the non-inverting input terminal (+) of the comparator 74b are all connected to the output terminal of the first ramp signal VR1. The second terminal of the switch 72c and the second terminal of the capacitor 73b are connected to the application terminal (e.g., the ground terminal) of the first voltage VR1L (corresponding to the bottom value VR1L of the first ramp signal VR1 and the inverted first ramp signal VR1B). The inverting input terminal (-) of the comparator 74b is connected to the application terminal of the second voltage VR1H (corresponding to the peak value VR1H of the first ramp signal VR1 and the inverted first ramp signal VR1B). The output terminal of the comparator 74b is connected to the input terminal of the delay unit 77.

[0156] A first terminal of the switch 72d and a first terminal of the capacitor 73c are all connected to the application terminal of the second voltage VR1H. A second terminal of the switch 72d, a second terminal of the capacitor 73c, and a first terminal of the current source 71d are all connected to the output terminal of the inverted first ramp signal VR1B. A second terminal of the current source 71d is connected to the application terminal of the first voltage VR1L. The control terminals of the switches 72c and 72d are all connected to the output terminal of the delay unit 77 (=the output terminal of the second clock signal CLK2).

[0157] In the oscillator 70 having the above configuration, the current source 71c generates a charging current I71c for charging the capacitor 73b, and the current source 71d generates a charging current I71d for charging the capacitor 73c. ​​The charging currents I71c and I71d are set to be equal to each other.

[0158] Moreover, both of the switches 72c and 72d are turned on / off in response to the second clock signal CLK2 so as to discharge the capacitors 73b and 73c. ​​More specifically, when the second clock signal CLK2 is at a low level, both of the switches 72c and 72d are turned off, so that the capacitors 73b and 73c are charged by the charging currents I71c and I71d, respectively. Therefore, the first ramp signal VR1 monotonically rises from the bottom value VR1L to the peak value VR1H at a predetermined upward slew rate, and the inverted first ramp signal VR1B monotonically falls from the peak value VR1H to the bottom value VR1L at a downward slew rate equal to the upward slew rate (with the opposite polarity) (see times t11 to t12 in FIG. 25).

[0159] On the other hand, when the second clock signal CLK2 is at a high level, the switches 72c and 72d are both turned on, thereby discharging the capacitors 73b and 73c without delay (=a state in which both ends of each are shorted). As a result, the first ramp signal VR1 is reset to the bottom value VR1L, and the inverted first ramp signal VR1B is reset to the peak value VR1H (see times t12 to t13 in FIG. 25).

[0160] The comparator 74b compares the first ramp signal VR1 with the second voltage VR1H (corresponding to the peak value VR1H) to generate a comparison signal S74b. Note that the comparison signal S74b goes to a low level when the first ramp signal VR1 is lower than the peak value VR1H, and goes to a high level when the first ramp signal VR1 is higher than the peak value VR1H.

[0161] The delay unit 77 performs a delay process on the comparison signal S74b to generate the second clock signal CLK2. More specifically, when the comparison signal S74b rises to the high level, the delay unit 77 immediately raises the second clock signal CLK2 to the high level (see time t12 in FIG. 25). On the other hand, when the comparison signal S74b falls to the low level, the delay unit 77 waits for a predetermined delay time to elapse and then lowers the second clock signal CLK2 to the low level (see times t12 to t13 in FIG. 25). With such a configuration, it becomes possible to reliably discharge the capacitors 73b and 73c.

[0162] In this way, the comparator 74b and the delay unit 77 function as a clock signal generation unit that compares the first lamp signal VR1 with the second voltage VR3H (corresponding to the peak value VR1H) to generate the second clock signal CLK2.

[0163] The timing control unit 120 receives the input of the second clock signal CLK2 described above, and generates a timing control signal ST so that the sampling of the coil current IL is performed at the timing when the logic level thereof changes (= the reset timing of the first lamp signal VR1 and the inverted first lamp signal VR1B). Hereinafter, a specific operation example of the timing control unit 120 will be described in detail.

[0164] FIG. 26 is a waveform diagram showing an operation example of the timing control unit 120 in the seventh embodiment, and depicts, in order from the top, the first analog signal VC1 (dashed-dotted line), the first lamp signal VR1 (solid line), and the inverted first lamp signal VR1B (dashed line), the coil current IL, and the timing control signal ST.

[0165] As also shown in FIG. 25 above, the first lamp signal VR1 and the inverted first lamp signal VR1B repeat rising or falling and resetting with a common switching period T while having opposite polarities to each other between the peak value VR1H and the bottom value VR1L. On the other hand, the first analog signal VC1 varies within a voltage range of VR1L < VC1 < (VR1H + VR1L) / 2.

[0166] When the first analog signal VC1 is higher than at least one of the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 is in an on-period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than both the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 is in an off-period toff, and the coil current IL decreases.

[0167] That is, the higher the first analog signal VC1, the larger the on-duty Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty Don of the switch output stage 10 becomes.

[0168] Here, the timing control section 120 generates a one-shot pulse in the timing control signal ST at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B (corresponding to the timing at which the second clock signal CLK2 rises to a high level).

[0169] As shown in the figure, the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B coincides with the center timing of the on-period ton (=the timing when ton / 2 has elapsed since the coil current IL started to increase).

[0170] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the on-period ton.

[0171] Eighth embodiment FIG. 27 is a diagram showing an eighth embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is characterized in that, based on the seventh embodiment (FIG. 23), an AND gate 180 is used instead of the OR gate 170. Therefore, for the components similar to those in the seventh embodiment, the same reference numerals as in FIG. 23 are given, and redundant explanations are omitted. Hereinafter, the characteristic parts of the eighth embodiment will be mainly described.

[0172] In the DC / DC converter 1 of this embodiment, the AND gate 180 generates a logical product signal SY (= corresponding to the control signal of the switch output stage 10) of the first comparison signal CMP1 and the second comparison signal CMP2 and outputs it to the driver 90. The logical product signal SY becomes high level when both the first comparison signal CMP1 and the second comparison signal CMP2 are high level, and becomes low level when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is low level.

[0173] FIG. 28 is a waveform diagram showing an operation example of the timing control unit 120 in the eighth embodiment. Similar to the previous FIG. 26, from top to bottom in order, the first analog signal VC1 (dashed-dotted line), the first lamp signal VR1 (solid line), and the inverted first lamp signal VR1B (dashed line), the coil current IL, and the timing control signal ST are depicted.

[0174] Also in the operation example of this figure, the first lamp signal VR1 and the inverted first lamp signal VR1B repeat rising or falling and reset at a common switching period T while having opposite polarities to each other between the peak value VR1H and the bottom value VR1L. On the other hand, the first analog signal VC1 varies within a voltage range of (VR1H + VR1L) / 2 < VC1 < VR1H.

[0175] When the first analog signal VC1 is higher than both the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 is in an on-period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than at least one of the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 is in an off-period toff, and the coil current IL decreases.

[0176] That is, the higher the first analog signal VC1, the larger the on-duty Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty Don of the switch output stage 10 becomes.

[0177] Here, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B (corresponding to the timing at which the second clock signal CLK2 rises to a high level).

[0178] As shown in the figure, the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B coincides with the center timing of the off period toff (=the timing when toff / 2 has elapsed since the coil current IL started to decrease).

[0179] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL during the off period toff.

[0180] <Ninth embodiment> Fig. 29 is a diagram showing a ninth embodiment of a DC / DC converter. The DC / DC converter 1 of this embodiment is based on the seventh embodiment (Fig. 23) and the eighth embodiment (Fig. 27), but is characterized in that the switch output stage 10 is changed to a step-up / step-down type, the input polarities of the PWM comparators 80 and 160 are reversed, and a logic operation unit 190 is used instead of the OR gate 170 and the AND gate 180. Therefore, the same components as those of the seventh and eighth embodiments are given the same reference numerals as those in Figs. 23 and 27, and redundant explanations are omitted, and the following description focuses on the characteristic parts of the ninth embodiment.

[0181] In the DC / DC converter 1 of this embodiment, the switch output stage 10 includes, in addition to the step-down output transistor 11 and the synchronous rectification transistor 12, a step-up output transistor 15 (an NMOSFET in this figure) and a synchronous rectification transistor 16 (a PMOSFET in this figure), and steps down or steps up the input voltage Vin to generate the desired output voltage Vout.

[0182] The source of the output transistor 11 is connected to the application terminal of the input voltage Vi. The drain of the output transistor 11 and the drain of the synchronous rectifier transistor 12 are connected to a first terminal of the coil 13. The source of the synchronous rectifier transistor 12 is connected to the ground terminal. The drain of the output transistor 15 and the drain of the synchronous rectifier transistor 16 are connected to a second terminal of the coil 13. The source of the output transistor 15 is connected to the ground terminal. The source of the synchronous rectifier transistor 16 is connected to the output terminal of the output voltage Vo and the first terminal of the capacitor 14. The second terminal of the capacitor 14 is connected to the ground terminal.

[0183] The output transistor 11 is turned on when the step-down drive signal D1 is at a low level, and turned off when the step-down drive signal D1 is at a high level. The synchronous rectification transistor 12 is turned on when the step-down drive signal D2 is at a high level, and turned off when the step-down drive signal D2 is at a low level. The output transistor 15 is turned on when the step-up drive signal U1 is at a high level, and turned off when the step-up drive signal U1 is at a low level. The synchronous rectification transistor 16 is turned on when the step-up drive signal U2 is at a low level, and turned off when the step-up drive signal U2 is at a high level.

[0184] Furthermore, in the DC / DC converter 1 of this embodiment, the logic operation unit 190 includes a NAND gate 191 and an OR gate 192, and receives the first comparison signal CMP1 and the second comparison signal CMP2, to generate a step-down control signal D0 and a step-up control signal U0.

[0185] The NAND gate 191 generates the step-down control signal D0 by performing a NAND operation on the first comparison signal CMP1 and the second comparison signal CMP2. Therefore, the step-down control signal D0 is at a low level when both the first comparison signal CMP1 and the second comparison signal CMP2 are at a high level, and is at a high level when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is at a low level.

[0186] The OR gate 192 generates the boost control signal U0 by performing a logical OR operation on the first comparison signal CMP1 and the second comparison signal CMP2. Therefore, the boost control signal U0 is at a low level when both the first comparison signal CMP1 and the second comparison signal CMP2 are at a low level, and is at a high level when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is at a high level.

[0187] That is, the logic operation unit 190 receives the input of the first comparison signal CMP1 and the second comparison signal CMP2, extracts a state in which the first analog signal VC1 is lower than both the first ramp signal VR1 and the inverted first ramp signal VR1B (CMP1=CMP2=H), and conversely, a state in which the first analog signal VC1 is higher than both the first ramp signal VR1 and the inverted first ramp signal VR1B (CMP1=CMP2=L), and generates a step-down control signal D0 based on one extraction result and generates a step-up control signal U0 based on the other extraction result.

[0188] Furthermore, in the DC / DC converter 1 of this embodiment, the driver 90 receives input of a step-down control signal D0 and a step-up control signal U0, generates step-down drive signals D1 and D2, and step-up drive signals U1 and U2, and uses these to drive the switch output stage 10.

[0189] FIG. 30 is a timing chart showing the operation of generating the step-down drive signals D1 and D2, depicting the step-down control signal D0 and the step-down drive signals D1 and D2.

[0190] The step-down drive signal D1 goes low with a delay of delay time d from the rising edge of the step-down control signal D0 and goes high simultaneously with the falling edge of the step-down control signal D0. On the other hand, the step-down drive signal D2 goes low with a delay of delay time d from the falling edge of the step-down control signal D0 and goes high.

[0191] In this way, the step-down drive signals D1 and D2 are basically logically inverted signals of the step-down control signal D0. Therefore, the output transistor 11 and the synchronous rectifier transistor 12 are turned on / off complementarily. However, the step-down drive signals D1 and D2 are provided with a period (so-called dead time) during which both the output transistor 11 and the synchronous rectifier transistor 12 are turned off over the delay time d. Therefore, it is possible to prevent the occurrence of a through current caused by the output transistor element 11 and the synchronous rectifier transistor 12 being turned on simultaneously.

[0192] FIG. 31 is a timing chart showing the operation of generating the boost drive signals U1 and U2, depicting the boost control signal U0 and the boost drive signals U1 and U2.

[0193] The boost drive signal U1 goes low simultaneously with the rising edge of the boost control signal U0, and goes high after a delay of a delay time d from the falling edge of the boost control signal U0. On the other hand, the boost drive signal U2 goes low after a delay of a delay time d from the rising edge of the boost control signal U0, and goes high simultaneously with the falling edge of the boost control signal U0.

[0194] In this way, the boost drive signals U1 and U2 are basically the logical inversion signals of the boost control signal U0. Therefore, the output transistor 15 and the synchronous rectifier transistor 16 are turned on / off complementarily. However, the boost drive signals U1 and U2 are provided with a period (so-called dead time) during which both the output transistor 15 and the synchronous rectifier transistor 16 are turned off over the delay time d. Therefore, it is possible to prevent the generation of a through current caused by the output transistor 15 and the synchronous rectifier transistor 16 being turned on simultaneously.

[0195] Figure 32 is a waveform diagram showing a first operation example (during voltage step-down) of the timing control unit 120 in the ninth embodiment, and depicts, from top to bottom, the first analog signal VC1 (dash line), the first ramp signal VR1 (solid line), the inverted first ramp signal VR1B (dashed line), the first comparison signal CMP1 and the second comparison signal CMP2, the voltage step-down control signal D0 and the voltage step-up control signal U0, the coil current IL, and the timing control signal ST.

[0196] As also shown in FIG. 25 above, the first ramp signal VR1 and the inverted first ramp signal VR1B have opposite polarities to each other and repeatedly rise or fall and reset in a common switching period T between a peak value VR1H and a bottom value VR1L.

[0197] Here, when VR1L < VC1 < (VR1H + VR1L) / 2, since the boost control signal U0 is always at a high level, the output transistor 15 is always off and the synchronous rectification transistor 16 is always on. On the other hand, the buck control signal D0 is in a state of being pulse-driven with an on-duty Don (= the ratio of the on-period ton to the switching period T) corresponding to the first analog signal VC1, so the output transistor 11 and the synchronous rectification transistor 12 are complementarily turned on / off.

[0198] When the output transistor 11 is on and the synchronous rectification transistor 12 is off, energy is stored in the coil 13. On the other hand, when the output transistor 11 is off and the synchronous rectification transistor 12 is on, the energy stored in the coil 13 is released. By repeating such energy storage and release, an output voltage Vo obtained by stepping down the input voltage Vi is generated.

[0199] Note that when the first analog signal VC1 is higher than at least one of the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 becomes the on-period ton and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than both the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 becomes the off-period toff and the coil current IL decreases.

[0200] That is, during the buck operation of this figure, the higher the first analog signal VC1, the larger the on-duty Don (= ton / T) of the switch output stage 10. Conversely, the lower the first analog signal VC1, the smaller the on-duty Don of the switch output stage 10.

[0201] Here, the timing control unit 120 generates a one-shot pulse for the timing control signal ST at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B (corresponding to the timing when the second clock signal CLK2 rises to a high level).

[0202] Note that, as shown in this figure, the reset timings of the first lamp signal VR1 and the inverted first lamp signal VR1B coincide with the center timing of the on period ton (= the timing when ton / 2 has elapsed since the coil current IL started to increase).

[0203] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the on period ton by sampling the coil current IL triggered by the one-shot pulse of the timing control signal ST. In this way, the sampling timing during the step-down operation is the same as that in FIG. 26 described above.

[0204] FIG. 33 is a waveform diagram showing a second operation example (during boost) of the timing control unit 120 in the ninth embodiment. In order from the top, the first analog signal VC1 (dashed-dotted line), the first lamp signal VR1 (solid line) and the inverted first lamp signal VR1B (dashed line), the first comparison signal CMP1 and the second comparison signal CMP2, the step-down control signal D0 and the boost control signal U0, the coil current IL, and the timing control signal ST are depicted.

[0205] Also in the operation example of this figure, the first lamp signal VR1 and the inverted first lamp signal VR1B repeat rising, falling, and resetting at a common switching period T while having opposite polarities to each other between the peak value VR1H and the bottom value VR1L.

[0206] Here, when (VR1H + VR1L) / 2 < VC1 < VR1H, the step-down control signal D0 is always at a high level, so the output transistor 11 is always on and the synchronous rectification transistor 12 is always off. On the other hand, since the boost control signal U0 is in a state of being pulse-driven with an on duty Don (= the ratio of the on period ton to the switching period T) corresponding to the first analog signal VC1, the output transistor 15 and the synchronous rectification transistor 16 are complementarily turned on / off.

[0207] When the output transistor 15 is on and the synchronous rectifier transistor 16 is off, energy is stored in the coil 13. On the other hand, when the output transistor 15 is off and the synchronous rectifier transistor 16 is on, the energy stored in the coil 13 is released. By repeating such storage and release of energy, an output voltage Vo is generated by boosting the input voltage Vi.

[0208] When the first analog signal VC1 is higher than both the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 is in an on-period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than at least one of the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 is in an off-period toff, and the coil current IL decreases.

[0209] That is, during the boost operation in this figure, the higher the first analog signal VC1, the larger the on-duty Don (=ton / T) of the switch output stage 10, and conversely, the lower the first analog signal VC1, the smaller the on-duty Don of the switch output stage 10.

[0210] Here, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B (corresponding to the timing at which the second clock signal CLK2 rises to a high level).

[0211] As shown in the figure, the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B coincides with the center timing of the off period toff (=the timing when toff / 2 has elapsed since the coil current IL started to decrease).

[0212] Therefore, the current detection unit 50 samples the coil current IL using the one-shot pulse of the timing control signal ST as a trigger, and can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the off period toff. In this way, the sampling timing during boost operation is the same as that shown in Figure 28 above.

[0213] Tenth embodiment The DC / DC converter 1 of this embodiment has a configuration basically similar to that of the first embodiment (FIG. 1), and is characterized by the circuit configuration of the timing control unit 120. Therefore, a description of the overall configuration of the DC / DC converter 1 will be omitted, and the following description will focus on the characteristic parts of the tenth embodiment.

[0214] First, before describing the configuration and operation of the timing control section 120, a supplementary description will be given of the configuration and operation of the oscillator 70 with reference to FIG.

[0215] Fig. 34 is a circuit diagram showing a configuration example of the oscillator 70 in the tenth embodiment. The oscillator 70 of this configuration example is based on the seventh embodiment (Fig. 24), but omits the components related to the generation of the inverted first ramp signal VR1B (the current source 71d, the switch 72d, and the capacitor 73c).

[0216] For ease of understanding, the oscillator 70 of this configuration example generates a first ramp signal VR1 whose peak value is the reference voltage Vref and whose bottom value is the ground voltage GND. More specifically, the reference voltage Vref is input to the inverting input terminal (-) of the comparator 74b, and the ground voltage GND is applied to the second terminal of the capacitor 73b.

[0217] Furthermore, in the oscillator 70 of this configuration example, P-channel MOS field effect transistors P1 and P2, an N-channel MOS field effect transistor N1, an operational amplifier AMP1, and a resistor R1 are specifically depicted as circuit elements that form the current source 71c.

[0218] The sources of the transistors P1 and P2 are both connected to a terminal to which a power supply voltage VDD is applied. The gates of the transistors P1 and P2 are both connected to a drain of the transistor P1. The drain of the transistor P1 is connected to a drain of the transistor N1. The drain of the transistor P2 is connected to a first terminal of the capacitor 73b as an output terminal of the charging current I71c.

[0219] The non-inverting input terminal (+) of the operational amplifier AMP1 is connected to the application terminal of the constant voltage V1. The inverting input terminal (-) of the operational amplifier AMP1 is connected to the source of the transistor N1 and the first terminal of the resistor R1. The output terminal of the operational amplifier AMP1 is connected to the gate of the transistor N1. The second terminal of the resistor R1 is connected to the ground terminal.

[0220] In the current source 71c configured as above, the operational amplifier AMP1 controls the gate of the transistor N1 so that the non-inverting input terminal (+) and the inverting input terminal (-) are imaginarily shorted. Therefore, a constant voltage V1 is applied to the first terminal of the resistor R1, and a predetermined drain current (V1 / R1) flows through the transistor N1.

[0221] The transistors P1 and P2 form a current mirror, and by mirroring the drain current (V1 / R1) with a mirror ratio α, a charging current I71c (=α×(V1 / R1)) for the capacitor 73b is generated.

[0222] In addition, when the current value of the charging current I71c is I0 and the capacitance value of the capacitor 73b is C0, in order to generate the first ramp signal VR1 and the second clock signal CLK2 at a desired switching period T, the above-mentioned mirror ratio α, the voltage value of the constant voltage V1, and the resistance value of the resistor R1 can be appropriately set so that I0=Vref×C0×(1 / T) is satisfied.

[0223] 35 is a circuit diagram showing a configuration example of the timing control section 120 in the tenth embodiment. The timing control section 120 of this configuration example includes a first internal signal generation section 121, a second internal signal generation section 122, and a comparator 123.

[0224] The first internal signal generating unit 121 is a circuit unit that generates a first internal signal V11 by charging and discharging the capacitor C1 in synchronization with an on signal ON, and includes the capacitor C1, current sources CS1 to CS3, switches SW1 and SW2, a pnp bipolar transistor Qp, an npn bipolar transistor Qn, and resistors R11 and R12.

[0225] The first terminals of the current sources CS1 to CS3 are all connected to the power supply terminal. The second terminal of the current source CS1 is connected to the base of the transistor Qp and the first terminal of the switch SW1. The second terminal of the switch SW1 is connected to the first terminal of the capacitor C1 and the first terminal of the switch SW2. The second terminal of the current source CS2 is connected to the base of the transistor Qn and the emitter of the transistor Qp. The second terminal of the current source CS3 is connected to the non-inverting input terminal (+) of the comparator 123, the collector of the transistor Qn, and the first terminal of the resistor R12. The emitter of the transistor Qn is connected to the first terminal of the resistor R11. The second terminal of the capacitor C1, the second terminal of the switch SW2, the collector of the transistor Qp, and the second terminals of the resistors R11 and R12 are all connected to the ground terminal. The control terminal of the switch SW1 is connected to the application terminal of the on signal ON. The control terminal of the switch SW2 is connected to the application terminal of the reset signal RST.

[0226] The switch SW1 is turned on when the switch output stage 10 is in an on-period ton (e.g., ON=H) and is turned off when the switch output stage 10 is in an off-period toff (e.g., ON=L). The on signal ON is a logic signal synchronized with the on / off control of the switch output stage 10, and may be, for example, the first comparison signal CMP1.

[0227] The switch SW2 is turned on when the reset signal RST is at a high level, and turned off when the reset signal RST is at a low level. The reset signal RST is a signal for discharging the capacitor C1 prior to the on-period ton, and may be, for example, the second clock signal CLK2 (see FIG. 34).

[0228] The second internal signal generating unit 122 is a circuit unit that generates the second internal signal V12 by charging and discharging the capacitor C2 in synchronization with the off signal OFF, and includes a capacitor C2, a current source CS4, and a switch SW3.

[0229] A first terminal of the current source CS4 is connected to the power supply terminal. A second terminal of the current source CS4 is connected to the inverting input terminal (-) of the comparator 123, a first terminal of the capacitor C2, and a first terminal of the switch SW3. A second terminal of the capacitor C2 and a second terminal of the switch SW3 are connected to the ground terminal. A control terminal of the switch SW3 is connected to an application terminal of an off signal OFF.

[0230] The switch SW3 is turned on when the switch output stage 10 is in an on-period ton (e.g., OFF=H) and is turned off when the switch output stage 10 is in an off-period toff (e.g., OFF=L). The off signal OFF is a logic signal synchronized with the on / off control of the switch output stage 10, and may be, for example, the first comparison signal CMP1.

[0231] The comparator 123 compares the first internal signal V11 input to the non-inverting input terminal (+) with the second internal signal V12 input to the inverting input terminal (-) to generate a timing control signal ST. The timing control signal ST goes to high level when the first internal signal V11 is higher than the second internal signal V12, and goes to low level when the first internal signal V11 is lower than the second internal signal V12.

[0232] Thus, unlike the previous fourth to ninth embodiments (FIGS. 8 to 33), the timing control section 120 in this embodiment generates a timing control signal ST such that sampling of the coil current IL is performed at the center timing of the off period toff of the switch output stage 10, using the first internal signal V11 and the second internal signal V12 that are generated by itself in synchronization with the on / off control of the switch output stage 10. A specific example of the operation of the timing control section 120 will be described in detail below with reference to FIG. 36 together with this figure.

[0233] Figure 36 is a waveform diagram showing an example of operation of the timing control unit 120 in the tenth embodiment, and depicts, from the top, the first ramp signal VR1 (solid line) and the first analog signal VC1 (dotted line), the first comparison signal CMP1 (= on signal ON and off signal OFF), the coil current IL, the reset signal RST, the charging voltage V10 of the capacitor C1, the first internal signal V11 (solid line) and the second internal signal V12 (dashed line), and the timing control signal ST.

[0234] First, the overall operation of the DC / DC converter 1 will be reviewed with reference to the top three rows (VR1 / VC1, CMP1, and IL) of the diagram.

[0235] When the first analog signal VC1 is higher than the first ramp signal VR1, the switch output stage 10 is in an on-period ton (=times t21 to t22), and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first ramp signal VR1, the switch output stage 10 is in an off-period toff (=times t22 to t24), and the coil current IL decreases. That is, the higher the first analog signal VC1, the larger the on-duty Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1, the smaller the on-duty Don of the switch output stage 10 becomes.

[0236] Thus, the overall operation of the DC / DC converter 1 is no different from that of the first embodiment (FIG. 1).

[0237] Next, the operation of the timing control section 120 will be described in detail with reference to the bottom four rows (RST, V10, V11 / V12, and ST) of the diagram.

[0238] First, focusing on the first internal signal generating unit 121, at time t21, a one-shot pulse is generated in the reset signal RST prior to the on-period ton of the switch output stage 10. As a result, the switch SW2 is turned on and the capacitor C1 is discharged, so that the charging voltage V10 is reset to zero (=GND).

[0239] Thereafter, during the on-period ton (=time t21 to t22) of the switch output stage 10, the switch SW1 is turned on, and conduction is established between the current source CS1 and the capacitor C1. As a result, the capacitor C1 is charged using the charging current I1 supplied from the current source CS1, and the charging voltage V10 rises with the passage of time t at a predetermined slope (=I1 / C1). Therefore, if I1=Vref×C1×(1 / T) is set, the charging voltage V10[t] after the passage of time t from time t21 can be expressed as V10[t]=Vref×(t / T). That is, at time t21 (t=0), V10=GND, and at time t22 (t=ton), V10=Vref×(ton / T).

[0240] The charging voltage V10 is applied to a first terminal of the resistor R11 via the transistors Qp and Qn that receive the drive current I2 from the current source CS2. Therefore, a lower current I11 (=V10 / R11) corresponding to the charging voltage V10 flows through the resistor R11. In this way, the current source CS2, the transistors Qp and Qn, and the resistor R11 function as a voltage / current converter that converts the charging voltage V10 of the capacitor C1 into the lower current I11.

[0241] Furthermore, a differential current I12 (=I3-I11) obtained by subtracting the above-mentioned lower current I11 from the upper current I3 generated by the current source CS3 flows through the resistor R12. Therefore, the first internal signal V11 output from the first end of the resistor R12 can be expressed as V11=I12×R12. In this manner, the resistor R12 functions as a current / voltage converter that converts the differential current I12 between the upper current I3 and the lower current I11 into the first internal signal V11.

[0242] Here, if I3=Vref / R11 and R11=2×R12 are set, the first internal signal V11[t] after a time t has elapsed since time t21 can be expressed as V11[t]=(1 / 2)×Vref×{1-(t / T)}. That is, at time t21 (t=0), V11=(1 / 2)×Vref, and at time t22 (t=ton), V11=(1 / 2)×Vref×(toff / T).

[0243] On the other hand, during the off period toff (=times t22 to t24) of the switch output stage 10, the switch SW1 is turned off. Therefore, the increase in the charging voltage V10 stops, and the first internal signal V11 is maintained at the voltage value (=(1 / 2)×Vref×(toff / T)) just before it was turned off.

[0244] In this way, the first internal signal V11 changes during the on-period ton of the switch output stage 10 from half the value of the reference voltage Vref (=(1 / 2)×Vref) to a value (=(1 / 2)×Vref×(toff / T)) multiplied by the off-duty of the switch output stage 10 (=toff / T, i.e., the proportion of the off-period toff in the switching period T), and is then maintained at that value during the off-period toff of the switch output stage 10.

[0245] Next, focusing on the second internal signal generating unit 122, during the on-period ton (=times t21 to t22) of the switch output stage 10, the switch SW3 is on and both ends of the capacitor C2 are shorted, so that the second internal signal V12 is maintained at zero value (=GND). Therefore, during the on-period ton of the switch output stage 10, the first internal signal V11 is always higher than the second internal signal V12, so that the timing control signal ST is maintained at a low level.

[0246] On the other hand, during the off period toff (=times t22 to t24) of the switch output stage 10, the switch SW3 is turned off. As a result, the capacitor C2 is charged using the charging current I4 supplied from the current source CS4, so that the second internal signal V12 rises with the passage of time t at a predetermined slope (=I4 / C2). Therefore, if I4=Vref×C2×(1 / T) is set, the second internal signal V12[t] after the passage of time t from time t22 can be expressed as V12[t]=Vref×(t / T). That is, at time t22 (t=0), V12=GND, and at time t24 (t=toff), V12=Vref×(toff / T).

[0247] In this way, the second internal signal V12 is held at zero value (=GND) during the on period ton of the switch output stage 10, and then changes from the zero value to a value (=Vref×(toff / T)) obtained by multiplying the reference voltage Vref by the off duty (=toff / T) during the off period toff of the switch output stage 10.

[0248] Here, the timing (=time t23) at which the first internal signal V11 and the second internal signal V12 cross each other coincides with the center timing of the off period toff (=the timing when toff / 2 has elapsed since the coil current IL started to decrease). That is, the timing control signal ST rises from low level to high level at time t23.

[0249] Therefore, the current detection unit 50 samples the coil current IL using the rising edge of the timing control signal ST as a trigger, and can generate a current sense signal ISNS that corresponds to the center value Ic of the coil current IL in the off period toff.

[0250] <Summary> The following provides an overview of the various embodiments described above.

[0251] The DC / DC converter disclosed in this specification has a current detection unit that generates a current sense signal by sampling the coil current of a switch output stage at a timing corresponding to a timing control signal, and a timing control unit that generates the timing control signal using first and second internal signals generated by itself in synchronization with the on / off control of the switch output stage so that the coil current is sampled at the center timing of the off period of the switch output stage, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control method using the current sense signal (first configuration).

[0252] In addition, in the DC / DC converter having the above-mentioned first configuration, it is preferable that the timing control unit has a configuration (second configuration) including a first internal signal generating unit that generates the first internal signal in synchronization with the on period, a second internal signal generating unit that generates the second internal signal in synchronization with the off period, and a comparator that compares the first internal signal with the second internal signal to generate the timing control signal.

[0253] Furthermore, in a DC / DC converter having the above-mentioned second configuration, it is preferable that the first internal signal changes from half the value of a reference voltage to a value obtained by multiplying this value by an off-duty of the switch output stage during the on-period, and is then held at that value during the off-period, and the second internal signal is held at a zero value during the on-period, and then changes from the zero value to a value obtained by multiplying the reference voltage by the off-duty during the off-period (third configuration).

[0254] Furthermore, in a DC / DC converter having the above-mentioned third configuration, it is preferable that the first internal signal generating unit includes a first capacitor, a first current source that generates a charging current for the first capacitor, a first switch that charges the first capacitor during the on-period, a second switch that discharges the first capacitor prior to the on-period, a second current source that generates a predetermined upper current, a voltage / current conversion unit that converts the charging voltage of the first capacitor into a lower current, and a current / voltage conversion unit that converts a differential current between the upper current and the lower current into the first internal signal (fourth configuration).

[0255] Furthermore, in the DC / DC converter having the above third or fourth configuration, it is preferable that the second internal signal generating unit has a configuration (fifth configuration) including a second capacitor, a current source that generates a charging current for the second capacitor, and a switch that charges the second capacitor during the off period.

[0256] Furthermore, a DC / DC converter having any of the above first to fifth configurations may be configured (sixth configuration) to have an error amplifier that generates an error signal corresponding to the difference between the output voltage or a feedback voltage corresponding to the output voltage, and a predetermined reference voltage, an oscillator that generates a ramp signal at a predetermined switching period, a differential amplifier that generates an analog signal corresponding to the difference between the error signal and the current sense signal, a comparator that compares the analog signal with the ramp signal to generate a comparison signal, and a driver that generates a drive signal for the switch output stage in response to the comparison signal.

[0257] Moreover, the DC / DC converter having the sixth configuration may be configured (seventh configuration) further including a clamper that limits the error signal to a value equal to or lower than a predetermined upper limit value or equal to or higher than a predetermined lower limit value.

[0258] In addition, the DC / DC converter having the sixth or seventh configuration may be further configured (eighth configuration) to have a light load detection comparator that compares the error signal with a predetermined threshold value to control whether or not the switch output stage is operable.

[0259] The DC / DC converter disclosed in this specification has a comparator that compares a first analog signal with a ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, an average value generation unit that generates a second analog signal having a simple average value of the signal value of the first analog signal and the start value or the end value of the ramp signal, and a timing control unit that generates the timing control signal using the ramp signal and the second analog signal so that the coil current is sampled at the center timing of the on period or the off period of the switch output stage, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control type using the current sense signal (ninth configuration).

[0260] The DC / DC converter disclosed in this specification has a comparator that compares a first analog signal with a first ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, an average value generation unit that generates a second analog signal having a weighted average value of the signal value of the first analog signal and a start value or an end value of the first ramp signal, and a timing control unit that generates the timing control signal using the second ramp signal and the second analog signal so that the coil current is sampled at the center timing of the on period or the off period of the switch output stage, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control method using the current sense signal (tenth configuration).

[0261] Also, in the DC / DC converter having the tenth configuration described above, the second analog signal has a weighted average value of the signal value (weight m) of the first analog signal and the starting value (weight n) of the first ramp signal (where m + n = 1, 0 < m < 1, 0 < n < 1, m ≠ n), and the second ramp signal may have a slew rate that is 2m / (m + n) times that of the first ramp signal (eleventh configuration).

[0262] Also, in the DC / DC converter having any of the ninth to eleventh configurations described above, the first ramp signal and the second ramp signal may both have a sawtooth waveform that repeats rising or falling and resetting in a common switching period (twelfth configuration).

[0263] Also, the DC / DC converter having any of the ninth to twelfth configurations described above may further include an error amplifier that generates an error signal according to the difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage, and a differential amplifier that generates the first analog signal according to the difference between the error signal and the current sense signal (thirteenth configuration).

[0264] Also, the DC / DC converter having the thirteenth configuration described above may further include a clamper that limits the error signal to be equal to or less than a predetermined upper limit value or equal to or greater than a predetermined lower limit value (fourteenth configuration).

[0265] Also, the DC / DC converter having the thirteenth or fourteenth configuration described above may further include a light load detection comparator that compares the error signal with a predetermined threshold value to control the operability of the switch output stage (fifteenth configuration).

[0266] In addition, the DC / DC converter disclosed in this specification has an oscillator that generates a triangular waveform ramp signal with equal up / down slew rates, a comparator that compares an analog signal with the ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at a timing when the ramp signal takes its peak value or bottom value, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control method using the current sense signal (sixteenth configuration).

[0267] It is to be noted that in the DC / DC converter having the above-mentioned 16th configuration, the oscillator may be configured to include a capacitor connected between the output terminal of the ramp signal and a constant potential terminal, a first current source which generates a predetermined charging current, a second current source which generates a discharging current equal to the charging current, a switch which switches whether the capacitor is charged by the charging current or discharged by the discharging current in response to a clock signal, and a clock signal generating unit which compares the ramp signal with the peak value and the bottom value to generate the clock signal (17th configuration).

[0268] In the DC / DC converter having the above-mentioned seventeenth configuration, the timing control section may be configured to generate the timing control signal by using the clock signal (eighteenth configuration).

[0269] The DC / DC converter disclosed in this specification includes an oscillator that generates a sawtooth ramp signal and an inverted ramp signal that have opposite polarities to each other and repeatedly rise or fall and reset in a common switching period, a first comparator and a second comparator that compare an analog signal with the ramp signal and the inverted ramp signal, respectively, to generate a first comparison signal and a second comparison signal, a logic operation unit that generates a control signal for a switch output stage by logic operation using the first comparison signal and the second comparison signal, a current detection unit that generates a current sense signal by sampling a coil current in the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the reset timing of the ramp signal and the inverted ramp signal, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control method using the current sense signal (a nineteenth configuration).

[0270] In addition, in the DC / DC converter having the above-mentioned 19th configuration, the oscillator may be configured to include a first capacitor connected between the output terminal of the ramp signal and an application terminal of a first voltage, a second capacitor connected between an application terminal of a second voltage different from the first voltage and the output terminal of the inverted ramp signal, a first current source and a second current source which generate charging currents for the first capacitor and the second capacitor, respectively, a first switch and a second switch which discharge the first capacitor and the second capacitor according to a clock signal, and a clock signal generating unit which compares the ramp signal with the second voltage to generate the clock signal (20th configuration).

[0271] In the DC / DC converter having the above-mentioned twentieth configuration, the timing control section may be configured to generate the timing control signal by using the clock signal (twenty-first configuration).

[0272] In addition, in a DC / DC converter having any of the above-mentioned 19th to 21st configurations, it is preferable that the switch output stage is configured (22nd configuration) to be in an on period when the analog signal is higher than at least one of the ramp signal and the inverted ramp signal, and in an off period when the analog signal is lower than both the ramp signal and the inverted ramp signal.

[0273] In addition, in a DC / DC converter having any of the above-mentioned 19th to 21st configurations, the switch output stage may be configured (23rd configuration) to be in an on period when the analog signal is higher than both the ramp signal and the inverted ramp signal, and to be in an off period when the analog signal is lower than at least one of the ramp signal and the inverted ramp signal.

[0274] In addition, the DC / DC converter having any of the above-mentioned sixteenth to twenty-third configurations may be configured (twenty-fourth configuration) further including an error amplifier that generates an error signal according to the difference between the output voltage or a feedback voltage corresponding thereto, and a predetermined reference voltage, and a differential amplifier that generates the analog signal according to the difference between the error signal and the current sense signal.

[0275] Moreover, the DC / DC converter having the twenty-fourth configuration may be configured (twenty-fifth configuration) further including a clamper that limits the error signal to a value equal to or lower than a predetermined upper limit value or equal to or higher than a predetermined lower limit value.

[0276] In addition, the DC / DC converter having the above-mentioned 24th or 25th configuration may be configured (26th configuration) further including a light load detection comparator that compares the error signal with a predetermined threshold value to control whether the switch output stage is operable.

[0277] Furthermore, the DC / DC converter disclosed in this specification is configured to generate a desired output voltage from an input voltage by sampling the coil current of the switch output stage at the center timing of the on-period or off-period of the switch output stage and performing output feedback control of a current mode control type using a current sense signal corresponding to the sampled value (27th configuration).

[0278] The DC / DC converter having the above-mentioned 27th configuration may be configured to perform output feedback control of the current mode control type (28th configuration) by inputting the current sense signal or a signal obtained by performing a predetermined arithmetic process on the current sense signal, and a signal having error information of the output voltage to an amplifier or comparator.

[0279] In addition, the DC / DC converter having the 27th configuration may be configured to perform output feedback control using a current mode control method (29th configuration) by adding or subtracting the current sense signal and a signal having error information of the output voltage and inputting the result to an amplifier or a comparator.

[0280] In addition, the DC / DC converter having the above-mentioned 27th configuration may be configured (30th configuration) to monitor the current sense signal and control whether or not the switch output stage is operable depending on the result of comparing the current sense signal with a predetermined threshold value.

[0281] In addition, the DC / DC converter having the above-mentioned 28th or 29th configuration may be configured (31st configuration) to perform overcurrent protection or reverse current protection for the coil current by clamping a signal that is added to or subtracted from the current sense signal, or a signal that is the difference or compared with the current sense signal by the amplifier or comparator.

[0282] In addition, the DC / DC converter having the above-mentioned 28th or 29th configuration may be configured to monitor a signal to be added to or subtracted from the current sense signal, or a signal to be differentiated from or compared with the current sense signal by the amplifier or comparator, and control whether or not to operate the switch output stage depending on the result of comparing this with a predetermined threshold value (32nd configuration).

[0283] Furthermore, a DC / DC converter having any of the above-mentioned configurations 27 to 32 may be configured (configuration 33) to have a current detection unit that generates the current sense signal by sampling the coil current at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on-period or off-period of the switch output stage.

[0284] In addition, the DC / DC converter having the above-mentioned 33rd configuration may be configured to have an error amplifier that generates an error signal corresponding to the difference between the output voltage or a feedback voltage corresponding to the output voltage, and a predetermined reference voltage, an oscillator that generates a ramp signal at a predetermined switching period, a differential amplifier that generates an analog signal corresponding to the difference between the error signal and the current sense signal, a comparator that compares the analog signal with the ramp signal to generate a comparison signal, and a driver that generates a drive signal for the switch output stage in response to the comparison signal (34th configuration).

[0285] The DC / DC converter having the thirty-fourth configuration may be further provided with a clamper that limits the error signal to a value equal to or lower than a predetermined upper limit value or equal to or higher than a predetermined lower limit value (thirty-fifth configuration).

[0286] In addition, the DC / DC converter having the thirty-fourth or thirty-fifth configuration may be further configured (thirty-sixth configuration) to have a light load detection comparator that compares the error signal with a predetermined threshold value to control whether or not the switch output stage is operable.

[0287] In addition, the DC / DC converter disclosed in this specification has a comparator that compares an analog signal with a first ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal using a second ramp signal having a slew rate twice that of the first ramp signal so that the coil current is sampled at the center timing of the on period or off period of the switch output stage, and is configured to generate a desired output voltage from an input voltage by performing output feedback control of a current mode control method using the current sense signal (configuration 37).

[0288] In the DC / DC converter having the thirty-seventh configuration, the timing control section may be configured to compare the analog signal with the second ramp signal to generate the timing control signal (thirty-eighth configuration).

[0289] In addition, in the DC / DC converter having the above-mentioned 38th configuration, the first ramp signal and the second ramp signal both repeatedly rise and reset in a common switching period, and the switch output stage is in an on period when the analog signal is higher than the first ramp signal, and is in an off period when the analog signal is lower than the first ramp signal (39th configuration).

[0290] Furthermore, in the DC / DC converter having the thirty-eighth configuration, the first ramp signal and the second ramp signal both repeatedly rise and reset in a common switching period, and the switch output stage may be configured (fortieth configuration) to be in an off period when the analog signal is higher than the first ramp signal, and to be in an on period when the analog signal is lower than the first ramp signal.

[0291] Furthermore, in the DC / DC converter having the above-mentioned thirty-eighth configuration, the first ramp signal and the second ramp signal may both repeatedly decrease and reset in a common switching period, and the switch output stage may be in an on period when the analog signal is higher than the first ramp signal, and in an off period when the analog signal is lower than the first ramp signal (forty-first configuration).

[0292] Moreover, in the DC / DC converter having the thirty-eighth configuration, the second ramp signal may be configured to start changing with a delay of 1 / 2 of a switching period from the point at which the first ramp signal starts to change (forty-second configuration).

[0293] In addition, in a DC / DC converter having any of the configurations 38 to 42 above, the timing control section may be configured (configuration 43) to compare an equivalent analog signal having equivalent information with the second ramp signal, instead of the analog signal.

[0294] In addition, the DC / DC converter having any of the configurations 37 to 43 above may be configured (configuration 44) further including an error amplifier that generates an error signal according to the difference between the output voltage or a feedback voltage corresponding to the output voltage, and a predetermined reference voltage, and a differential amplifier that generates the analog signal according to the difference between the error signal and the current sense signal.

[0295] Moreover, the DC / DC converter having the forty-fourth configuration may be configured (forty-fifth configuration) further including a clamper that limits the error signal to a value equal to or lower than a predetermined upper limit value or equal to or higher than a predetermined lower limit value.

[0296] In addition, the DC / DC converter having the above-mentioned 44th or 45th configuration may be configured (46th configuration) further including a light load detection comparator that compares the error signal with a predetermined threshold value to control whether the switch output stage is operable.

[0297] <Other Modifications> In the above embodiment, a step-down or step-up / step-down DC / DC converter has been described as an example, but the configuration of the present invention is not limited to this and can also be applied to DC / DC converters employing other output formats (step-up, inverting).

[0298] In addition, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation, in addition to the above-mentioned embodiments. For example, bipolar transistors and MOS field effect transistors can be replaced with each other, and the logic levels of various signals can be inverted as desired. In other words, the above-mentioned embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-mentioned embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Industrial Applicability]

[0299] The DC / DC converter disclosed in this specification can be used as a power supply means for a variety of applications. [Explanation of symbols]

[0300] 1 DC / DC Converter 10 Switch output stage 11 Output transistor (for step-down) 12 Synchronous rectification transistor (for step-down) 13 Coil 14 Capacitor 15 Output transistor (for boosting) 16 Synchronous rectification transistor (for boost) 20 Feedback voltage generator 21, 22 Resistance 30 Error Amplifier 40 Phase compensation section 41 Resistance 42 Capacitor 50 Current detection section 60 Differential Amplifier 70 Oscillators 71a, 71b, 71c current source 72a, 72b, 72c, 72d Switches 73a, 73b, 73c Capacitors 74a, 74b Comparator 75a, 75b, 75c resistor 76 Selector 77 Delay section 80 PWM Comparator 90 Driver 91 NAND Gate 92 AND Gate 100 Clamper 110 Light Load Detection Comparator 120 Timing control section 121 1st internal signal generation section 122 Second internal signal generation section 123 Comparator 130, 140 arithmetic unit 150 Average value generator 160 PWM Comparator 170 OR Gate 180 AND Gate 190 Logic Operation Section 191 NAND Gate 192 OR Gate P1, P2 P-channel MOS field effect transistor N1 N-channel MOS field effect transistor AMP1 Operational Amplifier R1, R11, R12 resistors C0, C1, C2 capacitors CS1, CS2, CS3, CS4 current sources SW1, SW2, SW3 switches Qp pnp bipolar transistor Qn npn bipolar transistor

Claims

1. a comparator for comparing the analog signal with the first ramp signal to generate a control signal for the switch output stage; a current detection unit that generates a current sense signal by sampling a coil current of the switch output stage at a timing corresponding to a timing control signal; a timing control unit that generates the timing control signal so that sampling of the coil current is performed at a center timing of an on-period or an off-period of the switch output stage by using a second ramp signal having a slew rate twice that of the first ramp signal; having A DC / DC converter that generates a desired output voltage from an input voltage by performing output feedback control of a current mode control system using the current sense signal.

2. 2. The DC / DC converter according to claim 1, wherein the timing control section generates the timing control signal by comparing the analog signal with the second ramp signal.

3. The first ramp signal and the second ramp signal both repeatedly rise and reset in a common switching period; 3. The DC / DC converter of claim 2, wherein the switch output stage is in an on-period when the analog signal is higher than the first ramp signal, and is in an off-period when the analog signal is lower than the first ramp signal.

4. The first ramp signal and the second ramp signal both repeatedly rise and reset in a common switching period; 3. The DC / DC converter of claim 2, wherein the switch output stage is in an off period when the analog signal is higher than the first ramp signal, and is in an on period when the analog signal is lower than the first ramp signal.

5. The first ramp signal and the second ramp signal both repeatedly fall and reset in a common switching period; 3. The DC / DC converter of claim 2, wherein the switch output stage is in an on-period when the analog signal is higher than the first ramp signal, and is in an off-period when the analog signal is lower than the first ramp signal.

6. 3. The DC / DC converter according to claim 2, wherein the second ramp signal starts to change with a delay of 1 / 2 of a switching period from a point in time when the first ramp signal starts to change.

7. 7. The DC / DC converter according to claim 2, wherein said timing control section compares, instead of said analog signal, an equivalent analog signal having equivalent information with said second ramp signal.

8. an error amplifier that generates an error signal corresponding to a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage; a differential amplifier for generating the analog signal in response to a difference between the error signal and the current sense signal; 8. The DC / DC converter according to claim 1, further comprising:

9. 9. The DC / DC converter according to claim 8, further comprising a clamper for limiting the error signal to a value equal to or lower than a predetermined upper limit value or equal to or higher than a predetermined lower limit value.

10. 10. The DC / DC converter according to claim 8, further comprising a light load detection comparator that compares the error signal with a predetermined threshold value to control whether or not the switch output stage is operable.

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