Stacked image sensor and manufacturing method thereof

Abstract

To provide a semiconductor device that realizes many functions on a logic circuit chip.SOLUTION: A semiconductor device includes a first chip that includes a plurality of photosensitive devices, and the plurality of photosensitive devices are formed as a first array. The semiconductor device includes a second chip bonded to a first chip and including a plurality of groups of pixel transistors and a plurality of input / output transistors, the plurality of groups of pixel transistors are formed as a second array, and a plurality of input / output circuits are formed outside the second array. The semiconductor device includes a third chip bonded to the second chip and including a plurality of logic circuits.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] As technology evolves, complementary metal-oxide semiconductor (CMOS) image sensors are gaining popularity over traditional charge-coupled devices (CCDs) due to certain advantages inherent to CMOS image sensors. Specifically, CMOS image sensors have higher image capture rates, lower operating voltages, lower power consumption, and higher noise immunity. In addition, CMOS image sensors can be manufactured on the same high-volume wafer processing lines as logic and memory devices. As a result, a CMOS image chip can contain both the image sensor and all the necessary logic, such as amplifiers, A / D converters, etc. Summary of the Invention [Problem to be solved by the invention]

[0002] As technology nodes continue to advance more and more, it may be desirable to implement (eg, integrate) more functionality on-chip in logic circuits by forming more advanced transistors on-chip. [Means for solving the problem]

[0003] The present disclosure provides a semiconductor device. The semiconductor device includes a first chip, a second chip, and a third chip. The first chip includes a plurality of photosensitive devices. The plurality of photosensitive devices are formed as a first array. The second chip is bonded to the first chip and includes a plurality of groups of pixel transistors and a plurality of input / output transistors. The plurality of groups of pixel transistors are formed as a second array. The plurality of input / output transistors are provided outside the second array. The third chip is bonded to the second chip and includes a plurality of logic transistors.

[0004] The present disclosure provides a semiconductor device. The semiconductor device includes a first chip, a second chip, and a third chip. The first chip includes a first semiconductor substrate, a plurality of photosensitive devices, a plurality of transfer gate transistors, and a plurality of capacitors. The plurality of photosensitive devices are formed on the first semiconductor substrate. The plurality of transfer gate transistors are formed on the first semiconductor substrate. The plurality of capacitors are formed on the first semiconductor substrate. The second chip includes a second semiconductor substrate, a plurality of reset transistors, a plurality of source followers, a plurality of row selectors, and a plurality of input / output transistors. The plurality of reset transistors are formed on the second semiconductor substrate. The plurality of source followers are formed on the second semiconductor substrate. The plurality of row selectors are formed on the second semiconductor substrate. The plurality of input / output transistors are formed on the second semiconductor substrate. The third chip includes a third semiconductor substrate and a plurality of logic transistors. The plurality of logic transistors are formed on the third semiconductor substrate. The first to third chips are vertically joined to each other.

[0005] The present disclosure provides a method for manufacturing a semiconductor device, the method including forming a first chip including a plurality of photosensitive devices disposed on a first semiconductor substrate, forming a second chip including (i) a plurality of reset transistors disposed on a second semiconductor substrate, (ii) a plurality of source followers disposed on the second semiconductor substrate, (iii) a plurality of row selectors disposed on the second semiconductor substrate, and (iv) a plurality of input / output transistors disposed on the second semiconductor substrate, bonding the second chip to the first chip, forming a third chip including a plurality of logic transistors disposed on a third semiconductor substrate, and bonding the third chip to the second chip. Effect of the Invention

[0006] The present disclosure provides various embodiments of a vertically integrated backside illuminated (BSI) image sensor that allows further improvements over existing BSI image sensors. [Brief description of the drawings]

[0007] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard practice in the industry, various features have not been drawn to scale, and in fact, the dimensions of various features illustrated in the accompanying drawings may be arbitrarily expanded or reduced for illustrative clarity. [Figure 1] FIG. 1 is a schematic diagram of an exemplary image sensor including several chips vertically integrated with each other, according to some embodiments. [Diagram 2] 2 is a circuit diagram of an example pixel unit of the image sensor of FIG. 1 according to some embodiments. [Diagram 3] 3, 4, 5, 6, 7, 8, 9, 10, and 11 represent cross-sectional views of the image sensor of FIG. 1 during various stages of fabrication, according to some embodiments. [Figure 4] 3, 4, 5, 6, 7, 8, 9, 10, and 11 represent cross-sectional views of the image sensor of FIG. 1 during various stages of fabrication, according to some embodiments. [Diagram 5] 3, 4, 5, 6, 7, 8, 9, 10, and 11 represent cross-sectional views of the image sensor of FIG. 1 during various stages of fabrication, according to some embodiments. [Figure 6] 3, 4, 5, 6, 7, 8, 9, 10, and 11 represent cross-sectional views of the image sensor of FIG. 1 during various stages of fabrication, according to some embodiments. [Figure 7] 3, 4, 5, 6, 7, 8, 9, 10, and 11 represent cross-sectional views of the image sensor of FIG. 1 during various stages of fabrication, according to some embodiments. [Figure 8] 3, 4, 5, 6, 7, 8, 9, 10, and 11 represent cross-sectional views of the image sensor of FIG. 1 during various stages of fabrication, according to some embodiments. [Figure 9] 3, 4, 5, 6, 7, 8, 9, 10, and 11 represent cross-sectional views of the image sensor of FIG. 1 during various stages of fabrication, according to some embodiments. [Figure 10]3, 4, 5, 6, 7, 8, 9, 10, and 11 represent cross-sectional views of the image sensor of FIG. 1 during various stages of fabrication, according to some embodiments. [Figure 11] 3, 4, 5, 6, 7, 8, 9, 10, and 11 represent cross-sectional views of the image sensor of FIG. 1 during various stages of fabrication, according to some embodiments. [Figure 12] FIG. 12 is a top view of an example image sensor array of the image sensor of FIG. 1 according to some embodiments. [Figure 13] FIG. 13 is a flow diagram of an exemplary method for manufacturing an image sensor, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The following embodiments provide many different embodiments or examples for implementing different features of the present disclosure. To simplify the present disclosure, specific examples of elements and arrangements are described below. Of course, these are illustrative and not intended to be limiting. For example, a configuration of a first feature above or on a second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and may also be an embodiment in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat symbols in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate a relationship between the various embodiments and / or configurations referred to.

[0009] Additionally, spatially relative terms such as "below," "lower," "upper," "top," "bottom," and the like may be used to facilitate the description to explain the relationship of one element or feature depicted in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0010] A CMOS image sensor is a pixelated metal oxide semiconductor. A CMOS image sensor typically includes an array of photosensitive pixels (also called pixel units), each of which includes several transistors (e.g., switching transistors and reset transistors), a capacitor, and a photosensitive device (e.g., a photodiode). A CMOS image sensor utilizes a photosensitive CMOS circuit to convert photons into electrons. The photosensitive CMOS circuit typically includes a photodiode formed on a silicon substrate. When the photodiode is exposed to light, a charge is induced in the photodiode. Each pixel generates electrons proportional to the amount of light that falls on the pixel when light is incident on the pixel from a subject scene. The electrons are further converted into a voltage signal at the pixel, which is further converted into a digital signal through several logic circuits (e.g., an analog-to-digital converter (ADC) circuit, a digital-to-analog converter (DAC) circuit, etc.). A number of other logic circuits (e.g., a static random access memory (SRAM) circuit, a controller, a buffer storage, etc.) receive the digital signals and process them to display an image of the subject scene.

[0011] CMOS image sensors may include multiple additional layers, such as dielectric layers and interconnect metal layers formed on top of the substrate, which are used to couple the photodiodes to the surrounding circuitry. The side of a CMOS image sensor that has the additional layers is commonly called the front side, and the side that has the substrate is called the back side. Depending on the difference in the optical path, CMOS image sensors are further divided into two main categories: front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors.

[0012] In an FSI image sensor, light from a subject scene enters the front side of the CMOS image sensor, passes through dielectric layers and interconnect layers, and finally falls on the photodiode. Additional layers (e.g., non-transparent reflective metal layers) in the light path limit the amount of light absorbed by the photodiode, lowering the quantum efficiency. Conversely, in a BSI image sensor, there is no obstruction from additional layers (e.g., metal layers). Light enters the back side of the CMOS image sensor. As a result, light can hit the photodiode through a direct path. Such a direct path helps improve photonic performance by increasing the number of photons converted to electrons (i.e., higher efficiency in photon capture).

[0013] To further improve the photonic performance of BSI image sensors, the photodiodes of the pixel units are typically formed over a relatively large area, which forces the corresponding transistors of the pixel units to be formed over a relatively small area. Although the photonic performance may be improved, the overall performance of the image sensor may be degraded by the compromised electrical performance (due to the area reduction for forming the transistors of the pixel units). This leads to proposals to separate the photodiodes and the transistors of the pixel units. For example, in some existing image sensors, the photodiodes, the transistors of the pixel units, and the logic circuits are formed on three different chips, which are then integrated (e.g., vertically) with each other.

[0014] As technology nodes continue to advance, it may be desirable to realize (e.g., integrate) more functionality on-chip with logic circuits by forming more advanced transistors on-chip. The present disclosure provides various embodiments of vertically integrated back-side illuminated (BSI) image sensors that allow further improvements over existing BSI image sensors. For example, a BSI image sensor described herein includes (i) a first chip including several photosensitive elements (e.g., respective photodiodes and corresponding switching transistors of pixel units) formed as a first array, (ii) a second chip including several corresponding other transistors (also called pixel transistors) of pixel units formed as a second array and several first logic circuits, and (iii) a third chip including several second logic circuits. The first and second arrays may have a pixel-to-pixel mapping, and the first logic circuit may be formed around the second array to directly input and / or output electrical signals generated from the second array. Thus, the first logic circuit and the second logic circuit formed on different chips can be fabricated and operated independently. For example, all of the second logic circuits can be fabricated in a more advanced technology node compared to the technology node for forming the first logic circuits, which can significantly reduce the amount of available area on the third chip. Furthermore, the second logic circuits (mainly configured to process data generated from the first array and / or the second array) can operate at a lower voltage compared to the voltage at which the first logic circuits (mainly configured to input / output data generated from the second array) operate. In this manner, various performances (e.g., power consumption, electrical / photon speed, etc.) of the disclosed image sensor can be correspondingly improved.

[0015] The present disclosure is described with respect to embodiments in a particular context: a vertically integrated back-illuminated image sensor, although embodiments of the present disclosure may also be applied to a variety of image sensors and semiconductor devices. Various embodiments are described in detail hereinafter with reference to the accompanying drawings.

[0016] 1, an exemplary schematic diagram of an image sensor 100 including three chips vertically integrated with each other is illustrated, according to various embodiments. For example, the image sensor 100 may be a back-side illuminated (BSI) image sensor with the chips stacked on top of each other. However, the stacking scheme used by the BSI image sensor 100 may also be applied to a front-side illuminated (FSI) image sensor 100 while remaining within the scope of the present disclosure.

[0017] As shown, a first chip 110 including an array 112 (having several photosensitive elements, e.g., photodiodes) is bonded to a second chip 120 including an array 122 (having several pixel transistors) along with several input / output circuits / components 124, e.g., through metal-to-metal or hybrid bonding including both metal-to-metal and oxide-to-oxide bonding. In some embodiments, each photodiode of the array 112 together with a corresponding group of pixel transistors of the array 122 may be referred to as a pixel unit. The second chip 120 is further bonded to a third chip 130, which may be an application specific integrated circuit (ASIC) chip. The third chip 130 may include image signal processing (ISP) circuits 132, 134, 136, and may or may not further include other circuits related to BSI applications. The bonding of the chips 110, 120, 130 may be at the wafer level. In such wafer level bonding, the wafers 115, 125, 135 on which the chips 110, 120, 130 are formed, respectively, are bonded together and then cut into dies or chips as shown. Alternatively, bonding may be performed at the chip level.

[0018] When image sensor 100 is implemented as a BSI image sensor, light may be received from its backside. For example, array 112 may receive emitted light 150 through the backside of chip 110 / wafer 115. When image sensor 100 is implemented as an FSI image sensor, light may be received from its frontside. For example, array 112 may receive emitted light 150 through the frontside of chip 130 / wafer 135.

[0019] 2 illustrates an exemplary circuit diagram of one of the disclosed pixel units, such as pixel unit 200, according to various embodiments. As illustrated, pixel unit 200 includes a first portion 210 formed in or on chip 110 and a second portion 220 formed in or on chip 120. In some embodiments, first portion 210 includes a photodiode 230, a transfer gate (switching) transistor 232, and a floating diffusion capacitor 234, and second portion 220 includes a reset transistor 236, a source follower 238, and a row selector 240, also collectively referred to as pixel transistors.

[0020] It should be understood that the circuit diagram of pixel unit 200 shown in Figure 2 is merely exemplary, and thus each pixel unit may omit or include any of various other components while remaining within the scope of the present disclosure. For example, although pixel unit 200 is configured in a four-transistor structure, it can be configured in various other structures, including, but not limited to, a three-transistor structure, a five-transistor structure, etc.

[0021] Specifically, the photodiode 230 has an anode coupled to electrical ground and a cathode coupled to a source of a transfer gate transistor 232 having a gate coupled to a signal line. The signal line is labeled "TRANSFER" in FIG. 2 and is also referred to as a transfer line. The transfer line of the pixel unit 200 may be connected to the ISP circuits 132-136 (FIG. 1) formed on the chip 130 and / or may be connected to the input / output circuit 124 formed on the chip 120 to receive control signals. The drain of the transfer gate transistor 232 may be coupled to the drain of the reset transistor 236 and to the gate of the source follower 238. The reset transistor 236 has a gate coupled to a reset line RST, which may be connected to the ISP circuits 132-136 (FIG. 1) formed on the chip 130 to receive further control signals. The source of the reset transistor 236 may be coupled to a pixel power supply voltage VDD1 higher than 2 volts (V), such as 2.5V, 2.8V, 3.3V, etc., according to various embodiments. The floating diffusion capacitor 234 may be coupled between the source / drain of the transfer gate transistor 232 and the gate of the source follower 238. The reset transistor 236 is used to preset the voltage at the floating diffusion capacitor 234 to VDD1. The drain of the source follower 238 is coupled to the same power supply voltage VDD1. The source of the source follower 238 is coupled to the row selector 240. The source follower 238 can provide a high impedance output for the pixel unit 200. The row selector 240 may function as a selection transistor for each pixel unit 200, and the gate of the row selector 240 is coupled to a selection line SEL formed as one of several rows of the array 122. The select line / row may be electrically coupled to (e.g., controlled by) input / output circuitry 124 (FIG. 1) formed on chip 120. A drain of row selector 240 is coupled to an output line formed as one of several columns of array 122. The output line / column may be electrically coupled to input / output circuitry 124 formed on chip 120 for outputting a signal generated by photodiode 230.

[0022] In operation of the pixel unit 200, when light is received by the photodiode 230, the photodiode 230 generates a charge, the amount of charge being related to the intensity or brightness of the incident light. The charge is transferred by enabling the transfer gate transistor 232 through a transfer signal applied to the gate of the transfer gate transistor 232. The charge may be stored in the floating diffusion capacitor 234. The charge enables the source follower 238, thereby allowing the charge generated by the photodiode 230 to pass through the source follower 238 to the row selector 240. When sampling is desired, the select line SEL is enabled or the corresponding row is asserted (e.g., by one or more of the input / output circuits 124), allowing the charge to be conducted through the row selector 240 and the corresponding column (e.g., asserted by one or more of the input / output circuits 124) to the data processing circuits, such as the ISP circuits 132-136, coupled to the output of the row selector 240.

[0023] Referring to FIG. 1, the array 112 of the chip 110 and the array 122 of the chip 120 may be bonded together at the pixel level. Each photodiode (e.g., 230) of the array 112 has a one-to-one physical and electrical correspondence with a respective group of pixel transistors (e.g., 236-240) of the array 122. In other words, pixel units formed from components of different arrays 112 and 122, respectively, can uniformly form an image sensor array, as shown in FIG. 12. For example, when the chips 120 and 110 are bonded together, directly below / above each group of pixel transistors of the chip 120 is a corresponding one of the photodiodes of the chip 110. Such corresponding pairs of pixel transistors and photodiodes can be electrically coupled to each other through one or more connector structures according to the present embodiment. Furthermore, at the periphery of the array 122, the chip 120 includes several input / output transistors (collectively functioning as input / output circuitry 124) electrically connected to the pixel transistors of the array 122. The pixel transistors of array 122 and the input / output transistors of circuitry 124 are also referred to as "in-array transistors 122" and "out-array transistors 124," respectively.

[0024] Instead of being formed at the pixel level (as are the in-array transistors 122), the out-of-array transistors 124 may be formed at the column level or row level. For example, the in-array transistors 122 may be formed as a number of columns and a number of rows that cross each other. Corresponding to (e.g., operatively coupled to) each column or group of columns of the in-array transistors 122 is a respective one or group of the out-array transistors 124. In this manner, each one or each group of the out-array transistors 124 can control (e.g., access, output, etc.) a corresponding column of the in-array transistors 122. In another example, corresponding to (e.g., operatively coupled to) each row or group of rows of the in-array transistors 122 is a respective one or group of the out-array transistors 124. In this manner, each one or each group of the out-array transistors 124 can control (e.g., access, output, etc.) a corresponding row of the in-array transistors 122. In various embodiments, the off-array transistors 124 can collectively function as at least one of the following circuits: electrostatic discharge (ESD) protection circuitry, column control circuitry (column decoder), row control circuitry (row decoder), or level shifting circuitry.

[0025] 3-11 depict cross-sectional views of various intermediate stages for forming an image sensor 100, according to some example embodiments. It should be understood that the image sensor 100 depicted in FIGS. 3-11 is simplified for illustrative purposes, and thus the image sensor device 100 can include various other components while remaining within the scope of the present disclosure.

[0026] FIG. 3 illustrates an exemplary cross-sectional view of a chip 110, which may be part of a wafer 115 including multiple chips 110, according to various embodiments. The chip 110 includes a semiconductor substrate 302, which may be a semiconductor substrate formed from a crystalline silicon substrate or other semiconductor material. Throughout this description, the surface 302A is referred to as the front surface of the semiconductor substrate 302, and the surface 302B is referred to as the back surface of the semiconductor substrate 302. An image sensor 304 is formed on the front surface 302A of the semiconductor substrate 302. The image sensor 304 is configured to convert optical signals (photons) into electrical signals, and may be a photosensitive metal oxide semiconductor (MOS) transistor or a photosensitive diode. Thus, throughout this description, the image sensors 304 are interchangeably referred to as photodiodes 230, although they may be other types of image sensors. In some embodiments, each photodiode 230 extends from the surface 302A into the semiconductor substrate 302, collectively forming an image sensor array depicted in the top view shown in FIG. 12.

[0027] In some embodiments, each photodiode 230 is electrically coupled to a first source / drain region of a corresponding transfer gate transistor 232 that includes a gate 306. The first source / drain region of the transfer gate transistor 232 may be shared by the connecting photodiodes 230. A floating diffusion capacitor 234 is formed in the substrate 302, for example, through implantation into the substrate to form a pn junction that serves as the floating diffusion capacitor 234. The floating diffusion capacitor 234 may be formed in a second source / drain region of the transfer gate transistor 232, such that one of the capacitor plates of the floating diffusion capacitor 234 is electrically coupled to the second source / drain region of the transfer gate transistor 232. The photodiode 230, the transfer gate transistor 232, and the floating diffusion capacitor 234 form the portion 210 (as shown in FIG. 2 ) of each pixel unit 200.

[0028] In some embodiments, chip 110 and wafer 115 (on which it is formed) do not include or are substantially free of additional logic devices (e.g., logic transistors) other than transfer gate transistor 232. Furthermore, chip 110 and wafer 115 do not include the peripheral circuitry of an image sensor chip, including image signal processor (ISP) circuitry, which may include, for example, an analog-to-digital converter (ADC), correlated double sampling (CDS) circuitry, row decoders, column decoders, etc.

[0029] Referring to FIG. 3, several front interconnect structures 310 are formed above the semiconductor substrate 302 and are used to electrically interconnect devices in the chip 110. The front interconnect structures 310 include one or more dielectric layers incorporating a corresponding number of metal lines 314 and vias 316. Throughout this description, the metal lines 314 within the same dielectric layer are collectively referred to as metal layers or metallization layers. The interconnect structures 310 may include multiple metal layers. The dielectric layers 312 include a low-k dielectric layer and possibly a passivation layer above the low-k dielectric layer. The low-k dielectric layer has a low dielectric constant value, e.g., less than 3.0. The passivation layer may be formed of a non-low-k dielectric material having a dielectric constant value greater than 3.9.

[0030] On the front side of the substrate 302 are metal pads 318 that may have a high degree of planar flatness achieved by a planarization process such as chemical mechanical polishing (CMP). The top surface of the metal pads 318 is substantially level with the top surface of the uppermost one of the dielectric layers 312 and is substantially free of dishing or erosion. The metal pads 318 may include copper, aluminum, and possibly other metals. In some embodiments, each gate 306 of the transfer gate transistors 232 may be electrically coupled to one of the metal pads 318. Thus, the gates 306 may receive a transfer signal through the metal pads 318, for example, from the ISP circuits 132-136 (FIG. 1) in the chip 130. Each floating diffusion capacitor 234 is electrically coupled to one of the metal pads 318, and charge stored in the diffusion capacitors 234 may be discharged through the metal pads 318 that are respectively coupled to the gates 306 to one or more pixel transistors, for example, the source follower 238 (FIG. 2). Thus, each portion 210 (FIG. 2) may include at least two metal pads 318. It should be understood that the number of metal pads 318 in each portion 210 is related to the configuration of the corresponding pixel unit 200. Thus, each portion 210 may include a different number of metal pads 318, e.g., 3, 4, 5, etc., while remaining within the scope of the present disclosure.

[0031] FIG. 4 illustrates an exemplary cross-sectional view of the chip 120 in a wafer 125 including multiple identical device chips identical to the chip 120 according to various embodiments. The chip 120 includes a semiconductor substrate 402, which may be a semiconductor substrate formed from a crystalline silicon substrate or other semiconductor material. The substrate 402 is a silicon substrate in some embodiments. Alternatively, the substrate 402 is formed from other semiconductor materials, such as silicon germanium, silicon carbon, III-V compound semiconductor materials, etc. The chip 120 further includes several pixel transistors formed on the front side of the substrate 402, which form the portion 220 (FIG. 2) of the pixel unit 200. As shown in FIG. 4, the chip 120 includes multiple transistors, including a row selector 240, a source follower 238, and a reset transistor 236. The row selector 240, the source follower 238, and the reset transistor 236 may form portions 220 of a plurality of pixel units 200, with each portion 220 including one of the row selectors 240, one of the source followers 238, and one of the reset transistors 236.

[0032] In various embodiments, the chip 120 further includes several input / output transistors 424 that collectively form the input / output circuit 124. As mentioned above, the pixel transistors 236-240 may be referred to as in-array transistors, the input / output transistors 424 may be referred to as out-of-array transistors, and the pixel transistors 236-240 (forming the portion 220 of the pixel unit 200) may have a one-to-one correspondence with the photodiode 230, the transfer gate transistor 232, and the capacitor 234 (forming the portion 210 of the pixel unit 200). In this manner, the input / output transistors 424 may not form an array. Instead, the out-of-array transistors 424 may be formed along an edge or side of the array formed by the in-array transistors 236-240.

[0033] A number of interconnect structures 410 are formed above the portion 220 and configured to electrically couple the portion 220 to the input / output circuitry 124 in the chip 120 and / or the ISP circuitry 132-136 of the chip 130 (FIG. 1). The interconnect structures 410 include multiple metal layers in multiple dielectric layers 412. Metal lines 414 and vias 416 are provided in the dielectric layers 412. For example, a gate of the row selector 240 can be electrically coupled to a source or drain of one of the input / output transistors 424 through one or more of the metal lines 414 and vias 416, and a source of the row selector 240 can be electrically coupled to a source or drain of another of the input / output transistors 424 through one or more of the metal lines 414 and vias 416. In some embodiments, the dielectric layer 412 includes a low-k dielectric layer. The low-k dielectric layer has a low dielectric constant value of less than about 3.0. The dielectric layer 412 may further include a passivation layer formed of a non-low-k dielectric material having a dielectric constant value greater than 3.9. In some embodiments, the passivation layer includes a silicon oxide layer, an undoped silicate glass layer, and / or the like.

[0034] The metal pads 418 are formed on the surface of the wafer 125, and the metal pads 418 may have a high surface planarity achieved by CMP, with substantially low dishing or erosion effect on the top surface of the top dielectric layer 412. The metal pads 418 may also include copper, aluminum, and / or other metals. In some embodiments, the gate of each source follower 238 may be electrically coupled to one of the metal pads 418. Thus, the source follower 238 may be enabled by the floating diffusion capacitor 234 in the chip 110 to allow charge generated by the photodiode 230, also on the chip 110, to pass through the source follower 238 to the row selector 240. Thus, each portion 220 is electrically connected to at least one of the metal pads 418.

[0035] Please refer to FIG. 5, which illustrates an exemplary cross-sectional view of an image sensor 100 in which the chip 110 (wafer 115) and the chip 120 (wafer 125) are bonded together through bonding the metal pads 318 to corresponding metal pads 418, according to various embodiments. The bonding may be a bonding without applying extra pressure and may be performed at room temperature (e.g., around 21° C.). When the metal pads 318 are bonded to the metal pads 418, the top oxide layer (not shown) of the chip 110 is bonded to the top oxide layer (not shown) of the chip 120 through an oxide-to-oxide bond. As a result of the bonding, the photodiode 230, the transfer gate transistor 232, the floating diffusion capacitor 234, the row selector 240, the source follower 238, and the reset transistor 236 are combined to form several pixel units 200. In some embodiments, the pixel units 200 can form an image sensor array corresponding to the array of photodiodes 230, as shown in FIG. 12. Accordingly, the corresponding metal pads 318 and 418 may also be arranged in an array. As further shown in FIG. 12, input / output transistors 424 (collectively functioning as the input / output circuit 124) may be arranged around such an image sensor array of the pixel unit 200.

[0036] In the illustrated example of FIG. 5, the chips 110 and 120 are bonded together in a face-to-face (F2F) manner, i.e., the front surface of the chip 110 faces the front surface of the chip 120. When bonded together in such a F2F manner, metal pads of each of the chips 110 and 120 may be utilized to electrically couple the respective components (e.g., couple the first portion 210 of each pixel unit 200 to its second portion 220). However, it should be understood that the chips 110 and 120 may be bonded together in other manners while remaining within the scope of the present disclosure. For example, the chips 110 and 120 may be bonded together in a front-to-back (F2B) manner, i.e., the front surface of the chip 110 faces the back surface of the chip 120.

[0037] 6 illustrates an exemplary cross-sectional view of an image sensor 100 in which the chips 110 and 120 are bonded together in a front-to-back (F2B) manner, according to various embodiments. As illustrated, the front side of the substrate 302 on which the chip 110 is formed faces the back side of the substrate 402 on which the chip 120 is formed. Although not illustrated, an oxide layer may be optionally formed between the chips 110 and 120. To electrically couple the chip 110 to the chip 120, the chip 120 may further include several through silicon / substrate via (TSV) structures 602 extending through the substrate 402. Specifically, each TSV structure 602 may be in electrical contact with a corresponding one of the metal pads 318 of the chip 110. For example, the floating diffusion capacitor 234 (of chip 110) can be electrically coupled to the reset transistor 236 and the source follower 238 (of chip 120) through one or more interconnect structures (e.g., 310 in FIG. 3) of the chip 110 at at least one of the metal pads 318 and at least one of the TSV structures 602, thereby forming a corresponding one of the pixel units 200 (as shown in FIG. 6).

[0038] For purposes of clarity, the following manufacturing steps for forming image sensor 100 are based on chips 110 and 120 bonded together in a F2F fashion. It should be understood that these manufacturing steps can also be used to form a complete image sensor 100 with chips 110 and 120 bonded together in a F2B fashion while remaining within the scope of this disclosure. For example, another chip (e.g., chip 130) can be connected to chip 120 using metal pads 418, either on the chip's metal pads (in a F2F fashion) or on the TSV structures 602 (in a F2B fashion).

[0039] Please refer to FIG. 7, which illustrates an example cross-sectional view of the image sensor 100 with an oxide layer 702 formed on the backside of the substrate 402, according to various embodiments. For the process of forming the TSV structure 602 as shown in FIG. 8, a process of thinning the substrate 402 to an optimized thickness may be performed before the formation of the oxide layer 702. In some embodiments, the formation of the oxide layer 702 is formed through oxidation of the substrate 402. In an alternative embodiment, the oxide layer 702 is deposited on the backside of the substrate 402. The oxide layer 702 may include, for example, silicon oxide.

[0040] 8, an exemplary cross-sectional view of the image sensor 100 is shown with several TSV structures 802 formed thereon, according to various embodiments. The formation process may include etching the oxide layer 702, the substrate 402, and one or more other dielectric layers formed in the chip 120 to form the TSV openings until the metal lines (or metal pads) 414A are exposed. The metal pads 414A may be provided in the bottom metal layer closest to the devices 236-240, or may be provided in a metal layer further away from the devices 236-240 than the bottom metal layer. The TSV openings are then filled with a conductive material, such as a metal or metal alloy, followed by chemical mechanical polishing (CMP) to remove excess portions of the conductive material. As a result of the CMP, the top surface of the TSV structures 802 may be substantially level with the top surface of the oxide layer 702, which allows for bonding of the chip 120 to the chip 130 as shown in FIG. 9. For example, one of the TSV structures 802 (as shown in FIG. 8 ) can electrically couple the gate of the reset transistor 236 to one or more logic circuits of the chip 130. In another example, another of the TSV structures 802 (not shown) can electrically couple the source and gate of the row selector 240 to one or more respective logic circuits of the chip 130.

[0041] Reference is made to FIG. 9, which illustrates an exemplary cross-sectional view of an image sensor 100 in which a wafer 125 (including chips 120) is bonded to a wafer 135 including several chips 130, according to various embodiments. The wafer 135 includes a semiconductor substrate 902 and logic transistors 910 formed adjacent to a front surface of the semiconductor substrate 902. In some embodiments, the logic transistors 910 include one or more ISP circuits (e.g., 132-136 in FIG. 1) used to process image-related signals acquired from the chips 110 and 120. Exemplary ISP circuits include ADC circuits, DAC circuits, CDS circuits, SRAM circuits, controllers, buffer storage, and / or the like. The logic transistors 910 may function as application specific circuits customized for a particular application. Through such design, if the resulting package including the stacked chips 110-130 is redesigned for a different application, the design of the chips 110 and 120 does not need to be changed and the chip 130 may be redesigned.

[0042] In some embodiments, the devices (e.g., 230, 232, 234) of the chip 110 and the devices (e.g., 236, 238, 240, 424) of the chip 120 may be operated at a first power supply voltage (e.g., VDD1), and the devices (e.g., 910) of the chip 130 may be operated at a second power supply voltage (e.g., VDD2) different from the first power supply voltage. By way of non-limiting example, VDD1 may be greater than 2V (e.g., 2.5V, 2.8V, 3.3V, etc.), and VDD2 may be less than 2V (e.g., 1.8V). Thus, in some embodiments, the devices (e.g., 230, 232, 234) of the chip 110 and the devices (e.g., 236, 238, 240, 424) of the chip 120 may be formed with a relatively thin gate dielectric, and the devices (e.g., 910) of the chip 130 may be formed with a relatively thick gate dielectric.

[0043] Further, the devices formed on each wafer (e.g., devices 230-234 on wafer 115, devices 236-238 and 424 on wafer 125, and device 910 on wafer 135) may be fabricated at different technology nodes. For example, devices 230-234, 236-238, and 424 on wafers 115 and 125 may be fabricated at a relatively mature (e.g., larger) technology node, and device 910 on wafer 135 may be fabricated at a relatively advanced (e.g., smaller) technology node. In another example, devices 230-234 on wafer 115 may be fabricated at a relatively mature (e.g., larger) technology node, and devices 236-238, 424, and 910 on wafers 125 and 135 may be fabricated at a relatively advanced (e.g., smaller) technology node. By way of non-limiting example, a larger technology node may also be referred to as a long channel length or long gate length. Similarly, the smaller technology nodes may also be referred to as short channel lengths or short gate lengths.

[0044] 10, an exemplary cross-sectional view of the image sensor 100 is shown in which backgrinding is performed to thin the semiconductor substrate 302, reducing the thickness of the substrate 302 to a desired value, according to various embodiments. With the semiconductor substrate 302 having a thin thickness, light can penetrate into the semiconductor substrate 302 from the backside 302B to reach the image sensor 230. In the thinning process, the wafers 125 and 135 may collectively act as a carrier to provide mechanical support to the wafer 115, preventing the wafer 115 from being damaged even though the wafer 115 has a relatively thin thickness during and after the thinning process. Therefore, no additional carrier may be required during backgrinding.

[0045] 10 further illustrates etching of the substrate 302 and forming electrical connectors 1002. The electrical connectors 1002 may be bond pads, such as wire bond pads used to form wire bonds, through which each chip 110, 120, 130 may be electrically coupled to an external circuit component (not shown).

[0046] As shown in FIG. 10, the electrical connector 1002 may be formed in the same horizontal plane as the substrate 302. In some exemplary fabrication processes, the substrate 302 is etched first. For example, the edges of the substrate 302 are etched, and the central portion of the substrate 302 where the image sensor 230 is formed is not etched. As a result, some of the metal lines 314 and vias 316 may extend beyond the edge 302C of the substrate 302, as shown. In some embodiments, after partial substrate 302 removal, the underlying dielectric layer is exposed. In some embodiments, the exposed dielectric layer is an inter-layer dielectric (ILD), a contact etch stop layer (CESL), or the like. Next, a relatively deep via 316 is formed in the dielectric layer in the chip 110 and electrically coupled to one or more of the metal lines 314. The fabrication process includes etching the dielectric layer to form an opening and filling the resulting opening with a conductive material to form the deep via 316. Electrical connectors 1002 are then formed, for example, by a deposition step followed by a patterning step.

[0047] 11, an exemplary cross-sectional view of an image sensor 100 with a top layer 1102 (also called a buffer layer) formed on the backside of a substrate 302 according to various embodiments is shown. In some exemplary embodiments, the top layer 1102 includes one or more of a bottom anti-reflective coating (BARC), a silicon oxide layer, and a silicon nitride layer. In subsequent process steps, additional components such as a metal grid (not shown), a color filter 1104, a microlens 1106, and the like are further formed on the backside of the wafer 115. The resulting wafers 115, 125, and 135 are then cut into dies, with each die including one chip 110, one chip 120, and one chip 130.

[0048] According to various embodiments of the present disclosure, by moving at least some or possibly all of the row selector 240, the source follower 238, and the reset transistor 236 out of the chip 110, the fill factor of the pixel unit 200 is improved, which may be calculated by dividing the chip area occupied by the photodiode 230 by the total chip area of ​​each pixel unit 200. The improved fill factor results in an increase in the quantum efficiency of the pixel. Furthermore, by moving some logic circuits, such as the input / output transistors 424 (collectively functioning as the input / output circuit 124) from the chip 130 to the chip 120, the formation of some high-performance logic circuits (e.g., ADC circuits, DAC circuits, etc.) can be decoupled from the formation of these input / output circuits. In this way, the high-performance logic circuits and the input / output circuits can be formed in independent technology nodes, which can significantly reduce manufacturing costs and minimize the adverse effects of one on the other.

[0049] FIG. 12 is a top view of an exemplary image sensor array 1200 including several pixel units (e.g., 200) according to various embodiments. As shown, when at least chip 110 (wafer 115) and chip 120 (wafer 125) are bonded together, image sensor array 1200 including an array of several (e.g., 16) pixel units 200 is formed. Although 16 pixel units are shown in image sensor array 1200, it should be understood that image sensor array 1200 can include any number of pixel units while remaining within the scope of this disclosure. Each pixel unit 200 includes at least a photodiode (e.g., 230), a floating diffusion capacitor (e.g., 234), and several transistors (e.g., 232-240). Image sensor array 1200 may be formed by integration of array 112 and array 122 (FIG. 1) according to some implementations. Additionally, according to various embodiments, a number of input / output transistors (eg, 424) are formed surrounding the image sensor array 1200 and collectively function as the input / output circuitry 124 (FIG. 1).

[0050] FIG. 13 illustrates a flow diagram of an exemplary method 1300 for forming an image sensor having several vertically integrated chips according to various embodiments of the present disclosure. It should be noted that the method 1300 is merely exemplary and is not intended to limit the present disclosure. It should therefore be understood that the order of operations of the method 1300 can be changed, additional operations may be provided before, during, or after the method 1300 of FIG. 13, and some other operations may only be briefly described here. Such an image sensor manufactured by the method 1300 may include one or more components described above with respect to FIGS. 1-12. Accordingly, the operations of the method 1300 are also described in conjunction with FIGS. 1-12 as examples.

[0051] Method 1300 begins with operation 1302 of forming a first chip including several photodiodes formed as a first array, according to some embodiments. For example, several first chips (e.g., 110) can be formed on a first wafer (e.g., 115), each including a first array (e.g., 112) including several photodiodes (e.g., 230). Further, corresponding to each photodiode in the first array, a transfer gate transistor (e.g., 232) and a floating diffusion capacitor (e.g., 234) are formed. In other words, each first chip on the first wafer includes at least a first array made up of several photodiodes and several corresponding transfer gate transistors and floating diffusion capacitors.

[0052] The method 1300 continues with operation 1304 of forming a second chip including some pixel transistors formed as a second array and some input / output transistors formed outside the second array, according to some embodiments. For example, on a second wafer (e.g., 125), some second chips (e.g., 120) can be formed, each including a second array (e.g., 122) including some pixel transistors (e.g., 236-240). Additionally, around the periphery of the second array, some input / output transistors (e.g., 424) can be formed. The input / output transistors (also called off-array transistors, as opposed to the in-array transistors of the pixel transistors) can collectively function as one or more input / output circuits (e.g., electrostatic discharge (ESD) protection circuits, column control circuits (column decoders), row control circuits (row decoders), level shifting circuits) of the image sensor in some implementations.

[0053] The method 1300 continues with operation 1306 of bonding the first chip to the second chip, according to some embodiments. For example, the first chip 110 can be bonded to the second chip through a metal-to-metal bond or a hybrid bond including both metal-to-metal and oxide-to-oxide bonds. However, it should be understood that the first and second chips can be bonded to each other in any of a variety of other bonding techniques. In some embodiments, the first chip can be bonded to the second chip at the pixel level. Specifically, each element of the first array on the first chip (e.g., a photodiode and its corresponding transfer gate transistor and floating diffusion capacitor) can physically and electrically correspond to a corresponding element of the second array on the second chip (e.g., some pixel transistors). Furthermore, the first chip can be bonded to the second chip in a F2F manner (where the front side of the first chip faces the front side of the second chip) or a F2B manner (where the front side of the first chip faces the back side of the second chip).

[0054] Method 1300 continues with operation 1308 of forming a third chip including several transistors that collectively function as several image signal processing (ISP) circuits, according to some embodiments. For example, on a third wafer (e.g., 135), several third chips (e.g., 130) can be formed, each including several ISP circuits (e.g., 132-136). Exemplary ISP circuits include, but are not limited to, ADC circuits, DAC circuits, CDS circuits, SRAM circuits, controllers, buffer storage, etc.

[0055] Method 1300 continues with operation 1310 of bonding a third chip to the already bonded first and second chips, according to some embodiments. For example, following bonding of the first and second chips, the third chip can be bonded to the already bonded first and second chips. The third chip can be bonded to the second chip through a metal-to-metal bond or a hybrid bond including both metal-to-metal and oxide-to-oxide bonds. However, it should be understood that the third chip and the second chip can be bonded to each other in any of a variety of other bonding techniques. In some embodiments, the first to third chips can be bonded to each other by bonding the first wafer to the second wafer and then to the third wafer, followed by sawing the first to third wafers.

[0056] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a first chip including a plurality of photosensitive devices, the plurality of photosensitive devices being formed as a first array. The semiconductor device includes a second chip bonded to the first chip, the second chip including a plurality of groups of pixel transistors and a plurality of input / output transistors, the plurality of groups of pixel transistors being formed as a second array, and the plurality of input / output circuits being formed outside the second array. The semiconductor device includes a third chip bonded to the second chip, the third chip including a plurality of logic circuits.

[0057] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a first chip, a second chip, and a third chip. The first chip includes a first semiconductor substrate, a plurality of photosensitive devices formed on the first semiconductor substrate, a plurality of transfer gate transistors formed on the first semiconductor substrate, and a plurality of capacitors formed on the first semiconductor substrate. The second chip includes a second semiconductor substrate, a plurality of reset transistors formed on the second semiconductor substrate, a plurality of source followers formed on the second semiconductor substrate, a plurality of row selectors formed on the second semiconductor substrate, and a plurality of input / output transistors formed on the second semiconductor substrate. The third chip includes a third semiconductor substrate and a plurality of logic transistors formed on the third semiconductor substrate. The first to third chips are vertically joined to each other.

[0058] In yet another aspect of the present disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes forming a first chip including a plurality of photosensitive devices disposed on a first semiconductor substrate. The method includes forming a second chip including (i) a plurality of reset transistors disposed on a second semiconductor substrate, (ii) a plurality of source followers disposed on the second semiconductor substrate, (iii) a plurality of row selectors disposed on the second semiconductor substrate, and (iv) a plurality of input / output transistors disposed on the second semiconductor substrate. The method includes bonding the second chip to the first chip. The method includes forming a third chip including a plurality of logic transistors disposed on a third semiconductor substrate. The method includes bonding the third chip to the second chip.

[0059] As used herein, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, about 0.5 includes 0.45 and 0.55, about 10 includes 9-11, and about 1000 includes 900-1100.

[0060] The foregoing outlines features of some embodiments so that those skilled in the art may more easily understand aspects of the present disclosure. Those skilled in the art should appreciate that this disclosure may be readily used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various modifications, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure. [Industrial Applicability]

[0061] The present disclosure provides several embodiments of a vertically integrated BSI image sensor that allows further improvements over existing BSI image sensors. [Explanation of symbols]

[0062] 100, 304: Image sensor 110: First chip 115, 125, 135: Wafer 120: 2nd chip 122: Array 124: Input / Output Circuit 130: 3rd chip 132, 134, 136: Image signal processing circuit 150, 160: light 200: Pixel unit 210: Part 1 220:Second part 230: Photodiode 232: Transfer gate transistor 234: Floating diffusion capacitor 236: Reset transistor 238: Source Follower 240: Line selector 302, 902: Semiconductor substrate 302A: Front of 302 302B: Back of 302 302C: 302 Edge 306: Gate 310, 410: interconnect structure 312, 412: dielectric layer 318: Metal pad 402: Substrate 414: Metal wire 414A, 418: Metal pad 416:Beer 424: Input / Output Circuit 602, 802: Silicon / substrate through-via structure 702: Oxide layer 910: Logic transistor 1102:Top layer 1104: Color filter 1106: Microlens 1300: Method 1302, 1304, 1306, 1308, 1310: Operation

Claims

1. a first chip including a plurality of photosensitive devices formed in a first array; a plurality of groups of pixel transistors formed as a second array; a plurality of input / output transistors disposed outside the second array and configured to input or output electrical signals generated by the second array, collectively functioning as an electrostatic discharge (ESD) protection circuit; a second chip joined to the first chip; a third chip coupled to the second chip, the third chip including a plurality of logic transistors configured to process the electrical signal and collectively functioning as an image signal processing (ISP) circuit selected from the group consisting of an analog-to-digital converter (ADC) circuit, a digital-to-analog converter (DAC) circuit, a correlated double sampling (CDS) circuit, and combinations thereof; Including, the plurality of groups of pixel transistors and the plurality of input / output transistors are formed with a first channel length; the plurality of logic transistors are formed with a second channel length; The first channel length is substantially greater than the second channel length.

2. 2. The semiconductor device of claim 1, wherein each of the photosensitive devices of the first array corresponds physically and electrically to a corresponding one of a plurality of groups of the pixel transistors of the second array.

3. The semiconductor device of claim 1 , wherein each said photosensitive device and a corresponding one of a plurality of groups of said pixel transistors at least partially form one of a plurality of pixel units of an image sensor array.

4. the plurality of groups of pixel transistors and the plurality of input / output transistors operate at a first power supply voltage; the plurality of logic transistors operate at a second power supply voltage; 2. The semiconductor device of claim 1, wherein the first power supply voltage is substantially higher than the second power supply voltage.

5. A first semiconductor substrate; a plurality of photosensitive devices formed on the first semiconductor substrate; a plurality of transfer gate transistors formed on the first semiconductor substrate; a plurality of capacitors formed on the first semiconductor substrate; A first chip including: A second semiconductor substrate; a plurality of reset transistors formed on the second semiconductor substrate; a plurality of source followers formed on the second semiconductor substrate; a plurality of row selectors formed on the second semiconductor substrate and configured as a second array with the plurality of reset transistors and the plurality of source followers; a plurality of input / output circuits formed on the second semiconductor substrate and configured to input or output electrical signals generated from the second array, collectively functioning as electrostatic discharge (ESD) protection circuits; A second chip including: A third semiconductor substrate; a third semiconductor substrate formed on the third semiconductor substrate and configured to process the electrical signal; Specifically, analog-to-digital converter (ADC) circuits, digital-to-analog converters (DAC) a correlated double sampling (CDS) circuit, and combinations thereof. A set of multiple logic transistors that function as integrated image signal processing (ISP) circuits. With A third chip including: Including, the first chip to the third chip are bonded vertically to each other; The transistors in the first chip and the second chip are both formed with a first channel length; The transistors in the third chip are all formed with a second channel length; The first channel length is substantially greater than the second channel length.

6. the first chip is bonded to the second chip with a front side of the first semiconductor substrate facing a front side of the second semiconductor substrate; The semiconductor device of claim 5 , wherein the second chip is bonded to the third chip through one or more through-substrate via (TSV) structures.

7. the first chip is bonded to the second chip through one or more through-substrate-via (TSV) structures with a front side of the first semiconductor substrate facing a back side of the second semiconductor substrate; The semiconductor device of claim 6 , wherein the second chip is bonded to the third chip through one or more metal pads.

8. forming a first chip including a plurality of photosensitive devices disposed on a first semiconductor substrate; (i) a plurality of reset transistors disposed on a second semiconductor substrate; (ii) a plurality of source followers disposed on the second semiconductor substrate; (iii) a plurality of row selectors disposed on the second semiconductor substrate and formed as a second array with the plurality of reset transistors and the plurality of source followers; (iv) a plurality of input / output transistors disposed on the second semiconductor substrate and configured to input or output electrical signals generated from the second array, collectively functioning as an electrostatic discharge (ESD) protection circuit; forming a second chip, bonding the second chip to the first chip; forming a third chip including a plurality of logic transistors disposed on a third semiconductor substrate and configured to process the electrical signal, collectively functioning as an image signal processing (ISP) circuit selected from the group consisting of an analog-to-digital converter (ADC) circuit, a digital-to-analog converter (DAC) circuit, a correlated double sampling (CDS) circuit, and combinations thereof; bonding the third chip to the second chip; Including, The transistors in the first chip and the second chip are both formed with a first channel length; The transistors in the third chip are all formed with a second channel length; The method of manufacturing a semiconductor device, wherein the first channel length is substantially greater than the second channel length.

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