High-speed optical sensing device III

Abstract

To detect light by using a photodetector.SOLUTION: A circuit includes: a photodetector including first and second readout terminals; a first readout circuit coupled with the first readout terminal and configured to output first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output second readout voltage; and a common-mode analog-to-digital converter (ADC). The common mode ADC includes: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first and second readout voltages, and to generate common-mode voltage between the first readout voltage and the second readout voltage; and a first output terminal configured to output a first output signal corresponding to a magnitude of current generated by the photodetector.SELECTED DRAWING: Figure 5D

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of, and claims the benefit of, U.S. Provisional Application No. 15 / 908,447, filed February 28, 2018, which is a continuation-in-part of, and claims the benefit of, U.S. Provisional Application No. 62 / 465,139, filed February 28, 2017, U.S. Provisional Application No. 62 / 479,322, filed March 31, 2017, U.S. Provisional Application No. 62 / 504,531, filed May 10, 2017, U.S. Provisional Application No. 62 / 485,003, filed April 13, 2017, U.S. Provisional Application No. 62 / 511,977, filed May 27, 2017, U.S. Provisional Application No. 62 / 534,179, filed July 18, 2017, U.S. Provisional Application No. 62 / 520,363, filed September 21, 2017, and U.S. Provisional Application No. 62 / 535,179, filed May 22, 2017. No. 62 / 561,266, filed Jan. 3, 2018, U.S. Provisional Patent Application No. 62 / 613,054, filed Jan. 15, 2018, and which is a continuation-in-part of, and claims the benefit of, U.S. Provisional Patent Application No. 15 / 338,660, filed Oct. 31, 2016, which claims priority to U.S. Provisional Patent Application No. 62 / 294,436, filed Feb. 12, 2016, U.S. Provisional Patent Application No. 62 / 271,386, filed Dec. 28, 2015, and U.S. Provisional Patent Application No. 62 / 251,691, filed Nov. 6, 2015, all of which are incorporated herein by reference in their entireties.

[0002] This application also claims priority to U.S. Provisional Application No. 62 / 481,131, filed April 4, 2017, U.S. Provisional Application No. 62 / 511,977, filed May 27, 2017, U.S. Provisional Application No. 62 / 542,329, filed August 8, 2017, U.S. Provisional Application No. 62 / 561,256, filed September 21, 2017, U.S. Provisional Application No. 62 / 581,720, filed November 5, 2017, U.S. Provisional Application No. 62 / 581,777, filed November 5, 2017, and U.S. Provisional Application No. 62 / 596,914, filed December 11, 2017, all of which are incorporated by reference in their entireties.

[0003] This specification relates to detecting light using a photodetector. [Background technology]

[0004] The light propagates in free space or the optical medium is coupled to a photodetector that converts the optical signal into an electrical signal for processing. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Publication No. US20170040362A1 [Patent Document 2] U.S. Patent No. 9,786,715 Summary of the Invention [Means for solving the problem]

[0006] According to an innovative aspect of the subject matter described herein, light reflected from the three-dimensional object may be detected by a photodetector of an imaging system. The photodetector converts the detected light into an electric charge. Each photodetector may include two groups of switches that collect the electric charge. The collection of the electric charge by the two groups of switches may vary over time, and thus the imaging system may determine phase information of the sensed light. The imaging system may use the phase information to analyze properties associated with the three-dimensional object, including depth information or material composition. The imaging system may also use the phase information to analyze properties associated with eye tracking, gesture recognition, three-dimensional model scanning / video recording, motion tracking, and / or augmented / virtual reality applications.

[0007] In general, one innovative aspect of the subject matter described herein includes a photodetector having a first readout terminal and a second readout terminal different from the first readout terminal, and a first readout subcircuit having a first MOSFET transistor and a second MOSFET transistor, the first MOSFET transistor having a first gate terminal coupled to a first control voltage source, a first channel terminal, and a second channel terminal coupled to the first readout terminal of the photodetector, the second MOSFET transistor having a second gate terminal coupled to a second control voltage source, a third channel terminal coupled to a power supply voltage node, and a third channel terminal coupled to the first channel terminal. and a second readout sub-circuit comprising a third MOSFET transistor and a fourth MOSFET transistor, the third MOSFET transistor having a third gate terminal coupled to the first control voltage source, a fifth channel terminal, and a sixth channel terminal coupled to the second readout terminal of the photodetector, and the fourth MOSFET transistor having a fourth gate terminal coupled to the second control voltage source, a seventh channel terminal coupled to the supply voltage node, and an eighth channel terminal coupled to the fifth channel terminal. During operation of the circuit, the first control voltage source generates a first control voltage configured to cause a first voltage difference between a supply voltage at the supply voltage node and a first voltage at the first readout terminal and a second voltage difference between a supply voltage at the supply voltage node and a second voltage at the second readout terminal.

[0008] Embodiments of the circuit may include one or more of the following features: For example, during operation of the circuit, the first control voltage is configured to operate the first and third MOSFET transistors in their respective sub-threshold or saturation regions.

[0009] In some embodiments, the first voltage difference and the second voltage difference are greater than or equal to 10% of the power supply voltage.

[0010] In some embodiments, during operation of the circuit, the first controlled voltage source reduces a first dark current collected through the first readout terminal and a second dark current collected through the second readout terminal compared to a comparable circuit without the first and third MOSFET transistors.

[0011] In some embodiments, the photodetector further comprises a p-type doped body portion, the first and second read terminals comprise n-type doped regions, and the first and third MOSFET transistors are n-type MOSFET transistors.

[0012] In some embodiments, the photodetector further comprises an n-type doped body portion, the first and second read terminals comprise p-type doped regions, and the first and third MOSFET transistors are p-type MOSFET transistors.

[0013] In some embodiments, the photodetector is a switched photodetector configured to perform time-of-flight detection.

[0014] In some embodiments, the photodetector further comprises a light absorbing region comprising germanium. The photodetector may further comprise a first control terminal and a second control terminal. The photodetector may comprise a recess, and at least a portion of the light absorbing region may be embedded within the recess.

[0015] Another innovative aspect of the subject matter described herein may be embodied in a method for operating a circuit including a photodetector having a first readout terminal coupled to a first readout subcircuit and a second readout terminal coupled to a second readout subcircuit, the method including: generating, through a first control voltage source coupled to the first readout subcircuit and the second readout subcircuit, a first control voltage configured to operate a first MOSFET transistor of the first readout subcircuit and a third MOSFET transistor of the second readout subcircuit within their respective subthreshold or saturation regions; and performing a photodetector readout step including setting a first output terminal of the first readout subcircuit to a fifth voltage and a second output terminal of the second readout subcircuit to a sixth voltage, wherein controlling the first control voltage source causes a first voltage difference between a power supply voltage of the first and second readout subcircuits and a first voltage of the first readout terminal and a second voltage difference between the power supply voltage and a second voltage of the second readout terminal.

[0016] Another innovative aspect of the subject matter described herein may be embodied in a circuit comprising: a light emitting device having a cathode and an anode coupled to a first power supply voltage node, a MOSFET transistor having a gate terminal coupled to an input signal source, a first channel terminal coupled to the anode of the light emitting device, and a second channel terminal coupled to a second power supply voltage node, a first inductor having a first terminal coupled to a third power supply voltage node or current source and a second terminal coupled to the anode of the light emitting device, a third terminal coupled to the gate terminal of the MOSFET transistor, and a fourth terminal, a second inductor having a second inductance set such that an LC resonant frequency associated with the gate terminal of the MOSFET transistor corresponds to an input frequency of the input signal source.

[0017] Embodiments of the circuit may include one or more of the following features. For example, the circuit may further include a first capacitor arranged between the input signal source and the gate terminal of the MOSFET transistor, the first capacitor having a first terminal coupled to the gate terminal of the MOSFET transistor and a second terminal coupled to the input signal source, and a fourth terminal of the second inductor may be coupled to a MOSFET bias voltage source.

[0018] In some embodiments, during operation of the circuit, the MOSFET bias voltage supply is controlled to adjust the duty cycle of the light output by the light emitting device.

[0019] In some embodiments, the light emitting device comprises a light emitting diode array or a laser diode array.

[0020] Another innovative aspect of the subject matter described herein may be embodied in a circuit comprising: a photodetector having a first readout terminal and a second readout terminal different from the first readout terminal; a first readout circuit coupled to the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled to the second readout terminal and configured to output a second readout voltage; and a common mode analog-to-digital converter (ADC), the common mode analog-to-digital converter (ADC) having a first input terminal coupled to a first voltage source and a second input terminal coupled to a common mode generator, the second input terminal configured to receive the first readout voltage and the second readout voltage and generate a common mode voltage between the first readout voltage and the second readout voltage; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

[0021] Embodiments of the circuit may include one or more of the following features: For example, the circuit may further comprise a differential mode ADC, comprising a third input terminal coupled to the first readout circuit and configured to receive the first readout voltage, a fourth input terminal coupled to the second readout circuit and configured to receive the second readout voltage, and a second output terminal configured to output a second output signal corresponding to the time-of-flight information generated by the photodetector, wherein the circuit is operable to simultaneously generate the first output signal and the second output signal.

[0022] In some embodiments, the first readout circuit comprises a first capacitor coupled to the first readout terminal and a first source follower circuit coupled to the first capacitor and configured to generate a first readout voltage, and the second readout circuit comprises a second capacitor coupled to the second readout terminal and a second source follower circuit coupled to the second capacitor and configured to generate a second readout voltage.

[0023] In some embodiments, the first readout circuit comprises a first MOSFET transistor having a first gate terminal coupled to a first control voltage source, a first channel terminal, and a second channel terminal coupled to the first readout terminal of the photodetector, a second MOSFET transistor having a second gate terminal coupled to a second control voltage source, a third channel terminal coupled to a power supply voltage node, and a fourth channel terminal coupled to the first channel terminal, a first capacitor coupled to the first channel terminal of the first MOSFET transistor, and a first source follower circuit coupled to the first capacitor and configured to generate the first readout voltage. The second readout circuit comprises a third MOSFET transistor having a third gate terminal coupled to the first control voltage source, a fifth channel terminal, and a sixth channel terminal coupled to the second readout terminal of the photodetector, a fourth MOSFET transistor having a fourth gate terminal coupled to the second control voltage source, a seventh channel terminal coupled to the power supply voltage node, and an eighth channel terminal coupled to the fifth channel terminal, a second capacitor coupled to the fifth channel terminal of the third MOSFET transistor, and a second source follower circuit coupled to the second capacitor and configured to generate a second readout voltage.

[0024] In some embodiments, the first voltage source comprises a third source follower circuit.

[0025] Another innovative aspect of the subject matter described herein may be embodied in a method for characterizing performance of a time-of-flight detection device comprising a photodetector having a first readout terminal coupled to a first readout circuit and configured to output a first readout voltage and a second readout circuit coupled to a second readout circuit and configured to output a second readout voltage, the method including measuring a dark current of the photodetector by measuring a common mode output signal between the first readout voltage and the second readout voltage in the absence of ambient light and a time-of-flight optical signal, determining that the dark current of the photodetector is greater than a first value, and determining that the time-of-flight detection device does not meet a performance specification based on determining that the dark current of the photodetector is greater than the first value.

[0026] Embodiments of the method may include one or more of the following features. For example, measuring the dark current of the photodetector may include performing, via a 1-bit or multi-bit ADC, one or more measurements of a common-mode output signal between a first readout voltage and a second readout voltage in the absence of ambient light and a time-of-flight optical signal, and determining the dark current based on the one or more measurements of the common-mode output signal.

[0027] In some embodiments, the one or more measurements are a plurality of measurements, each of the plurality of measurements corresponding to a different integration time or a different replica voltage input to a 1-bit ADC or a multi-bit ADC.

[0028] In some embodiments, the method further includes measuring a demodulation contrast of the time-of-flight detection device by measuring a differential mode output signal between the first readout voltage and the second readout voltage when the time-of-flight optical signal is present, determining that the demodulation contrast of the time-of-flight detection device is lower than a second value, and determining that the time-of-flight detection device does not meet a performance specification based on determining that the demodulation contrast of the time-of-flight detection device is lower than the second value.

[0029] Advantageous implementations may include one or more of the following features: Germanium is an efficient absorbing material for near infrared wavelengths, which reduces the problem of slow photocarriers generated at larger substrate depths when inefficient absorbing materials, e.g., silicon, are used. For a photodetector with a p-doped region and a p-doped region processed at two different depths, the photocarrier travel distance is limited by the depth of the absorbing material, not the width of the absorbing material. As a result, if an efficient absorbing material with a short absorption length is used, the distance between the p-doped region and the n-doped region can also be shortened to generate a strong field with a small bias, resulting in an increased operating speed. For such a photodetector, two groups of switches may be inserted and positioned laterally in an interdigitated arrangement, which may collect photocarriers with different optical phases relative to the time-of-flight system. The increased operating speed allows the use of higher modulation frequencies in the time-of-flight system, resulting in greater depth resolution. In a time-of-flight system where the duty cycle of the light pulse is lowered while the peak intensity of the light pulse is increased, the signal-to-noise ratio (and therefore depth accuracy) can be improved while maintaining the same power consumption for a time-of-flight system. This is made possible when the operating speed is increased so that the duty cycle of the light phase can be lowered without distorting the pulse shape. In addition, by using germanium as an absorbing material, light pulses with wavelengths longer than 1 μm can be used. Since longer NIR wavelengths (e.g., 1.31 μm, 1.4 μm, 1.55 μm) are generally recognized as safer for human eyes, light pulses can be output at longer wavelengths and higher intensities, improving the signal-to-noise ratio (and therefore better depth accuracy) while still meeting eye safety requirements.

[0030] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other potential features and advantages will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0031] [Figure 1A] FIG. 1 illustrates an example of a switched photodetector. [Figure 1B] FIG. 1 illustrates an example of a switched photodetector. [Figure 1C] FIG. 1 illustrates an example of a switched photodetector. [Figure 1D] FIG. 1 illustrates an example of a switched photodetector. [Figure 2A] FIG. 1 illustrates an example of a switched photodetector. [Figure 2B] FIG. 1 illustrates an example of a switched photodetector. [Figure 2C] FIG. 1 illustrates an example of a switched photodetector. [Figure 2D] FIG. 1 illustrates an example of a switched photodetector. [Figure 3A] FIG. 1 illustrates an example of a switched photodetector. [Figure 3B] FIG. 1 illustrates an example of a switched photodetector. [Figure 3C] FIG. 1 illustrates an example of a switched photodetector. [Figure 3D] FIG. 1 illustrates an example of a switched photodetector. [Figure 4A] FIG. 1 illustrates an example of a switched photodetector. [Figure 4B] FIG. 1 illustrates an example of a switched photodetector. [Figure 4C] FIG. 1 illustrates an example of a switched photodetector. [Figure 4D] FIG. 1 illustrates an example of a switched photodetector. [Figure 4E] FIG. 1 illustrates an example of a switched photodetector. [Figure 4F]FIG. 1 illustrates an exemplary design for selectively forming an absorbing layer on a substrate. [Figure 4G] FIG. 1 illustrates an exemplary design for selectively forming an absorbing layer on a substrate. [Figure 4H] FIG. 1 illustrates an exemplary design for selectively forming an absorbing layer on a substrate. [Figure 4I] FIG. 1 illustrates an exemplary design for selectively forming an absorbing layer on a substrate. [Figure 5A] FIG. 2 illustrates an example of a photodetector. [Figure 5B] FIG. 2 illustrates an example of a photodetector. [Figure 5C] FIG. 2 illustrates an example of a photodetector. [Figure 5D] FIG. 1 illustrates an example of a switched photodetector. [Figure 5E] FIG. 1 illustrates an example of a switched photodetector. [Figure 5F] FIG. 1 illustrates an example of a switched photodetector. [Figure 5G] FIG. 1 illustrates an example of a switched photodetector. [Figure 5H] FIG. 1 illustrates an example of a switched photodetector. [Figure 5I] FIG. 1 illustrates an example of a switched photodetector. [Figure 5J] FIG. 1 illustrates an example of a switched photodetector. [Figure 5K] FIG. 1 illustrates an example of a switched photodetector. [Figure 6A] FIG. 1 illustrates an example of a switched photodetector. [Figure 6B] FIG. 1 illustrates an example of a switched photodetector. [Figure 7A] 1 is a cross-sectional view illustrating an exemplary configuration of a microlens integrated with a photodetector. [Figure 7B] 1 is a cross-sectional view illustrating an exemplary configuration of a microlens integrated with a photodetector. [Figure 8A]FIG. 13 is a diagram showing an example of a switch for a switched photodetector. [Figure 8B] FIG. 13 is a diagram showing an example of a switch for a switched photodetector. [Figure 8C] FIG. 13 is a diagram showing an example of a switch for a switched photodetector. [Figure 9A] FIG. 13 illustrates an example of electrical terminals for a switched photodetector. [Figure 9B] FIG. 13 illustrates an example of electrical terminals for a switched photodetector. [Figure 9C] FIG. 13 illustrates an example of electrical terminals for a switched photodetector. [Figure 9D] FIG. 13 illustrates an example of electrical terminals for a switched photodetector. [Figure 9E] FIG. 13 illustrates an example of electrical terminals for a switched photodetector. [Figure 10A] FIG. 2 illustrates an exemplary configuration of a photodetector comprising an absorber region and a substrate. [Figure 10B] FIG. 2 illustrates an exemplary configuration of a photodetector comprising an absorber region and a substrate. [Figure 10C] FIG. 2 illustrates an exemplary configuration of a photodetector comprising an absorber region and a substrate. [Figure 10D] FIG. 2 illustrates an exemplary configuration of a photodetector comprising an absorber region and a substrate. [Figure 10E] FIG. 2 illustrates an exemplary configuration of a photodetector comprising an absorber region and a substrate. [Figure 10F] FIG. 2 illustrates an exemplary configuration of a photodetector comprising an absorber region and a substrate. [Figure 10G] FIG. 2 illustrates an exemplary configuration of a photodetector comprising an absorber region and a substrate. [Figure 10H] FIG. 2 illustrates an exemplary configuration of a photodetector comprising an absorber region and a substrate. [Figure 10I] FIG. 2 illustrates an exemplary configuration of a photodetector comprising an absorber region and a substrate. [Figure 11A] FIG. 2 is a top view of an example of a switched photodetector. [Figure 11B] FIG. 2 is a side view of an example of a switched photodetector. [Figure 11C] FIG. 2 is a top view of an example of a switched photodetector. [Figure 11D] FIG. 2 is a side view of an example of a switched photodetector. [Figure 11E] FIG. 2 is a side view of an example of a switched photodetector. [Figure 11F] FIG. 2 is a side view of an example of a switched photodetector. [Figure 12A] FIG. 2 is a top view of an example of a switched photodetector. [Figure 12B] FIG. 2 is a side view of an example of a switched photodetector. [Figure 12C] FIG. 2 is a side view of an example of a switched photodetector. [Figure 12D] FIG. 2 is a side view of an example of a switched photodetector. [Figure 12E] FIG. 2 is a top view of an example of a switched photodetector. [Figure 12F] FIG. 2 is a side view of an example of a switched photodetector. [Figure 12G] FIG. 2 is a side view of an example of a switched photodetector. [Figure 12H] FIG. 2 is a side view of an example of a switched photodetector. [Figure 13A] FIG. 2 is a top view of an example of a switched photodetector. [Figure 13B] FIG. 2 is a top view of an example of a switched photodetector. [Figure 13C] FIG. 2 is a top view of an example of a switched photodetector. [Figure 13D] FIG. 2 is a top view of an example of a switched photodetector. [Figure 13E] FIG. 2 is a top view of an example of a switched photodetector. [Figure 13F] FIG. 2 is a top view of an example of a switched photodetector. [Figure 13G] FIG. 2 is a top view of an example of a switched photodetector. [Figure 14A] FIG. 2 is a top view of an example of a switched photodetector. [Figure 14B] FIG. 2 is a top view of an example of a switched photodetector. [Figure 15A] 1 is a cross-sectional view illustrating an example configuration of pixel separation of a sensor. [Figure 15B] 1 is a cross-sectional view illustrating an example configuration of pixel separation of a sensor. [Figure 15C] 1 is a cross-sectional view illustrating an example configuration of pixel separation of a sensor. [Figure 15D] 1 is a cross-sectional view illustrating an example configuration of pixel separation of a sensor. [Figure 15E] 1 is a cross-sectional view illustrating an example configuration of pixel separation of a sensor. [Figure 15F] 1 is a cross-sectional view illustrating an example configuration of pixel separation of a sensor. [Figure 15G] 1 is a cross-sectional view illustrating an example configuration of pixel separation of a sensor. [Figure 16A] FIG. 2 is a cross-sectional view illustrating an exemplary configuration of a photodetector. [Figure 16B] FIG. 2 is a cross-sectional view illustrating an exemplary configuration of a photodetector. [Figure 16C] FIG. 2 is a cross-sectional view illustrating an exemplary configuration of a photodetector. [Figure 16D] FIG. 2 is a cross-sectional view illustrating an exemplary configuration of a photodetector. [Figure 16E] FIG. 2 is a cross-sectional view illustrating an exemplary configuration of a photodetector. [Figure 16F] FIG. 2 is a cross-sectional view illustrating an exemplary configuration of a photodetector. [Figure 16G] FIG. 2 is a cross-sectional view illustrating an exemplary configuration of a photodetector. [Figure 16H] FIG. 2 is a cross-sectional view illustrating an exemplary configuration of a photodetector. [Figure 16I] FIG. 2 is a cross-sectional view illustrating an exemplary configuration of a photodetector. [Figure 16J]FIG. 2 is a cross-sectional view illustrating an exemplary configuration of a photodetector. [Figure 17A] 1A-1C are cross-sectional views illustrating exemplary configurations of absorbent region surface modifications. [Figure 17B] 1A-1C are cross-sectional views illustrating exemplary configurations of absorbent region surface modifications. [Figure 17C] 1A-1C are cross-sectional views illustrating exemplary configurations of absorbent region surface modifications. [Figure 17D] 1A-1C are cross-sectional views illustrating exemplary configurations of absorbent region surface modifications. [Figure 17E] 1A-1C are cross-sectional views illustrating exemplary configurations of absorbent region surface modifications. [Figure 18A] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 18B] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 18C] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 18D] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 18E] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 18F] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 18G] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 19A] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 19B] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 19C] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 19D] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 19E] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 19F] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 19G] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 19H] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 20A] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 20B] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 20C] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 20D] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 20E] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 20F] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 20G] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 20H] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 20I] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 20J] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 20K] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 20L] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 21A] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 21B] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 21C] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 21D] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 21E] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 21F] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 22A]FIG. 2 is a top view of an exemplary switched photodetector. [Figure 22B] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 22C] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 22D] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 23A] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 23B] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 24A] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 24B] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 24C] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 24D] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 24E] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 24F] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 24G] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 25A] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 25B] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 25C] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 25D] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 25E] FIG. 2 is a top view of an exemplary switched photodetector. [Figure 25F] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 25G] FIG. 2 is a top view of an exemplary switched photodetector. [Fig. 25H] FIG. 2 is a side view of an exemplary switched photodetector. [Figure 26] FIG. 1 illustrates an exemplary unit cell of a rectangular photodetector. [Figure 27] FIG. 2 illustrates an exemplary rectangular switched photodetector with phototransistor gain. [Figure 28A] FIG. 1 is a block diagram of an example imaging system. [Figure 28B] 1 illustrates an example of a technique for determining a property of an object using an imaging system. [Figure 28C] 1 illustrates an example of a technique for determining a property of an object using an imaging system. [Figure 29] FIG. 1 illustrates an example of a flow diagram for determining a property of an object using an imaging system. [Diagram 30] FIG. 1 is a block diagram of an exemplary receiver unit for time-of-flight (ToF) detection. [Figure 31A] 1A and 1B are schematic and cross-sectional views of an example ToF receiver unit with enhanced capacitance; [Figure 31B] 1A and 1B are schematic and cross-sectional views of an example ToF receiver unit with enhanced capacitance; [Figure 31C] 1A and 1B are schematic and cross-sectional views of an example ToF receiver unit with enhanced capacitance; [Figure 31D] 1A and 1B are schematic and cross-sectional views of an example ToF receiver unit with enhanced capacitance; [Figure 31E] 1A and 1B are schematic and cross-sectional views of an example ToF receiver unit with enhanced capacitance; [Fig. 31F] 1A and 1B are schematic and cross-sectional views of an example ToF receiver unit with enhanced capacitance; [Figure 31G] 1A and 1B are schematic and cross-sectional views of an example ToF receiver unit with enhanced capacitance; [Fig. 31H] 1A and 1B are schematic and cross-sectional views of an example ToF receiver unit with enhanced capacitance; [Fig. 31I]1A and 1B are schematic and cross-sectional views of an example ToF receiver unit with enhanced capacitance; [Diagram 32] FIG. 2 is a block diagram of an example receiver unit for ToF detection. [Figure 33A] 1 is a schematic cross-sectional view of an exemplary receiver unit for ToF detection. [Figure 33B] 1 is a schematic cross-sectional view of an exemplary receiver unit for ToF detection. [Figure 33C] 1 is a schematic cross-sectional view of an exemplary receiver unit for ToF detection. [Figure 33D] 1 is a schematic cross-sectional view of an exemplary receiver unit for ToF detection. [Figure 33E] 1 is a schematic cross-sectional view of an exemplary receiver unit for ToF detection. [Diagram 34] 1A-1C are schematic cross-sectional views of an exemplary bonding process of an exemplary receiver unit for ToF detection. [Diagram 35] FIG. 1 is a schematic diagram of a circuit for operating a ToF pixel. [Figure 36A] FIG. 1 is a schematic side view of an exemplary testing apparatus. [Figure 36B] FIG. 1 is a schematic side view of an exemplary testing apparatus. [Figure 37A] FIG. 1 is a schematic diagram of a circuit for binarizing measurements from a ToF pixel. [Figure 37B] FIG. 2 is a schematic diagram of an example pixel circuit. [Figure 37C] FIG. 2 is a schematic diagram of an example pixel circuit. [Figure 37D] 1 is a schematic diagram of an exemplary common mode detection circuit. [Figure 37E] 37B is an exemplary timing diagram associated with the operation of the circuit of FIG. 37A. [Figure 37F] FIG. 1 illustrates an example of a flow diagram for characterizing the performance of a ToF detection device. [Figure 38A] 1 is a schematic diagram of a circuit for operating a light emitting device. [Figure 38B] 1 is a schematic diagram of a circuit for operating a light emitting device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Like reference numbers and designations in the various drawings indicate like elements. It will also be understood that the various exemplary embodiments shown in the figures are illustrations only and are not necessarily drawn to scale.

[0033] A photodetector may be used to detect an optical signal and convert the optical signal into an electrical signal that can be further processed by another circuit. In a time-of-flight (TOF) application, depth information of a three-dimensional object may be determined using the phase difference between a transmitted light pulse and a detected light pulse. For example, a two-dimensional array of pixels may be used to reconstruct a three-dimensional image of a three-dimensional object, and each pixel may include one or more photodetectors to derive phase information of the three-dimensional object. In some implementations, a time-of-flight application uses a light source having a wavelength in the near-infrared (NIR) range. For example, a light-emitting diode (LED) may have a wavelength of 850 nm, 940 nm, 1050 nm, or 1.3 μm to 1.6 μm. Some photodetectors may use silicon as an absorbing material, but silicon is an inefficient absorbing material for NIR wavelengths. In particular, photocarriers may be generated deep within the silicon substrate (e.g., greater than 10 μm deep), and these photocarriers may drift and / or diffuse slowly to the photodetector junction, resulting in a slower operating speed. Furthermore, a small voltage amplitude is typically used to control the operation of the photodetector to minimize power consumption. For a large absorption region (e.g., 10 μm diameter), a small voltage amplitude creates only a small lateral / vertical field across the large absorption region, which affects the drift speed of the photocarriers swept across the absorption region. Thus, the operating speed is further limited. For TOF applications using NIR wavelengths, switched photodetectors with innovative design structures and / or using germanium-silicon (GeSi) as the absorption material solve the technical problems described above. In this application, the term "photodetector" may be used interchangeably with the term "optical sensor". In this application, the term "germanium-silicon (GeSi)" refers to GeSi alloys having alloy compositions ranging from 1% germanium (Ge), i.e., 99% silicon (Si), to 99% Ge, i.e., 1% Si.In this application, the GeSi material may be grown using blanket epitaxy, selective epitaxy, or other applicable techniques. Furthermore, an absorber layer including GeSi material may be formed on a planar surface, a mesa-top surface, or a trench-bottom surface that is at least partially surrounded by an insulator (e.g., oxide, nitrite), a semiconductor (e.g., Si, Ge), or a combination thereof. Furthermore, a strained superlattice structure, or a multiple quantum well structure with an exchange layer such as a GeSi layer containing two or more different alloy compositions for the absorber layer may be used. Furthermore, a Si layer, or a GeSi layer with a low Ge concentration (e.g., <10%) may be used to passivate the surface of a Ge-rich (e.g., >50%) GeSi layer, which may reduce the dark or leakage current at the surface of the Ge-rich GeSi layer.

[0034] 1A is an exemplary switched photodetector 100 for converting an optical signal to an electrical signal. The switched photodetector 100 comprises an absorbing layer 106 fabricated on a substrate 102. The substrate 102 may be any suitable substrate on which a semiconductor device may be fabricated. For example, the substrate 102 may be a silicon substrate. The absorbing layer 106 comprises a first switch 108 and a second switch 110.

[0035] In general, the absorbing layer 106 receives the optical signal 112 and converts the optical signal 112 into an electrical signal. The absorbing layer 106 may be intrinsic, p-type, or n-type. In some implementations, the absorbing layer 106 may be formed of p-type GeSi material. The absorbing layer 106 is selected to have a high absorption coefficient in a desired wavelength range. For NIR wavelengths, the absorbing layer 106 may be a GeSi mesa, where the GeSi absorbs photons in the optical signal 112 and creates electron-hole pairs. The material composition of germanium and silicon in the GeSi mesa may be selected for a particular process or application. In some implementations, the absorbing layer 106 is designed to have a thickness t. For example, for wavelengths of 850 nm or 940 nm, the thickness of the GeSi mesa may be about 1 μm to have substantial quantum efficiency. In some implementations, the surface of the absorbing layer 106 is designed to have a particular shape. For example, the GeSi mesa may be circular, square, or rectangular depending on the spatial profile of the optical signal 112 on the surface of the GeSi mesa. In some implementations, the absorbing layer 106 is designed to have a lateral dimension d to receive the optical signal 112. For example, the GeSi mesa may have a circular or rectangular shape, and d may be in the range of 1 μm to 50 μm.

[0036] A first switch 108 and a second switch 110 are fabricated in the absorbing layer 106. The first switch 108 is coupled to a first control signal 122 and a first readout circuit 124. The second switch 110 is coupled to a second control signal 132 and a second readout circuit 134. In general, the first control signal 122 and the second control signal 132 control whether the electrons or holes generated by the absorbed photons are collected by the first readout circuit 124 or the second readout circuit 134.

[0037] In some implementations, the first switch 108 and the second switch 110 may be fabricated to collect electrons. In this case, the first switch 108 includes a p-type doped region 128 and an n-type doped region 126. For example, the p-type doped region 128 may have a p+ type doping, and the active dopant concentration may be as high as the fabrication process can achieve, for example, a peak concentration of about 5×10 when the absorbing layer 106 is germanium and doped with boron. 20 cm -3 In some implementations, the doping concentration of p-type doped region 128 can be 5×10 to reduce processing complexity at the expense of increased contact resistance. 20 cm -3 The n-type doped region 126 may have n+ type doping and the active dopant concentration may be as high as the fabrication process can achieve, for example, a peak concentration of about 1×10 when the absorbing layer 106 is germanium and doped with phosphorus. 20 cm -3 In some implementations, the doping concentration of n-type doped region 126 can be 1×10 to reduce processing complexity at the expense of increased contact resistance. 20 cm -3 The distance between the p-type doped region 128 and the n-type doped region 126 may be designed based on fabrication process design rules. In general, the closer the distance between the p-type doped region 128 and the n-type doped region 126, the higher the switching efficiency of the generated photocarriers. However, decreasing the distance between the p-type doped region 128 and the n-type doped region 126 may increase the dark current associated with the PN junction formed between the p-type doped region 128 and the n-type doped region 126. As such, the distance may be set based on the performance requirements of the switched photodetector 100. The second switch 110 comprises a p-type doped region 138 and an n-type doped region 136. The p-type doped region 138 is similar to the p-type doped region 128, and the n-type doped region 136 is similar to the n-type doped region 126.

[0038] In some implementations, the p-type doped region 128 is coupled to the first control signal 122. For example, the p-type doped region 128 may be coupled to a voltage source, and the first control signal 122 may be an AC voltage signal from the voltage source. In some implementations, the n-type doped region 126 is coupled to the readout circuit 124. The readout circuit 124 may be a three-transistor configuration consisting of a reset gate, a source follower, and a select gate, a circuit including four or more transistors, or any circuit suitable for processing electric charge. In some implementations, the readout circuit 124 may be fabricated on the substrate 102. In other implementations, the readout circuit 124 may be fabricated on a separate substrate and integrated / co-packaged with the switched photodetector 100 via die / wafer bonding or stacking.

[0039] The p-type doped region 138 is coupled to a second control signal 132. For example, the p-type doped region 138 may be coupled to a voltage source, and the second control signal 132 may be an AC voltage signal having an opposite phase to the first control signal 122. In some implementations, the n-type doped region 136 is coupled to a readout circuit 134. The readout circuit 134 may be similar to the readout circuit 124.

[0040] The first control signal 122 and the second control signal 132 are used to control the collection of electrons generated by absorbed photons. For example, when a voltage is used, if the first control signal 122 is biased against the second control signal 132, an electric field is generated between the p-type doped region 128 and the p-type doped region 138, and free electrons drift toward the p-type doped region 128 or the p-type doped region 138 depending on the direction of the electric field. In some implementations, the first control signal 122 can be fixed at a voltage value Vi, and the second control signal 132 can alternate between a voltage value Vi±ΔV. The direction of the bias value determines the drift direction of the electrons. Thus, when one switch (e.g., first switch 108) is turned “on” (i.e., electrons drift toward p-doped region 128), the other switch (e.g., second switch 110) is turned “off” (i.e., electrons are blocked from entering p-doped region 138). In some implementations, the first control signal 122 and the second control signal 132 can be voltages that are differential with respect to each other.

[0041] In general, the difference between the Fermi level of the p-type doped region and the Fermi level of the n-type doped region (before equilibrium) generates an electric field between the two regions. In the first switch 108, an electric field is generated between the p-type doped region 128 and the n-type doped region 126. Similarly, in the second switch 110, an electric field is generated between the p-type doped region 138 and the n-type doped region 136. When the first switch 108 is turned "on" and the second switch 110 is turned "off", the electrons drift toward the p-type doped region 128, and the electric field between the p-type doped region 128 and the n-type doped region 126 further carries the electrons to the n-type doped region 126. The readout circuit 124 can then be enabled to process the charges collected by the n-type doped region 126. On the other hand, when the second switch 110 is turned “on” and the first switch 108 is turned “off”, the electrons drift towards the p-type doped region 138, and the electric field between the p-type doped region 138 and the n-type doped region 136 carries the electrons further to the n-type doped region 136. The readout circuitry 134 can then be enabled to process the charges collected by the n-type doped region 136.

[0042] In some implementations, applying a voltage between the p-type and n-type doped regions of the switch may operate the switch in the avalanche regime to increase the sensitivity of the switched photodetector 100. For example, if the absorption layer 106 comprises GeSi, a voltage of less than 7 V may be applied to generate avalanche gain between the p-type and n-type doped regions 128 and 126 when the distance between the p-type and n-type doped regions 128 and 126 is about 100 nm.

[0043] In some implementations, the substrate 102 may be coupled to an external controller 116. For example, the substrate 102 may be coupled to ground or a preset voltage that is lower than the voltage at the n-type doped regions 126 and 136. In some other implementations, the substrate 102 may be floating and not coupled to an external controller.

[0044] 1B is a diagram of an example switched photodetector 160 for converting an optical signal to an electrical signal. The switched photodetector 160 is similar to the switched photodetector 100 of FIG. 1A, except that the first switch 108 and the second switch 110 further comprise n-well regions 152 and 154, respectively. In addition, the absorption layer 106 may be a p-type doped region. In some implementations, the doping levels of the n-well regions 152 and 154 are 10 15 cm -3 From 10 17 cm -3 The doping level of the absorbing layer 106 may be in the range of 10 14 cm -3 From 10 16 cm -3 may be in the range.

[0045] The arrangement of the p-type doped region 128, the n-type well region 152, the p-type doped absorption layer 106, the n-type well region 154, and the p-type doped region 138 forms a PNPNP junction structure. In general, the PNPNP junction structure reduces leakage current from the first control signal 122 to the second control signal 132, or alternatively from the second control signal 132 to the first control signal 122. The arrangement of the n-type doped region 126, the p-type doped absorption layer 106, and the n-type doped region 136 forms an NPN junction structure. In general, the NPN junction structure reduces charge coupling from the first readout circuit 124 to the second readout circuit 134, or alternatively from the second readout circuit 134 to the first readout circuit 124.

[0046] In some implementations, the p-type doped region 128 is formed entirely within the n-type well region 152. In some other implementations, the p-type doped region 128 is formed partially within the n-type well region 152. For example, a portion of the p-type doped region 128 may be formed by embedding a p-type dopant in the n-type well region 152, while another portion of the p-type doped region 128 may be formed by embedding a p-type dopant in the absorbing layer 106. Similarly, in some implementations, the p-type doped region 138 is formed entirely within the n-type well region 154. In some other implementations, the p-type doped region 138 is formed partially within the n-type well region 154. In some implementations, the depth of the n-type well regions 152 and 154 is shallower than the depth of the p-type doped regions 128 and 138.

[0047] 1C is a diagram of an example switched photodetector 170 for converting an optical signal to an electrical signal. The switched photodetector 170 is similar to the switched photodetector 100 of FIG. 1A, but the absorption layer 106 further comprises an n-type well region 156. In addition, the absorption layer 106 may be a p-type doped region. In some implementations, the doping level of the n-type well region 156 is 10 15 cm -3 From 10 17 cm -3 The doping level of the absorbing layer 106 may be in the range of 10 14 cm -3 From 10 16 cm -3 may be in the range.

[0048] The arrangement of the p-type doped region 128, the n-type well region 156, and the p-type doped region 138 forms a PNP junction structure. In general, the PNP junction structure reduces leakage current from the first control signal 122 to the second control signal 132, or alternatively from the second control signal 132 to the first control signal 122. The arrangement of the n-type doped region 126, the p-type doped absorption layer 106, and the n-type doped region 136 forms an NPN junction structure. In general, the NPN junction structure reduces charge coupling from the first readout circuit 124 to the second readout circuit 134, or alternatively from the second readout circuit 134 to the first readout circuit 124. In some implementations, when the depth of the n-type well region 156 is deep, the arrangement of the n-type doped region 126, the p-type doped absorption layer 106, the n-type well region 156, the p-type doped absorption layer 106, and the n-type doped region 136 forms an NPNPN junction structure, which further reduces charge coupling from the first readout circuit 124 to the second readout circuit 134, or alternatively from the second readout circuit 134 to the first readout circuit 124.

[0049] In some implementations, p-type doped regions 128 and 138 are formed entirely within n-type well region 156. In some other implementations, p-type doped regions 128 and 138 are formed partially within n-type well region 156. For example, a portion of p-type doped region 128 may be formed by embedding p-type dopants in n-type well region 156, while another portion of p-type doped region 128 may be formed by embedding p-type dopants in absorption layer 106. In some implementations, n-type well region 156 is shallower in depth than p-type doped regions 128 and 138.

[0050] 1D is a diagram of an example switched photodetector 180 for converting an optical signal to an electrical signal. Switched photodetector 180 is similar to switched photodetector 100 of FIG. 1A, except that switched photodetector 180 further comprises p-type well region 104 and n-type well regions 142 and 144. In some implementations, the doping levels of n-type well regions 142 and 144 are between 10 and 150 nm.16 cm -3 From 10 20 cm -3 The doping level of the p-type well region 104 may be in the range of 10 16 cm -3 From 10 20 cm -3 may be in the range.

[0051] In some implementations, the absorbing layer 106 may not completely absorb the incident photons in the optical signal 112. For example, if the GeSi mesa does not completely absorb the incident photons in the NIR optical signal 112, the NIR optical signal 112 may penetrate the silicon substrate 102, which may absorb the penetrating photons and generate slow-to-recombine photocarriers deep within the substrate. These slow photocarriers have a negative impact on the operating speed of the switched photodetector. Furthermore, the photocarriers generated within the silicon substrate 102 may be collected by adjacent pixels, which may cause undesirable signal crosstalk between pixels. Furthermore, the photocarriers generated within the silicon substrate 102 may cause the substrate 102 to charge up, which may cause reliability issues for the switched photodiode.

[0052] To further remove slow photocarriers, the switched photodetector 150 may include a connection that shorts the n-well regions 142 and 144 with the p-well region 104. For example, the connection may be formed by a silicide process or a deposited metal pad that connects the n-well regions 142 and 144 with the p-well region 104. The short between the n-well regions 142 and 144 and the p-well region 104 allows photocarriers generated in the substrate 102 to recombine at the short node, thus improving the operating speed and / or reliability of the switched photodetector. In some implementations, the p-well region 104 is used to passivate and / or minimize the electric field around interface defects between the absorbing layer 106 and the substrate 102, reducing the dark current of the device.

[0053] 1A-1D, in some implementations, the optical signal may reach the switched photodetector from the back side of the substrate 102. One or more optical components (e.g., microlenses or optical waveguides) may be fabricated on the back side of the substrate 102 to focus, collimate, defocus, filter, or otherwise process the optical signal.

[0054] 1A-1D, in some other implementations, the first switch 108 and the second switch 110 may alternatively be fabricated to collect holes instead of electrons. In this case, the p-doped regions 128 and 138 are replaced by n-doped regions, and the n-doped regions 126 and 136 are replaced by p-doped regions. The n-well regions 142, 144, 152, 154, and 156 are replaced by p-well regions. The p-well region 104 is replaced by an n-well region.

[0055] Although not shown in FIGS. 1A-1D , in some implementations, the absorbing layer 106 may be bonded to a substrate after fabrication of the switched photodetectors 100, 160, 170, and 180. The substrate may be any material that allows the optical signal 112 to be transmitted to reach the switched photodetectors. For example, the substrate may be a polymer or glass. In some implementations, one or more optical components (e.g., microlenses or optical waveguides) may be fabricated on the carrier substrate to focus, collimate, defocus, filter, or otherwise manipulate the optical signal 112.

[0056] Although not shown in FIGS. 1A-1D, in some implementations, the switched photodetectors 100, 160, 170, and 180 may be bonded (e.g., metal-to-metal, oxide-film, hybrid) to a second substrate having circuitry with control signals, and / or readout circuitry, and / or a phase-locked loop (PLL), and / or an analog-to-digital converter (ADC). A metal layer may be deposited on the switched photodetector that may be used as a reflector to reflect the optical signal incident from the backside of the substrate 102. Adding such a mirror-like metal layer may increase the absorption efficiency (quantum efficiency) of the absorbing layer 106. For example, the absorption efficiency of photodetectors operating at longer NIR wavelengths between 1.0 μm and 1.6 μm may be significantly improved by adding a reflective metal layer. An oxide layer may be included between the metal layer and the absorbing layer to increase the reflectivity. The metal layer may be used as a bonding layer for wafer bonding processes. In some implementations, one or more switches similar to 108 and 110 may be added to interface the control signals / readout circuitry.

[0057] 1A-1D, in some implementations, the absorbing layer 106 may be partially or completely embedded / inlaid within the substrate 102 to mitigate surface irregularities and thus facilitate the fabrication process. An example of the technology of the embodiments is described in U.S. Patent Publication No. US20170040362A1, entitled "Germanium-Silicon Light Sensing Apparatus," which is incorporated herein by reference in its entirety.

[0058] 2A is a diagram of an exemplary switched photodetector 200 for converting an optical signal to an electrical signal, where a first switch 208 and a second switch 210 are fabricated on a substrate 202. The switched photodetector 200 includes an absorbing layer 206 fabricated on the substrate 202. The substrate 202 may be any suitable substrate on which a semiconductor device may be fabricated. For example, the substrate 202 may be a silicon substrate.

[0059] In general, the absorbing layer 206 receives the optical signal 212 and converts the optical signal 212 into an electrical signal. The absorbing layer 206 is similar to the absorbing layer 106. The absorbing layer 206 may be intrinsic, p-type, or n-type. In some implementations, the absorbing layer 206 may be formed from a p-type GeSi material. In some implementations, the absorbing layer 206 may include a p-type doped region 209. The p-type doped region 209 may repel photo-electrons from the absorbing layer 206 to the substrate 202, thereby increasing the operating speed. For example, the p-type doped region 209 may have p+ type doping, with a dopant concentration as high as the fabrication process can achieve, e.g., a peak concentration of about 5×10 when the absorbing layer 206 is germanium and doped with boron. 20 cm -3 In some implementations, the doping concentration of p-type doped region 209 can be 5×10 to reduce processing complexity at the expense of increased contact resistance. 20 cm -3 In some implementations, the p-type doped region 209 may be a graded p-type doped region.

[0060] A first switch 208 and a second switch 210 are fabricated in the substrate 202. The first switch 208 is coupled to a first control signal 222 and a first readout circuit 224. The second switch 210 is coupled to a second control signal 232 and a second readout circuit 234. In general, the first control signal 222 and the second control signal 232 control whether the electrons or holes generated by the absorbed photons are collected by the first readout circuit 224 or the second readout circuit 234. The first control signal 222 is similar to the first control signal 122. The second control signal 232 is similar to the second control signal 132. The first readout circuit 224 is similar to the first readout circuit 124. The second readout circuit 234 is similar to the second readout circuit 134.

[0061] In some implementations, the first switch 208 and the second switch 210 may be fabricated to collect electrons generated by the absorbing layer 206. In this case, the first switch 208 comprises a p-type doped region 228 and an n-type doped region 226. For example, the p-type doped region 228 may have a p+ type doping and the active dopant concentration may be as high as the fabrication process can achieve, for example, a peak concentration of about 2×10 when the substrate 202 is silicon and doped with boron. 20 cm -3 In some implementations, the doping concentration of p-type doped region 228 can be 2×10 to reduce processing complexity at the expense of increased contact resistance. 20 cm -3 The n-type doped region 226 may have n+ type doping and the active dopant concentration may be as high as the fabrication process can achieve, for example, a peak concentration of about 5×10 when the substrate 202 is silicon and doped with phosphorus. 20 cm -3 In some implementations, the doping concentration of n-type doped region 226 can be 5×10 to reduce processing complexity at the expense of increased contact resistance. 20 cm -3 The distance between the p-type doped region 228 and the n-type doped region 226 may be designed based on fabrication process design rules. In general, the closer the distance between the p-type doped region 228 and the n-type doped region 226, the higher the switching efficiency of the generated photocarriers. The second switch 210 comprises a p-type doped region 238 and an n-type doped region 236. The p-type doped region 238 is similar to the p-type doped region 228, and the n-type doped region 236 is similar to the n-type doped region 226.

[0062] In some implementations, the p-type doped region 228 is coupled to the first control signal 222. The n-type doped region 226 is coupled to the readout circuit 224. The p-type doped region 238 is coupled to the second control signal 232. The n-type doped region 236 is coupled to the readout circuit 234. The first control signal 222 and the second control signal 232 are used to control the collection of electrons generated by absorbed photons. For example, when the absorbing layer 206 absorbs a photon in the optical signal 212, electron-hole pairs are generated and drift or diffuse into the substrate 202. When a voltage is used, if the first control signal 222 is biased against the second control signal 232, an electric field is generated between the p-type doped region 228 and the p-type doped region 238, and free electrons from the absorbing layer 206 drift toward the p-type doped region 228 or the p-type doped region 238 depending on the direction of the electric field. In some implementations, the first control signal 222 may be fixed at a voltage value V i , and the second control signal 232 may alternate between voltage values ​​V i ±ΔV. The direction of the bias value determines the drift direction of the electrons. Thus, when one switch (e.g., the first switch 208) is turned "on" (i.e., electrons drift toward the p-doped region 228), the other switch (e.g., the second switch 210) is turned "off" (i.e., electrons are prevented from entering the p-doped region 238). In some implementations, the first control signal 222 and the second control signal 232 may be voltages that are differential with respect to each other.

[0063] In the first switch 208, an electric field is generated between the p-type doped region 228 and the n-type doped region 226. Similarly, in the second switch 210, an electric field is generated between the p-type doped region 238 and the n-type doped region 236. When the first switch 208 is turned "on" and the second switch 210 is turned "off", the electrons drift towards the p-type doped region 228, and the electric field between the p-type doped region 228 and the n-type doped region 226 carries the electrons further to the n-type doped region 226. The readout circuit 224 can then be enabled to process the charge collected by the n-type doped region 226. On the other hand, when the second switch 210 is turned “on” and the first switch 208 is turned “off”, the electrons drift towards the p-type doped region 238, and the electric field between the p-type doped region 238 and the n-type doped region 236 carries the electrons further to the n-type doped region 236. The readout circuitry 234 can then be enabled to process the charges collected by the n-type doped region 236.

[0064] In some implementations, applying a voltage between the p-type and n-type doped regions of the switch may operate the switch in the avalanche regime to increase the sensitivity of the switched photodetector 200. For example, if the substrate 202 comprises GeSi, a voltage of less than 7 V may be applied to generate avalanche gain between the p-type and n-type doped regions 228 and 226 when the distance between the p-type and n-type doped regions 228 and 226 is about 100 nm.

[0065] In some implementations, the p-type doped region 209 may be coupled to an external controller 214. For example, the p-type doped region 209 may be coupled to ground. In some other implementations, the p-type doped region 209 may be floating and not coupled to an external controller. In some implementations, the substrate 202 may be coupled to an external controller 216. For example, the substrate 202 may be coupled to ground or a preset voltage that is lower than the voltage at the n-type doped regions 226 and 236. In some other implementations, the substrate 202 may be floating and not coupled to an external controller.

[0066] 2B is a diagram of an example switched photodetector 250 for converting an optical signal to an electrical signal. The switched photodetector 250 is similar to the switched photodetector 200 of FIG. 2A, except that the first switch 208 and the second switch 210 further comprise an n-well region 252 and an n-well region 254, respectively. In addition, the absorption layer 206 may be a p-type doped region and the substrate 202 may be a p-type doped substrate. In some implementations, the doping levels of the n-well regions 252 and 254 are between 10 15 cm -3 From 10 17 cm -3 The doping levels of the absorbing layer 206 and the substrate 202 may be in the range of 10 14 cm -3 From 10 16 cm -3 may be in the range.

[0067] The arrangement of the p-type doped region 228, the n-type well region 252, the p-type doped substrate 202, the n-type well region 254, and the p-type doped region 238 forms a PNPNP junction structure. In general, the PNPNP junction structure reduces leakage current from the first control signal 222 to the second control signal 232, or alternatively from the second control signal 232 to the first control signal 222. The arrangement of the n-type doped region 226, the p-type doped substrate 202, and the n-type doped region 236 forms an NPN junction structure. In general, the NPN junction structure reduces charge coupling from the first readout circuit 224 to the second readout circuit 234, or alternatively from the second readout circuit 234 to the first readout circuit 224.

[0068] In some implementations, p-type doped region 228 is formed entirely within n-type well region 252. In some other implementations, p-type doped region 228 is formed partially within n-type well region 252. For example, a portion of p-type doped region 228 may be formed by implanting p-type dopants in n-type well region 252, while another portion of p-type doped region 228 may be formed by implanting p-type dopants in substrate 202. Similarly, in some implementations, p-type doped region 238 is formed entirely within n-type well region 254. In some other implementations, p-type doped region 238 is formed partially within n-type well region 254. In some implementations, the depth of n-type well regions 252 and 254 is shallower than the depth of p-type doped regions 228 and 238.

[0069] 2C is a diagram of an example switched photodetector 260 for converting an optical signal to an electrical signal. The switched photodetector 260 is similar to the switched photodetector 200 of FIG. 2A, except that the substrate 202 further comprises an n-well region 244. In addition, the absorbing layer 206 may be a p-doped region and the substrate 202 may be a p-doped substrate. In some implementations, the doping level of the n-well region 244 is 10 15 cm -3 From 10 17 cm -3The doping levels of the absorbing layer 206 and the substrate 202 may be in the range of 10 14 cm -3 From 10 16 cm -3 may be in the range.

[0070] The arrangement of the p-type doped region 228, the n-type well region 244, and the p-type doped region 238 forms a PNP junction structure. In general, the PNP junction structure reduces leakage current from the first control signal 222 to the second control signal 232, or alternatively from the second control signal 232 to the first control signal 222. The arrangement of the n-type doped region 226, the p-type doped substrate 202, and the n-type doped region 236 forms an NPN junction structure. In general, the NPN junction structure reduces charge coupling from the first readout circuit 224 to the second readout circuit 234, or alternatively from the second readout circuit 234 to the first readout circuit 224. In some implementations, when the depth of the n-type well region 244 is deep, the arrangement of the n-type doped region 226, the p-type doped substrate 202, the n-type well region 244, the p-type doped substrate 202, and the n-type doped region 236 forms an NPNPN junction structure, which further reduces charge coupling from the first readout circuit 224 to the second readout circuit 234, or alternatively from the second readout circuit 234 to the first readout circuit 224. In some implementations, the n-type well region 244 also effectively reduces the potential energy barrier seen by electrons flowing from the absorbing layer 206 to the substrate 202.

[0071] In some implementations, p-type doped regions 228 and 238 are formed entirely within n-type well region 244. In some other implementations, p-type doped regions 228 and 238 are formed partially within n-type well region 244. For example, a portion of p-type doped region 228 may be formed by implanting p-type dopants in n-type well region 244, while another portion of p-type doped region 228 may be formed by implanting p-type dopants in substrate 202. In some implementations, n-type well region 244 has a shallower depth than p-type doped regions 228 and 238.

[0072] 2D is a diagram of an example switched photodetector 270 for converting an optical signal to an electrical signal. The switched photodetector 270 is similar to the switched photodetector 200 of FIG. 2A, except that the switched photodetector 270 further comprises one or more p-type well regions 246 and one or more p-type well regions 248. In some implementations, the one or more p-type well regions 246 and the one or more p-type well regions 248 may be part of a ring structure surrounding the first switch 208 and the second switch 210. In some implementations, the doping level of the one or more p-type well regions 246 and 248 may be between 10 and 200 . 15 cm -3 From 10 20 cm -3 One or more p-type well regions 246 and 248 may be used as opto-electronic isolation from adjacent pixels.

[0073] 2A-2D, in some implementations, the optical signal may reach the switched photodetector from the back side of the substrate 202. One or more optical components (e.g., microlenses or optical waveguides) may be fabricated on the back side of the substrate 202 to focus, collimate, defocus, filter, or otherwise manipulate the optical signal.

[0074] 2A-2D, in some other implementations, first switch 208 and second switch 210 may alternatively be fabricated to collect holes instead of electrons. In this case, p-type doped region 228, p-type doped region 238, and p-type doped region 209 are replaced by n-type doped regions, and n-type doped region 226 and n-type doped region 236 are replaced by p-type doped regions. N-type well regions 252, 254, and 244 are replaced by p-type well regions. P-type well regions 246 and 248 are replaced by n-type well regions.

[0075] 2A-2D, in some implementations, the absorbing layer 206 may be bonded to a substrate after fabrication of the switched photodetectors 200, 250, 260, and 270. The carrier substrate may be any material that allows the optical signal 212 to be transmitted to reach the switched photodetectors. For example, the substrate may be a polymer or glass. In some implementations, one or more optical components (e.g., microlenses or optical waveguides) may be fabricated on the carrier substrate to focus, collimate, defocus, filter, or otherwise manipulate the optical signal 212.

[0076] Although not shown in FIGS. 2A-2D, in some implementations, the switched photodetectors 200, 250, 260, and 270 may be bonded (e.g., metal-to-metal, oxide, hybrid) to a second substrate having circuitry with control signals, and / or readout circuitry, and / or a phase-locked loop (PLL), and / or an analog-to-digital converter (ADC). A metal layer may be deposited on top of the switched photodetectors that may be used as a reflector to reflect the optical signal incident from the backside of the substrate 202. Adding such a mirror-like metal layer may increase the absorption efficiency (quantum efficiency) of the absorbing layer 206. For example, the absorption efficiency of photodetectors operating at longer NIR wavelengths between 1.0 μm and 1.6 μm may be significantly improved by adding a reflective metal layer. An oxide layer may be included between the metal layer and the absorbing layer to increase the reflectivity. The metal layer may be used as a bonding layer for wafer bonding processes. In some implementations, one or more switches similar to 208 and 210 may be added to interface the control signals / readout circuitry.

[0077] 2A-2D, in some implementations, the absorbing layer 206 may be partially or completely embedded / inlaid within the substrate 202, which may mitigate surface irregularities and thus facilitate the fabrication process. An example of the technology of the embodiments is described in U.S. Patent Publication No. US20170040362A1.

[0078] FIG. 3A is a diagram of an exemplary switched photodetector 300 for converting an optical signal to an electrical signal, in which first switches 308a and 308b and second switches 310a and 310b are fabricated in a vertical configuration on a substrate 302. One characteristic of the switched photodetector 100 or the switched photodetector 200 is that the larger the size d of the optical window, the longer the photo-electron transit time required for electrons to drift or diffuse from one switch to the other. Thus, the operating speed of the photodetector may be affected. The switched photodetector 300 may further improve the operating speed by placing the p-type doped and n-type doped regions of the switches in a vertical configuration. Using this vertical configuration, the photoelectron travel distance is mostly limited by the thickness t (e.g., ∼1 μm) of the absorbing layer instead of the window size d (e.g., ∼10 μm) of the absorbing layer. The switched photodetector 300 comprises an absorbing layer 306 fabricated on a substrate 302. The substrate 302 may be any suitable substrate on which semiconductor devices may be fabricated. For example, the substrate 302 may be a silicon substrate.

[0079] In general, the absorbing layer 306 receives the optical signal 312 and converts the optical signal 312 to an electrical signal. The absorbing layer 306 is similar to the absorbing layer 206. The absorbing layer 306 may be intrinsic, p-type, or n-type. In some implementations, the absorbing layer 306 may be formed from a p-type GeSi material. In some implementations, the absorbing layer 306 may include a p-type doped region 309. The p-type doped region 309 is similar to the p-type doped region 209.

[0080] The first switches 308a and 308b and the second switches 310a and 310b are fabricated on the substrate 302. In particular, although only two first switches 308a and 308b and two second switches 310a and 310b are shown in FIG. 3A, there may be more or less first and second switches. The first switches 308a and 308b are coupled to a first control signal 322 and a first readout circuit 324. The second switches 310a and 310b are coupled to a second control signal 332 and a second readout circuit 334.

[0081] In general, the first control signal 322 and the second control signal 332 control whether the electrons or holes generated by the absorbed photons are collected by the first readout circuit 324 or the second readout circuit 334. The first control signal 322 is similar to the first control signal 122. The second control signal 332 is similar to the second control signal 132. The first readout circuit 324 is similar to the first readout circuit 124. The second readout circuit 334 is similar to the second readout circuit 134. In some implementations, the first switches 308a and 308b and the second switches 310a and 310b can be fabricated to collect electrons generated by the absorption layer 306. In this case, the first switches 308a and 308b include p-type doped regions 328a and 328b and n-type doped regions 326a and 326b, respectively. For example, p-type doped regions 328a and 328b may have p+ type doping and the active dopant concentration may be as high as the fabrication process can achieve, for example, a peak concentration of about 2×10 when substrate 302 is silicon and doped with boron. 20 cm -3 In some implementations, the doping concentration of p-type doped regions 328a and 328b can be 2×10 to reduce processing complexity at the expense of increased contact resistance. 20 cm -3The n-type doped regions 326a and 326b may have n+ type doping and the active dopant concentration may be as high as the fabrication process can achieve, for example, a peak concentration of about 5×10 when the substrate 302 is silicon and doped with phosphorus. 20 cm -3 In some implementations, the doping concentration of n-type doped regions 326a and 326b can be 5×10 to reduce processing complexity at the expense of increased contact resistance. 20 cm -3 The distance between the p-type doped region 328a and the n-type doped region 326a may be lower. The distance between the p-type doped region 328a and the n-type doped region 326a may be designed based on fabrication process design rules. For example, the distance between the p-type doped region 328a and the n-type doped region 326a may be controlled by the energy associated with the dopant implant. In general, the closer the distance between the p-type doped region 328a / 328b and the n-type doped region 326a / 326b, the higher the switching efficiency of the generated photocarriers. The second switches 310a and 310b include p-type doped regions 338a and 338b and n-type doped regions 336a and 336b, respectively. The p-type doped regions 338a / 338b are similar to the p-type doped regions 328a / 328b, and the n-type doped regions 336a / 336b are similar to the n-type doped regions 326a / 326b.

[0082] In some implementations, the p-type doped regions 328a and 328b are coupled to a first control signal 322. The n-type doped regions 326a and 326b are coupled to a readout circuit 334. The p-type doped regions 338a and 338b are coupled to a second control signal 332. The n-type doped regions 336a and 336b are coupled to a readout circuit 334. The first control signal 322 and the second control signal 332 are used to control the collection of electrons generated by absorbed photons. For example, when the absorption layer 306 absorbs a photon in the optical signal 312, electron-hole pairs are generated and drift or diffuse into the substrate 302. When a voltage is used, if the first control signal 322 is biased with respect to the second control signal 332, an electric field is generated between the p-type doped region 309 and the p-type doped region 328a / 328b or the p-type doped region 338a / 338b, and free electrons from the absorbing layer 306 drift toward the p-type doped region 328a / 328b or the p-type doped region 338a / 338b depending on the direction of the electric field. In some implementations, the first control signal 322 can be fixed at a voltage value Vi, and the second control signal 332 can alternate between a voltage value Vi±ΔV. The direction of the bias value determines the drift direction of the electrons. Thus, when one group of switches (e.g., first switches 308a and 308b) is turned “on” (i.e., electrons drift toward p-type doped regions 328a and 328b), the other group of switches (e.g., second switches 310a and 310b) is turned “off” (i.e., electrons are blocked from entering p-type doped regions 338a and 338b). In some implementations, the first control signal 322 and the second control signal 332 can be voltages that are differential with respect to each other.

[0083] In each of the first switches 308a / 308b, an electric field is generated between the p-type doped region 328a / 328b and the n-type doped region 326a / 326b. Similarly, in each of the second switches 310a / 310b, an electric field is generated between the p-type doped region 338a / 338b and the n-type doped region 336a / 336b. When the first switches 308a and 308b are turned "on" and the second switches 310a and 310b are turned "off", electrons drift toward the p-type doped regions 328a and 328b, and the electric field between the p-type doped region 328a and the n-type doped region 326a further carries the electrons to the n-type doped region 326a. Similarly, the electric field between the p-type doped region 328b and the n-type doped region 326b further carries the electrons to the n-type doped region 326b. The readout circuit 324 can then be enabled to process the charge collected by the n-type doped regions 326a and 326b. On the other hand, when the second switches 310a and 310b are turned "on" and the first switches 308a and 308b are turned "off", the electrons drift toward the p-type doped regions 338a and 338b, and the electric field between the p-type doped region 338a and the n-type doped region 336a further carries the electrons to the n-type doped region 336a. Similarly, the electric field between the p-type doped region 338b and the n-type doped region 336b further carries the electrons to the n-type doped region 336b. The readout circuit 334 can then be enabled to process the amount of charge collected by the n-type doped regions 336a and 336b.

[0084] In some implementations, applying a voltage between the p-type and n-type doped regions of the switch can operate the switch in the avalanche regime to increase the sensitivity of the switched photodetector 300. For example, if the substrate 302 comprises GeSi, a voltage of less than 7 V can be applied to generate avalanche gain between the p-type and n-type doped regions 328a, 326a when the distance between the p-type and n-type doped regions 328a, 326a is about 100 nm.

[0085] In some implementations, the p-type doped region 309 may be coupled to an external controller 314. For example, the p-type doped region 309 may be coupled to ground. In some implementations, the p-type doped region 309 may be floating and not coupled to an external controller. In some implementations, the substrate 302 may be coupled to an external controller 316. For example, the substrate 302 may be coupled to ground or a preset voltage that is lower than the voltage at the n-type doped regions 326 and 336. In some other implementations, the substrate 302 may be floating and not coupled to an external controller.

[0086] 3B is a diagram of an example switched photodetector 360 for converting an optical signal to an electrical signal. The switched photodetector 360 is similar to the switched photodetector 300 of FIG. 3A, except that the switched photodetector 360 further comprises an n-well region 344. In addition, the absorption layer 306 may be a p-type doped region and the substrate 302 may be a p-type doped substrate. In some implementations, the doping level of the n-well region 344 is 10 15 cm -3 From 10 17 cm -3 The doping levels of the absorbing layer 306 and the substrate 302 may be in the range of 10 14 cm -3 From 10 16 cm -3 may be in the range.

[0087] The arrangement of the p-type doped region 328a, the n-type well region 344, and the p-type doped region 338a forms a PNP junction structure. Similarly, the arrangement of the p-type doped region 328b, the n-type well region 344, and the p-type doped region 338b forms another PNP junction structure. In general, the PNP junction structure reduces leakage current from the first control signal 322 to the second control signal 332, or alternatively from the second control signal 332 to the first control signal 322. The arrangement of the n-type doped region 326a, the p-type doped substrate 302, and the n-type doped region 336a forms an NPN junction structure. Similarly, the arrangement of the n-type doped region 326b, the p-type doped substrate 302, and the n-type doped region 336b forms an NPN junction structure. In general, the NPN junction structure reduces charge coupling from the first readout circuit 324 to the second readout circuit 334, or alternatively from the second readout circuit 334 to the first readout circuit 324. In some implementations, the n-well region 344 also effectively reduces the potential energy barrier seen by electrons flowing from the absorbing layer 306 to the substrate 302.

[0088] In some other implementations, the p-type doped regions 328a, 338a, 328b, and 338b are formed entirely within the n-type well region 344. In some other implementations, the p-type doped regions 328a, 338a, 328b, and 338b are formed partially within the n-type well region 344. For example, a portion of the p-type doped region 328a may be formed by implanting a p-type dopant in the n-type well region 344, while another portion of the p-type doped region 328a may be formed by implanting a p-type dopant in the substrate 302. In some implementations, the depth of the n-type well region 344 is shallower than the depth of the p-type doped regions 328a, 338a, 328b, and 338b.

[0089] 3C is a diagram of an example switched photodetector 370 for converting an optical signal to an electrical signal. The switched photodetector 370 is similar to the switched photodetector 300 of FIG. 3A, except that the switched photodetector 370 further comprises one or more p-type well regions 346 and one or more p-type well regions 348. In some implementations, the one or more p-type well regions 346 and the one or more p-type well regions 348 may be part of a ring structure surrounding the first switches 308a and 308b and the second switches 310a and 310b. In some implementations, the doping level of the one or more p-type well regions is 10 15 cm -3 From 10 20 cm -3 One or more p-type well regions 346 and 348 may be used as opto-electronic isolation from adjacent pixels.

[0090] 3D illustrates a cross-sectional view of an exemplary switched photodetector 380. FIG 3D illustrates that the p-type doped regions 328a and 328b of the first switches 308a and 308b and the p-type doped regions 338a and 338b of the second switches 310a and 310b may be arranged in a mating arrangement on a first plane 362 of the substrate 302. FIG 3D further illustrates that the n-type doped regions 326a and 326b of the first switches 308a and 308b and the n-type doped regions 336a and 336b of the second switches 310a and 310b may be arranged in a mating arrangement on a second plane 364 of the substrate 302.

[0091] 3A-3D, in some implementations, the optical signal may reach the switched photodetector from the back side of the substrate 302. One or more optical components (e.g., microlenses or optical waveguides) may be fabricated on the back side of the substrate 302 to focus, collimate, defocus, filter, or otherwise manipulate the optical signal.

[0092] Although not shown in Figures 3A-3D, in some other implementations, the first switches 308a and 308b and the second switches 310a and 310b may alternatively be fabricated to collect holes instead of electrons. In this case, the p-type doped regions 328a and 328b, the p-type doped regions 338a and 338b, and the p-type doped region 309 are replaced by n-type doped regions, and the n-type doped regions 326a and 326b, and the n-type doped regions 336a and 336b are replaced by p-type doped regions. The n-type well region 344 is replaced by a p-type well region. The p-type well regions 346 and 348 are replaced by n-type well regions.

[0093] Although not shown in FIGS. 3A-3D , in some implementations, the absorbing layer 306 may be bonded to a substrate after fabrication of the switched photodetectors 300, 360, 370, and 380. The substrate may be any material that allows the optical signal 312 to be transmitted to reach the switched photodetectors. For example, the substrate may be a polymer or glass. In some implementations, one or more optical components (e.g., microlenses or optical waveguides) may be fabricated on the carrier substrate to focus, collimate, defocus, filter, or otherwise manipulate the optical signal 312.

[0094] Although not shown in FIGS. 3A-3D, in some implementations, the switched photodetectors 300, 360, 370, and 380 may be bonded (e.g., metal-to-metal, oxide-film, hybrid) to a second substrate having circuitry with control signals, and / or readout circuitry, and / or a phase-locked loop (PLL), and / or an analog-to-digital converter (ADC). A metal layer may be deposited on top of the switched photodetectors that may be used as a reflector to reflect the optical signal incident from the backside of the substrate 302. Adding such a mirror-like metal layer may increase the absorption efficiency (quantum efficiency) of the absorbing layer 306. For example, the absorption efficiency of photodetectors operating at longer NIR wavelengths between 1.0 μm and 1.6 μm may be significantly improved by adding a reflective metal layer. An oxide layer may be included between the metal layer and the absorbing layer to increase the reflectivity. The metal layer may be used as a bonding layer for wafer bonding processes. In some implementations, one or more switches similar to 308a (or 308b) and 310a (or 310b) may be added to interface the control signals / readout circuitry.

[0095] 3A-3D, in some implementations, the absorbing layer 306 may be partially or completely embedded / inlaid within the substrate 302, which may mitigate surface irregularities and thus facilitate the fabrication process. An example of the technology of the embodiments is described in U.S. Patent Publication No. US20170040362A1.

[0096] 4A is a diagram of an example switched photodetector 400 for converting an optical signal to an electrical signal. The switched photodetector 400 comprises an absorbing layer 406 fabricated on a substrate 402. The substrate 402 may be any suitable substrate on which a semiconductor device may be fabricated. For example, the substrate 402 may be a silicon substrate. The absorbing layer 406 comprises a first switch 408 and a second switch 410.

[0097] In general, the absorbing layer 406 receives the optical signal 412 and converts the optical signal 412 into an electrical signal. The absorbing layer 406 may be intrinsic, p-type, or n-type. In some implementations, the absorbing layer 406 may be formed of p-type GeSi material. The absorbing layer 406 is selected to have a high absorption coefficient in a desired wavelength range. For NIR wavelengths, the absorbing layer 406 may be a GeSi mesa, where the GeSi absorbs photons in the optical signal 412 and creates electron-hole pairs. The material composition of germanium and silicon in the GeSi mesa may be selected for a particular process or application. In some implementations, the absorbing layer 406 is designed to have a thickness t. For example, for wavelengths of 850 nm or 940 nm, the thickness of the GeSi mesa may be about 1 μm to have substantial quantum efficiency. In some implementations, the surface of the absorbing layer 406 is designed to have a particular shape. For example, the GeSi mesa may be circular, square, or rectangular depending on the spatial profile of the optical signal 412 on the surface of the GeSi mesa. In some implementations, the absorbing layer 406 is designed to have a lateral dimension d to receive the optical signal 412. For example, the GeSi mesa may have a circular or rectangular shape, and d may be in the range of 1 μm to 50 μm.

[0098] A first switch 408 and a second switch 410 are fabricated in the absorbing layer 406 and the substrate 402. The first switch 408 is coupled to a first control signal 422 and a first readout circuit 424. The second switch 410 is coupled to a second control signal 432 and a second readout circuit 434. In general, the first control signal 422 and the second control signal 432 control whether the electrons or holes generated by the absorbed photons are collected by the first readout circuit 424 or the second readout circuit 434.

[0099] In some implementations, the first switch 408 and the second switch 410 may be fabricated to collect electrons. In this case, the first switch 408 comprises a p-type doped region 428 embedded in the absorbing layer 406 and an n-type doped region 426 embedded in the substrate 402. For example, the p-type doped region 428 may have p+ doping and the active dopant concentration may be as high as the fabrication process can achieve, for example, a peak concentration of about 5×10 when the absorbing layer 106 is germanium and doped with boron. 20 cm -3 In some implementations, the doping concentration of p-type doped region 428 can be 5×10 to reduce processing complexity at the expense of increased contact resistance. 20 cm -3 The n-type doped region 426 may have n+ type doping and the active dopant concentration may be as high as the fabrication process can achieve, for example, a peak concentration of about 5×10 when the substrate 402 is silicon and doped with phosphorus. 20 cm -3 In some implementations, the doping concentration of n-type doped region 426 can be 5×10 to reduce processing complexity at the expense of increased contact resistance. 20 cm -3 The distance between the p-type doped region 428 and the n-type doped region 426 may be designed based on fabrication process design rules. In general, the closer the distance between the p-type doped region 428 and the n-type doped region 426, the higher the switching efficiency of the generated photocarriers. The second switch 410 comprises a p-type doped region 438 and an n-type doped region 436. The p-type doped region 438 is similar to the p-type doped region 428, and the n-type doped region 436 is similar to the n-type doped region 426.

[0100] In some implementations, the p-type doped region 428 is coupled to a first control signal 422. For example, the p-type doped region 428 may be coupled to a voltage source, and the first control signal 422 may be an AC voltage signal from the voltage source. In some implementations, the n-type doped region 426 is coupled to a readout circuit 424. The readout circuit 424 may be a three-transistor configuration consisting of a reset gate, a source follower, and a select gate, a circuit including four or more transistors, or any circuit suitable for processing electric charge. In some implementations, the readout circuit 424 may be fabricated on the substrate 402. In other implementations, the readout circuit 424 may be fabricated on a separate substrate and integrated / co-packaged with the switched photodetector 400 via die / wafer bonding or stacking.

[0101] The p-type doped region 438 is coupled to a second control signal 432. For example, the p-type doped region 438 may be coupled to a voltage source, and the second control signal 432 may be an AC voltage signal having an opposite phase to the first control signal 422. In some implementations, the n-type doped region 436 is coupled to a readout circuit 434. The readout circuit 434 may be similar to the readout circuit 424.

[0102] The first control signal 422 and the second control signal 432 are used to control the collection of electrons generated by absorbed photons. For example, when a voltage is used, if the first control signal 422 is biased against the second control signal 432, an electric field is generated between the p-type doped region 428 and the p-type doped region 438, and free electrons drift toward the p-type doped region 428 or the p-type doped region 438 depending on the direction of the electric field. In some implementations, the first control signal 422 can be fixed at a voltage value Vi, and the second control signal 432 can alternate between a voltage value Vi±ΔV. The direction of the bias value determines the drift direction of the electrons. Thus, when one switch (e.g., the first switch 408) is turned “on” (i.e., electrons drift toward the p-doped region 428), the other switch (e.g., the second switch 410) is turned “off” (i.e., electrons are prevented from entering the p-doped region 438). In some implementations, the first control signal 422 and the second control signal 432 can be voltages that are differential with respect to each other.

[0103] In general, the difference between the Fermi level of the p-type doped region and the Fermi level of the n-type doped region (before equilibrium) generates an electric field between the two regions. In the first switch 408, an electric field is generated between the p-type doped region 428 and the n-type doped region 426. Similarly, in the second switch 410, an electric field is generated between the p-type doped region 438 and the n-type doped region 436. When the first switch 408 is turned "on" and the second switch 410 is turned "off", the electrons drift toward the p-type doped region 428, and the electric field between the p-type doped region 428 and the n-type doped region 426 further carries the electrons to the n-type doped region 426. The readout circuit 424 can then be enabled to process the charges collected by the n-type doped region 426. On the other hand, when the second switch 410 is turned “on” and the first switch 408 is turned “off”, the electrons drift towards the p-type doped region 438, and the electric field between the p-type doped region 438 and the n-type doped region 436 carries the electrons further to the n-type doped region 436. The readout circuitry 434 can then be enabled to process the charges collected by the n-type doped region 436.

[0104] In some implementations, the substrate 402 may be coupled to an external controller 416. For example, the substrate 402 may be coupled to ground or a preset voltage that is lower than the voltage at the n-type doped regions 426 and 436. In some other implementations, the substrate 402 may be floating and not coupled to an external controller.

[0105] 4B is a diagram of an example switched photodetector 450 for converting an optical signal to an electrical signal. The switched photodetector 450 is similar to the switched photodetector 400 of FIG. 4A, except that the first switch 408 and the second switch 410 further comprise an n-well region 452 and an n-well region 454, respectively. In addition, the absorption layer 406 may be a p-type doped layer and the substrate 402 may be a p-type doped substrate. In some implementations, the doping levels of the n-well regions 452 and 454 are between 10 15 cm-3 From 10 17 cm -3 The doping levels of the absorbing layer 406 and the substrate 402 may be in the range of 10 14 cm -3 From 10 16 cm -3 may be in the range.

[0106] The arrangement of p-type doped region 428, n-type well region 452, absorbing layer 406, n-type well region 454, and p-type doped region 438 forms a PNPNP junction structure. In general, the PNPNP junction structure reduces leakage current from the first control signal 422 to the second control signal 432, or alternatively from the second control signal 432 to the first control signal 422.

[0107] The arrangement of the n-type doped region 426, the p-type doped substrate 402, and the n-type doped region 436 forms an NPN junction structure. In general, the NPN junction structure reduces charge coupling from the first readout circuit 424 to the second readout circuit 434, or alternatively from the second readout circuit 434 to the first readout circuit 424.

[0108] In some implementations, the p-type doped region 428 is formed entirely within the n-type well region 452. In some other implementations, the p-type doped region 428 is formed partially within the n-type well region 452. For example, a portion of the p-type doped region 428 may be formed by embedding a p-type dopant in the n-type well region 452, while another portion of the p-type doped region 428 may be formed by embedding a p-type dopant in the absorbing layer 406. Similarly, in some implementations, the p-type doped region 438 is formed entirely within the n-type well region 454. In some other implementations, the p-type doped region 438 is formed partially within the n-type well region 454. In some implementations, the depth of the n-type well regions 452 and 454 is shallower than the depth of the p-type doped regions 428 and 438.

[0109] 4C is a diagram of an example switched photodetector 460 for converting an optical signal to an electrical signal. The switched photodetector 460 is similar to the switched photodetector 400 of FIG. 4A, except that the absorption layer 406 further comprises an n-well region 456. In addition, the absorption layer 406 may be a p-doped region and the substrate 402 may be a p-doped substrate. In some implementations, the doping level of the n-well region 456 is 10 15 cm -3 From 10 17 cm -3 The doping levels of the absorbing layer 406 and the substrate 402 may be in the range of 10 14 cm -3 From 10 16 cm -3 may be in the range.

[0110] The arrangement of the p-type doped region 428, the n-type well region 456, and the p-type doped region 438 forms a PNP junction structure. In general, the PNP junction structure reduces leakage current from the first control signal 422 to the second control signal 432, or alternatively from the second control signal 432 to the first control signal 422.

[0111] The arrangement of the n-type doped region 426, the p-type doped absorption layer 406, and the n-type doped region 436 forms an NPN junction structure. In general, the NPN junction structure reduces charge coupling from the first readout circuit 424 to the second readout circuit 434, or alternatively from the second readout circuit 434 to the first readout circuit 424.

[0112] In some implementations, the p-type doped regions 428 and 438 are formed entirely within the n-type well region 456. In some other implementations, the p-type doped regions 428 and 438 are formed partially within the n-type well region 456. For example, a portion of the p-type doped region 428 may be formed by embedding a p-type dopant in the n-type well region 456, while another portion of the p-type doped region 428 may be formed by embedding a p-type dopant in the absorption layer 406. In some implementations, the n-type well region 456 is shallower in depth than the p-type doped regions 428 and 438.

[0113] 4D is a diagram of an example switched photodetector 470 for converting an optical signal to an electrical signal. The switched photodetector 470 is similar to the switched photodetector 460 of FIG. 4C, except that the n-well region 458 is formed to extend from the absorbing layer 406 into the substrate 202. In addition, the absorbing layer 406 may be a p-type doped region and the substrate 402 may be a p-type doped substrate. In some implementations, the doping level of the n-well region 456 is between 10 15 cm -3 From 10 17 cm -3 The doping levels of the absorbing layer 406 and the substrate 402 may be in the range of 10 14 cm -3 From 10 16 cm -3 may be in the range.

[0114] The arrangement of the p-type doped region 428, the n-type well region 458, and the p-type doped region 438 forms a PNP junction structure, which further reduces leakage current from the first control signal 422 to the second control signal 432, or alternatively from the second control signal 432 to the first control signal 422. The arrangement of the n-type doped region 426, the p-type doped substrate 402, the n-type well region 458, the p-type doped substrate 402, and the n-type doped region 436 forms an NPNPN junction structure, which further reduces charge coupling from the first readout circuit 424 to the second readout circuit 434, or alternatively from the second readout circuit 434 to the first readout circuit 424. In some implementations, the n-type well region 458 also effectively reduces the potential energy barrier seen by electrons flowing from the absorbing layer 406 to the substrate 402.

[0115] 4E is a diagram of an example switched photodetector 480 for converting an optical signal to an electrical signal. The switched photodetector 480 is similar to the switched photodetector 400 of FIG. 4A, except that the switched photodetector 480 further comprises one or more p-type well regions 446 and one or more p-type well regions 448. In some implementations, the one or more p-type well regions 446 and the one or more p-type well regions 448 may be part of a ring structure surrounding the first switch 408 and the second switch 410. In some implementations, the doping level of the one or more p-type well regions 446 and 448 may be between 10 and 200 . 15 cm -3 From 10 20 cm -3 One or more p-type well regions 446 and 448 may be used as opto-electronic isolation from adjacent pixels.

[0116] 4A-4E, in some implementations, the optical signal may reach the switched photodetector from the back side of the substrate 402. One or more optical components (e.g., microlenses or optical waveguides) may be fabricated on the back side of the substrate 402 to focus, collimate, defocus, filter, or otherwise manipulate the optical signal.

[0117] 4A-4E, in some other implementations, the first switch 408 and the second switch 410 may alternatively be fabricated to collect holes instead of electrons. In this case, p-type doped regions 428 and 438 are replaced by n-type doped regions, and n-type doped regions 426 and 436 are replaced by p-type doped regions. N-type well regions 452, 454, 456, and 458 are replaced by p-type well regions. P-type well regions 446 and 448 are replaced by n-type well regions.

[0118] Although not shown in FIGS. 4A-4E , in some implementations, the absorbing layer 406 may be bonded to a substrate after fabrication of the switched photodetectors 400, 450, 460, 470, and 480. The substrate may be any material that allows the optical signal 412 to be transmitted to reach the switched photodetectors. For example, the substrate may be a polymer or glass. In some implementations, one or more optical components (e.g., microlenses or optical waveguides) may be fabricated on the carrier substrate to focus, collimate, defocus, filter, or otherwise manipulate the optical signal 412.

[0119] Although not shown in FIGS. 4A-4E, in some implementations, the switched photodetectors 400, 450, 460, 470, and 480 may be bonded (e.g., metal-to-metal, oxide-film, hybrid) to a second substrate having circuitry with control signals, and / or readout circuitry, and / or a phase-locked loop (PLL), and / or an analog-to-digital converter (ADC). A metal layer may be deposited on top of the switched photodetectors that may be used as a reflector to reflect the optical signal incident from the backside of the substrate 402. Adding such a mirror-like metal layer may increase the absorption efficiency (quantum efficiency) of the absorbing layer 406. For example, the absorption efficiency of photodetectors operating at longer NIR wavelengths between 1.0 μm and 1.6 μm may be significantly improved by adding a reflective metal layer. An oxide layer may be included between the metal layer and the absorbing layer to increase reflectivity. The metal layer may be used as a bonding layer for wafer bonding processes. In some implementations, one or more switches similar to 408 and 410 may be added to interface the control signals / readout circuitry.

[0120] 4A-4E, in some implementations, the absorbing layer 406 may be partially or completely embedded / inlaid within the substrate 402, which may mitigate surface irregularities and thus facilitate the fabrication process. An example of the technology of the embodiments is described in U.S. Patent Publication No. US20170040362A1.

[0121] 4F-I show an exemplary design 490 for selectively forming an absorbing layer on a substrate. The design 490 may be used, for example, to fabricate the switched photodetector described in FIGS. 1A-4E. Referring to FIG. 4F, a recess 492 is formed on a substrate 402. The recess 492 may define a photodetector area for a NIR pixel. The recess may be formed using lithography followed by dry etching of the substrate 402. The shape of the recess may correspond to the shape of the pixel, such as a square, a circle, or other suitable shape.

[0122] 4G, a dielectric layer may be deposited over the substrate and a directional etch may be performed to form sidewall spacers 494. The directional etch may be an anisotropic dry etch. The spacers 494 may be dielectric materials such as various oxides and nitrides that separate the sidewalls of the absorber layer to be formed from the substrate 402. In some implementations, the spacers 494 may be omitted and the buried portion of the absorber layer to be formed may be in direct contact with a surface of the recess 492 formed in the substrate 402, such as the

[0110] sidewalls of a silicon substrate.

[0123] 4H, a germanium or germanium-silicon absorbing layer 496 is selectively grown from the substrate 402. For example, the absorbing layer 496 may be formed using epitaxial growth via a chemical vapor deposition (CVD) system. The resulting absorbing layer 496 is partially embedded within a recess 492 formed on the substrate 402. The absorbing layer 496 may be, for example, the absorbing layer of a switched photodetector as described in FIGS. 1A-4E.

[0124] 4I, the germanium or germanium-silicon absorber layer 496 is planarized with the substrate 402, resulting in a fully buried absorber layer 496. The germanium or germanium-silicon absorber layer 496 may be planarized using chemical mechanical polishing (CMP) or any other suitable technique. In some implementations, planarization of the germanium or germanium-silicon absorber layer 496 with respect to the surface of the substrate 402 may be omitted if the surface unevenness is acceptable for subsequent processing steps.

[0125] 5A illustrates an exemplary photodetector 500 for converting an optical signal to an electrical signal. The photodetector 500 includes an absorbing layer 506 fabricated on a substrate 502 and a first layer 508 formed on the absorbing layer 506 and the substrate 502. The substrate 502 may be similar to the substrate 102 previously described, and the absorbing layer 506 may be similar to the absorbing layer 106 previously described, and may be formed, for example, from Ge or GeSi with a Ge concentration in the range of 1-99%. The background doping polarity and doping level of the Ge or GeSi absorbing layer 506 is p-type and is 10 14 cm -3 From 10 16 cm -3 The background doping level may be in the range of 0.1 to 1.0 nm. The background doping level may be due to, for example, explicit incorporation of doping or due to material defects introduced during formation of the absorbing layer 506. The absorbing layer 506 of the photodetector 500 has a mesa structure and is supported by the substrate 502, and although vertical sidewalls are shown, the shape of the mesa structure and sidewall profile may depend on the details of the growth and fabrication process of the absorbing layer 506.

[0126] The first layer 508 covers the upper and side surfaces of the absorbing layer 506 and covers a portion of the upper surface of the substrate 502 on which the absorbing layer 506 is formed. The first layer 508 may be formed from a complementary metal oxide semiconductor (CMOS) process compatible material (CPCM), such as amorphous silicon, polysilicon, epitaxial silicon, aluminum oxide family (e.g., Al2O3), silicon oxide family (e.g., SiO2), germanium oxide family (e.g., GeO2), germanium-silicon family (e.g., Ge0.4Si0.6), silicon nitride family (e.g., Si3N4), high-k materials (e.g., HfOx, ZnOx, LaOx, LaSiOx), and any combination thereof. The presence of the first layer 508 on the surface of the absorbing layer 506 may produce various effects. For example, the first layer 508 may act as a surface passivation layer to the absorbing layer 506, which may reduce dark or leakage currents caused by defects present on the surface of the absorbing layer 506. In the case of a germanium (Ge) or germanium-silicon (GeSi) absorbing layer 506, the surface defects may be a significant source of dark or leakage currents, which contribute to an increase in the noise level of the photocurrent generated by the photodetector 500. By forming the first layer 508 on the surface of the absorbing layer 506, the dark or leakage currents may be reduced, thereby reducing the noise level of the photodetector 500. As another example, the first layer 508 may modulate the Schottky barrier level between contacts formed on the photodetector 500 and the absorbing layer 506 and / or the substrate 502. This barrier modulation effect is explained in a later paragraph.

[0127] FIG. 5B illustrates an exemplary photodetector 510 for converting an optical signal to an electrical signal. The photodetector 510 is similar to the photodetector 500 of FIG. 5A, except that the absorbing layer 506 is partially embedded in a recess formed on the substrate 502, and the photodetector 510 further includes a spacer 512. The spacer 512 may be a dielectric material, such as various oxides and nitrides, that separates the sidewalls of the absorbing layer 506 from the substrate 502. In some implementations, the spacer 512 may be omitted, and the embedded portion of the absorbing layer 506 may be in direct contact with a surface of the recess formed in the substrate 502, such as the sidewalls of a silicon substrate. An example of the technology of the embodiments is described in U.S. Patent Publication No. US20170040362A1.

[0128] 5C illustrates an exemplary photodetector 520 for converting an optical signal into an electrical signal. The photodetector 520 is similar to the photodetector 510 of FIG. 5B, except that the absorbing layer 506 is fully embedded within a recess formed on the substrate 502. An example of the technology of the embodiment is described in U.S. Patent Publication No. US20170040362A1.

[0129] 5D illustrates an exemplary switched photodetector 530 for converting an optical signal to an electrical signal. The switched photodetector 530 is similar to the photodetector 510 of FIG. 5B, except that a first switch 532 and a second switch 542 are fabricated in the absorbing layer 506 and the first layer 508. The first switch 532 may be similar to the first switch 108 of FIG. 1A, but further comprises a first read contact 535 coupled to the first n-type doped region 534 and a first control contact 538 coupled to the first p-type doped region 537. Similarly, the second switch 542 may be similar to the second switch 110 of FIG. 1A, but further comprises a second read contact 545 coupled to the second n-type doped region 544 and a second control contact 548 coupled to the second p-type doped region 547. The first and second p-type doped regions 537 and 547 may be control regions, and the first and second n-type doped regions 534 and 544 may be readout regions. The first and second readout contacts 535 and 545 are connected to respective readout circuits similar to the readout circuits 124 and 134 shown in Figure 1A. The first and second control contacts 538 and 548 are connected to respective control signals, such as the control signals 122 and 132 shown in Figure 1A.

[0130] Contacts 535, 538, 545, and 548 provide electrical contacts to the respective doped regions and may be formed from a variety of conductive materials. Examples of contact materials include various silicides, Ta-TaN-Cu stacks, Ti-TiN-W stacks, aluminum, and various combinations of such materials. In some implementations, read contacts 535 and 545 may be formed from a different material than control contacts 538 and 548. Contacts 535, 538, 545, and 548 may have a variety of physical configurations. The dimensions of the contacts may be in the range of tens of nanometers or so in diameter or width. Although a single contact 535, 538, 545, or 548 is shown coupled to each of the doped regions, two or more contacts may be coupled to the doped regions, for example, to reduce contact resistance or improve reliability, as is conventional in semiconductor device manufacturing processes.

[0131] 5E illustrates an example switched photodetector 550 for converting an optical signal to an electrical signal. Switched photodetector 550 is similar to switched photodetector 530 of FIG. 5D, except that first switch 532 and second switch 542 further comprise n-well regions 539 and 549, respectively, and p-well regions 536 and 546, respectively. The addition of n-well and p-well regions may modify the electrical and / or optical properties of photodetector 550. In some implementations, the doping levels of n-well regions 539 and 549 and p-well regions 536 and 546 are between 10 and 550. 15 cm -3 From 10 17 cm -3 may be in the range.

[0132] The arrangement of the p-type doped region 537, the n-type well region 539, the p-type absorption layer 506, the n-type well region 549, and the p-type doped region 547 forms a PNPNP junction structure. In general, the PNPNP junction structure reduces leakage current flow from the first control signal 122 to the second control signal 132, or alternatively from the second control signal 132 to the first control signal 122. The arrangement of the n-type doped region 534, the p-type well region 536, the p-type absorption layer 506, the p-type well region 546, and the n-type doped region 544 forms an NPN junction structure. In general, the NPN junction structure reduces charge coupling from the first readout circuit 124 to the second readout circuit 134, or alternatively from the second readout circuit 134 to the first readout circuit 124.

[0133] In some implementations, the p-type doped region 537 is formed entirely within the n-type well region 539. In some other implementations, the p-type doped region 537 is formed partially within the n-type well region 539. For example, a portion of the p-type doped region 537 may be formed by embedding a p-type dopant within the n-type well region 539, while another portion of the p-type doped region 537 may be formed by embedding a p-type dopant within the absorbing layer 506. Similarly, in some implementations, the p-type doped region 547 is formed entirely within the n-type well region 549. In some other implementations, the p-type doped region 547 is formed partially within the n-type well region 549. In some implementations, the n-type well regions 539 and 549 form a continuous n-type well region that includes at least a portion of both the p-type doped regions 537 and 547.

[0134] In some implementations, the n-type doped region 534 is formed entirely outside of the p-type well region 536. In some other implementations, the n-type doped region 534 is formed partially within the p-type well region 536. For example, a portion of the n-type doped region 534 may be formed by embedding an n-type dopant in the p-type well region 536, while another portion of the n-type doped region 534 may be formed by embedding an n-type dopant in the absorbing layer 506. Similarly, in some implementations, the n-type doped region 544 is formed entirely outside of the p-type well region 546. In some other implementations, the n-type doped region 544 is formed partially within the p-type well region 546.

[0135] Although Figures 5D and 5E show a switched photodetector with a partially buried absorbing region 506, the same configuration can be applied to a photodetector 500 with a non-buried absorbing layer 506, and to a photodetector 520 with a fully buried absorbing layer 506 to achieve a similar effect.

[0136] Although n-type well regions 539 and 549 and p-type well regions 536 and 546 are shown in combination for illustrative purposes, these wells may be implemented individually or in any combination.

[0137] Figure 5F illustrates an exemplary switched photodetector 560 for converting an optical signal to an electrical signal. Switched photodetector 560 is similar to switched photodetector 530 of Figure 5D, except that p-type doped regions 537 and 547 of switches 532 and 542, respectively, are omitted. As a result, first and second control contacts 538 and 548 form Schottky junctions to first layer 508. A Schottky junction is a semiconductor that is purposely undoped or has a doping density of about 1 x 10 15 cm -3Region 562 marks a leakage path between first control contact 538 and second control contact 548 through first layer 508 and absorbing layer 506, which is described in further detail with respect to FIG.

[0138] FIG. 5G illustrates an exemplary band diagram 570 of a leakage path formed between the control contact 538 and the control contact 548. The band diagram 570 illustrates the energy levels experienced by charge carriers, such as electrons 572 and holes 574, at various positions along the leakage path. The vertical axis corresponds to the energy level E, and the horizontal axis corresponds to the position x along the leakage path formed between the control contact 538 and the control contact 548. An exemplary scenario is illustrated in which the potential energy of the first control contact 538 is higher than the second control contact 548 (e.g., the first control signal 122 has a lower voltage than the second control signal 132). The potential difference appears as a downward slope of the overall band diagram from the first control contact 538 to the second control contact 548. The energy levels and positions as illustrated are for illustrative purposes and may not represent actual values.

[0139] Electron barrier 573 and hole barrier 575 are examples of Schottky barriers. Schottky junctions are characterized by the presence of a Schottky barrier, which is a potential energy barrier that electrons 572 and holes 574 must overcome in order for those carriers to flow across the Schottky junction. The values ​​of barriers 573 and 575 can vary depending on the materials of contacts 538 and 548, as well as the work function of the material of first layer 508. As such, desired levels of electron barrier 573 and hole barrier 575 can be set by selecting the appropriate combination of contact materials and first layer materials.

[0140] The electrons 572 must overcome an electron barrier 573 between the first control contact 538 and the first layer 508. By providing a sufficiently high electron barrier 573, the potential of the control signal 122 applied to the first control contact may not be able to overcome the barrier 573. As such, the electron barrier 573 may block the electrons 572 from flowing into the absorbing layer 506. If the electrons 572 overcome the electron barrier 573, which may be due to statistical fluctuations in the thermal energy of the electrons 572 ("thermonic emission") or quantum tunneling, the electrons 572 may flow across the absorbing layer 506 to the first layer 508 adjacent to the second control contact 548. Another electron barrier is provided by the junction formed between the absorbing layer 506 and the first layer 508, which may further block the electrons 572 from flowing into the second control contact 548, thereby reducing the leakage current of electrons from the first control contact 538 to the second control contact 548.

[0141] Similarly, the holes 574 must overcome a hole barrier 575 between the second control contact 548 and the first layer 508. By providing a sufficiently high hole barrier 575, the potential of the control signal 132 applied to the second control contact may not be able to overcome the barrier 575. As such, the hole barrier 575 may block the holes 574 from flowing into the absorbing layer 506. If the holes 574 overcome the hole barrier 575, which may be due to statistical fluctuations in the thermal energy of the holes 574 ("thermonic emission") or quantum tunneling, the holes 574 may flow across the absorbing layer 506 to the first layer 508 adjacent to the first control contact 538. Another hole barrier is provided by the junction formed between the absorbing layer 506 and the first layer 508, which may further block holes 574 from flowing into the first control contact 538, thereby reducing hole leakage current from the second control contact 548 to the first control contact 538.

[0142] When light is being shone on the absorbing layer 506, a photon 576 of the light may be absorbed by an electron in the valence band of the absorbing layer 506, resulting in the generation of an electron-hole as indicated by the vertical arrow adjacent to the photon 576. The electron of this electron-hole pair forms a photocurrent that should be captured by the readout circuit 124 and / or 134 through the respective readout contact 535 and / or 545 and should not flow into the control contacts 538 and 548. In this case, the barrier formed by the interface between the first layer 508 and the absorbing layer 506 may prevent such flow, thereby improving the photocurrent collection efficiency of the readout circuit.

[0143] When a first layer 508, such as amorphous silicon or polysilicon or crystalline silicon or germanium-silicon, is inserted between the control contacts 538 and 548 and an absorbing layer 506, such as a GeSi mesa, the Schottky barrier of the metal-semiconductor (MS) junction is modified, such that electrons or holes are partially blocked by the contacts 538 and 548 from being injected into the first layer 508, as described above. The power consumption of a ToF pixel, such as a switched photodetector described herein, is determined in part by the leakage current that flows between the two control contacts 538 and 548, which are connected to two control circuits. As such, by partially blocking the injection of electrons or holes by the contacts 538 and 548, the power consumption of the ToF pixel can be significantly reduced.

[0144] 5H illustrates an exemplary switched photodetector 580 for converting an optical signal to an electrical signal. The switched photodetector 580 is similar to the switched photodetector 560 of FIG. 5F, except that the photodetector 580 further comprises n-type well regions 539 and 549 and p-type well regions 536 and 546. The structure and effect of the n-type well regions 539 and 549 and the p-type well regions 536 and 546 have already been described with respect to FIG. 5E. In addition, the n-type well regions 539 and 549 overlap at least a portion of the first layer 508 under the control contacts 538 and 548, which may contribute to enhancing the voltage drop inside the absorption layer 506. Increasing the voltage drop inside the absorption layer 506 increases the magnitude of the electric field established within the absorption layer 506, which may improve the efficiency of capture of photo-generated electrons by the readout circuits 124 and / or 134 through their respective readout contacts 535 and / or 545.

[0145] FIG. 5I illustrates an exemplary switched photodetector 582 for converting an optical signal to an electrical signal. The switched photodetector 582 is similar to the switched photodetector 550 of FIG. 5E, except that the first switch 532 is now disposed on the substrate 502 adjacent to the left absorbing layer 506, and the second switch 542 is now disposed on the substrate 502 adjacent to the right absorbing layer 506. The operation of the switched photodetector 582 is similar to that of the switched photodetectors already described. However, because electrical contacts formed between contacts, such as read contacts 535 and 545 or control contacts 538 and 548, and the silicon substrate 502 typically have lower dark or leakage currents than electrical contacts formed between the contacts and the Ge or GeSi absorbing layer 506 (e.g., because the substrate 502 has fewer material defects than the absorbing layer 506), the overall dark or leakage current may be lower compared to the configuration of the photodetector 550 illustrated in FIG. 5E. Furthermore, with the switch located on the substrate 502, photo-generated carriers from light absorbed by the absorbing region 506 will now flow from the absorbing region 506 to the substrate 502 before reaching the readout circuits 124 and 134. Depending on the particular geometry of the absorbing region 506 and the spacer 512 and their materials, the photo-carriers may be conducted through the spacer 512, flow around the spacer 512, or a combination of both may occur.

[0146] In some implementations, p-type doped regions 537 and 547 may be omitted in a configuration similar to that shown in Figure 5F. Although n-type well regions 539 and 549 and p-type well regions 536 and 546 are shown combined for illustrative purposes, these wells may be omitted, implemented separately, or implemented in any combination.

[0147] FIG. 5J illustrates an exemplary switched photodetector 586 for converting an optical signal to an electrical signal. Switched photodetector 586 is similar to switched photodetector 582 of FIG. 5I, except that p-type doped regions 537 and 547 of switches 532 and 542, respectively, are omitted. As a result, first and second control contacts 538 and 548 form Schottky junctions to first layer 508. The effect of Schottky junctions is described with respect to FIGS. 5F-5H. Band diagram 570 of FIG. 5G is still applicable to region 562 of photodetector 586, and the geometry of photodetector 586 has been modified with respect to photodetector 506 so that the barrier formed by first layer 508 now corresponds to the barrier formed by first layer 508, substrate 502, and spacer 512.

[0148] Although n-type well regions 539 and 549, and p-type well regions 536 and 546 are shown combined for illustrative purposes, these wells may be omitted, implemented separately, or implemented in any combination.

[0149] FIG 5K illustrates an exemplary switched photodetector 588 for converting an optical signal to an electrical signal. The switched photodetector 588 is similar to the switched photodetector 582 of FIG 5I, except that the first switch 532 further comprises a second p-type doped region 537a, a third control contact 538a coupled to the second p-type doped region 537a, and a second n-type well region 539a in contact with the second p-type doped region 537a, and the second switch 542 further comprises a second p-type doped region 547a, a fourth control contact 548a coupled to the second p-type doped region 547a, and a second n-type well region 549a in contact with the second p-type doped region 547a. The second p-type doped regions 537a and 537b are similar to the second p-type doped regions 537 and 547, respectively. Second n-type well regions 539a and 549a are similar to second n-type regions 539 and 549, respectively. First control contact 538a is similar to first control contact 538, and fourth control contact 548a is similar to second control contact 548. First control contact 538a is connected to first control signal 122, and fourth control contact 548a is connected to second control signal 132.

[0150] Because the first control contact 538 and associated doped regions are not in direct contact with the absorbing layer 506, the electric field generated in the absorbing layer 506 by application of the first control signal 122 to the first control contact 538 may be a relatively weaker electric field compared to a configuration in which the first control contact 538 is in direct contact with the absorbing layer 506, such as in the configuration of the photodetector 550 of FIG. 5E. By adding the third and fourth control contacts 538a and 548a and associated doped regions, the carrier collection control efficiency of the photodetector 586 may be improved over that of the photodetector 582 of FIG. 5I and may be comparable to that of the photodetector 550 in FIG. 5E, while at least partially retaining the advantage of reducing dark or leakage current by moving the contacts to the substrate 502. Furthermore, the addition of control contacts 538a and 548a may also contribute to improving the operating speed of photodetector 588, as the larger the electric field in the absorption region, the greater the bandwidth of the photodetector, allowing for faster switching speeds between the first switch 532 and the second switch 542.

[0151] Although the third control contact 538a and the fourth control contact 548a are shown sharing the respective control signals 122 and 132 with the first control contact 538 and the second control contact 548, in some implementations the contacts 538a and 548a may have independent control signals that may be different from the first and second control signals 122 and 132. For example, the control signal for the third control contact 538a may be smaller than the first control signal 122 for the first control contact 538 because the control signal applied to the third control contact 538a may have a larger effect on the photo-generated carriers compared to the first control signal 122 applied to the first control contact 538 due to the proximity of the second p-type doped region 537a to the carriers generated in the absorption layer 506, and the same is true for the control signal for the fourth control contact 548a.

[0152] In some implementations, the second p-type doped regions 537a and 547a may be omitted to form a Schottky junction, the effect of which has already been described with respect to Figures 5F-5H. Although the n-type well regions 539 and 549 and the p-type well regions 536 and 546 are shown in combination for illustrative purposes, these wells may be omitted, implemented separately, or implemented in any combination.

[0153] Although various configurations of switched photodetectors having a partially buried absorbing layer 506 have been described in Figures 5D-5K, the described configurations can be applied to switched photodetectors having a fully protruding absorbing layer 506, such as the configuration shown in Figure 5A, and to switched photodetectors having a fully buried absorbing layer 506, such as the configuration shown in Figure 5C, to similar effect.

[0154] 5A-5K can be incorporated into a front-side illuminated (FSI) image sensor or a back-side illuminated (BSI) image sensor. In an FSI configuration, light enters the photodetector from the top through the first layer 508. In a BSI configuration, light enters the photodetector from the bottom through the substrate 502.

[0155] The control regions (e.g., p-doped regions 537 and 547) and readout regions (e.g., n-doped regions 534 and 544) may be at different heights. For example, for photodetectors 530, 550, 560, and 580, and any configuration in which the control and readout regions are both disposed on the absorber region 506, a portion of the absorber region 506 corresponding to the readout or control region may be etched, and the readout or control region may be formed in the etched portion, resulting in a vertical offset between the control and readout regions. Similarly, for photodetectors 582, 586, and 588, and any configuration in which the control and readout regions are both disposed on the substrate 502, a portion of the substrate 502 corresponding to the readout or control region may be etched, and the readout or control region may be formed in the etched portion, resulting in a vertical offset between the control and readout regions.

[0156] In some implementations, a lens may be placed in the optical path of the light incident on the photodetector. The lens may be, for example, a microball lens or a Fresnel Zone Plate (FZP) lens. As another example, for a silicon substrate 502, the lens may be formed directly on the substrate 502 by etching the substrate 502. Details regarding the lens configuration are provided with respect to Figures 7A-7C.

[0157] In some implementations, the interface between the absorbing layer 506 and the spacer 512 may be doped with an n-type or p-type dopant to improve electrical isolation for holes and electrons, respectively. In some implementations, the interface between the absorbing layer 506 and the substrate 502 (e.g., the bottom interface) may be doped with an n-type or p-type dopant to improve electrical isolation for holes and electrons, respectively.

[0158] 6A shows an exemplary switched photodetector 600 for converting an optical signal to an electrical signal. The switched photodetector 600 comprises a substrate 502, an absorbing region 506, a first switch 532, a second switch 542, and a counter-doped region 610. The counter-doped region 610 is disposed within the absorbing region 506. The first and second switches 532 and 542 are disposed on the absorbing layer 506. The substrate 502, the absorbing region 506, and the first and second switches 532 and 542 have already been described with respect to FIG. 5D.

[0159] The counterdoped region 610 is a portion of the absorber region 506 that is doped with a dopant species that reduces the net carrier concentration of the absorber region 506. Undoped semiconductor materials have a certain concentration of charge carriers that can contribute to current conduction even in the absence of dopants, which is referred to as the intrinsic carrier concentration of the semiconductor. The absorber region 506 is typically formed from a semiconductor material, such as silicon, germanium, or an alloy of the two, and has an associated intrinsic carrier concentration. This intrinsic carrier concentration can vary due to various factors, such as the material fabrication method and defect level (defect concentration). Examples of material fabrication methods include epitaxial growth, chemical vapor deposition (CVD), metalorganic CVD (MOCVD), and physical vapor deposition (PVD), and materials fabricated using different methods can have different material defect levels. Typically, a higher number of material defects correlates to a higher level of intrinsic carrier concentration. For example, bulk crystalline germanium has a lattice constant of about 2*10 at room temperature. 13 cm -3 While epitaxially grown germanium may have an intrinsic p-type like carrier concentration of about 5*10 14 cm -3 Depending on the material type and the nature of the defects, the semiconductor material may be p-type or n-type like.

[0160] Reducing leakage current in switched photodetectors such as photodetector 600 is important in reducing power consumption in time-of-flight pixels. One of the factors contributing to leakage current in switched photodetectors is leakage current flowing between control regions, for example, current flow between p-type doped regions 537 and 547. One approach to reduce such current flow is by reducing the net carrier concentration in the absorption region 506 between the two p-type doped regions 537 and 547. The net carrier concentration is the concentration of carriers available to conduct current and may be determined by a combination of the contributions of the intrinsic carrier concentration and the extrinsic carrier concentration contributed by dopants. By appropriately selecting the electrical type, chemical species, and concentration of the dopant, the intrinsic carrier concentration may be compensated, or "counter-doped," by the dopant, resulting in a lower net carrier concentration for the semiconductor material. Typically, the leakage current between the control regions is proportional to the net carrier concentration when the intrinsic and net carriers have the same polarity, ie, both are p-like or n-like.

[0161] The type of dopant to be used for the counterdoped region 610 may be selected based on various factors, such as the material forming the absorber region 506 and the nature of the defects present in the absorber region 506. For example, epitaxially grown Ge on a Si substrate 502 is typically a p-type material. In such a case, an n-type dopant species such as P, As, Sb, or F may be used to dope the counterdoped region 610. The doping may be performed in various ways, including implantation, diffusion, and in-situ doping as the material is grown. In some cases, a dopant such as fluorine may passivate the defects. The passivated defects cease to act as a source of charge carriers, and thus the net carrier concentration of the fluorine doped absorber region 506 may be reduced and become more intrinsic.

[0162] The concentration of dopant to be used in the counterdoped region 610 may be selected based on the intrinsic carrier concentration of the absorption region 506. For example, about 5*10 14 cm -3 Epitaxially grown germanium with an intrinsic carrier concentration of about 5*10 14 cm -3 is doped with a counterdopant concentration of about 2*10 13 cm -3 In general, the counterdoping concentration is 1*10 13 cm -3 From 1*10 16 cm -3 In some implementations, the counter-doped region 610 may have a dopant concentration that varies across its region. For example, a region closer to the material interface, such as the bottom of the absorber 506, may have a higher intrinsic carrier concentration due to increased defect levels, which may be better compensated for by a correspondingly higher counter-doping level. In some implementations, the counter-dopant concentration may be higher than the intrinsic carrier concentration of the absorber region 506. In such cases, the polarity of the absorber region 506 may be changed from p-type to n-type or vice versa.

[0163] Although counter-doped region 610 is shown completely covering n-type doped regions 534 and 544, as well as p-type doped regions 537 and 547, in general, counter-doped region 610 may only cover p-type doped regions 537 and 547 or n-type doped regions 534 and 544. In addition, although counter-doped region 610 is shown to be a continuous region, in general, counter-doped region 610 may be two or more separate regions. Furthermore, although counter-doped region 610 is shown to be only a portion of absorber region 506, in general, counter-doped region 610 may be formed throughout the entire absorber region 506.

[0164] In some implementations, the counter-doped region 610 acts as a dopant diffusion retarder, which may contribute to the formation of an abrupt junction profile. The formation of an abrupt junction profile between the counter-doped region 610 and the p-type doped regions 537 and 547 may reduce leakage current, thereby reducing power consumption of the ToF pixel. For example, in the case of the Ge absorber region 506, fluorine doping may retard the diffusion of phosphorus dopants in the n-type doped region 534.

[0165] In general, counter-doped region 610 may be implemented in various implementations of switched photodetectors to reduce leakage current between the control regions.

[0166] In some implementations, p-type doped regions 537 and 547 are omitted, resulting in the formation of a Schottky junction, the effects of which have already been described with respect to Figures 5F-5H.

[0167] 6B illustrates an example switched photodetector 620 for converting an optical signal to an electrical signal. The switched photodetector 620 is similar to the photodetector 600 of FIG. 6A, except that the first switch 532 and the second switch 542 further comprise n-well regions 612 and 614, respectively. The addition of the n-well regions may modify the electrical and / or optical properties of the photodetector 620. In some implementations, the doping levels of the n-well regions 612 and 614 are between 10 15 cm -3 From 10 17 cm -3 In some implementations, the n-well regions 612 and 614 may extend from an upper surface of the absorbing region 506 to a lower surface of the counterdoped region 610 or to the interface between the absorbing layer 506 and the substrate 502.

[0168] The arrangement of p-type doped region 537, n-type well region 612, counter doped region 610, n-type well region 614, and p-type doped region 547 forms a PNINP junction structure. In general, the PNINP junction structure reduces leakage current flow from the first control signal 122 to the second control signal 132, or alternatively from the second control signal 132 to the first control signal 122.

[0169] In some implementations, the p-type doped region 537 is formed entirely within the n-type well region 612. In some other implementations, the p-type doped region 537 is formed partially within the n-type well region 612. For example, a portion of the p-type doped region 537 may be formed by implanting a p-type dopant within the n-type well region 612, while another portion of the p-type doped region 537 may be formed by implanting a p-type dopant within the counter-doped region 610. Similarly, in some implementations, the p-type doped region 547 is formed entirely within the n-type well region 614. In some other implementations, the p-type doped region 547 is formed partially within the n-type well region 614. In some implementations, the n-type well regions 612 and 614 form a continuous n-type well region that includes at least a portion of both the p-type doped regions 537 and 547.

[0170] The operating speed or bandwidth of a photodetector can be an important performance parameter for applications that benefit from fast detection of light, such as ToF detection. Characteristics that can affect the bandwidth of a photodetector are, among others, the physical size of the photodetector, such as the area of ​​the photodetector through which the received light passes. For example, reducing the area of ​​the photodetector can reduce the capacitance of the device, the carrier transit time, or a combination of both, which typically results in an increase in the bandwidth of the photodetector. However, reducing the detection area of ​​the photodetector can reduce the amount of light (i.e., the number of photons) detected by the photodetector. For example, for a given intensity of light per unit area, reducing the area of ​​the detector causes a decrease in the light detected.

[0171] For applications that benefit from both high bandwidth and high detection efficiency, such as ToF detection, it may be beneficial to add a microlens in front of the photodetector. The microlens can focus the incident light onto the photodetector, allowing a small-area photodetector to detect light incident over a larger area than itself. For example, a properly designed combination of a microlens lens and a spacer layer (SL) that separates the microlens from the photodetector by the effective focal length of the microlens may make it possible to focus the incident light into a diffraction-limited spot that is on the order of the square of the optical wavelength of the incident light. Such a scheme may make it possible to reduce the area of ​​the photodetector while mitigating the potential downsides of reducing the area of ​​the photodetector.

[0172] 7A shows a cross-sectional view of an exemplary configuration 700 of a silicon lens integrated with a photodetector. The configuration 700 includes a donor wafer 710 and a carrier wafer 730. The donor wafer 710 includes a plurality of pixels 720a-720c (collectively referred to as pixels 720), vias 714, metal pads 716, and a first bonding layer 712. The carrier wafer 730 includes a second bonding layer 732. The donor wafer 710 and the carrier wafer 730 are bonded to each other through the first bonding layer 712 and the second bonding layer 732. The substrate 710 may be similar to the substrate 502 of FIG. 5A. The absorber region 706 may be similar to the absorber region 506 of FIGS. 5A-5L.

[0173] The pixels 720a to 720c include an absorber region 706a to 706c, respectively, and a microlens 722a to 722c, respectively (collectively referred to as microlens 722). The microlens 722 is a convex lens integrated in or on the donor wafer 710. The addition of the microlens 722 may be beneficial in applications that benefit from high light collection efficiency, such as ToF detection. The convex configuration of the microlens 722 may focus light incident on the microlens 722 toward the absorber region 706, which may improve the light collection efficiency of the pixel 720 and, therefore, improve pixel performance. An arrangement of the pixel 720 in which the microlens 722 is placed on the backside of the donor wafer 710 may be referred to as backside illumination.

[0174] The microlens 722 has various characteristics that affect its performance, including the geometric parameters and materials from which it is formed. The microlens 722 is typically implemented in a plano-convex configuration, with one surface facing the incident light and convex with a radius of curvature, and the other surface being a planar surface that interfaces with the donor wafer 710 in which or on which the microlens 722 is formed. The plano-convex configuration of the microlens 722 itself may be suitable for fabrication through standard semiconductor processing techniques. The microlens 722 may have a height HL and a diameter DL, and may be separated from the lens-facing surface of the absorber region 706 by a height HO. In some implementations, HL may be in the range of 1 to 4 μm, HO may be in the range of 8 to 12 μm, HA may be in the range of 1 to 1.5 μm, and DL may be in the range of 5 to 15 μm. In some implementations, for a spherical microlens 722, its radius of curvature may be set such that the focal length of the microlens 722 is approximately equal to HO for optimal focusing of light onto the absorbing region 706. The determination of the focal length and radius of curvature may be performed using various simulation techniques, such as beam propagation method (BPM) and finite difference time domain (FDTD) techniques. In some implementations, the microlens 722 is an aspheric lens.

[0175] The microlenses 722 may be formed from a variety of materials and fabricated in a variety of ways. In general, a variety of materials may be used that are transparent to the wavelengths detected by the pixels 720. For example, the microlenses 722 may be fabricated from materials having a medium to high index of refraction (e.g., >1.5), such as crystalline silicon, polysilicon, amorphous silicon, silicon nitride, polymers, or combinations thereof. For visible wavelengths, polymeric materials may be used. For NIR wavelengths, silicon may be used because it is relatively transparent in the NIR and has a relatively high index of refraction (approximately 3.5 at 1000 nm), making it well suited as a lens material in the NIR. Furthermore, because silicon strongly absorbs visible wavelengths (e.g., <800 nm), a silicon microlens may block a substantial portion of visible light from reaching the absorbing region 706, which may be beneficial for applications where selective detection of NIR wavelengths is desired (e.g., ToF detection). The crystalline silicon microlenses 722 may be fabricated by patterning and etching the surface of the donor wafer 710, which is typically a crystalline silicon wafer. As another example, polysilicon or amorphous silicon may be deposited on the surface of the donor wafer 710, which may then be patterned and etched in a similar manner. Forming the microlenses 722 through etching of the crystalline silicon donor wafer 710 or by etching of polysilicon or amorphous silicon deposited on the donor wafer 710 are exemplary methods of integrally forming the microlenses 722 on the donor wafer 710.

[0176] The patterning of the microlenses 722 may be performed, for example, using grayscale lithography techniques. In grayscale lithography, the features to be patterned, such as the microlenses, are exposed using a local gradation in radiation dose that translates into a gradual change in the thickness of the resulting developed photoresist mask. For example, the photoresist mask may be patterned to have a similar shape, such as the microlenses 722. The photoresist mask is then transferred onto an underlying material, such as the crystalline silicon donor wafer 710, by a semiconductor etching technique, such as a plasma-based directional etching technique, to complete the fabrication of the microlenses 722. In some implementations, the local gradation in radiation dose may be achieved, for example, by varying a sub-wavelength fill factor on the photomask.

[0177] 5A 。 Carrier wafer 730 may include various electronic circuits coupled to the pixels 720. For example, the electronic circuits may be coupled through structures such as vias 714. The vias 714 are coupled to metal pads 716, which may interface with external electronic components, for example, through wire bonds.

[0178] The carrier wafer 730 and the donor wafer 710 can be bonded or mechanically attached to one another through a variety of techniques. For example, the first and second bonding layers 712 and 732 can be an oxide (e.g., silicon dioxide) and the bond can be an oxide-oxide bond. As another example, the first and second bonding layers 712 and 732 can be a metal (e.g., copper) and the bond can be a metal-metal bond. As yet another example, the first and second bonding layers 712 and 732 can be a combination of an oxide and a metal (e.g., silicon oxide and copper) and the bond can be a hybrid bond.

[0179] 7B shows a cross-sectional view of an exemplary configuration 740 of a microlens integrated with a photodetector. The configuration 740 includes a microlens 742, an anti-reflective coating (ARC) layer 744, a spacer layer 746, a first layer 748, a second layer 750, a silicon layer 752, and a photodetector 754. The ARC layer 744 is supported by the microlens 742. The microlens 742 is supported by the spacer layer 746. The photodetector 754 may be supported by or formed within the silicon layer 752. The first layer 748 and the second layer 750 may be intermediate layers between the silicon layer 752 and the spacer layer 746.

[0180] An ARC layer 744 is provided to reduce reflection of light incident on the microlens 742. The ARC layer 744 can be designed, for example, to have a refractive index that is the square root of the refractive index of the microlens 742 and a thickness that corresponds to ¼ of the incident wavelength. In some implementations, the ARC layer 744 can be formed from silicon dioxide. In some implementations, the ARC layer 744 can include multiple layers to form a multi-layer ARC.

[0181] The configuration 740 may correspond to the integration of the microlens 742 in a backside illuminated (BSI) image sensor configuration. For example, the silicon layer 752 may be a silicon substrate such as the substrate 710 of FIG. 7A or the substrate 502 of FIG. 5D, and the photodetector 754 may be, for example, the switched photodetector 530 of FIG. 5D. The interface between the silicon layer 752 and the second layer 750 may correspond to the bottom surface of the substrate 502 facing the absorbing region 506 of FIG. 5D. In such a BSI configuration, the second layer 750 formed on the silicon layer 752, for example, the backside of the substrate 502, may include various structures and layers that are typical in the processing of BSI illuminated sensor wafers. Examples of such structures and layers include an ARC layer to reduce light reflection at the interface of the silicon layer 752, and a metal grid, such as a tungsten grid, to block light into the silicon layer 752 other than the area for receiving light, such as the area under the microlens 742. The first layer 748 may be a thin layer of material that promotes adhesion of the spacer layer 746 to the second layer 750 to improve manufacturability and reliability of the configuration 740, among other things. The material for the first layer 748 may be, for example, various dielectric materials (e.g., SiO2, SiON, and SiN) or a polymer. In some implementations, the first layer 748 may be omitted depending on the interaction between the second layer 750 and the spacer layer 746 (e.g., if the spacer layer 746 has good adhesion with the second layer 750).

[0182] Configuration 740 provides a sensor wafer including a silicon layer 752, a photodetector 754, and a second layer 750, which may be fabricated by depositing a first layer 748, a spacer layer 746, a microlens 742, and an ARC layer 744 in a given order, and then patterning and etching to expose metal pads similar to metal pads 716 shown in FIG. 7A. Microlens 742 may be patterned and etched using techniques described with respect to fabrication of microlens 722 in FIG. 7A. Although ARC layer 744 is illustrated as being limited to a surface of microlens 742, in general, ARC layer 744 may extend to other surfaces, such as side surfaces of microlens 742 and an upper surface of spacer layer 746.

[0183] Various characteristics of the components of a particular implementation of configuration 740 configured for an operating wavelength of 940 nm are provided by way of example. The microlens 742 has a refractive index of 1.5316, a radius of curvature of 6 μm, a height of 4 μm, and a diameter DL of 10 μm. The ARC layer 744 is formed from SiO2, which has a refractive index of 1.46 at 940 nm and a thickness of 160.96 nm. The spacer layer 746 has a refractive index of 1.5604 and a thickness of 10 μm. The first layer 748 has a refractive index of 1.5507 and a thickness of 60 μm. The second layer 750 includes an ARC layer for a silicon layer 752 and a tungsten grid. Although particular characteristics are presented, the characteristics may be modified to adapt the configuration 740 for different operating wavelengths, materials, and sizes of the photodetector 754, for example.

[0184] In some implementations, the second layer 750, which may be referred to as a "top layer" formed on the back side of the silicon substrate of the BSI image sensor, may be modified to improve the overall optical performance of the configuration 740. The second layer 750, as previously described, typically includes a metal grid embedded in a dielectric layer, such as a tungsten grid embedded in a layer of SiO2. This layer of SiO2 may act as an ARC layer if light were incident on the silicon layer 752 directly from air. However, with the addition of the microlens 742, the spacer layer 746, and the first layer 748, which all have refractive indices significantly higher than that of air (approximately 1.0), the SiO2 layer may not effectively function to reduce the reflection of light at the interface between the silicon layer 752 and the stack of the first layer 748 and / or the spacer layer 746.

[0185] Table 1 shows the simulation parameters and calculated transmittance of one implementation of configuration 740. The layers and thicknesses have been adapted and / or approximated for the purpose of performing simulations that approximate the expected transmittance of different implementations of configuration 740.

[0186] [Table 1]

[0187] Referring to Table 1, Case 1 corresponds to a second layer 750 including a standard single layer of SiO2, resulting in a simulated transmittance of about 79%. For applications where it is important to detect as much incident light as possible, such a 21% loss of incident light may be unacceptable. Such a reduction in transmittance may be mitigated by including a Si3N4 layer in the second layer 750 below the SiO2 layer as an intermediate layer between the SiO2 layer and the silicon layer 752. By including about 121 nm of Si3N4, the transmittance can be improved to about 97.6%. As such, the intermediate layer may be referred to as an anti-reflective layer. In general, various optically transparent materials with refractive indices higher than that of SiO2 may be used in place of Si3N4. Exemplary materials include SiON, SiN, Al2O3, HfO2, ZrO2, and La2O3, as well as high-k materials (e.g., materials with high dielectric constants) that are compatible with CMOS manufacturing processes. Suitable materials may have a refractive index higher than, for example, 1.6, 1.7, 1.8, 1.9, or 2.0 The thickness of the material should be adapted to be an odd multiple of ¼ of the wavelength of light in the material.

[0188] Adding a Si3N4 or high-k material layer directly on top of the silicon layer 752 may result in an increase in dark current of the photodetector 754 due to, for example, increased surface defects at the silicon-Si3N4 interface compared to the silicon-SiO2 interface. To mitigate such an increase in dark current, in some implementations, a second layer of SiO2 may be inserted between the Si3N4 layer and the silicon layer 752. Inserting a second layer of SiO2 with a thickness in the range of 10 nm to 50 nm results in a transmittance in the range of about 97.1% to 85%, respectively. As such, inserting a thin layer of SiO2, such as 10 nm, may be beneficial in mitigating the increase in dark current while maintaining a high optical transmittance.

[0189] As already explained, low leakage current flowing across the control region of the switched photodetector is an important performance parameter because it contributes to lower power consumption of a device that includes the photodetector. Another important aspect of the performance parameter is the dark current flowing between the readout and control regions of the switched photodetector because the dark current contributes to noise in the signal detected by the switched photodetector and reduces the signal-to-noise ratio (SNR) of the measured ToF signal.

[0190] FIG. 8A illustrates an exemplary switch 800 for a switched photodetector. The switch 800 may be used as a first or second switch in the various switched photodetectors described herein. The switch 800 is formed in an absorption region 506 having a first layer 508, previously described with respect to FIG. 5A. The switch 800 comprises an n-type doped region 802, a read contact 804 coupled to the n-type doped region 802, a lightly doped n-type well region 806, a p-type doped region 812, a control contact 814 coupled to the p-type doped region 812, a lightly doped p-type well region 816, and an n-type well region 818. The edges of the n-type doped region 802 and the p-type doped region 812 are separated by a distance S. The n-type doped region 802 and the p-type doped region 812 may be similar to the first n-type doped region 534 and the first p-type doped region 537 of Figure 5E. The n-type well region 818 may be similar to the n-type well region 539 in Figure 5E. The read contact 804 and the control contact 814 may be similar to the first read contact 535 and the first control contact 538 in Figure 5E. The p-type doped region 812 may be the control region and the n-type doped region 802 may be the readout region.

[0191] Sources of dark current in the lateral PIN diode formed by the control region (p-doped region 812), the absorber region 506 (undoped / intrinsic), and the readout region (n-doped region 802) include Shockley-Read-Hall (SRH) generation and band-to-band tunneling. SRH generation can be affected by the presence of surface defects at the surface of the absorber region 506. The addition of the first layer 508 can, in part, reduce the surface defects, which can reduce the dark current due to SRH generation. Increasing the distance S between the n-doped region 802 and the p-doped region 812 can also reduce the dark current due to, for example, a reduction in the electric field between the n-doped region 802 and the p-doped region 812, which in turn reduces the rate of SRH generation between the regions. For example, the distance S should be kept greater than 400 nm. However, increasing the distance S can result in a reduction in the bandwidth of the photodetector due to, for example, an increase in carrier transit time. Adding lightly doped n-type well regions 806, lightly doped p-type well regions 816, or a combination thereof may help overcome such a trade-off.

[0192] Each of the lightly doped regions 806 and 816 has a lower dopant concentration than each of the n-type doped region 802 and p-type doped region 812. For example, the lightly doped regions 806 and 816 have a dopant concentration of 1*10 17 cm -3 It is possible to have a dopant concentration of about 1*10 19 cm -3 The presence of the lightly doped regions provides a region of intermediate dopant concentration that is less than the concentration of n-type doped region 802 and p-type doped region 812, which may have a dopant concentration of about 1*10 15 cm -3The doping concentration of the lightly doped regions 806 and 816 may be set based on various factors such as the switch geometry, the doping concentration of the doped regions 802 and 812, and the absorber region 506, which may have a dopant concentration of about 100 .ANG. or less, thereby reducing the electric field value at the edges of the doped regions 802 and 812. By reducing the electric field value, band-to-band tunneling may also be reduced, which results in a lower dark current between the two doped regions 802 and 812. In addition, the contribution from SRH generation may be reduced. In general, the doping concentration of the lightly doped regions 806 and 816 may be set based on various factors such as the switch geometry, the doping concentration of the doped regions 802 and 812, and the doping concentration of the absorber region 506.

[0193] Figure 8B shows an example switch 820 for a switched photodetector. Switch 820 is similar to switch 800 of Figure 8A, except that instead of lightly doped regions 806 and 816, a trench 822 is formed in absorbing region 506, which is filled with a dielectric fill material 824. Trench 822 filled with dielectric fill material 824 can help reduce dark current.

[0194] The dielectric fill 824 is typically an electrically insulating material with a dielectric constant lower than that of the surrounding absorber region 506. The electric field can penetrate further into the region with the lower dielectric constant compared to the region with the higher dielectric constant. By placing the dielectric filled trench 822 in close proximity to the doped regions 802 and 812, a portion of the high electric field region formed around the doped regions 802 and 812 and in the depletion region ("space charge region") surrounding the doped regions 802 and 812 is pulled into the dielectric fill 824. Thus, SRH generation and / or interband tunneling in the absorber region 506 is reduced. Furthermore, unlike the germanium absorber region 506, the dielectric fill 824, such as SiO2, is an insulator and does not contribute to SRH generation and / or interband tunneling. Thus, dark current generation through SRH generation and / or interband tunneling caused by the high electric field regions at the edges of the doped regions 802 and 812 may be reduced.

[0195] The trench 822 may be formed by etching the absorber region through dry etching (e.g., plasma etching) or wet etching (e.g., liquid chemical bath) techniques. The trench 822 may be etched to a depth similar to that of the doped regions 802 and 812 (e.g., 10-200 nm). The trench 822 should overlap at least a portion of the high electric field region surrounding at least one of the n-type doped region 802 or the p-type doped region 812. In some implementations, the trench 822 is dug into the doped regions 802 and 812, removing a portion of the n-type doped region 802 and the p-type doped region 812. After the trench 822 is formed, the first layer 508 may be deposited over the trench 822 to passivate defects present on the surface of the trench 822. For the germanium absorber region 806, the first layer 508 may be, for example, amorphous silicon, polysilicon, germanium-silicon, or a combination thereof. The trench 822 is then filled with a dielectric fill 824, which may be, for example, SiO2. The dielectric fill 824 should be clean without significant impurity concentrations to avoid the generation of dark current.

[0196] In some implementations, the trench depth may be deeper than the depth of the doped regions 802 and 812. For example, for doped regions 802 and 812 that are about 100 nm deep, a trench depth of 200 nm may further reduce SRH generation and / or band-to-band tunneling. In some implementations, a greater than 50% reduction in SRH generation and / or band-to-band tunneling around the doped regions 802 and 812 may be observed.

[0197] Figure 8C illustrates an example switch 830 for a switched photodetector. Switch 830 is similar to switch 800 of Figure 8A, but further includes trench 822 and dielectric filler 824 of Figure 8B. When lightly doped regions 806 and 816 and trench 822 are implemented simultaneously, band-to-band tunneling, SRH recombination, or a combination thereof may be further reduced compared to when either lightly doped regions 806 and 816 or trench 822 are implemented individually in isolation.

[0198] In general, the reduction of dark current through the use of lightly doped regions 806 and 816 or trench 822 depends on the particular design of the switch and the overall design of the switched photodetector that includes the switch. As such, while the implementation shown in Figure 8C includes both lightly doped regions 806 and 816 and trench 822, the decision to implement lightly doped regions, trenches, or a combination of the two may be based on the particular design of the switched photodetector in which the switch is to be included. Additionally, although a single trench 822 is shown, in general, trench 822 may be split into two or more trenches.

[0199] Although the first layer 508 and the n-type well 818 are included in the implementations shown in Figures 8A-8D, the first layer 508, the n-type well 818, or both may be omitted in some implementations.

[0200] Thus far, various implementations of switched photodetectors and switches for switched photodetectors have been described. Next, details of the various structures and components of switched photodetectors will be described.

[0201] Switched photodetectors are typically fabricated on substrates, such as substrates 102, 202, 302, 402, and 502. A substrate is a carrier material on which a switched photodetector is fabricated. A semiconductor wafer is an example of a substrate. Although the substrate may be part of a switched photodetector, in general, the substrate may simply provide a mechanical platform on which the switched photodetector is fabricated. Substrates may be formed from different materials, such as silicon, germanium, compound semiconductors (e.g., III-V, II-VI), silicon carbide, glass, and sapphire. A substrate may house various layers. For example, a silicon-on-insulator (SOI) substrate includes a base layer of silicon, an insulating layer (e.g., SiO2) on the base layer of silicon, and a device layer of silicon on the layer of insulator. The SOI may include additional device layer-insulating layer pairs. For example, a double SOI (DSOI) wafer includes two device layer-insulating layer pairs.

[0202] The switched photodetector includes an absorption region configured to absorb incident light and convert the absorbed light into charge carriers. Absorption layers 106, 206, 306, and 406, and absorption regions 506 and 706 are examples of absorption regions. The absorption region may be formed from various absorber materials that absorb light at the operating wavelength of the switched photodetector. Exemplary materials for the absorption region include silicon, germanium, IV-IV semiconductor alloys (e.g., GeSn, GeSi), III-V compound semiconductors (e.g., GaAs, InGaAs, InP, InAlAs, InGaAlAs), and other materials in groups III, IV, and V of the periodic table. In some implementations, the absorption region may be a region in a substrate. For example, a region of a silicon substrate may be used as an absorption region for visible light.

[0203] In some implementations, absorbing regions can be defined in the light-absorbing material by changing the material composition (e.g., different GeSi compositions), by doping regions in the absorbing material (e.g., counter-doped regions), or by forming optical windows that transmit light (e.g., tungsten grid openings in a BSI image sensor).

[0204] The absorber material may be deposited on a substrate. For example, the absorber material may be blanket deposited on the substrate. In some implementations, the absorber material may be deposited on an intermediate layer formed on the substrate. In general, the intermediate layer may be selected based on the absorber material, the substrate, or both. Such an intermediate layer may improve device manufacturability and / or improve device performance. Exemplary materials for the intermediate layer include silicon, graded germanium-silicon compound materials, graded III-V materials, germanium, GaN, and SiC. Graded materials refer to materials that vary in material composition along at least one direction. For example, a graded GeSi material may have a composition that varies from 1% germanium at one end of the material to 99% germanium at the other end of the material. In general, the starting and ending compositions may be set based on, for example, the substrate composition and the absorber material composition.

[0205] In some implementations, the absorber material can be epitaxially grown on the intermediate layer in two or more steps. For example, the absorber material (e.g., Ge, GeSi) can be deposited on a dielectric layer with an opening to the underlying substrate (e.g., a crystalline silicon substrate). Such a multi-step growth procedure can improve material quality (e.g., reducing the number of material defects) when the absorber material is deposited on a substrate having a mismatched lattice constant. An example of such a multi-step growth procedure is described in U.S. Pat. No. 9,786,715, entitled "High Efficiency Wide Spectrum Sensor," which is incorporated herein by reference in its entirety.

[0206] 9A-9D show exemplary electrical terminals for use in a switched photodetector. With reference to FIG. 9A, electrical terminal 900 includes region 902, contact metal 904, and doped region 906. Region 902 is the material on which electrical terminal 900 is formed and may correspond to an absorbing region, such as absorber region 506, and a substrate, such as substrate 502. Doped region 906 may be a p-type (acceptor) doped region or an n-type (donor) doped region, depending on the type of dopant. Doped region 906 typically has a high doping concentration (e.g., 1*10) such that an ohmic contact may be formed between contact metal 904 and region 902. 19 From 5*10 20 cm -3 Such a level of doping concentration may be referred to as "degenerate doping."

[0207] Contact metal 904 is a metallic material that contacts region 902 through doped region 906. The contact metal may be selected from a variety of metals and alloys based on the material of region 902 and the dopants of doped region 906. Examples include Al, Cu, W, Ti, Ta-TaN-Cu stacks, Ti-TiN-W stacks, and various suicides.

[0208] 9B, electrical terminal 910 is similar to electrical terminal 900 of FIG. 9A, except that it omits doped region 906. If contact metal 904 were placed directly on region 902 without doped region 906, a Schottky contact, an Ohmic contact, or a combination thereof with intermediate properties between the two may be formed, depending on various factors including the material of region 902, contact metal 904, and impurity or defect levels in region 902.

[0209] 9C, electrical terminal 920 is similar to electrical terminal 910 of FIG. 9B, except that a dielectric layer 922 is inserted between contact metal 904 and region 902. For example, for (crystalline) germanium region 902, dielectric layer 922 may be amorphous silicon, polysilicon, or germanium-silicon. As another example, for (crystalline) silicon region 902, dielectric layer 922 may be amorphous silicon, polysilicon, or germanium-silicon. Inserting dielectric layer 922 may form a Schottky contact, an Ohmic contact, or a combination thereof with intermediate properties between the two.

[0210] 9D, electrical terminal 930 is similar to electrical terminal 910 of FIG. 9B, except that an insulating layer 932 is interposed between contact metal 904 and region 902. Insulating layer 932 prevents direct current from flowing from contact metal 904 to region 902, but allows an electric field to be established in region 902 in response to a voltage being applied to contact metal 904. The established electric field may attract or repel charge carriers in region 902. Insulating layer 932 may be SiO2, Si3N4, or a high-k material.

[0211] A switch, such as the first switch 532 in FIG. 5D, of the switched photodetector comprises a carrier control terminal and a carrier collection (readout) terminal. The carrier control terminal is a terminal configured to direct photo-generated carriers in the region 902 in a particular direction (e.g., toward the carrier collection terminal) by applying a control voltage, for example, through an external bias circuit. The operation of the carrier control terminal is described with respect to the control signals 122 and 132 in FIG. 1A. Different types of electrical terminals may be used to implement the carrier control terminal. For example, electrical terminals 900, 910, 920, and 930 may be used to implement the carrier control terminal.

[0212] The carrier collection terminal is a terminal configured to collect photo-generated carriers in region 902. The carrier collection terminal may be configured to collect electrons (e.g., n-type doped region 906) or holes (e.g., p-type doped region 906). The operation of the carrier collection terminal is described with respect to readout circuits 124 and 134 in FIG. 1A. Different types of electrical terminals may be used to implement the carrier collection terminal. For example, electrical terminals 900, 910, and 920 may be used to implement the carrier collection terminal.

[0213] The number of carrier control terminals and carrier collection terminals may vary based on various considerations, such as target device performance. By way of example, a switched photodetector may have the following exemplary configurations: two carrier control terminals and two carrier collection terminals, two carrier control terminals and one carrier collection terminal, four carrier control terminals and two carrier collection terminals, and four carrier control terminals and four carrier collection terminals. In general, a switched photodetector may have any number of carrier control terminals and carrier collection terminals greater than one.

[0214] Furthermore, when two or more control terminals are implemented in a switched photodetector, various combinations of the electrical terminals previously described may be used, such as ohmic and Schottky / ohmic terminals (e.g., terminals 900 and 920), ohmic and insulating (e.g., terminals 900 and 930), insulating and Schottky / ohmic (e.g., terminals 930 and 920), and ohmic and Schottky / ohmic and insulating (e.g., terminals 900, 920, and 930).

[0215] Additionally, when two or more carrier collection terminals are implemented in a switched photodetector, a combination of ohmic and Schottky / ohmic terminals (eg, terminals 900 and 920) may be used.

[0216] The electrical terminals may have various shapes based on various considerations, such as manufacturability and device performance. FIG. 9E shows an example top view of various shapes of the electrical terminals. The terminals 940 may be rectangular, triangular, circular, polygonal in shape, or a combination of such shapes. The corners of the terminals may be sharp or rounded. The shapes may be defined using doped regions, metal silicides, contact metals, or any combination thereof.

[0217] The absorbent regions and substrate may be arranged in various configurations, and the absorbent regions may take on various shapes based on various considerations, such as manufacturability and device performance. With reference to FIGS. 10A-10I, exemplary configurations of absorbent regions and substrates are illustrated. In particular, with reference to FIG. 10A, configuration 1000 includes a substrate 1002 and an absorbent region 1004 protruding from an upper surface of the substrate 1002. The substrate 1002 may be similar to the substrate 502 described with reference to FIG. 5D, and the absorbent region 1004 may be similar to the absorbent region 506 described with reference to FIG. 5D. Configuration 1000 may be fabricated by depositing the absorbent region 1004 on the substrate 1002 and etching the absorbent region 1004 into a protruding structure.

[0218] 10B, configuration 1010 is similar to configuration 1000 of FIG. 10A, but now includes an intermediate layer 1006 between the absorber region 1004 and the substrate 1002. The intermediate layer may be a buffer layer that facilitates the growth of the absorber region 1004 on the substrate 1002. Configuration 1010 may be fabricated by depositing the intermediate layer 1006 on the substrate 1002, depositing the absorber region 1004 on the intermediate layer 1006, and etching the absorber region 1004 and the intermediate layer 1006 into protruding structures.

[0219] 10C, configuration 1020 is similar to configuration 1000 of FIG. 10A, but here, absorber regions 1004 are partially embedded within substrate 1002. Configuration 1020 may be fabricated by forming recesses on substrate 1002 and selectively depositing absorber regions 1004 within the formed recesses. Alternatively, configuration 1020 may be fabricated by depositing a sacrificial layer over substrate 1002, etching through the deposited sacrificial layer to form recesses in substrate 1002, selectively depositing absorber material, removing the absorber material deposited outside the recesses by performing a planarization step, such as a chemical mechanical polishing (CMP) step, and removing the sacrificial layer through a selective etch, such as a wet chemical etch.

[0220] 10D, configuration 1030 is similar to configuration 1020 of FIG. 10C, except here, the absorber region 1004 is completely embedded within the substrate 1002. Configuration 1030 may be fabricated by forming a recess in the substrate 1002, depositing a selective layer of absorber material over the substrate 1002, and removing the absorber material deposited outside the recess by performing a planarization step, such as a chemical mechanical polishing (CMP) step.

[0221] 10E, configuration 1040 is similar to configuration 1030 of FIG. 10D, but here, intermediate layer 1006 is interposed within a recess between absorber region 1004 and substrate 1002. Configuration 1040 may be fabricated by forming a recess in substrate 1002, depositing a conformal layer of intermediate layer 1006, depositing a blanket layer of absorber material over intermediate layer 1006, and removing the absorber material and intermediate layer deposited outside the recess by performing a planarization step, such as a chemical mechanical polishing (CMP) step.

[0222] 10F, configuration 1050 is similar to configuration 1040 of FIG. 10E, except that here, second interlayer 1008 replaces first interlayer 1006 at the interface between the sidewalls of absorber region 1004 and the sidewalls of the recess in substrate 1002. Configuration 1050 may be fabricated by forming a recess in substrate 1002, depositing a conformal layer of second interlayer 1008, performing an anisotropic blanket etch to remove second interlayer 1008 along vertical surfaces, depositing a conformal layer of first interlayer 1006, performing an anisotropic blanket etch to remove first interlayer 1006 along non-vertical surfaces, depositing a selective layer of absorbent material, and removing the absorbent material and first interlayer deposited outside the recess by performing a planarization step, such as a chemical mechanical polishing (CMP) step. In one exemplary implementation, the first intermediate layer 1006 may be formed from SiO 2 and the second intermediate layer 1008 may be formed from GeSi.

[0223] 10G, configuration 1060 is similar to configuration 1000 of FIG. 10A, but now includes a stepped interlayer 1062 in which an absorber region 1004 is embedded. The stepped interlayer 1062 includes an opening 1064 to the substrate 1002 and a recess 1066 in which the absorber region 1004 is embedded. The absorber region 1004 contacts the substrate 1002 through the opening 1064. Configuration 1060 may be fabricated by depositing an interlayer on the substrate 1002, etching the opening 1064 through the entire thickness of the deposited interlayer, etching the recess 1066 in the deposited interlayer, depositing the absorber region 1004 on the stepped interlayer 1062, and removing the absorber material deposited outside of the recess 1066 by performing a planarization step, such as a chemical mechanical polishing (CMP) step.

[0224] 10H, configuration 1070 is similar to configuration 1060 of FIG. 10G, but now includes a second interlayer 1072 in which a recess 1066 is formed. Configuration 1070 may be fabricated by depositing a first interlayer 1062 on substrate 1002, depositing a second interlayer 1072, etching an opening 1064 through first interlayer 1062 and second interlayer 1072, etching a recess 1066 in second interlayer 1072, depositing an absorber region 1004, and removing the absorber material deposited outside of the recess 1066 by performing a planarization step, such as a chemical mechanical polishing (CMP) step.

[0225] 10I, configuration 1080 is similar to configuration 1040 of FIG. 10E, but now includes an opening 1084 formed on intermediate layer 1006. Absorber region 1004 contacts substrate 1002 through opening 1084. Configuration 1080 may be fabricated by forming a recess in substrate 1002, depositing a conformal layer of intermediate layer 1006, etching opening 1084, depositing a blanket layer of absorber material over intermediate layer 1006, and removing the absorber material and intermediate layer deposited outside of the recess by performing a planarization step, such as a chemical mechanical polishing (CMP) step.

[0226] The absorber region, carrier control terminals, and carrier collection terminals may be arranged in various configurations based on various considerations, such as manufacturability and device performance. FIGS. 11A-11B show top and side views of an exemplary switched photodetector 1100 in which the carrier control terminals and carrier collection terminals are disposed on a substrate, and a portion of the substrate is an absorber region. In this example, the switched photodetector 1100 comprises a substrate 1102, an absorber region 1104, a carrier collection terminal 1106, and a carrier control terminal 1108. The absorber region 1104 is a region within the substrate 1102. For example, for a silicon substrate 1102, the absorber region 1104 is formed of silicon, and the absorber region 1104 may absorb visible light. The absorber region 1104 may have various shapes, for example, a square shape in the top view of the photodetector 1100. The absorber region 1104 may penetrate from the upper surface of the substrate 1102 to a desired depth below the upper surface. For example, the absorber region 1104 may extend 1 μm, 2 μm, 3 μm, 5 μm, or 10 μm below the upper surface of the substrate 1102. Adjacent pairs of carrier collection terminals 1106 and carrier control terminals 1108 form a switch. The absorber region 1104 is arranged between adjacent pairs of carrier collection terminals 1106 and carrier control terminals 1108. In some implementations, adjacent pairs of carrier collection terminals and carrier control terminals are arranged symmetrically around the absorber region 1104 (e.g., on opposite sides or four sides of the absorber region 1104). Such a symmetric arrangement may improve matching of the carrier control and collection performance of the two switches formed by these pairs.

[0227] 11C-11F show top and side views of an exemplary switched photodetector in which the absorber region is formed from a different material than the substrate. Referring to FIG. 11C-11D, the switched photodetector 1120 includes a substrate 1102, an absorber region 1124, a carrier collection terminal 1106, and a carrier control terminal 1108. FIG. 11C shows a top view of the switched photodetector 1120, and FIG. 11D shows a side view of the switched photodetector 1120. The switched photodetector 1120 is similar to the switched photodetector 1100 of FIG. 11A-11B, except that the absorber region 1124 of the switched photodetector 1120 is formed from a different material than the substrate 1102. For example, the absorber region 1124 may be formed from germanium and the substrate 1102 may be a silicon substrate. The absorber region 1124 is completely embedded within a recess formed in the substrate 1102. Although specific details of the embedded structure are not shown, the embedded absorber region 1124 may be implemented, for example, as described with respect to Figures 10D-10F and 5C.

[0228] 11E, a switched photodetector 1130 is similar to the switched photodetector 1120 of FIGURES 11C-11D, except that here, the absorbing region 1124 is partially embedded within the substrate 1102. Although specific details of the partially embedded structure are not shown, the partially embedded absorbing region 1124 may be implemented, for example, as described with respect to FIGURES 10C and 5B.

[0229] 11F, switched photodetector 1140 is similar to switched photodetector 1120 of Figures 11C-11D, except that here, absorbing region 1124 is fully protruding above substrate 1102. Although specific details of the fully protruding structure are not shown, fully protruding absorbing region 1124 may be implemented as described, for example, with respect to Figures 10A-10B and 5A.

[0230] In some configurations of the switched photodetector, the carrier collection terminal, the carrier control terminal, or both may be located on the absorbing region. Details of the implementation of the substrate, the absorbing region, the carrier control terminal, and the carrier collection terminal are omitted for brevity. FIGS. 12A-12B show top and side views of an exemplary switched photodetector 1200 in which the carrier collection terminal is located on the substrate and the carrier control terminal is located on the absorbing region. The switched photodetector 1200 comprises a substrate 1202, an absorbing region 1204, a light receiving region 1205, a carrier collection terminal 1206, and a carrier control terminal 1208. The light receiving region 1205 may indicate the portion of the absorbing region 1204 on which the input light is incident and may be physically indistinguishable from the remainder of the absorbing region 1204. For example, a combination of a light blocking body (e.g., a tungsten grid) and a microlens may block and focus the incident light onto the light receiving region 1205. A carrier collection terminal 1206 is disposed on the substrate 1202, and a carrier control terminal 1208 is disposed on the absorbing region 1204 in a position that does not overlap the light receiving region 1205. For the switched photodetector 1200, the absorbing region 1204 is fully protruding. The absorbing region 1204 may be partially recessed as shown in FIG. 12C for the switched photodetector 1220, or fully recessed as shown in FIG. 12D for the switched photodetector 1230.

[0231] 12E-12F show top and side views of an exemplary switched photodetector 1240 in which both the carrier collection and carrier control terminals are placed on the absorbing region. The switched photodetector 1240 is similar to the switched photodetector 1200 of FIGS. 12A-12B, except that the carrier collection terminal 1206 is placed on the absorbing region 1204 in a position that does not overlap the light receiving region 1205. For the switched photodetector 1240, the absorbing region 1204 is fully protruding. The absorbing region 1204 can be partially embedded as shown in FIG. 12G for the switched photodetector 1250, or fully embedded as shown in FIG. 12H for the switched photodetector 1260.

[0232] 12A-12H are illustrated as not overlapping with the carrier collection or carrier control terminals, in general, the light receiving region 1205 may overlap at least a portion of the carrier control terminal, at least a portion of the carrier collection terminal, and at least a portion of the various n-type or p-type doped regions. For example, such overlap may be present for pixels used in both FSI and BSI configurations.

[0233] In some configurations of switched photodetectors, each switch may include multiple carrier collection terminals, multiple carrier control terminals, or multiple of both. Details of the implementation of the substrate, absorber region, light-receiving region, carrier control terminal, and carrier collection terminal are omitted for brevity. FIGS. 13A-13G show top views of an exemplary switched photodetector having a switch including multiple carrier control terminals or multiple carrier collection terminals. Referring to FIG. 13A, switched photodetector 1300 includes substrate 1302, absorber region 1304, light-receiving region 1305, substrate carrier collection terminal 1306, substrate carrier control terminal 1308, and absorber carrier control terminal 1309. Substrate carrier collection terminal 1306 is a carrier collection terminal that is disposed on a substrate, such as substrate 1302. Substrate carrier control terminal 1308 is a carrier control terminal that is disposed on a substrate, such as substrate 1302. The absorber carrier control terminal 1309 is a carrier control terminal that is located on an absorber region, such as absorber region 1304. The effect and implementation details of the absorber carrier control terminal 1309 in combination with the substrate carrier control terminal 1308 are described with respect to Figure 5K. In some implementations, the illustrated arrangement of the substrate carrier collection terminal 1306, the substrate carrier control terminal 1308, and the absorber carrier control terminal 1309 may be repeated in a second row as shown in Figure 13B.

[0234] 13B, switched photodetector 1310 is similar to switched photodetector 1300 of FIG. 13A, except that the substrate carrier control terminals 1308 are omitted and a second row of pairs of terminals 1306 and 1309 is added. The second pair of control and collection terminals may function independently or in combination with the first pair of control and collection terminals adjacent to the second pair of terminals.

[0235] 13C, a switched photodetector 1320 is similar to the switched photodetector 1310 of FIG. 13B, except that one of the substrate carrier collection terminals 1306 is removed from each side of the light receiving area 1305. A pair of absorber carrier control terminals 1309 on each side of the light receiving area 1305 in combination with the respective substrate carrier collection terminals 1306 can function as a switch.

[0236] Referring to FIG. 13D, switched photodetector 1330 is similar to switched photodetector 1310 of FIG. 13B, except that the carrier collection terminal 1306 of the substrate has been moved onto the absorbing region 1304 as the carrier collection terminal 1307 of the absorber.

[0237] 13E, a switched photodetector 1340 is similar to the switched photodetector 1330 of FIG. 13D, except that one of the absorber carrier collection terminals 1307 is removed from each side of the light receiving area 1305. A pair of absorber carrier control terminals 1309 on each side of the light receiving area 1305 in combination with the respective absorber carrier collection terminal 1307 can function as a switch.

[0238] 13F, a switched photodetector 1350 is similar to the switched photodetector 1330 of FIG. 13D, except that one of the absorber carrier control terminals 1309 is removed from each side of the light receiving area 1305. The pair of absorber carrier collection terminals 1307 on each side of the light receiving area 1305 in combination with the respective absorber carrier control terminal 1309 can function as a switch.

[0239] Referring to FIG. 13G, the switched photodetector 1360 is similar to the switched photodetector 1330 of FIG. 13D, except that four pairs of absorber carrier collection terminals 1307 and carrier control terminals 1309 are now arranged symmetrically around the light receiving area 1305. Each pair of terminals 1307 and 1309 can function as a switch. Each switch can function independently or in conjunction with another switch. For example, the east and west switches can be controlled as a first switch and the north and south switches can be controlled as a second switch. As another example, the east and south switches can be controlled as a first switch and the west and north switches can be controlled as a second switch.

[0240] 13A-13G are illustrated as not overlapping with the carrier collection or carrier control terminals, in general, the light receiving region 1305 may overlap at least a portion of the carrier control terminal, at least a portion of the carrier collection terminal, and at least a portion of the various n-type or p-type doped regions. For example, such overlap may be present for pixels used in both FSI and BSI configurations.

[0241] For switches with two or more carrier control terminals, the carrier control terminals may be independently biased with independently controlled bias voltages, or the carrier control terminals may be shorted together and biased with a single bias voltage. FIGS. 14A-14B show top views of an exemplary switched photodetector having a switch including multiple carrier control terminals. Referring to FIG. 14A, the switched photodetector 1400 is similar to the switched photodetector 1300 of FIG. 13A. To the left of the light receiving area 1305, the carrier collection terminal 1306 of the substrate, the carrier control terminal 1308 of the substrate, and the carrier control terminal 1309 of the absorber form a first switch 1410. To the right of the light receiving area 1305, the carrier collection terminal 1306 of the substrate, the carrier control terminal 1308 of the substrate, and the carrier control terminal 1309 of the absorber form a second switch 1420.

[0242] In the switches 1410 and 1420, the substrate carrier control terminal 1308 and the absorber carrier control terminal 1309 may be shorted together and biased with a single bias voltage or biased with independently controlled bias voltages. For example, the substrate carrier control terminal 1308 of the first switch 1410 is biased with a voltage VB1 and the absorber carrier control terminal 1309 is biased with a voltage VA1. Similarly, the substrate carrier control terminal 1308 of the second switch 1420 is biased with a voltage VB2 and the absorber carrier control terminal 1309 is biased with a voltage VA2. In some implementations, the control terminals located near the light receiving region 1305, such as the absorber carrier control terminal 1309, may be biased with respective control voltages VA1 and VA2 to direct photogenerated carriers in the light receiving region 1305 toward the substrate carrier collection terminal 1306, which is biased with voltages VC1 and VC2 as shown. At the same time, the substrate control terminal 1308 may be biased to voltages VB1 and VB2, establishing a high electric field between the substrate control terminal 1308 and the substrate carrier collection terminal 1306. If the electric field between the terminals 1308 and 1306 is high enough, a region of avalanche multiplication may be established between the terminals 1308 and 1306, providing avalanche gain to the photo-generated carriers guided by the absorber carrier control terminal 1309 towards the substrate carrier collection terminal 1306. As a result, the photo-generated carriers may be multiplied by the avalanche gain, which may increase the photocurrent signal generated by the switched photodetector 1400.

[0243] Referring to Figure 14B, a switched photodetector 1430 is similar to the switched photodetector 1400 of Figure 14A, except that the carrier collection terminal 1306 of the substrate has been relocated above the absorbing region 1304 as the carrier collection terminal 1407 of the absorber, and the carrier control terminal 308 of the substrate has been relocated above the absorbing region 1304 as the carrier control terminal 1409 of the absorber. The effect of different biases on the terminals is similar to that described with respect to Figure 14A.

[0244] 14A-14B are illustrated as not overlapping with the carrier collection or carrier control terminals, in general, the light receiving region 1305 may overlap at least a portion of the carrier control terminal, at least a portion of the carrier collection terminal, and at least a portion of the various n-type doped or p-type doped regions. For example, such overlap may be present for pixels used in both FSI and BSI configurations.

[0245] In a typical implementation of an image sensor, multiple sensor pixels (e.g., photodetectors) are arranged in an array such that the image sensor can capture an image having multiple image pixels. To achieve high integration density, multiple sensor pixels are typically arranged in close proximity to each other on a common substrate. For semiconductor substrates such as p-type doped silicon substrates, the close proximity of the sensor pixels can cause electrical and / or optical crosstalk between the sensor pixels, for example, reducing the signal-to-noise ratio of the sensor pixels. As such, various isolation structures can be implemented to improve electrical isolation between the sensor pixels.

[0246] 15A-15G show cross-sectional views illustrating an exemplary configuration of a sensor pixel isolation. Referring to FIG. 15A, an exemplary configuration 1500 includes a substrate 1502, sensor pixels 1510a and 1510b (collectively sensor pixels 1510), and an isolation structure 1506. The sensor pixels 1510a and 1510b include respective absorbing regions 1504a and 1504b. Each sensor pixel 1510 may be a switched photodetector, such as the switched photodetector of FIGS. 5A-5L. Details of the sensor pixels 1510 have been omitted for clarity.

[0247] The isolation structure 1506 may enhance electrical isolation between the sensor pixels 1510a and 1510b. In the configuration 1500, the isolation structure extends from the upper surface of the substrate 1502 and penetrates from the upper surface to a predetermined depth. In some implementations, the isolation structure 1506 is a doped region that is doped with a p-type dopant or an n-type dopant. The doping of the isolation structure 1506 may form a potential energy barrier caused by a band gap offset that prevents current from flowing across the isolation structure 1506, improving the electrical isolation between the pixels 1510a and 1510b. In some implementations, the isolation structure 1506 is a trench filled with a semiconductor material different from the substrate 1502. The interface between the two different semiconductors formed between the substrate 1502 and the isolation structure 1506 may form a potential energy barrier caused by a band gap offset that prevents current from flowing across the isolation structure 1506, improving the electrical isolation between the pixels 1510a and 1510b.

[0248] In some implementations, the isolation structure 1506 is a trench filled with a dielectric or insulator. Filled with a low conductivity dielectric or insulator, the isolation structure 1506 provides a region of high electrical resistance between the sensor pixels 1510a and 1510b, which can prevent current from flowing across the isolation structure 1506 and improve electrical isolation between the pixels 1510a and 1510b.

[0249] Although a single isolation structure 1506 is illustrated, in general, multiple isolation structures 1506 may be arranged between each adjacent pair of sensor pixels 1510. For example, in a 2D array of sensor pixels 1510, a single sensor pixel 1510 may be surrounded by four nearest neighbor sensor pixels 1510. In such a case, the isolation structure 1506 may be placed along the four nearest interface interfaces. In some implementations, the isolation structure 1506 may be a continuous structure that surrounds the sensor pixel 1510. The isolation structure 1506 may be shared at the interface between the pixels 1510.

[0250] With reference to FIG. 15B, an exemplary configuration 1520 is similar to configuration 1500 of FIG. 15A, except that absorbing regions 1504a and 1504b are embedded entirely within substrate 1502.

[0251] 15C, an example configuration 1530 is similar to the configuration 1500 of FIG. 15A, except that the isolation structures 1506 extend through the entire depth of the substrate 1502 from an upper surface of the substrate 1502 to a lower surface of the substrate 1502. The configuration 1530 may eliminate an alternative conduction path between the sensor pixels 1510 that bypasses the isolation structures 1506, and may improve electrical isolation between the sensor pixels 1510.

[0252] With reference to FIG. 15D, an exemplary configuration 1540 is similar to configuration 1530 of FIG. 15C, except that absorbing regions 1504a and 1504b are embedded completely within substrate 1502.

[0253] 15E, an exemplary configuration 1550 includes a substrate 1502, sensor pixels 1510a and 1510b (collectively referred to as sensor pixels 1510), and isolation structures 1556a and 1556b (collectively referred to as isolation structures 1556). The isolation structures 1556a and 1556b are similar to the isolation structures 1506 described with respect to FIG. 15A, except that the isolation structures 1556 are arranged in a portion of the substrate 1502 directly below the respective absorption regions 1504. Such an arrangement of the isolation structures 1556 between the absorption regions 1504 and the substrate 1502 may help confine the photo-generated carriers to the absorption regions 1504 and help reduce leakage of the photo-generated carriers into the substrate 1502. For example, the sensor pixels 1510a and 1510b may be implemented as the switched photodetector 530 of FIG. 5D, which has all electrical terminals on the absorption regions 1504. In such cases, the electrical isolation provided by the isolation structure 1556 (eg, a thin p-type doped layer) may improve the photocurrent collection efficiency and / or bandwidth of the sensor pixel 1510.

[0254] 15F, an exemplary configuration 1560 is similar to the configuration 1550 of FIG. 15E, except that the absorber regions 1504a and 1504b are fully embedded within the substrate 1502, and the isolation structure 1556 partially or completely surrounds the absorber region 1504. For isolation structures 1556 formed from an insulator or dielectric, the isolation structure 1556 may include an opening below the absorber and partially surround the buried absorber region 1504. For isolation structures 1556 that are doped regions, the isolation structure 1556 may be a continuous structure that completely surrounds the buried absorber region 1504 without an opening.

[0255] Although isolation structures that are doped regions, dielectric materials, or insulators have been described, in general, the isolation structures may be a combination of such implementations. Referring to FIG. 15G, an exemplary configuration 1570 is similar to the configuration 1500 of FIG. 15A, except that the isolation structure 1506 includes a first isolation structure 1576 and a second isolation structure 1577. The first isolation structure 1576 may be a trench filled with a semiconductor material different from the substrate 1502 or a trench filled with a dielectric or insulator. The second isolation structure 1577 may be a doped region doped with a p-type dopant or an n-type dopant. The isolation structure 1506 that implements both different materials and doped regions may further improve the electrical isolation between the sensor pixels 1510 than an isolation structure that implements them in isolation. In some implementations, doping isolation may be used to form a second isolation structure 1577, while material isolation through trench fill may be used to form a first isolation structure 1576 in which the doping isolation is shallower than the material isolation.

[0256] The light detection efficiency of a photodetector, such as a switched photodetector, can be enhanced by the addition of various structures that modify the optical properties of the photodetector. For example, mirrors, dielectric layers, and anti-reflective coating (ARC) layers can be added alone or in combination to achieve various effects including increased absorption of light by an absorbing region, formation of an optical resonant cavity, and / or change in the spectral sensitivity of the photodetector. FIGS. 16A-16J show cross-sectional views of exemplary configurations for improving the detection efficiency of a photodetector. Referring to FIG. 16A, an exemplary configuration 1600 includes a substrate 1602, an absorbing region 1604, and a metallic mirror 1606. The absorbing region 1604 forms a photodetector. The metallic mirror 1606 reflects incident light.

[0257] The optical signal 1605 is incident on the absorbing region 1604 from above as shown, which may be referred to as a front-side illuminated (FSI) configuration. In such a configuration, in some cases, the optical signal 1605 may not be completely absorbed by the absorbing region 1604, and a portion of the optical signal 1605 may pass through the absorbing region 1604. Such light that passes through the absorbing region 1604 without being absorbed may reduce the detection efficiency of the photodetector. By placing a metal mirror 1606 on the lower surface of the substrate 1602 to reflect the passed portion of the optical signal 1605, the passed portion may be reflected back towards the absorbing region 1604 for a second pass through the absorbing region 1604, improving the detection efficiency.

[0258] The portion of the optical signal 1605 absorbed by the absorbing region 1604 may vary depending on the optical absorption coefficient of the absorbing region 1604, the thickness of the absorbing region 1604 along the direction of light incidence (e.g., along the perpendicular direction), and the wavelength of the optical signal 1605.

[0259] The metallic mirror 1606 may be formed from a variety of optically reflective metals, such as copper, aluminum, gold, and platinum. The metallic mirror 1606 may have a reflectivity of greater than 50%, 60%, 70%, 80%, 90%, or 95% at the operating wavelength of the photodetector of the configuration 1600. The thickness of the metallic mirror 1606 may be greater than the skin depth of the metal. For example, the metallic mirror 1606 may have a thickness in the range of 50 nm to 500 nm.

[0260] 16B, an exemplary configuration 1610 is similar to the configuration 1600 of FIG. 16A, except that the exemplary configuration 1610 further includes a dielectric layer 1608 disposed between the substrate 1602 and the metallic mirror 1606. The dielectric layer 1608 can change the light reflectance spectrum of the metallic mirror 1606. For example, due to thin film interference caused by the dielectric layer 1608 (e.g., a SiO2 layer), the reflection of light incident on the metallic mirror 1606 (e.g., an Al layer) can be enhanced at certain wavelengths (e.g., reflectivity is enhanced from <90% to >97%) and decreased at some other wavelengths.

[0261] Referring to FIG. 16C, an exemplary configuration 1620 is similar to the configuration 1600 of FIG. 16A, except that the metal mirror 1606 of the configuration 1600 is replaced with a dielectric mirror 1626. The dielectric mirror may be a single layer of a dielectric film or a stack of various dielectric films. The dielectric mirror 1626 may be formed from various dielectric materials such as SiO2, Si3N4, SiON, and Si. The dielectric mirror 1626 may have a reflectivity of more than 50%, 60%, 70%, 80%, 90%, or 95% at the operating wavelength of the photodetector of the configuration 1620. The thickness of the dielectric mirror 1626 may be in the range of 50 nm to 4000 nm.

[0262] Referring to FIG. 16D, an exemplary configuration 1630 is similar to the configuration 1620 of FIG. 16C, except that the dielectric mirror 1626 of the configuration 1620 is replaced with a distributed Bragg reflector (DBR) mirror 1632. The DBR mirror comprises a plurality of first dielectric layers 1634 and a plurality of second dielectric layers 1636 stacked on top of each other in an alternating manner. The second dielectric layers 1636 have a refractive index different from that of the first dielectric layers 1634. The first layers 1634 and the second layers 1636 may have a thickness corresponding to ¼ of the operating wavelength in the respective dielectric materials. The reflectivity and reflection bandwidth may depend on the thickness, the refractive index of the first layers 1634 and the second layers 1636, and the number of pairs of first layers.

[0263] 16E, an example configuration 1640 includes a substrate 1602, an absorptive region 1604, and an anti-reflective coating (ARC) layer 1648. The ARC layer 1648 may reduce reflection of an optical signal 1605 incident on the absorptive region 1604. The ARC layer 1648 may be similar to the ARC layer 744 of FIG.

[0264] Referring to Figure 16F, an exemplary configuration 1650 is similar to the configuration 1600 of Figure 16A, except that now a metallic mirror 1606 is placed on the upper surface of the substrate 1602, on the side of the absorbing region 1604. The optical signal 1605 is now incident on the absorbing region 1604 through the lower surface of the substrate 1602, which may be referred to as a back-side illuminated (BSI) configuration. The effect of the metallic mirror 1606 is similar to that described with respect to Figure 16A.

[0265] 16G, an exemplary configuration 1660 is similar to the configuration 1610 of FIG. 16B, except that here a dielectric layer 1608 and a metallic mirror 1606 are placed on the upper surface of the substrate 1602, at the side of the absorbing region 1604. The optical signal 1605 is now incident on the absorbing region 1604 through the lower surface of the substrate 1602, which may be referred to as a back-side illuminated (BSI) configuration. The effect of the dielectric layer 1608 and the metallic mirror 1606 is similar to that described with respect to FIG. 16B.

[0266] Referring to Figure 16H, an exemplary configuration 1670 is similar to the configuration 1620 of Figure 16C, except that now a dielectric mirror 1626 is placed on the upper surface of the substrate 1602, on the side of the absorbing region 1604. The optical signal 1605 is now incident on the absorbing region 1604 through the lower surface of the substrate 1602, which may be referred to as a back-side illuminated (BSI) configuration. The effect of the dielectric mirror 1626 is similar to that described with respect to Figure 16C.

[0267] Referring to Figure 16I, an exemplary configuration 1680 is similar to the configuration 1630 of Figure 16D, except that now a DBR mirror 1632 is placed on the upper surface of the substrate 1602, at the side of the absorbing region 1604. The optical signal 1605 is now incident on the absorbing region 1604 through the lower surface of the substrate 1602, which may be referred to as a back-side illuminated (BSI) configuration. The effect of the DBR mirror 1632 is similar to that described with respect to Figure 16D.

[0268] 16J, an exemplary configuration 1690 is similar to the configuration 1640 of FIG. 16E, except that now an ARC layer 1648 is placed on the lower surface of the substrate 1602, on the side of the substrate 1602 opposite the absorbing region 1604. The optical signal 1605 is now incident on the absorbing region 1604 through the lower surface of the substrate 1602, which may be referred to as a back-side illuminated (BSI) configuration. The effect of the ARC layer 1648 is similar to that described with respect to FIG. 16E.

[0269] In general, the mirror structures, such as the metal mirror 1606, the dielectric layer 1608, the dielectric mirror 1626, and the DBR mirror 1632, may be fabricated in a variety of ways. For example, the mirror structures may be deposited directly on the substrate 1602. Alternatively, or in addition, the mirror structures may be fabricated on a separate substrate and bonded to the substrate 1602 through wafer bonding techniques.

[0270] Although individual implementations are shown having the metal mirror 1606, the dielectric layer 1608, the dielectric mirror 1626, and the DBR mirror 1632 on the lower or upper surface of the substrate 1602, in general, the described structures may be implemented on both sides of the substrate 1602. For example, the DBR mirror 1632 may be implemented on both sides of the substrate 1602, which may form an optical resonant cavity around the absorbing region 1604, modifying the spectral sensitivity of the photodetector. As another example, the ARC layer 1648 may be implemented on the upper surface of the substrate 1602 in combination with a mirror structure on the lower surface of the substrate 1602 (e.g., configurations 1600, 1610, 1620, and 1630) to further enhance the detection efficiency of the photodetector. In general, mirrors such as the metal mirror 1606, the dielectric layer 1608, the dielectric mirror 1626, and the DBR mirror 1632 may be partially reflective and partially transmissive.

[0271] The surface of the absorber region can be modified in various ways to modify various performance characteristics of the photodetector. Examples of modifying the surface of the absorber region include adding doped regions, introducing external elements, changing the material composition, introducing surface irregularities on the surface of the absorber region, and depositing dielectric or semiconductor materials. Examples of performance characteristics include light absorption efficiency, light absorption spectrum, carrier collection efficiency, dark or leakage current, photodetector operating power, and photodetector bandwidth.

[0272] 17A-17E show cross-sectional views of example configurations of absorber region surface modifications. With reference to FIG. 17A, surface modified absorber region 1700 includes germanium-silicon based absorber region 1704 and surface modification layer 1706. Germanium-silicon based absorber region 1704 may be the absorber region of a switched photodetector, such as switched photodetector 530 of FIG. 5D.

[0273] The GeSi-based absorption region 1704 is a Si x Ge 1-xThe composition (X) may be a compound. For example, the composition (X) may vary from 0.01, at which the GeSi-based absorbing region 1704 may have properties closer to Ge, to 0.99, at which the GeSi-based absorbing region 1704 may have properties closer to Si. The composition of the GeSi-based absorbing region may affect the light absorption efficiency for a given wavelength and may also affect the overall light absorption spectrum. For example, a composition with a lower (X), corresponding to a higher Ge concentration, may absorb more strongly at near-infrared wavelengths (e.g., >1 μm) compared to a composition with a higher (X), corresponding to a higher Si composition.

[0274] The surface modification layer 1706 can modify the optical and / or electrical properties of the GeSi-based absorber region 1704 and the photodetector that includes the absorber region 1704. The surface modification layer can be formed of amorphous silicon, polysilicon, epitaxial silicon, Si with varying composition (Y), or a combination of both. Y Ge 1-Y Compounds, Ge with variable composition (Z) Z Sn 1-Z The material may be formed from a variety of materials, such as, for example, aluminum, copper, silver, arsenic, tantalum, tungsten, tantalum, carbide, carbide-containing, carbide-containing compounds, and any combination thereof.

[0275] In some implementations, Si x Ge 1-x For a GeSi-based absorber region 1704 having a composition, the surface modification layer 1706 is Si Y Ge 1-Ylayer, with compositions (X) and (Y) being different. For example, by having a composition (X) greater than composition (Y), the surface modification layer 1706 may have a higher absorption coefficient at longer wavelengths compared to the GeSi-based absorber region 1704. As such, incident light at longer wavelengths may be strongly absorbed by the surface modification layer 1706 without penetrating deep into the GeSi-based absorber region 1704. By absorbing incident light closer to the surface of the GeSi-based absorber region 1704, the bandwidth of a photodetector including the absorber region 1704 may be improved due to reduced diffusion of photogenerated carriers within the absorber region 1704. In some implementations, for a pure germanium absorber region 1704 (i.e., X=0), the surface modification layer 1706 may have a Si Y Ge 1-Y In some implementations, the surface modification layer 1706 may be a layer. In some implementations, the composition of the surface modification layer 1706 and the GeSi-based absorber region 1704 may vary along a direction, such as a vertical direction, forming a graded GeSi absorber region 1704. Grading the GeSi composition may further improve the bandwidth of the photodetector. In some implementations, the surface modification layer 1706 may be multi-layered. For example, a GeSi layer may be deposited on the GeSi-based absorber region 1704 for passivation, and another Si layer may be deposited on the GeSi layer for further passivation.

[0276] In some implementations, the surface modification layer 1706 is a germanium-tin alloy Ge with varying composition (Z). Z Sn 1-Z Adding tin to the surface modification layer 1706 may improve the light absorption efficiency at longer wavelengths, such as beyond the bandgap of germanium (approximately 1.55 μm), beyond which the absorption efficiency of pure germanium decreases significantly.

[0277] 17B, ​​the surface-modified absorber region 1710 includes a germanium-silicon based absorber region 1704 and a first doped region 1712. In some implementations, the first doped region 1712 can be doped with a p-type or n-type dopant. The p-type or n-type dopant can modify the electrical properties of the absorber region 1704. For example, photo-generated electrons (or holes) are repelled away from the surface by the first doped region 1712, thereby avoiding surface recombination, resulting in higher collection efficiency when the first doped region 1712 is doped with a p-type (or n-type) dopant. In some implementations, the first doped region 1712 can be doped with impurities that modify the optical properties of the absorber region 1704, such as silicon and tin.

[0278] 17C, surface modified absorbing region 1720 is similar to surface modified absorbing region 1710, except that it further includes a second doped region 1722. The second doped region 1722 may be similar to the first doped region 1712 or may have a different polarity, depth, and width such that photogenerated carriers are attracted by the second doped region 1722 and repelled from the first doped region 1712.

[0279] 17D, the surface modified absorber region 1730 includes a germanium-silicon based absorber region 1704 and a dielectric well 1732. The dielectric well 1732 may be filled with a variety of dielectric materials, such as SiO2, Si3N4, and high-k materials. The dielectric well may contribute to reducing dark or leakage current, reducing the operating power of the photodetector, and / or improving the photodetector bandwidth, for example, when placed inside a PN junction or between surface electrical terminals.

[0280] Referring to Figure 17E, a switched photodetector 1740 includes the surface modified Ge absorption region 1710 of Figure 17B. The switched photodetector 1740 is similar to the switched photodetector 160 of Figure 1B, except that it further includes a surface modification layer 1706, as well as the carrier collection terminal 1106 and the carrier control terminal 1108 of Figure 11A. The addition of the surface modification layer 1706 can contribute to improving various performance characteristics of the switched photodetector 1740, such as light absorption efficiency, light absorption spectrum, carrier collection efficiency, dark or leakage current, photodetector operating power, and photodetector bandwidth.

[0281] Although individual implementations of the surface modifications of the absorber regions are illustrated, in general, the described surface modifications may be implemented in various combinations to achieve a desired effect. For example, the surface modification layer 1706 may be implemented in combination with the first doped region 1712 and / or the second doped region 1722. As another example, the surface modification layer 1706 may be implemented in combination with the dielectric well 1732. In yet another example, the surface modification layer 1706 may be implemented in combination with the first doped region 1712 and / or the second doped region 1722, as well as the dielectric well 1732.

[0282] Various doped regions and wells, such as p-type doped regions and wells and n-type doped regions and wells, can be arranged at various locations in the absorber region, substrate, or intermediate layer to modify device performance characteristics, including optical absorption efficiency, optical absorption spectrum, carrier collection efficiency, dark or leakage current, photodetector operating power, and photodetector bandwidth.

[0283] The depth of the doping regions and wells may be determined based on various considerations, such as manufacturability and device performance. One or more of the doping wells and regions may be connected to a voltage or current source. One or more of the doping wells and regions may not be connected to a voltage or current source (i.e., floating) and / or connected to each other (i.e., shorted).

[0284] 18A-18B show top and side views of an exemplary switched photodetector 1800. The switched photodetector 1800 is similar to the switched photodetector 160 of FIG. 1B, but further includes the carrier collection terminal 1106 and the carrier control terminal 1108 of FIG. 11A. As already described with respect to FIG. 1B, the n-well regions 152 and 154 may reduce leakage current of the first control signal 122 to the second control signal 132 and may reduce charge coupling between the n-doped regions 126 and 136. The reduced leakage current contributes to a reduced operating power of the switched photodetector 1800.

[0285] 18C-18D show top and side views of an example switched photodetector 1820. The switched photodetector 1820 is similar to the switched photodetector 1800 of FIGS. 18A-18B, but further includes a p-well region 1822. The p-well region 1822 may be similar to the p-well regions 246 and 248 of FIG. 2D. The p-well region 1822 may increase the collection efficiency of photo-generated electrons of the switched photodetector 1820 compared to the switched photodetector 1800.

[0286] In some cases, photo-generated carriers in the absorber region 106 may not be completely collected by the n-doped regions 126 and 136. In such cases, the photo-generated carriers may reach a material interface between the substrate 102 and the absorber region 106, where a material defect may exist. The material defect may capture the photo-generated carriers and release the carriers after a period of time, which may be collected by the n-doped regions 126 and 136. Such capture and release of carriers by the material defects at the interface and subsequent collection by the n-doped regions 126 and 136 may reduce the bandwidth of the switched photodetector 1800 due to the time delay caused by the capture and release of carriers. As such, such bandwidth reduction may be mitigated by adding a p-well region 1822, which may block photo-generated carriers not collected by the n-doped regions 126 and 136 from reaching the interface between the absorber region 106 and the substrate 102.

[0287] FIG. 18E illustrates a top view of an exemplary switched photodetector 1830. The switched photodetector 1830 is similar to the switched photodetector 1820 of FIGS. 18C-18D, but further includes a p-well region 1832. The p-well region 1832 is similar to the p-well region 1822. The combination of the p-well regions 1822 and 1832 surrounds the respective n-doped regions 126 and 136, which may further block photo-generated carriers not collected by the n-doped regions 126 and 136 from reaching the interface between the absorber region 106 and the substrate 102. Although illustrated as separate p-well regions 1822 and 1832, the p-well regions 1822 and 1832 may be coupled into respective "C" shaped regions surrounding the respective n-doped regions 126 and 136.

[0288] 18F-18G show top and side views of an exemplary switched photodetector 1840. The switched photodetector 1840 is similar to the switched photodetector 1800 of FIGS. 18A-18B, except that it omits the n-well regions 152 and 154 and includes a p-well region 1842. The p-well region 1842 may be similar to the p-well regions 246 and 248 of FIG. 2D. The p-well region 1842 surrounds the absorber region 106, which is embedded in the substrate 102. The p-well region 1842 may block photo-generated electrons in the absorber region 106 from reaching the substrate 102. Such blocking may increase the collection efficiency of photo-generated carriers of the switched photodetector 1840 compared to the switched photodetector 1800. The p-type well region 1842 may be formed in the absorber region 106, the substrate 102, an intermediate layer between the absorber region 106 and the substrate 102, or a combination thereof.

[0289] Although separate implementations of n-type well regions 152 and 154, and p-type well regions 1822, 1832, and 1842 are shown, in general, the described n-type well and p-type well regions can be implemented in various combinations to achieve desired effects.

[0290] Thus far, various implementations of the elements of the switched photodetector and various arrangements of those elements have been described. Next, various exemplary combinations of the previously described elements and their arrangements will be described. The combinations described are not intended to be an exhaustive list of all combinations.

[0291] 19A-19B show top and side views of an exemplary switched photodetector 1900. The switched photodetector 1900 is similar to the switched photodetector 100 of FIG. 1A, except that the absorber region 106 of the photodetector 1900 is embedded entirely within the substrate 102 and further includes the carrier collection terminal 1106 and the carrier control terminal 1108 of FIG. 11A. The light receiving region 1205 is described with respect to FIGS. 12A-12B. The presence of p-type doped regions 128 and 138 results in an ohmic contact being formed at the interface between the carrier control terminal 1108 and the absorber region 106.

[0292] 19C-19D show top and side views of an exemplary switched photodetector 1910. Switched photodetector 1910 is similar to switched photodetector 1900 of FIGS. 19A-19B, except that p-doped regions 128 and 138 are omitted. As a result of the omission of p-doped regions 128 and 138, a Schottky junction is formed at the interface between carrier control terminal 1108 and absorption region 106.

[0293] 19E-19F show top and side views of an exemplary switched photodetector 1920. Switched photodetector 1920 is similar to switched photodetector 1900 of FIGS. 19A-19B, except that additional p-type doped regions 128 and 138 and carrier control terminal 1108 have been added on each side of light receiving area 1205.

[0294] Figures 19G-19H show top and side views of an exemplary switched photodetector 1930. Switched photodetector 1930 is similar to switched photodetector 1920 of Figures 19E-19F, except that p-doped regions 128 and 138 are omitted. As a result of the omission of p-doped regions 128 and 138, a Schottky junction is formed at the interface between carrier control terminal 1108 and absorption region 106.

[0295] 20A-20B show top and side views of an exemplary switched photodetector 2000. The switched photodetector 2000 is similar to the switched photodetector 1900 of FIGS. 19A-19B, except for the addition of the intermediate layer 1006 of FIG. 10I. As previously described with respect to FIG. 10I, the intermediate layer 1006 has an opening to the substrate 102, and the absorbing region 106 fills the opening to the substrate 102 and the opening formed by the intermediate layer 1006. In some implementations, the intermediate layer 1006 can be SiO2, SiNx, AlOx, or any oxide or nitride based insulator.

[0296] 20C-20D show top and side views of an exemplary switched photodetector 2010. The switched photodetector 2010 is similar to the switched photodetector 2000 of FIGS. 19A-19B, except that the intermediate layer 1006 of FIGS. 20A-20B is replaced with an intermediate layer 2012. The intermediate layer 2012 is similar to the intermediate layer 1006 in terms of its material, except that the intermediate layer 2012 is a uniform layer that extends across the upper surface of the substrate 102 with an opening into the substrate 102. The absorber region 106 is embedded within the opening of the intermediate layer 2012. In some implementations, the intermediate layer 2012 can be SiO2, SiNx, AlOx, or any oxide or nitride based insulator.

[0297] 20E-20F show top and side views of an exemplary switched photodetector 2020. Switched photodetector 2020 is similar to switched photodetector 2010 of FIGS. 20C-20D, except that p-doped regions 128 and 138 are omitted. As a result of the omission of p-doped regions 128 and 138, a Schottky junction is formed at the interface between carrier control terminal 1108 and absorption region 106.

[0298] 20G-20H show top and side views of an exemplary switched photodetector 2030. Switched photodetector 2030 is similar to switched photodetector 2010 of FIGS. 20C-20D, except that intermediate layer 2012 of FIGS. 20C-20D has been replaced with intermediate layer 2032. Intermediate layer 2032 is similar to intermediate layer 2012 of FIGS. 20C-20D, except that intermediate layer 2032 has a first opening 2034 to substrate 102 and a second opening 2036 that is larger than first opening 2034 and extends toward an upper surface of intermediate layer 2032.

[0299] Figures 20I-20J show top and side views of an exemplary switched photodetector 2040. Switched photodetector 2040 is similar to switched photodetector 2030 of Figures 20G-20H, except that p-type doped regions 128 and 138 are omitted. As a result of the omission of p-type doped regions 128 and 138, a Schottky junction is formed at the interface between carrier control terminal 1108 and absorption region 106.

[0300] Figures 20K-20L show top and side views of an exemplary switched photodetector 2050. Switched photodetector 2050 is similar to switched photodetector 2030 of Figures 20G-20H, except for the addition of n-well regions 152 and 154. N-well regions 152 and 154 are described with respect to Figure 1B.

[0301] 21A-21B show top and side views of an exemplary switched photodetector 2100. Switched photodetector 2100 is similar to switched photodetector 1900 of FIGS. 19A-19B, except that n-type doped regions 126 and 136, p-type doped regions 128 and 138, carrier collection terminal 1106, and carrier control terminal 1108 have been moved from the absorption region 106 to the substrate 102. Such terminals 1106 and 1108 may be referred to as substrate carrier collection terminals and substrate carrier control terminals.

[0302] Figures 21C-21D show top and side views of an exemplary switched photodetector 2110. Switched photodetector 2110 is similar to switched photodetector 2100 of Figures 21A-21B, except that absorber p-type doped regions 2128 and 2138 and absorber carrier control terminal 2108 are placed on absorber region 106. Substrate carrier collection terminal 1106, substrate carrier control terminal 1108, and absorber carrier control terminal 2108 are similar to substrate carrier collection terminal 1306, substrate carrier control terminal 1308, and absorber carrier control terminal 1309 described with respect to Figure 14A and may have similar effects.

[0303] Figures 21E-21F show top and side views of an exemplary switched photodetector 2120. Switched photodetector 2120 is similar to switched photodetector 2110 of Figures 21C-21D, except that absorber p-doped regions 2128 and 2138 are omitted. As a result of omitting absorber p-doped regions 2128 and 2138, a Schottky junction is formed at the interface between absorber carrier control terminal 2108 and absorber region 106.

[0304] Figures 22A-22B show top and side views of an exemplary switched photodetector 2200. Switched photodetector 2200 is similar to switched photodetector 1840 of Figures 18F-18G, except for the addition of n-well regions 152 and 154 of Figures 18A-18B.

[0305] Figures 22C-22D show top and side views of an exemplary switched photodetector 2210. Switched photodetector 2210 is similar to switched photodetector 2110 of Figures 21C-21D, except for the addition of n-well regions 152 and 154 of Figures 18A-18B.

[0306] Figure 23A shows a top view of an exemplary switched photodetector 2300, and Figure 23B shows a side view of the exemplary switched photodetector 2300 along line AA. The switched photodetector 2300 is similar to the switched photodetector 2110 of Figures 21C-21D, except that a p-type well region 2302 has been added at the interface between the absorber region 106 and the substrate 102. The p-type well region 2302 may help to mitigate carrier trapping and emission at the interface between the absorber region 106 and the substrate 102, as described with respect to Figures 18C-18D.

[0307] Figures 24A-24B show top and side views of an exemplary switched photodetector 2400. Switched photodetector 2400 is similar to switched photodetector 1820 of Figures 18C-18D, except that n-well regions 152 and 154 are omitted.

[0308] Figure 24C shows a top view of an exemplary switched photodetector 2410. Switched photodetector 2410 is similar to switched photodetector 1830 of Figure 18E, except that p-well regions 1822 and 1832 of Figure 18E have been merged into a continuous p-well region 2412.

[0309] 24D-24E show top and side views of an exemplary switched photodetector 2420. The switched photodetector 2420 is similar to the switched photodetector 2400 of FIGS. 24A-24B, except that a dielectric well 2422 is added within the n-doped regions 126 and 136. The dielectric well 2422 is similar to the dielectric well 1732 of FIG. 17D. The dielectric well 2422 is disposed in a portion of the n-doped region 126 between the carrier collection terminal 1106 and the carrier control terminal 1108. The dielectric well 2422 may reduce dark current between the carrier collection terminal 1106 and the carrier control terminal 1108. The depth of the dielectric well 2422 may be less than, equal to, or greater than the depth of the n-doped region 126.

[0310] 24F-24G show top and side views of an exemplary switched photodetector 2430. The switched photodetector 2430 is similar to the switched photodetector 2420 of FIGS. 24D-24E, except that the dielectric well 2422 has been moved from the n-doped regions 126 and 136 to the p-doped regions 128 and 138. The depth of the dielectric well 2422 may be less than, equal to, or greater than the depth of the p-doped region 128. In general, the dielectric well 2422 may be located anywhere between the n-doped region 126 and the p-doped region 128, and between the n-doped region 136 and the p-doped region 138.

[0311] 25A-25B show top and side views of an exemplary switched photodetector 2500. The switched photodetector 2500 is similar to the switched photodetector 1900 of FIGS. 19A-19B, except that the metallic mirror 1606 of FIG. 16F is added as metallic mirror 2502 on the upper surface of the absorbing region 106, on which the carrier collection terminal 1106 and the carrier control terminal 1108 are located. The metallic mirror 2502 may be placed above the light receiving region 1205. In some implementations, the metallic mirror 2502 may be implemented by the first metal layer (M1) or the second metal layer (M2) or a combination thereof in a CMOS process.

[0312] Figures 25C-25D show top and side views of an exemplary switched photodetector 2510. Switched photodetector 2510 is similar to switched photodetector 2500 of Figures 25A-25B, except that p-type doped regions 128 and 138 are omitted. As a result of the omission of p-type doped regions 128 and 138, a Schottky junction is formed at the interface between carrier control terminal 1108 and absorption region 106.

[0313] 25E-25F show top and side views of an exemplary switched photodetector 2520. The switched photodetector 2520 is similar to the switched photodetector 2050 of FIGS. 20K-20L, except that the metallic mirror 1606 of FIG. 16F is added as metallic mirror 2502 on the upper surface of the absorbing region 106, on which the carrier collection terminal 1106 and the carrier control terminal 1108 are located. The metallic mirror 2502 may be placed above the light receiving region 1205. In some implementations, the metallic mirror 2502 may be implemented by the first metal layer (M1) or the second metal layer (M2) or a combination thereof in a CMOS process.

[0314] 25G-25H show top and side views of an exemplary switched photodetector 2530. The switched photodetector 2530 is similar to the switched photodetector 1840 of FIGS. 18F-18G, except that the metallic mirror 1606 of FIG. 16F is added as metallic mirror 2502 on the upper surface of the absorbing region 106, on which the carrier collection terminal 1106 and the carrier control terminal 1108 are located. The metallic mirror 2502 may be placed above the light receiving region 1205. In some implementations, the metallic mirror 2502 may be implemented by the first metal layer (M1) or the second metal layer (M2) or a combination thereof in a CMOS process.

[0315] In a typical implementation of an image sensor, multiple sensor pixels (e.g., switched photodetectors) are arranged in an array so that the image sensor can capture an image having multiple image pixels. Square sensor pixels with equal dimensions on both sides when viewed from above may form a simple 2D array. However, in some applications, such as ToF, some sensor pixels may have shapes other than square, such as rectangular shapes. For example, referring again to FIG. 1B, a switched photodetector 160 has two carrier control terminals (e.g., p-type doped regions 128 and 138) and two carrier collection terminals (e.g., n-type doped regions 126 and 136). These four terminals are typically arranged along a straight line, which results in a rectangular sensor pixel shape that is longer along the straight line where the terminals are aligned (e.g., switched photodetector 1800 in FIG. 18A).

[0316] Such rectangular sensor pixels may pose challenges for efficient array placement of pixels due to design rules associated with semiconductor processing, for example, at a foundry. The design rules may impose various minimum separations of features such as doped regions, doped wells, dielectric wells, and germanium absorption regions. One approach to improve compactness and symmetry is by forming a photodetector unit cell comprising four rectangular photodetectors. FIG. 26 illustrates an exemplary unit cell of a rectangular photodetector. The unit cell 2600 comprises the four switched photodetectors 1800 of FIG. 18A and four isolation structures 2602 surrounding each of the switched photodetectors 1800. The isolation structures 2602 are described with respect to FIGS. 15A-15D. The unit cell 2600 may improve the compactness and symmetry of the sensor pixel compared to a rectangular unit cell.

[0317] FIG. 27 shows a top view of an exemplary rectangular switched photodetector 2700 along with the gain of the phototransistor gain. The switched photodetector 2700 is similar to the switched photodetector 1800 of FIG. 18A, except that an electron emitter 2710 has been added onto the substrate 102. The electron emitter 2710 may be similar to the n-type doped regions 126 and 136. The rectangular shape of the switched photodetector 1800 allows a photocurrent integrating capacitor (e.g., a floating diffusion capacitor) to be coupled to a bipolar junction transistor (BJT) 2720 formed by the n-type doped regions 126 and 136, the p-type doped regions 128 and 138, and the electron emitter 2710, resulting in an NPN BJT. The BJT 2720, when properly biased, may provide a phototransistor gain in response to an incident optical signal, improving the light-to-photocurrent conversion efficiency of the photodetector 2700. For example, BJT 2720 may be biased as follows: n-type doped regions 126 and 136 are biased at a voltage between 1V and 3V, p-type doped regions 128 and 138 are biased at a voltage between 0V and 1V, and electron emitter 2710 is biased lower than the bias of the respective n-type doped regions 126 and 136.

[0318] Generally, the electron emitter 2710 and / or the n-type doped regions 126 and 136 should be biased to an external voltage or shorted to a p-type doped region through a metal connection to enable electrons to be emitted by the electron emitter 2710.

[0319] Although various implementations of switched photodetectors having particular combinations and arrangements of n-type and p-type regions and wells have been described, in general, the polarity of the doped regions and wells may be reversed and similar operation and functionality may be achieved. For example, all instances of p-type wells and p-type doped regions may be converted to n-type wells and n-type doped regions, respectively, and all instances of n-type wells and n-type doped regions may be converted to p-type wells and p-type doped regions, respectively.

[0320] 28A illustrates an exemplary imaging system 2800 for determining characteristics of a target object 2810. The target object 2810 may be a three-dimensional object. The imaging system 2800 may include a transmitter unit 2802, a receiver unit 2804, and a processing unit 2806. In general, the transmitter unit 2802 emits light 2812 toward the target object 2810. The transmitter unit 2802 may include one or more light sources, control circuits, and / or optical elements. For example, the transmitter unit 2802 may include one or more NIR LEDs or lasers, and the emitted light 2812 may be collimated by a collimating lens to propagate in free space.

[0321] In general, the receiver unit 2804 receives reflected light 2814 reflected from the target object 2810. The receiver unit 2804 may include one or more photodetectors, control circuitry, and / or optical elements. For example, the receiver unit 2804 may include an image sensor, which may include a number of pixels fabricated on a semiconductor substrate. Each pixel may include one or more switched photodetectors for detecting the reflected light 2814, which may be focused onto the switched photodetectors. Each switched photodetector may be a switched photodetector as disclosed herein.

[0322] In general, the processing unit 2806 processes the optical carriers generated by the receiver unit 2804 to determine a characteristic of the target object 2810. The processing unit 2806 may comprise a control circuit, one or more processors, and / or a computer storage medium that may store instructions for determining a characteristic of the target object 2810. For example, the processing unit 2806 may comprise a readout circuit and a processor that may process information related to the collected optical carriers to determine a characteristic of the target object 2810. In some implementations, the characteristic of the target object 2810 may be depth information of the target object 2810. In some implementations, the characteristic of the target object 2810 may be a material composition of the target object 2810.

[0323] 28B illustrates one exemplary technique for determining a characteristic of a target object 2810. The transmitter unit 2802 may emit a light pulse 2812 modulated at a frequency fm with a duty cycle of 50%. The receiver unit 2804 may receive a reflected light pulse 2814 with a phase shift Φ. The switched photodetectors are controlled such that readout circuit 1 reads the collected charge Q1 in phase with the emitted light pulse and readout circuit 2 reads the collected charge Q2 in anti-phase with the emitted light pulse. In some implementations, the distance D between the imaging system 2800 and the target object 2810 is determined by the formula

[0324]

number

[0325] where c is the speed of light.

[0326] FIG. 28C illustrates another exemplary technique for determining the characteristics of a target object 2810. The transmitter unit 2802 may emit light pulses 2812 modulated at a frequency fm with a duty cycle of less than 50%. By simultaneously reducing the duty cycle of the light pulses to 1 / N and increasing the intensity of the light pulses by a factor of N, the signal-to-noise ratio of the received reflected light pulses 2814 may be improved while maintaining substantially the same power consumption for the imaging system 2800. This is made possible when the device bandwidth is increased so that the duty cycle of the light pulses can be lowered without distorting the pulse shape. The receiver unit 2804 may receive the reflected light pulses 2814 with a phase shift Φ. The multi-gate photodetector is controlled such that the readout circuit 1 reads the collected charge Q1' in phase with the emitted light pulse, and the readout circuit 2 reads the collected charge Q2' in delayed phase with the emitted light pulse. In some implementations, the distance D between the imaging system 2800 and the target object 2810 is calculated using the formula

[0327]

number

[0328] It may be derived using

[0329] 29 shows an example of a flow diagram 2900 for determining a characteristic of an object using an imaging system. The process 2900 may be performed by a system such as the imaging system 2800.

[0330] The system receives 2902 the reflected light. For example, the transmitter unit 2802 may emit a NIR light pulse 2812 toward the target object 2810. The receiver unit 2804 may receive a reflected NIR light pulse 2814 reflected from the target object 2810.

[0331] The system determines 2904 the phase information. For example, the receiver unit 2804 may include an image sensor, which may include a number of pixels fabricated on a semiconductor substrate. Each pixel may include one or more switched photodetectors for detecting the reflected light pulses 2814. The type of switched photodetector may be a switched photodetector disclosed in the present application, and the phase information may be determined using techniques described with reference to FIG. 28B or FIG. 28C.

[0332] The system determines 2906 a property of the object. For example, the processing unit 2806 may determine depth information of the object 2810 based on the phase information using the techniques described with reference to Figure 28B or 28C.

[0333] In some implementations, the image sensor comprises a plurality of pixels fabricated on a semiconductor substrate, each pixel may include one or more switched photodetectors 100, 160, 170, 180, 200, 250, 260, 270, 300, 360, 370, 380, 400, 450, 460, 470, and 480 for detecting reflected light as illustrated in Figures 28A and 28B. Isolation between these pixels may be implemented based on dielectric isolation, such as using an oxide or nitride layer, or based on implant isolation, such as using p-type or n-type regions to block the electrons or holes of the signal, or based on an intrinsic built-in energy barrier, such as using a germanium-silicon heterojunction interface.

[0334] Up to this point, various implementations of switched photodetectors have been described, and how they can be used in a time-of-flight (ToF) detection system, such as the imaging system 2800 of FIG. 28A. The receiver unit 2804 of the imaging system 2800 will now be described in more detail. FIG. 30 shows a block diagram of an exemplary receiver unit 3000 for ToF detection. The receiver unit 3000 comprises a pixel array 3010, an amplifier array 3020, and an analog-to-digital converter (ADC) array 3030. The pixel array 3010 is electrically coupled to the amplifier array 3020, which is electrically coupled to the ADC array 3030.

[0335] The pixel array 3010 comprises a plurality of photodetectors, such as the switched photodetectors already described, and a capacitor for accumulating photo-generated carriers from the switched photodetectors. The pixel array 3010 is a two-dimensional array of photodetectors and capacitors, with M rows and N columns (i.e., an M×N array). The capacitors may be integrated with the photodetectors or implemented separately. Examples of capacitors include floating diffusion capacitors, metal-oxide-metal (MOM) capacitors, and metal-insulator-metal (MIM) capacitors. The pixel array 3010 may further comprise a pixel transistor for controlling the operation of the photodetectors, such as controlling the charge readout of the switched photodetectors. The pixel array 3010 may be part of an image sensor that comprises various optical components associated with the detection of light, such as a reflector, a lens, and an anti-reflective coating layer.

[0336] The amplifier array 3020 includes one or more amplifiers 3022. The amplifiers 3022 amplify the electrical signals generated by the individual pixels of the pixel array 3010. The amplifiers 3022 may be voltage gain amplifiers, which amplify the voltage established by the integration of the photocurrent on a capacitor. The amplifiers 3022 may be charge-to-voltage amplifiers that convert the charge stored on the capacitor into a voltage output. The amplifiers 3022 may be variable gain amplifiers, which may be used in optimizing the detection sensitivity over a range of optical signal magnitudes received by the pixel array 3010. The amplifiers 3022 may be, for example, differential amplifiers that amplify the voltage difference between two outputs of a switched photodetector. Such a differential detection scheme may result in improved ToF detection sensitivity.

[0337] Various implementations of the amplifier array 3020 may have different numbers of amplifiers 3022. In some implementations, each pixel of the pixel array 3010 is coupled with a dedicated amplifier 3022. Such a configuration allows for simultaneous readout of all pixels, resulting in the highest image data acquisition speed. In some implementations, each row or column of the pixel array shares a single amplifier 3022. For example, for an M×N pixel array 3010, there may be M or N amplifiers 3022. Such a sharing configuration may improve the scalability of the receiver unit 3000 to a large number of pixels (millions of pixels). In some implementations, each row or column may be further divided into subsections with amplifiers 3022 shared within the subsections. In some implementations, for a small pixel array 3010, a single amplifier 3022 may be shared among all pixels of the array. In general, blocks of pixels from multiple rows and columns may be grouped together and the blocks of pixels may share a single amplifier 3022. For example, for an M×N pixel array 3010, there may be K×L amplifiers 3022, where K≦M and L≦N.

[0338] The ADC array 3030 comprises one or more ADCs. The ADC converts the analog voltage or current signal output by the amplifier 3022 to a digital output 3040 having N bits. The digital output 3040 may be received, for example, by the processing unit 506 of FIG. 5A to perform ToF detection. The number of output bits N determines the resolution of the ADC, which may be set based on considerations of sensitivity and speed of conversion for a given application. Examples of different types of ADCs include flash ADCs, successive approximation register ADCs, and delta-sigma ADCs. The ADC may be, for example, a differential ADC that converts the difference in amplified voltage between the outputs of the differential amplifiers 3022. Similar to the amplifier array 3020, various implementations of the ADC array 3030 may have different numbers of ADCs. The number of ADCs may be equal to the number of amplifiers 3022 in the amplifier array 3020 (i.e., a one-to-one correspondence) or less (i.e., multiple amplifiers share one ADC) depending on various design considerations, such as the desired conversion speed.

[0339] An imaging system such as the ToF imaging system 500 may be exposed to a wide range of optical signal magnitudes during operation. For example, the optical signal magnitude may be affected by ambient lighting conditions, the reflectivity of the target object, or the distance of the target object from the imaging system 500, and the signal magnitude may vary by several orders of magnitude (e.g., by more than 2x, more than 10x, or more than 100x) for various operating conditions. Typically, a change in the optical signal magnitude results in a linearly proportional change in the photocurrent generated by the photodetector of the pixel.

[0340] The pixel array 3010 operates by integrating the photocurrent generated by each of the pixel's photodetectors on their respective capacitors over a certain period of time (e.g., a nominal integration time) to generate an electrical signal proportional to the detected light signal. For example, the capacitors may be charged to a preset voltage (e.g., 1.8V) at the beginning of an image acquisition cycle, at which point they accumulate a charge Q determined by the formula Q=C*V, where C is the capacitance of the capacitor and V is the voltage of the capacitor. The charged capacitor is then discharged by a photocurrent Iph, defined as Iph=ΔQ / Δt, i.e., the change in the amount of charge Q for a given change at time t. The magnitude of the photocurrent Iph generated by a photodetector directly affects the rate at which the associated capacitor is discharged. The maximum integration time corresponds to the time tmax=Q / Iph, which is the time required to fully discharge the capacitor. A pixel is said to be "damaged" or "bloomed" when the maximum integration time is less than the nominal integration time and integration over the nominal integration time results in a full discharge of the capacitor (more generally, when the capacitor is discharged to a second preset voltage), at which point the pixel's electrical output is no longer proportional to the received optical input, resulting in a distorted acquired image or incorrect ToF measurement. As such, if the optical signal is large enough to damage one or more pixels within the preset integration time period, integration of the signal may be terminated prior to pixel damage. Such premature termination of optical signal integration may result in the generation of subframes, which are the result of partial integration over a fraction of the nominal integration time. Multiple subframes may be acquired over the nominal integration time, and the multiple subframes may be post-processed to generate a single image frame.

[0341] After the integration of the optical signal is completed, the electrical output of the pixel is amplified by the amplifier 3022 and converted to a digital output 3040 by the ADC array 3030 to generate a frame or subframe. After the conversion is completed, the capacitor is again charged to the preset voltage and the acquisition cycle is repeated. Since a larger optical signal correspondingly reduces the maximum integration time for each acquisition cycle, a larger optical input signal correspondingly increases the rate at which subframes and digital outputs 3040 are generated. For some applications, such an increase in data output may be undesirable, for example, due to increased power consumption or increased system complexity required to support the increased data throughput. As such, solutions that increase the maximum integration time of the pixel, reduce the output data rate of the ADC, reduce the output data rate of the ToF receiver unit 3000, or combinations thereof, are desired.

[0342] One approach to increasing the maximum integration time or decreasing the output data rate is to increase the capacitance of the capacitor associated with each pixel of the pixel array 3010. Increasing the capacitance by a fixed factor can increase the maximum integration time by approximately the same fixed factor, increasing the dynamic range of the ToF receiver unit. However, the capacitor is a physical structure fabricated in the device layer where the photodetector is fabricated or in the back-end interconnect layer, and the capacitance typically varies proportionally to its total area. As such, the capacitance of a capacitor monolithically integrated with the photodetector is limited by the available area in the sensor wafer on which the pixel array 3010 is fabricated. These challenges can be solved by fabricating additional capacitors on a second wafer and bonding them to the sensor wafer to further increase the capacitance of each of the pixels.

[0343] 31A and 31B show schematic and cross-sectional views of an exemplary ToF receiver unit 3100 with enhanced capacitance. The ToF receiver unit 3100 comprises an integrated circuit (IC) wafer 3110, a sensor wafer 3130, and an interconnect 3170. The IC wafer 3110 comprises a first capacitor 3112 and a pixel transistor 3120. The sensor wafer 3130 comprises a second capacitor 3132 and a ToF pixel 3140. The IC wafer 3110 and the sensor wafer 3130 are bonded together using, for example, a wafer bonding process, and the interconnect 3170, the first and second capacitors 3112 and 3132, and the pixel transistor 3120 are electrically coupled to the ToF pixel 3140. By utilizing the space available for fabricating the capacitors 3112 and 3132 on both the IC wafer 3110 and the sensor wafer 3130, the total capacitance available for integration of the ToF pixel 3140 can be increased by a factor of two compared to a configuration in which the first and second capacitors are both fabricated on a single wafer. Such an increase in capacitance can lengthen the maximum integration time of the ToF pixel 3140 and reduce the sub-frame generation rate and corresponding data throughput by the same factor.

[0344] The ToF pixel 3140 may be a switched photodetector, such as the switched photodetector 100. The ToF pixel 3140 comprises a first switch 3150 and a second switch 3160, each having a respective carrier readout (collection) terminal 3152 and 3162 ("R"), and a carrier control (modulation) terminal 3154 and 3164 ("C"). The first switch 3150 may be similar to, for example, the first switch 108 of FIG. 1A, with the carrier readout terminal 3152 being similar to the n-type doped region 126, and the carrier control terminal 3154 being similar to the p-type doped region 128. Similarly, the second switch 3160 may be similar to, for example, the second switch 110 of FIG. 1A, with the carrier readout terminal 3162 being similar to the n-type doped region 136, and the carrier control terminal 3164 being similar to the p-type doped region 138. The ToF pixel 3140 may be a backside illuminated (BSI) pixel in that an optical signal may enter the ToF pixel 3140 from the backside of the sensor wafer 3130 opposite the side on which the ToF pixel 3140 is fabricated.

[0345] The pixel transistor 3120 is a transistor configured to control the operation of the ToF pixel 3140. The pixel transistor 3120 includes first and second readout transistors 3122 and 3124 for collecting carriers from readout terminals 3152 and 3162. The pixel transistor 3120 may include a readout circuit having a 3T configuration (i.e., a three-transistor configuration having a reset, source follower, and row select transistor) or may include a circuit similar to the readout circuits 124 and 134 shown in FIG. 1A. The pixel transistor 3120 may include control transistors 3126 and 3128 for providing control signals to the control terminals 3154 and 3164. The control signals provided by the control transistors 3126 and 3128 may be similar to the control signals 122 and 132 shown in FIG. 1A.

[0346] The first and second capacitors 3112 and 3132 may be implemented using standard semiconductor IC processing techniques. Examples of the first and second capacitors 3112 and 3132 include metal-oxide-metal (MOM) capacitors and metal-insulator-metal (MIM) capacitors. In some implementations, the oxide or insulator of the capacitors may be replaced with a high-k dielectric constant material such as Al2O3, HfO2, ZrO2, or La2O3. Although the capacitors are illustrated as parallel plate capacitors, various structures having capacitance may be used as the capacitors 3112 and 3132, including floating diffusion capacitors and metal-oxide-semiconductor (MOS) capacitors. In general, the first and second capacitors 3112 and 3132 may each be implemented as a bank of parallel connected capacitors for manufacturability or performance reasons.

[0347] 31B, the first and second capacitors 3112 and 3132 are electrically coupled to the input terminals (e.g., source or drain terminals) of the readout transistors 3124 and 3122, respectively. The first readout transistor 3122 collects carriers from the carrier readout terminal 3152 and supplies the collected carriers to the second capacitor 3132 through an output terminal (e.g., source or drain terminal). The second readout transistor 3124 collects carriers from the carrier readout terminal 3162 and supplies the collected carriers to the first capacitor 3112 through an output terminal (e.g., source or drain terminal). In this configuration, a voltage can be applied to the gate terminals of the readout transistors 3122 and 3124 to control the movement of carriers from the ToF pixel 3140 to the respective capacitors 3132 and 3112.

[0348] Although a particular association of the capacitors 3112 and 3132 to the read terminals 3152 and 3162 has been described, in general the association between the capacitors 3112 and 3132 and the read terminals 3152 and 3162 can be swapped and operate in a similar manner. The respective terminals of the first and second capacitors 3112 and 3132 that are not connected to the read terminals 3152 and 3162 may be connected to ground, floating, or connected to a power supply, for example.

[0349] The IC wafer 3110 and the sensor wafer 3130 may be bonded together in a variety of ways. Examples of bonding techniques include metal-to-metal, oxide-to-oxide, and hybrid bonding. The interconnects 3170 may include bond pads 3172 that provide electrical coupling between portions of the interconnects 3170 formed in the IC wafer 3110 and the sensor wafer 3130. The bond pads 3172 may be copper pillars or pads and may provide a mechanical bond between the IC wafer 3110 and the sensor wafer 3130.

[0350] Although a single ToF pixel 3140 is shown in FIGS. 31A and 31B for illustrative purposes, in general, the receiver unit 3100 may include an array of ToF pixels 3140 connected to an array of pixel transistors 3120.

[0351] Although a ToF pixel 3140 having two switches 3150 and 3160 coupled to two capacitors 3132 and 3112 is shown in Figures 31A and 31B for illustrative purposes, in general, the ToF pixel 3140 may include three or more switches electrically coupled to three or more capacitors.

[0352] Figure 31C shows a schematic diagram of an exemplary ToF receiver unit 3180 with enhanced capacitance. The ToF receiver unit 3180 is similar to the ToF receiver unit 3100 of Figure 31A, except that the first and second capacitors 3112 and 3132 are electrically coupled directly to the respective carrier read terminals 3162 and 3152 without intervening transistors.

[0353] FIG. 31D shows a schematic diagram of an exemplary ToF receiver unit 3182 with enhanced capacitance. The ToF receiver unit 3180 is similar to the ToF receiver unit 3100 of FIG. 31A, except that the first capacitor 3132 is divided into first sub-capacitors 3133 and 3134, and the second capacitor 3112 is divided into second sub-capacitors 3113 and 3114. The sub-capacitors 3113 and 3133 are disposed in the sensor wafer 3130, and the sub-capacitors 3114 and 3134 are disposed in the IC wafer 3110. The first sub-capacitors 3113 and 3114 are electrically connected in a parallel configuration to achieve a similar capacitance enhancement as the configuration shown in FIG. 31A. The first sub-capacitors 3113 and 3114 are electrically coupled to the readout transistor 3124 and configured to be charged or discharged by carriers collected from the readout terminal 3162. Similarly, the second sub-capacitors 3133 and 3134 are electrically connected in a parallel configuration to achieve a similar capacitance increase as the configuration shown in Figure 31 A. The second sub-capacitors 3133 and 3134 are electrically coupled to the readout transistor 3122 and configured to be charged or discharged by carriers collected from the readout terminal 3152.

[0354] In general, the IC wafer 3110 and the sensor wafer 3130 are processed independently of each other. For example, the two wafers 3110 and 3130 may use different processing techniques, different process nodes, be processed by different foundries, and / or at different times, all of which may affect the capacitance of the capacitors fabricated in the wafer 3110 or 3130 due to finite manufacturing process tolerances and variations. By splitting the first capacitor associated with the read terminal 3162 into a sub-capacitor 3113 located in the sensor wafer 3130 and a sub-capacitor 3114 located in the IC wafer, and similarly for the second capacitor associated with the read terminal 3152 into sub-capacitors 3133 and 3134, any variation in the capacitor of one wafer will affect the sum of the first or second capacitances by an equal amount, thereby helping to reduce or eliminate potential imbalances in the two capacitances resulting from any variation or mismatch between the IC wafer 3110 and the sensor wafer 3130.

[0355] Figure 31E shows a schematic diagram of an exemplary ToF receiver unit 3184 with enhanced capacitance. The ToF receiver unit 3184 is similar to the ToF receiver unit 3182 of Figure 31D, except that the first sub-capacitors 3113 and 3114 and the second sub-capacitors 3133 and 3134 are electrically coupled directly to the respective carrier read terminals 3162 and 3152 without intervening transistors.

[0356] FIG. 31F shows a schematic diagram of an example ToF receiver unit 3186 with increased capacitance. The ToF receiver unit 3186 is similar to the ToF receiver unit 3100 of FIG. 31A, except that the pixel transistor 3120 is now moved from the IC wafer 3110 to the sensor wafer 3130. In some cases, the pixel transistor 3120 may be moved into unoccupied space in the sensor wafer 3130 surrounding the ToF pixel 3140. Such placement of the pixel transistor 3120 may improve the performance of the receiver unit 3186 and / or free up space in the IC wafer 3110 for other components of the receiver unit 3186, such as additional capacitors, memory, amplifiers, or ADCs.

[0357] FIG. 31G shows a schematic diagram of an example ToF receiver unit 3188 with increased capacitance. The ToF receiver unit 3188 is similar to the ToF receiver unit 3180 of FIG. 31C, except that the pixel transistor 3120 is now moved from the IC wafer 3110 to the sensor wafer 3130. In some cases, the pixel transistor 3120 may be moved into unoccupied space in the sensor wafer 3130 surrounding the ToF pixel 3140. Such placement of the pixel transistor 3120 may improve the performance of the receiver unit 3188 and / or free up space in the IC wafer 3110 for other components of the receiver unit 3188, such as additional capacitors, memory, amplifiers, or ADCs.

[0358] FIG. 31H shows a schematic diagram of an example ToF receiver unit 3190 with increased capacitance. The ToF receiver unit 3190 is similar to the ToF receiver unit 3182 of FIG. 31D, except that the pixel transistor 3120 is now moved from the IC wafer 3110 to the sensor wafer 3130. In some cases, the pixel transistor 3120 may be moved into unoccupied space in the sensor wafer 3130 surrounding the ToF pixel 3140. Such placement of the pixel transistor 3120 may improve the performance of the receiver unit 3190 and / or free up space in the IC wafer 3110 for other components of the receiver unit 3190, such as additional capacitors, memory, amplifiers, or ADCs.

[0359] FIG. 31I shows a schematic diagram of an example ToF receiver unit 3192 with increased capacitance. The ToF receiver unit 3192 is similar to the ToF receiver unit 3184 of FIG. 31E, except that the pixel transistor 3120 is now moved from the IC wafer 3110 to the sensor wafer 3130. In some cases, the pixel transistor 3120 may be moved into unoccupied space in the sensor wafer 3130 surrounding the ToF pixel 3140. Such placement of the pixel transistor 3120 may improve the performance of the receiver unit 3192 and / or free up space in the IC wafer 3110 for other components of the receiver unit 3192, such as additional capacitors, memory, amplifiers, or ADCs.

[0360] In general, the pixel transistors 3120 in the ToF receiver unit 3100 of Figures 31A and 31B, the ToF receiver unit 3182 of Figure 31D, the ToF receiver unit 3186 of Figure 31F, and the ToF receiver unit 3190 of Figure 31H can be controlled to select a total capacitance value appropriate for the target integration time while minimizing noise from the subsequent amplifier array 3020 and ADC 3030.

[0361] 32 shows a block diagram of an example receiver unit 3200 for ToF detection. The ToF receiver unit 3200 is similar to the ToF receiver unit 3000 of FIG. 30, but further includes a memory module 3210 and a digital signal processing (DSP) module 3220. The memory module 3210 is electrically coupled to the digital output 3040 of the ADC 3030 and an input of the DSP module 3220. The DSP module 3220 outputs digitally processed data as a DSP output 3230.

[0362] The memory module 3210 is configured to store the digital output 3040 of the ADC 3030 corresponding to the amplified electrical signal from the pixel array 3010. The memory module 3210 may store a plurality of digital outputs corresponding to subframes generated by a large amplitude input optical signal and buffer the subframes before outputting or for further processing of the digital output 3040. For example, the receiver unit 3200 may generate data at a rate faster than the data can be transferred to a system receiving the DSP output 3230. Such an increase in data generation rate may be due, for example, to a large amplitude optical signal or burst mode acquisition of ToF image frames. Under such conditions, the memory module 3210 may store excess data while the receiver unit 3200 transmits the DSP output 3230 to a data receiving system.

[0363] The DSP module 3220 is configured to digitally process the digital data stored by the memory module 3210. The DSP module 3220 may be configured to perform various arithmetic, Boolean, or specialized digital operations such as a fast Fourier transform (FFT), among others, on the data received from the memory module 3210. For example, the DSP module 3220 may process multiple subframes stored in the memory module 3210 into a single complete frame or a portion of a complete frame including an area of ​​interest to be output to a data receiving system. By processing multiple subframes to generate a single complete frame or a portion of a complete frame including an area of ​​interest and outputting the single complete frame or a portion of a complete frame including an area of ​​interest to a data receiving system, the total external data throughput of the receiver unit 3200 may be reduced. In some implementations, the total external data throughput of the receiver unit 3200 may be reduced by a factor corresponding to the number of subframes. As another example, the DSP module 3220 may process data stored in the memory module 3210 to determine and filter depth information from ToF measurements.

[0364] The memory module 3210 and the DSP module 3220 may be implemented alone or in combination with various configurations of the ToF receiver with enhanced capacitance as described with respect to FIGS. 31A-31I. The memory module 3210 and the DSP module 3220 in combination with the increased capacitance may reduce the external data throughput and reduce the number of subframes generated. Reducing the number of subframes may reduce the storage capacity requirements of the memory module 3210. Furthermore, reducing the number of subframes may reduce the number of processing operations performed by the DSP module 3220. As a result of such a reduction in the number of subframes and a corresponding reduction in memory capacity and / or processing operations, power consumption by the ToF receiver unit may also be reduced.

[0365] In some implementations, the DSP module 3220 may comprise the processing unit 506 of Figure 5A. The DSP module 3220 may be implemented, for example, as a general-purpose processor or as an application specific integrated circuit.

[0366] FIG. 33A shows a schematic cross-sectional view of an exemplary receiver unit 3300 for ToF detection. The receiver unit 3300 comprises an IC wafer 3110 and a sensor wafer 3130. The IC wafer 3110 comprises a pixel transistor array 3320, an amplifier array 3020, and an ADC 3030. The sensor wafer 3130 comprises a ToF pixel array 3010 and a memory module 3210. The pixel transistor array 3320 is an array of pixel transistors 3120 as described with respect to FIG. 31A. The IC wafer 3110 and the sensor wafer 3130 are bonded together through wafer bonding. Interconnects 3170 and bond pads 3172 electrically couple the various components of the receiver unit 3300.

[0367] The memory modules 3210 may be distributed around the unoccupied space in the sensor wafer 3130 surrounding the ToF pixel array 3010. For example, in a BSI configured receiver unit 3300, the area in the sensor wafer 3130 located above the amplifier array 3020 and the ADC 3030 may be unoccupied. By placing the memory modules 3210 in the unoccupied space located above the amplifier array 3020 and the ADC 3030, the performance of the receiver unit 3300 may be improved without increasing the size of the receiver unit 3300.

[0368] The memory module 3210 may be implemented using various memory technologies in various configurations. Examples of memory technologies include static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, resistive RAM (ReRAM), magnetic RAM (MRAM), phase change RAM (PRAM), and ferroelectric RAM (FeRAM). Different memory technologies typically share a common architecture of a bit storage element coupled with a read / write transistor. For example, a DRAM bit comprises a capacitor for storing a charge associated with the bit and a transistor for reading and writing to the capacitor. As another example, an SRAM bit comprises a flip-flop for storing a state associated with the bit and two transistors for reading and writing to the flip-flop. Similarly, ReRAM has a variable resistive storage element, MRAM has a magnetic storage element, PRAM has a phase change storage element, and FeRAM has a ferroelectric storage element for storing the bit. In some implementations, two or more memory technologies may be combined and work in conjunction with each other. 33A, the memory module 3210 includes both read / write transistors and associated bit storage elements. In some implementations, additional processing circuitry may be included to further expand the functionality of the memory module 3210. For example, a digital adder may be included to further process the bits stored by the memory.

[0369] FIG. 33B shows a schematic cross-sectional view of an exemplary receiver unit 3330 for ToF detection. The receiver unit 3330 is similar to the receiver unit 3300 of FIG. 33A, except that the memory module 3210 is replaced by a distributed memory module 3340. The distributed memory module 3340 comprises a storage element sub-block 3342 and a read / write transistor sub-block 3344. The storage element sub-block 3342 is disposed in the sensor wafer 3130, and the transistor sub-block is disposed in the IC wafer 3110. In some implementations, additional processing circuitry, such as a digital adder, may be included in the read / write transistor sub-block 3344 to further process the bits stored in the memory.

[0370] The memory elements 3342 are typically fabricated using specialized techniques and / or materials. For example, DRAM capacitors are typically fabricated using specialized processes, such as deep trench etching in silicon substrates, that may not be compatible with the fabrication processes used to fabricate the IC wafer 3110. Additionally, the fabrication process used to fabricate the IC wafer 3110 may be optimized for fabricating transistors, such as the read / write transistors 3344. For example, the fabrication process used for the IC wafer 3110 may be a more advanced process node with a smaller minimum feature size compared to that of the sensor wafer 3130. As such, decoupling the fabrication of the memory elements 3342 and the read / write transistors 3344 may improve the performance of the memory module 3340 by allowing independent optimization of the performance of the two sub-blocks 3342 and 3344, and may reduce the complexity of the fabrication process for the sensor wafer 3130 and the IC wafer 3110.

[0371] FIG. 33C shows a schematic cross-sectional view of an exemplary receiver unit 3350 for ToF detection. The receiver unit 3350 is similar to the receiver unit 3300 of FIG. 33A, except that the memory module 3210 is now located within the IC wafer 3110. For some memory technologies, such as SRAM and Flash, for a given process node, complete memory modules may be provided as intellectual property (IP) cores by a CMOS foundry or a third-party vendor. Incorporating these IP cores to implement the memory module 3210 of the IC wafer 3110 may reduce research and development efforts.

[0372] FIG. 33D shows a schematic cross-sectional view of an exemplary receiver unit 3360 for ToF detection. The receiver unit 3360 is similar to the receiver unit 3350 of FIG. 33C, except that the pixel transistor array 3320 is now disposed within the sensor wafer 3130. Placing the pixel transistor array 3320 within the sensor wafer 3130 may allow for improved space utilization within the IC wafer 3110. For example, the memory module 3210 may be placed in a position below the ToF pixel array 3010, which may be unoccupied since the amplifier array 3020 and the ADC 3030 are disposed below the pixel transistor array 3320 to simplify electrical connections between those components.

[0373] 33E shows a schematic cross-sectional view of an exemplary receiver unit 3370 for ToF detection. The receiver unit 3370 is similar to the receiver unit 3360 of FIG. 33D, except that the memory module 3210 is now disposed within the sensor wafer 3130.

[0374] While the ToF pixel array 3010, pixel transistor array 3320, memory module 3210, and ADC 3030, and amplifier array 3020 are shown as schematic blocks for purposes of illustration, in general, portions of each of those components may be distributed across the respective wafers 3110 and 3130. For example, the ToF pixels 3140 of the ToF pixel array 3010 and the pixel transistors 3120 of the pixel transistor array 3320 may be distributed across the wafers 3110 and / or 3130, and the memory bits of the memory modules 3210 or 3340 may be distributed across the wafers 3110 and / or 3130 in space not occupied by the ToF pixel array 3010 or pixel transistor array 3320.

[0375] In general, additional electrical and optical components may be added to the receiver units described in Figures 33A-33E. Examples of electrical components include resistors, inductors, data processing circuits (e.g., processors, FPGAs, ASICs), bias circuits (e.g., supplying bias voltages to the control terminals 3154 and 3164 of the sensor wafer 3130 and / or the ToF pixels 3140), and light source driver circuits (e.g., supplying electrical pulses to the transmitter unit 502 to generate light pulses). Examples of optical components include anti-reflective coatings (ARCs), microlenses, bandpass filters, and reflectors. Examples of microlenses include microball lenses, Fresnel zone plates, and integrated silicon microlenses.

[0376] In general, there may be an intermediate layer between the IC wafer 3110 and the sensor wafer 3130. The intermediate layer may provide various advantages, such as improved electrical coupling between the two wafers, improved bonding quality and yield of the two wafers, and improved optical performance of the receiver unit. The intermediate layer may be formed from a variety of materials, such as dielectrics, polymers, and optical index matching materials.

[0377] Although bidirectional bonding of IC wafer 3110 and sensor wafer 3130 is described with respect to Figures 33A-33E, in general, the receiver unit may be formed by bonding three or more wafers. For example, additional IC wafers may be bonded to integrate additional capacitors to further increase the capacitance associated with pixel array 3010. As another example, additional IC wafers may be bonded to integrate additional memory elements to further increase the memory capacity of memory module 3210.

[0378] In general, the receiver unit sensor wafer 3130 described with respect to Figures 33A-33E can be either a front-side illuminated sensor wafer or a back-side illuminated sensor wafer.

[0379] In general, the sensor wafer 3130, the ToF pixels 3140, or both, may be formed from III-V compound semiconductor materials, Group IV alloy semiconductor materials, or a combination thereof.

[0380] 34 is a schematic cross-sectional view of an exemplary bonding process of an exemplary receiver unit 3400 for ToF detection. The sensor wafer 3130 comprises a ToF pixel array 3140 and a back-end layer 3136. The IC wafer 3110 comprises a pixel transistor 3120 and a back-end layer 3116. The back-end layers 3116 and 3136 comprise interconnects 3170 and bond pads 3172 formed on the respective surfaces of the wafers 3110 and 3130. The surfaces of the back-end layers 3116 and 3136 include the dielectric and metal surfaces of the bond pads 3172. Prior to bonding, the sensor wafer is flipped so that the bond pads 3172 of the sensor wafer 3130 face the bond pads 3172 of the IC wafer 3110. The two wafers are brought into contact in a controlled manner, which may involve control of force, temperature, and forming environment. The combination of dielectric and metallic surfaces allows for hybrid bonding of wafers 3110 and 3130, resulting in both an electrical and mechanical bond between the two wafers.

[0381] Flipping the sensor wafer 3130 for wafer bonding allows for receipt of the optical signal 3410 through the backside of the sensor wafer 3130. The sensor wafer 3130 may be a silicon wafer that is transparent to infrared wavelengths (e.g., >1.1 μm). As such, the infrared optical signal 3410 may reach the ToF pixel 3140 through the backside of the sensor wafer 3130. Such a configuration is referred to as a backside illuminated (BSI) sensor.

[0382] In some implementations, the back-end layer 3136 of the sensor wafer 3130 may include a mirror 3420. The mirror 3420 is disposed below the light absorbing region of the ToF pixel 3140. As such, any light that passes through the pixel 3140 and is not absorbed by the ToF pixel 3140 is reflected by the mirror 3420 and reflected back toward the ToF pixel 3140 to be further absorbed by the ToF pixel 3140. The mirror 3420 may be, for example, a metallic mirror, a dielectric mirror, or a distributed Bragg reflector. The mirror 3420 may be a combination of a dielectric layer (e.g., silicon oxide or silicon nitride) followed by a metal layer. In some implementations, the mirror 3420 may be a concave mirror configured to reflect light toward a focal point disposed within the ToF pixel 3140.

[0383] In some implementations, the sensor wafer 3130 may include a partial mirror 3422. The partial mirror 3422 is formed on the backside of the sensor wafer 3130 and allows a portion of the light to pass into the ToF pixel 3140. The partial mirror 3142 may generate destructive interference at the interface between the partial mirror 3422 and air, such that light reflected by the mirror 3420 towards the partial mirror 3422 is reflected back towards the ToF pixel 3140. When such a condition is met, the partial mirror 3422 in combination with the mirror 3420 forms a resonant cavity, which allows light to be reflected multiple times between the two mirrors 3420 and 3422. The formed resonant cavity may improve the detection efficiency of the ToF pixel 3140 at the resonant frequency of the resonant cavity. The partial mirror 3422 may be, for example, a dielectric mirror or a distributed Bragg reflector. The partial mirror 3422 may have a transmittance substantially equal to the round trip attenuation of light passing through the ToF pixel 3140 and reflected by the mirror 3420 .

[0384] In some implementations, the back-end layer 3116 of the IC wafer 3110 may include a mirror 3424. After bonding the sensor wafer 3130 and the IC wafer 3110, the mirror 3424 is disposed under the light absorbing region of the ToF pixel 3140. As such, light that is not absorbed by the ToF pixel 3140 as it passes through the pixel 3140 is reflected by the mirror 3424 and reflected back toward the ToF pixel 3140 to be further absorbed by the ToF pixel 3140. The mirror 3424 may be, for example, a metal mirror, a dielectric mirror, or a distributed Bragg reflector. The mirror 3424 may be a combination of a dielectric layer (e.g., silicon oxide or silicon nitride) followed by a metal layer. In some implementations, the mirror 3424 may be a concave mirror configured to reflect light toward a focal point disposed within the ToF pixel 3140.

[0385] In the previous section, an approach to increase integration time by increasing capacitance was described. An important consideration when determining the integration time is the dark current of the photodetector, which is the current that flows in the absence of optical signal and ambient light. In general, the signal-to-noise ratio (SNR) of optical measurements made through a photodetector, such as ToF measurements made through a switched photodetector, is negatively affected by the presence of dark current. For example, the SNR of optical measurements through a photodetector is linearly proportional to the integration time. Furthermore, the integration time for a given capacitance may be limited by the dark current, as it continuously discharges the capacitor charge even in the absence of optical signal and ambient light.

[0386] The dark current of a photodetector is typically an exponential function of the reverse bias voltage established between the cathode and anode of the photodetector. As such, a controlled reduction in the reverse bias voltage while preserving the overall operation of the photodetector can result in improved SNR performance of the photodetector.

[0387] 35 shows a schematic diagram of a circuit 3500 for operating a ToF pixel. The circuit 3500 comprises a first readout subcircuit 3510 and a second readout subcircuit 3530 coupled to a switched photodetector 3550. The first readout subcircuit 3510 comprises a first MOSFET transistor 3512 and a second MOSFET transistor 3520. The second readout subcircuit 3530 comprises a third MOSFET transistor 3532 and a fourth MOSFET transistor 3540. The first readout subcircuit 3510 is coupled to a first source follower circuit 3560 and the second readout subcircuit 3530 is coupled to a second source follower circuit 3570. The first read subcircuit 3510 and the first source follower circuit 3560 may be referred to as a first read circuit, and the second read subcircuit 3530 and the second source follower circuit 3570 may be referred to as a second read circuit.

[0388] The switched photodetector 3550 comprises a body portion 3551, a first readout terminal 3552, and a second readout terminal 3554. The switched photodetector 3550 may be implemented as any of the switched photodetectors previously described, such as the switched photodetector 100 of FIG. 1A. The body portion 3551 may be similar to the light absorbing layer 106 or the substrates 202, 302, and 402, and may be doped with a p-type dopant. The first and second readout terminals 3552 and 3554 may be n-type doped regions, which may be similar to the n-type doped regions 126 and 136 of FIG. 1A, for example. A photocurrent generated by the switched photodetector 3550 may be collected by either the first readout terminal 3552 or the second readout terminal 3554 based on a control operation of the switched photodetector 3550.

[0389] Each of the MOSFET transistors 3512, 3520, 3532, and 3540 includes a source terminal, a drain terminal, and a gate terminal. The source and drain terminals may be identical in the underlying structure, but may be distinguished based on the direction of current flow through the transistor. For example, in an N-type MOSFET having a P-type channel region ("NMOS transistor"), current may flow through the channel region from the drain terminal to the source terminal, while in a P-type MOSFET having an N-type channel region ("PMOS transistor"), current may flow through the channel region from the source terminal to the drain terminal. Because the designation of the terms source and drain is based on convention, and because the underlying structures may be similar or identical, the source and drain terminals may be referred to as first and second channel terminals in describing the connectivity between the MOSFET and other circuit elements.

[0390] The gate terminal controls the flow of current through the source and drain terminals. For example, a control voltage higher than the threshold voltage Vth may allow current to flow through the source and drain terminals. Such an operating mode of a MOSFET transistor may be referred to as operating in the saturation region or the triode operating region, depending on the voltage of the source and drain terminals with respect to the gate terminal. In the saturation region, the current flowing through the source and drain terminals is less sensitive to changes in the difference between the source and drain voltages (i.e., the output impedance of the transistor is high). In the triode region, the current flowing through the source and drain terminals is approximately linearly proportional to the difference between the source and drain voltages (i.e., the transistor behaves similarly to a resistor). A control voltage lower than the threshold voltage may reduce the current flow through the source and drain terminals. For example, the current flow may decrease exponentially when the control voltage becomes lower than the threshold voltage. Such an operating mode of a MOSFET transistor may be referred to as operating in the subthreshold operating region.

[0391] For purposes of illustration, the circuit 3500 is implemented using N-type MOSFET transistors. For the first readout sub-circuit 3510, a source terminal of the first MOSFET 3512 is coupled to a first readout terminal 3552. A drain terminal of the first MOSFET 3512 is coupled to a source terminal of the second MOSFET 3520, and this node of coupling may be referred to as a first output node 3515 of the first readout sub-circuit 3510. A capacitor may be coupled to the first output node 3515, which may be similar to the capacitors 3112 and 3132 of FIGS. 31A and 31B. A drain terminal of the second MOSFET 3520 is coupled to the first power supply node 3508. Similarly, for the second readout sub-circuit 3530, a source terminal of the third MOSFET 3532 is coupled to a second readout terminal 3554. The drain terminal of the third MOSFET 3532 is coupled to the source terminal of the fourth MOSFET 3540, and this node of coupling may be referred to as a second output node 3535 of the second readout subcircuit 3530. A capacitor may be coupled to the second output node 3535, which may be similar to the capacitors 3112 and 3132 of Figures 31A and 31B. The drain terminal of the fourth MOSFET 3540 is coupled to the first power supply node 3508.

[0392] The first power supply node 3508 provides a first power supply voltage to the first and second readout subcircuits 3510 and 3530. The second power supply node 3502 provides a second power supply voltage to the first and second source follower circuits 3560 and 3570. One or more power supply voltage sources may provide suitable first and second power supply voltages to the first and second power supply nodes 3508 and 3502, which may depend on various factors including the particular process node, the circuit design, the characteristics of the switched photodetector 3550, the reset voltage of the capacitor coupled to the first output node 3515, and the charge-to-voltage conversion gain. The first power supply node 3508 may be referred to as a VU node, and the first power supply voltage of the VU node may be, for example, a user-defined...

Claims

1. A first substrate, one or more first capacitors; A switched photodetector pixel, comprising: an absorptive region configured to receive light and generate photocarriers; a first substrate including a switched photodetector pixel including a plurality of readout terminals configured to collect a portion of the photocarriers; a second substrate bonded to the first substrate, one or more second capacitors; a pixel transistor configured to collect photocarriers from the plurality of readout terminals, and a second substrate including a pixel transistor including a plurality of readout transistors each electrically coupled to a respective one of the plurality of readout terminals of the first substrate, the one or more first capacitors and the one or more second capacitors store photo-generated carriers from a switched photodetector; A time-of-flight photodetection device, wherein the plurality of readout transistors are electrically coupled to the one or more first capacitors in the first substrate and the one or more second capacitors in the second substrate.

2. 2. The photodetection device of claim 1, wherein the one or more first capacitors include a plurality of first sub-capacitors, the one or more second capacitors include a plurality of second sub-capacitors, and one of the plurality of first sub-capacitors and one of the plurality of second sub-capacitors are electrically connected in a parallel configuration and electrically coupled to a same readout transistor of the plurality of readout transistors.

3. the switched photodetector pixel further includes a plurality of control terminals configured to control a flow of photocarriers to the plurality of readout terminals; 2. The photodetection device of claim 1, wherein the pixel transistor further comprises a plurality of control transistors electrically coupled to the plurality of control terminals and configured to provide one or more control signals to the plurality of control terminals.

4. 2. The light detection device of claim 1, wherein the switched photodetector pixel is a back-illuminated pixel in which light enters the switched photodetector pixel from a back side of the first substrate opposite a front side of the first substrate on which the switched photodetector pixel is fabricated.

5. 2. The photo-sensing device of claim 1, wherein the plurality of readout transistors of the pixel transistors comprises a readout circuit having a three-transistor configuration including a reset transistor, a source follower transistor, and a row select transistor.

6. 2. The photodetection device of claim 1, wherein the one or more first capacitors and the one or more second capacitors comprise at least one of a parallel plate capacitor, a floating diffusion capacitor, a metal-oxide-semiconductor (MOS) capacitor, a metal-oxide-metal (MOM) capacitor, and a metal-insulator-metal (MIM) capacitor.

7. The photodetection device of claim 1 , wherein the one or more first capacitors and the one or more second capacitors are each implemented as a bank of capacitors in parallel.

8. each of the plurality of readout transistors includes a source terminal and a drain terminal; the plurality of readout transistors include a first readout transistor and a second readout transistor; the one or more first capacitors are electrically coupled to the source terminal or the drain terminal of the first readout transistor; The photodetection device of claim 1 , wherein the one or more second capacitors are electrically coupled to the source terminal or the drain terminal of the second readout transistor.

9. The photodetector device of claim 1 , wherein the first substrate and the second substrate are bonded by a metal-to-metal bond, an oxide-to-oxide bond, or a hybrid bond.

10. 2. The photodetection device of claim 1, wherein the one or more first capacitors and the one or more second capacitors are electrically coupled to respective readout terminals of the plurality of readout terminals of the switched photodetector pixel without a transistor.

11. 2. The photodetection device of claim 1, wherein the first substrate comprises silicon, the absorption region of the switched photodetector pixel comprises germanium, and the plurality of readout terminals of the switched photodetector pixel comprise germanium.

12. 2. The photodetection device of claim 1, wherein the first substrate comprises silicon, the absorption region of the switched photodetector pixel comprises germanium, and the plurality of readout terminals of the switched photodetector pixel comprise silicon.

13. 2. The photodetection device of claim 1, wherein an absorption region of the switched photodetector pixel is embedded in the first substrate.

14. A first substrate, one or more first capacitors; A switched photodetector pixel, comprising: an absorptive region configured to receive light and generate photocarriers; a plurality of readout terminals configured to collect a portion of the photocarriers; and a pixel transistor configured to collect photocarriers from the plurality of readout terminals, a pixel transistor including a plurality of readout transistors, each of the pixel transistors being electrically coupled to a respective one of the plurality of readout terminals; a second substrate bonded to the first substrate, and a second substrate including one or more second capacitors, the one or more first capacitors and the one or more second capacitors store photo-generated carriers from a switched photodetector; the pixel transistor is electrically coupled to the one or more first capacitors of the first substrate and the one or more second capacitors of the second substrate.

15. 15. The photodetection device of claim 14, wherein the one or more first capacitors include a plurality of first sub-capacitors, the one or more second capacitors include a plurality of second sub-capacitors, and one of the plurality of first sub-capacitors and one of the plurality of second sub-capacitors are electrically coupled in a parallel configuration and electrically coupled to a same readout transistor of the plurality of readout transistors.

16. the switched photodetector pixel further includes a plurality of control terminals configured to control a flow of photocarriers to the plurality of readout terminals; 15. The photodetection device of claim 14, wherein the pixel transistor further comprises a plurality of control transistors electrically coupled to the plurality of control terminals and configured to provide one or more control signals to the plurality of control terminals.

17. each of the plurality of readout transistors includes a source terminal and a drain terminal; the plurality of readout transistors include a first readout transistor and a second readout transistor; the one or more first capacitors are electrically coupled to the source terminal or the drain terminal of the first readout transistor; The photodetection device of claim 14 , wherein the one or more second capacitors are electrically coupled to the source terminal or the drain terminal of the second readout transistor.

18. 15. The photodetection device of claim 14, wherein the one or more first capacitors and the one or more second capacitors are electrically coupled to respective readout terminals of the plurality of readout terminals of the switched photodetector pixel without any intervening transistors.

19. 15. The photodetection device of claim 14, wherein the first substrate comprises silicon, the absorption region of the switched photodetector pixel comprises germanium, and the plurality of readout terminals of the switched photodetector pixel comprise germanium.

20. 15. The photodetection device of claim 14, wherein the first substrate comprises silicon, the absorption region of the switched photodetector pixel comprises germanium, and the plurality of readout terminals of the switched photodetector pixel comprise silicon.

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