CLOCK GENERATION CIRCUIT, PROCESSING METHOD, AND PROGRAM

Abstract

A clock generating circuit capable of generating a clock adjusted to an appropriate phase is provided. [Solution] The clock generating circuit includes a detection means for detecting, when a device operating according to a clock is initialized, a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency that is 1 / kth of the normal frequency, a conversion means for converting each of the first phase difference and the second phase difference into analog voltage values, a comparison means for comparing the two voltage values ​​after conversion by the conversion means, and a transmission means for transmitting an output characteristic control signal to a correction circuit at a value that minimizes the error, which is the comparison result by the comparison means.

Description

[Technical field]

[0001] The present disclosure relates to a clock generation circuit, a processing method, and a program. [Background technology]

[0002] In a device that processes digital data, the data processing may be performed based on a timing based on a clock. Patent Document 1 discloses a related technique, which relates to a circuit that adjusts the phase of a clock. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-116680 A Summary of the Invention [Problem to be solved by the invention]

[0004] Meanwhile, in a circuit related to the technique described in Patent Document 1, there is a demand for a technique capable of generating a clock whose phase is adjusted appropriately.

[0005] An object of each aspect of the present disclosure is to provide a clock generation circuit, a processing method, and a program that can solve the above problems. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, a clock generation circuit includes: a clock generating circuit to which a first clock and a second clock having an opposite phase to the first clock are input, the clock generating circuit comprising: detection means for detecting, at initialization of a device operating in accordance with the first clock and the second clock, a first phase difference between the first clock and the second clock, when the first clock and the second clock have a first frequency, the first phase difference corresponding to a phase difference that is j times the minimum phase adjustment amount that can be realized by a clock data recovery circuit; and detecting, at initialization of a device operating in accordance with the first clock and the second clock, a second phase difference between the first clock and the second clock, when the first clock and the second clock have a frequency that is 1 / k of the first frequency, the second phase difference corresponding to a phase difference that is (j / k) times the minimum phase adjustment amount. output means for outputting a signal of a first voltage magnitude which is an output signal when the first clock and the second clock at the first frequency are used as input differential signals at a timing when a phase difference is detected, and a signal of a second voltage magnitude which is an output signal when the first clock and the second clock at a frequency that is 1 / k of the first frequency at a timing when the second phase difference is detected are used as input differential signals; comparing means for comparing the signal of the first voltage magnitude with the signal of the second voltage magnitude; and transmitting means for transmitting a control signal to a correction circuit which is a circuit for adjusting the first phase difference and the second phase difference, based on a comparison result by the comparing means, to control the first phase difference and the second phase difference. .

[0007] According to another aspect of the present disclosure, a processing method includes: A processing method executed by a clock generating circuit to which a first clock and a second clock having an opposite phase to the first clock are input, the processing method including, at initialization of a device that operates according to the first clock and the second clock, detecting a first phase difference between the first clock and the second clock when the first clock and the second clock have a first frequency, the first phase difference corresponding to a phase difference that is j times a minimum phase adjustment amount that can be realized by a clock data recovery circuit, and detecting a second phase difference between the first clock and the second clock when the first clock and the second clock have a frequency that is 1 / k of the first frequency, the second phase difference corresponding to a phase difference that is (j / k) times the minimum phase adjustment amount. outputting a signal of a first voltage magnitude which is an output signal when the first clock and the second clock at the first frequency at a timing when the first phase difference is detected are input differential signals, and a signal of a second voltage magnitude which is an output signal when the first clock and the second clock at a frequency that is 1 / k of the first frequency at a timing when the second phase difference is detected are input differential signals; comparing a level of the signal of the first voltage magnitude with the signal of the second voltage magnitude; and transmitting a control signal to a correction circuit which is a circuit for adjusting the first phase difference and the second phase difference based on a comparison result, to cause the first phase difference and the second phase difference to be controlled. .

[0008] According to another aspect of the present disclosure, a program includes: The computer of the clock generating circuit executes the above processing method. . Effect of the Invention

[0009] According to each aspect of the present disclosure, a clock adjusted to an appropriate phase can be generated. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 is a diagram illustrating an example of a configuration of a receiving circuit according to some embodiments of the present disclosure. [Diagram 2] A diagram showing examples of clocks IN000, IN090, IN180, and IN270 in some embodiments of the present disclosure. [Diagram 3] FIG. 11 is a diagram showing an example of each adjustment code at the time of phase switching in some embodiments of the present disclosure. [Figure 4] FIG. 1 is a diagram illustrating an example of a configuration of a multi-phase clock generation circuit according to some embodiments of the present disclosure. [Diagram 5] FIG. 2 is a diagram showing an example of an image of a phase relationship of clocks output by a 4-phase / 8-phase conversion unit according to some embodiments of the present disclosure. [Figure 6] FIG. 2 is a diagram illustrating an example of a configuration of a PI circuit according to some embodiments of the present disclosure. [Figure 7] 5 is a diagram illustrating an example of a clock output by an eight-phase output switching unit according to some embodiments of the present disclosure. FIG. [Figure 8] FIG. 4 is a diagram illustrating a first example of a processing flow of a receiving circuit according to some embodiments of the present disclosure. [Figure 9] FIG. 11 is a diagram illustrating a second example of a processing flow of a receiving circuit according to some embodiments of the present disclosure. [Figure 10] FIG. 4 is a diagram illustrating an example of a clock generated by an eight-phase output switching unit according to some embodiments of the present disclosure. [Figure 11] FIG. 13 illustrates a portion of a waveform that has been interpolated and overwritten by a PI circuit according to some embodiments of the present disclosure. [Figure 12] FIG. 1 is a first diagram for explaining clock correction in some embodiments of the present disclosure. [Figure 13]FIG. 2 is a second diagram for explaining clock correction in some embodiments of the present disclosure. [Figure 14] FIG. 2 is a diagram illustrating an example of a configuration of a 4-phase / 8-phase conversion unit according to some embodiments of the present disclosure. [Figure 15] FIG. 2 is a diagram illustrating an example of a configuration of a clock generation circuit according to some embodiments of the present disclosure. [Figure 16] FIG. 2 is a diagram illustrating an example of a process flow of a clock generation circuit according to some embodiments of the present disclosure. [Figure 17] FIG. 1 is a schematic block diagram illustrating a configuration of a computer according to at least one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described in detail with reference to the drawings. <Embodiment> (Receiver circuit configuration) 1 according to an embodiment of the present disclosure will be described with reference to the drawings. In the receiving circuit 1, a multi-phase clock generating circuit 20 described later detects and corrects a deviation (variation) in the delay amount of one step of delay adjustment by a clock data recovery (CDR) circuit, which occurs when the clock speed is switched to a low speed (for example, operating at half the speed of a normal clock), when the receiving circuit 1 (an example of a device that operates according to a clock) is initialized after the receiving circuit 1 is powered on.

[0012] Fig. 1 is a diagram illustrating an example of a configuration of a receiving circuit 1 according to some embodiments of the present disclosure. As shown in Fig. 1, the receiving circuit 1 includes a PLL (Phase Locked Loop) 10, a multi-phase clock generating circuit 20, a sampling latch 30, a Demux 40, and a phase detection circuit 50. In the receiving circuit 1, the multi-phase clock generating circuit 20 and the phase detection circuit 50 form a clock data recovery (CDR) circuit.

[0013] The PLL10 outputs input differential clocks IN000 / IN180 and IN090 / IN270. The clock IN180 is a clock that is 180° inverted in phase with respect to the clock IN000. The input differential clocks IN000 / IN180 are shown as a pair of differential clocks, the clock IN000 and the clock IN180. The clock IN090 is a waveform that is delayed in phase by 90° with respect to the rising edge of the clock IN000. The clock IN270 is a clock that is 180° inverted in phase with respect to the clock IN090. The input differential clocks IN090 / IN270 are shown as a pair of differential clocks, the clock IN090 and the clock IN270. FIG. 2 is a diagram showing an example of the clocks IN000, IN090, IN180, and IN270 in some embodiments of the present disclosure. As shown in FIG. 2, the clocks IN000, IN090, IN180, and IN270 have waveforms that are delayed in phase by 90°, 180°, and 270°, respectively, with the clock IN000 as the reference.

[0014] The sampling latch 30, the Demux 40, and the phase detection circuit 50 detect the phase relationship between the data and the clock, which is a function of clock data recovery. The phase detection circuit 50 determines whether to delay or advance the phase of the sampling clock based on the result of this phase detection. FIG. 3 is a diagram showing an example of each adjustment code at the time of phase switching in some embodiments of the present disclosure. When delaying the phase of the clock, the phase detection circuit 50 controls the step in the plus direction (downward direction of the table) in the control code correspondence table shown in FIG. 3, for example, and when delaying, controls the step in the minus direction (upward direction of the table) in the control code correspondence table shown in FIG. 3, for example. As a result, the phase detection circuit 50 controls whether the 8-phase clock output in FIG. 1 (output in FIG. 3) is delayed by one step plus or minus with respect to the data. The PLL 10 is a clock generation source.

[0015] 4 is a diagram illustrating an example of a configuration of a multi-phase clock generating circuit 20 according to some embodiments of the present disclosure. As shown in FIG. 4, the multi-phase clock generating circuit 20 includes an input path switching unit 201, a 4-phase / 8-phase conversion unit 202, an 8-phase output switching unit 203, a control switching unit 204, and a phase difference detection unit 205.

[0016] The input path switching unit 201 switches the path of the clock signal that is input when performing (enabling) phase difference detection. The input path switching unit 201 normally selects the Low (logic 0) side according to the input path switching signal. Furthermore, when performing clock phase difference detection, the input path switching unit 201 switches the input path switching signal to the High (logic 1) side.

[0017] 4, the 4-phase / 8-phase conversion unit 202 includes buffers 202a and 202b. The 4-phase / 8-phase conversion unit 202 receives, as an input clock, a 4-phase clock that is the output of the input path switching unit 201 in the preceding stage.

[0018] The buffer 202a is, for example, a CML (Current Mode Logic) buffer. The buffer 202a delays each of the input differential clocks IN000 / IN180 and IN090 / IN270 by 45° to generate 8 phases from 4 phases. This delay amount varies due to manufacturing variations for each buffer 202a. As a result, the clock data recovery (CDR) circuit is susceptible to clock jitter due to variations for each buffer 202a, and in order to configure a clock data recovery (CDR) circuit compatible with a plurality of frequencies (transmission speeds), it is necessary to optimize each of them. The buffer 202b receives the differential signal output by the buffer 202a and outputs a desired differential signal to the 8-phase output switching unit 203.

[0019] 5 is a diagram illustrating an example of an image of the phase relationship of clocks output by the 4-phase / 8-phase converter 202 according to some embodiments of the present disclosure. If the clock corresponding to the input differential clock IN000 is clock clk000i, the clock corresponding to the input differential clock IN090 is clock clk090i, the clock corresponding to the input differential clock IN180 is clock clk180i, and the clock corresponding to the input differential clock IN270 is clock clk270i, the 4-phase / 8-phase converter 202 outputs clocks of eight phases, clocks clk000i, clk045i, clk090i, clk135i, clk180i, clk225i, clk270i, and clk315i, as shown in FIG. As shown in Figure 5, with clock clk000i as the reference, the clocks clk045i, clk090i, clk135i, clk180i, clk225i, clk270i, and clk315i have waveforms that are delayed in phase by 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively.

[0020] The output characteristic control signal shown in FIG. 4 makes it possible to control the slew rate of the buffers 202a and 202b.

[0021] 6 is a diagram illustrating an example of the configuration of a PI circuit 203b according to some embodiments of the present disclosure. The PI circuit 203b includes first to fourth MOS transistors M1 to M4, first and second resistors R1 and R2, and first and second current sources Ia and Ib. The first and third MOS transistors M1 and M3 have their sources connected in common and are connected to a power supply potential VDD via the resistor R1. The second and fourth MOS transistors M2 and M4 have their sources connected in common and are connected to a power supply potential VDD via the resistor R2. The first and second MOS transistors M1 and M2 have their drains connected in common and are connected to a current source Ia. The third and fourth MOS transistors M3 and M4 have their drains connected in common and are connected to a current source Ib.

[0022] Also, the gate of the first MOS transistor M1 is connected to the input terminal A. The gate of the second MOS transistor M2 is connected to the input terminal AB. The gate of the third MOS transistor M3 is connected to the input terminal B. The gate of the fourth MOS transistor M4 is connected to the input terminal BB. Also, a control bit SB is applied to the current source Ia through a control terminal, and a control bit SA is applied to the current source Ib through a control terminal. An output terminal OUT is connected between the commonly connected sources of the second and fourth MOS transistors M2 and M4 and the resistor R2, and an output terminal OUTB is connected between the commonly connected sources of the first and third MOS transistors M1 and M3 and the resistor R1.

[0023] The eight-phase output switching unit 203 includes a front-stage unit 203a and a rear-stage unit 203b (that is, the above-mentioned PI circuit 203b). The eight-phase output switching unit 203 receives the output of the four-phase / eight-phase conversion unit 202 as an input clock.

[0024] The front stage 203a switches the clock path by switching the control signal SELC[7:0] between 1 and 0. The rear stage 203b outputs a sampling clock in 1-STEP increments by switching the control of SELP1[15:0] and SELP2[15:0] between 1 and 0. FIG. 7 is a diagram showing an example of clocks output by the 8-phase output switching unit 203 according to some embodiments of the present disclosure, showing three clocks out of eight representative clocks. Part (a) of FIG. 7 shows an input clock. Part (c) of FIG. 7 shows an output clock. Part (b) of FIG. 7 shows how the phase of the clock changes by one STEP every time the control signal changes by one code. Since there are only eight output clocks, the phase of each clock is kept at 45°. Therefore, if the control code of the output clock shown in part (c) of FIG. 7 is a control code that delays the output clock by one STEP, the entire 8-phase clock is delayed by one STEP.

[0025] The control switching unit 204 switches between two groups of phase control signals according to a phase switching signal from the phase detection circuit 50 of the CDR circuit. The phase control signal of the first group is the phase control signal (Auto). The phase control signals (Auto) are SELC* and SELP*. During normal operation, the phase control signal of the control switching unit 204 is set (fixed) to Low (logic 0). This selects a path to the 8-phase output switching unit 203 through which the phase control signal (Auto) propagates.

[0026] The second group of phase control signals is the phase control signal (Manual). The control switching unit 204 sets the control switching signal to High (logic 1). This selects a path to the 8-phase output switching unit 203 through which the phase control signal (Manual) propagates.

[0027] The phase difference detection unit 205 detects the delay amount of the difference between the inputs of the OUT045 and OUT135 clocks output by the 8-phase output switching unit 203. The phase difference detection unit 205 then outputs the phase difference as a voltage level. For example, the internal circuit of the phase difference detection unit 205 is a phase detection circuit used in a general PLL or the like.

[0028] Note that the processing performed by the receiving circuit 1 according to the embodiment of the present disclosure is not limited to the above-mentioned processing. For example, the receiving circuit 1 may perform the processing described below.

[0029] (Processing performed by the receiving circuit) Next, a process performed by the receiving circuit 1 according to an embodiment of the present disclosure will be described. Fig. 8 is a diagram showing a first example of a process flow of the receiving circuit 1 according to some embodiments of the present disclosure. Fig. 9 is a diagram showing a second example of a process flow of the receiving circuit 1 according to some embodiments of the present disclosure. First, the operation of the entire multi-phase clock generation circuit 20 during normal operation will be described with reference to Fig. 8.

[0030] It is assumed that the following settings are made before the entire multi-phase clock generating circuit 20 starts operating during normal operation.

[0031] During normal operation, the input path switching signal is selected as Low (logic 0). As a result, it is assumed that the input path switching unit 201 is set to output IN090 / IN270 to the next-stage 4-phase / 8-phase conversion unit 202. Also, during normal operation, Low (0) is selected as the control switching signal. As a result, it is assumed that the phase control signal (Auto) output by the phase detection circuit 50 is selected. Also, it is assumed that the 4-phase / 8-phase conversion unit 202 is set to adjust the phase of the 4-phase clock between 0° and 90° by utilizing the delay of the CML buffer.

[0032] The input path switching unit 201 receives four-phase clocks, IN000, IN180, IN090, and IN270, shown in Fig. 2, which are output from the PLL 10 and have a phase shift relationship (step S1). In accordance with the settings, the input path switching unit 201 outputs IN090 / IN270 to the next-stage 4-phase / 8-phase conversion unit 202 (step S2).

[0033] In accordance with the setting, the 4-phase / 8-phase converter 202 adjusts the phase of the 4-phase clock between 0° and 90° using the delay of the CML buffer (step S3). For example, the 4-phase / 8-phase converter 202 generates 8-phase clocks with a phase shift of 45° between each clock, as shown in Fig. 5. The 4-phase / 8-phase converter 202 then outputs the generated 8-phase clocks to the 8-phase output switch 203 in the next stage.

[0034] 5 output from the 4-phase / 8-phase converter 202 (step S4). The 8-phase output switch 203 optimizes the phases of the 8-phase clock under the control of SELC[7:0], SELP1[15:0], and SELP2[15:0] (step S5).

[0035] According to the setting, the phase control signal (Auto) output by the phase detection circuit 50 is selected. Specifically, for example, the control code of the eight-phase output switching unit 203 is the control code shown in Fig. 3. The eight-phase output switching unit 203 generates an optimal clock according to SELC[7:0], SELP1[15:0], and SELP2[15:0] according to the code shown in Fig. 3.

[0036] Part (c) of Fig. 7 shows examples of output clocks OUT00, OUT045, and OUT090. Note that the output clocks OUT00, OUT045, and OUT090 shown in part (c) of Fig. 7 are examples in which SELC[7:0]=00000011 and SELP1[15:0]=SELP2[15:0]=0000000011111111 are selected as the internal control codes, respectively.

[0037] In this case, some of the input clocks to the 8-phase output switching unit 203 are the clocks clk000i, clk045i, and clk090i shown in part (a) of Fig. 7. Also, the waveform shown in part (b) of Fig. 7 is an image diagram of a composite waveform obtained by interpolating the waveform by the PI circuit 203b when the 16 stages of SELP*[15:0] are switched every 2 STEPs. In other words, the waveform shown in part (b) of Fig. 7 is a waveform displayed every 1 STEP, and only 8 waveforms out of the 16 waveforms are displayed, and further, 8 waveforms interpolated by the PI circuit 203b are displayed. More specifically, the PI circuit 203b interpolates the waveforms of 16 steps of the clocks clk000i and clk045i shown in part (a) of Fig. 7, interpolates the waveforms of 16 steps of the clocks clk045i and clk090i, and overlays the interpolated waveforms on the clock clk090i and the next clock clk135i to produce the waveform shown in part (b) of Fig. 7. Furthermore, the waveform shown in part (c) of Fig. 7 is an image diagram of the optimal clock output from the 8-phase output switching unit 203. However, in the waveform shown in part (c) of Fig. 7, the waveforms after OUT135 are omitted.

[0038] Fig. 10 is a diagram showing an example of a clock generated by the eight-phase output switching unit 203 according to some embodiments of the present disclosure. As a result, the eight-phase output switching unit 203 generates a clock optimally adjusted to the edge of the data change point and the center of the data, as shown in Fig. 10. The clock thus generated by the eight-phase output switching unit 203 is used as the clock of the sampling latch.

[0039] Here, let us consider the details of the waveforms interpolated and overwritten by the PI circuit 203b shown in part (b) of FIG. 7. FIG. 11 is a diagram showing a part of the waveforms interpolated and overwritten by the PI circuit 203b according to some embodiments of the present disclosure. As shown in FIG. 11, the waveforms interpolated and overwritten by the PI circuit 203b shown in part (b) of FIG. 7 may have a large delay amount near the center at intervals of 1 STEP, resulting in uneven delay amounts. This is because each phase interpolation by the PI circuit 203b is a phase interpolation synthesized with waveforms having a phase difference of 45°, and the maximum phase difference of 1 STEP is due to the waveform selected in the middle by SELP*[15:0]. In other words, 1 STEP is created by correction between each clock, and the phase of 45° is divided into 16, but it may be difficult to make the phase difference of each STEP from 0 to 15 the same delay difference. The tendency for the delay amount to be large near the center at one step intervals and for the delay amount to be non-uniform becomes more pronounced the faster the rising edge of the clock waveform and the slower the clock frequency. As a result, the optimal point of the sampling clock fluctuates, causing clock jitter and affecting the performance of the receiving circuit 1 (for example, deterioration of the transmission error rate (transmission error)). For this reason, it is desirable for the PI circuit 203b to correct the clock (i.e., to interpolate the phase of the clock) so that the steps are as uniform as possible.

[0040] Next, a second example of the process flow of the receiving circuit 1 according to some embodiments of the present disclosure shown in FIG. 9 will be described. The following method is an example of a method for correcting the clock so that the PI circuit 203b has as uniform a STEP as possible. In the multi-phase clock generating circuit 20, the input path switching signal of the input path switching unit 201 is set to High (logic 1) to use only the clocks of IN000 and IN180 (step S11). In addition, the control switching unit 204 separates the control code of the phase detection circuit 50 from the feedback by setting the control switching signal to High (logic 1) so that SELC[7:0], SELP1[15:0], and SELP2[15:0] can be freely switched (step S12). FIG. 12 is a first diagram for explaining the correction of the clock in some embodiments of the present disclosure. FIG. 13 is a second diagram for explaining the correction of the clock in some embodiments of the present disclosure. Here, a method for detecting the phase of jSTEP (or any STEP position, number of STEPs) (for example, 1 STEP) and correcting the clock will be described.

[0041] The diagram shown in part (a) of FIG. 12 is a diagram showing a state where the feedback of the phase detection circuit 50 is disconnected. It is assumed that the control code SELC[7:0]=00000011. When the phase difference detection unit 205 performs phase detection, it switches the input path switching unit 201 to "1". Therefore, when SELP1[15:0] and SELP2[15:0] have the same value, the 8-phase output switching unit 203 outputs clocks of the same phase to the clocks OUT045A and OUT045B, and the clocks OUT225A and OUT225B. When SELP2 is changed while SELP1 is fixed, the 8-phase output switching unit 203 outputs a clock with a phase difference. For example, when control codes SLEP1[0000000001111111] and SELP2[0000000111111111] are selected, the phase difference detection unit 205 outputs a voltage level that detects a phase difference ΔT of jSTEPs (e.g., 2STEPs) shown in part (b) of FIG. 12 to the clocks OUT045A and OUT045B shown in part (a) of FIG. 12 (step S13).

[0042] Next, the frequency of the clock of the PLL10 is reduced to 1 / k (e.g., 1 / 2), and further, by selecting only SELP2[15:0] to SELP2[0000000011111111], the phase difference detection unit 205 outputs a voltage level that detects a phase difference ΔT' of (j / k) steps (e.g., 1 step) to the clocks OUT045A' and OUT045B' shown in part (a) of FIG. 13 (step S14). Since the frequency (speed) of the clock is reduced to 1 / k (e.g., 1 / 2), and the step of SLEP2[15:0] is reduced to (j / k) steps (e.g., 1 step), ΔT=ΔT', and ideally the level outputs match (actually they are close). When the clock frequency is slow, the variation in the delay amount becomes noticeable. Therefore, the phase difference detection unit 205 uses the output level of the phase difference ΔT of (j / k) steps (for example, 2 steps) when the clock of the PLL 10 is a normal clock as a reference, and compares it with the voltage level of the phase difference ΔT' of (j / k) steps (for example, 1 step) when the clock frequency is 1 / k (for example, 1 / 2), so that the phase difference ΔT' becomes a phase difference ΔT with small step variation, and feeds it back to the output characteristic control signal shown in FIG. 4. This process by the phase difference detection unit 205 makes it possible to optimally adjust the phase difference of (j / k) steps (for example, 1 step) (that is, the delay amount for each (j / k) steps (for example, 1 step) becomes the same delay, and the phase difference variation is uniform, thereby improving the linearity when the delay amount is accumulated) (step S15). The output characteristic signal shown in FIG. 3 shows the control of the rise / fall of the output signal of the CML buffer of the buffers 202a and 202b. The phase difference detection unit 205 uses the output characteristic signal to perform control to smooth the output signals of the CML buffers 202a and 202b, thereby changing the input waveform of the 8-phase output switching unit 203. Note that the variation in the delay amount refers to the difference between the designed (j / k) step (e.g., 1 step) delay created by phase interpolation and the actual (j / k) step (e.g., 1 step) delay.

[0043] Fig. 14 is a diagram showing an example of the configuration of a 4-phase / 8-phase converter 202 according to some embodiments of the present disclosure. The 4-phase / 8-phase converter 202 shown in Fig. 14 shows a configuration of the 4-phase / 8-phase converter when phase interpolation from 0° to 45° cannot be adjusted by the slew rate alone. The 4-phase / 8-phase converter 202 shown in Fig. 14 not only controls the slew rate, but also changes the 45° phase switching for each frequency, thereby enabling a wider range of highly accurate adjustment of phase interpolation.

[0044] The receiving circuit 1 according to an embodiment of the present disclosure has been described above. In the multi-phase clock generating circuit 20 (an example of a clock generating circuit) of the receiving circuit 1, the phase difference detecting unit 205 (an example of a detecting means) detects a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency that is 1 / k of the normal frequency when the receiving circuit 1 (an example of a device that operates according to a clock) is initialized (for example, j and k are each 2, and the first phase difference of 2 steps at a normal frequency and the second phase difference of 1 step at a frequency that is 1 / 2 of the normal frequency are detected). The phase difference detecting unit 205 (an example of a converting means, an example of a comparing means, an example of a transmitting means) converts each of the first phase difference and the second phase difference into analog voltage values, compares the two converted voltage values, and transmits an output characteristic control signal with a value that minimizes the error to the 4-phase / 8-phase converting unit 202 (an example of a correction circuit).

[0045] Here, we will explain a typical multi-phase clock generation circuit that uses a PI (Phase Interpolator) circuit. A typical multi-phase clock generation circuit generates an intermediate phase by synthesizing clock waveforms with different phases (delays) and interpolates it to create a clock waveform with the optimal phase for sampling data. For example, the phase of a sampling clock in a digital circuit configuration created by a PI circuit can be switched over 360°. Therefore, if the circuit can divide the input phase by 360, it can create phases that are shifted by 1° (if the circuit can divide it by 180, it can create phases that are shifted by 2°).

[0046] However, when synthesizing waveforms with a phase shift of 45° (or 90°), it is necessary to optimize for each frequency, and when changing the operating speed, it is necessary to mount a frequency divider circuit or the like in the subsequent stage, or to control according to the speed. Generally, one of the drawbacks of a multi-phase clock generation circuit using a PI circuit is that if the operating speed is simply lowered, the synthesized waveform will have a phase shifted from the optimal delay, resulting in uneven STEPs (delay widths). Depending on the design, distortion may occur in the waveform, which may cause signal transmission errors or limit the specifications at the time of design. Therefore, a design that optimizes the clock according to the frequency is necessary. As an example, when the phase difference is large (for example, 45°), there is a method of adjusting the clock phase by making the phase linear by smoothing the waveform using a mechanism that controls the slew rate, or by adding a 45° phase delay that matches the frequency. However, simply adding a function to control the slew rate will cause waveform distortion and there is a limit to the clock phase adjustment, so it is desirable to add a circuit that generates a 45° phase. However, since the 45° phase is created by a delay buffer, it is necessary to design it more precisely according to the variation in the LSI process.

[0047] In contrast to such general multi-phase clock generating circuits, the multi-phase clock generating circuit 20 in the receiving circuit 1 can generate clocks that are adjusted to appropriate phases.

[0048] <Other embodiments> The multi-phase clock generating circuit 20 according to an embodiment of the present disclosure has been described as a multi-phase clock generating circuit with 4-phase input and 8-phase output conversion. However, the multi-phase clock generating circuit 20 according to other embodiments of the present disclosure may be a multi-phase clock circuit with 4-phase input and 4-phase output, or 4-phase input and 16-phase output, which realizes the same functions as the multi-phase clock generating circuit 20 according to an embodiment of the present disclosure.

[0049] Also, in the receiver circuit 1 according to one embodiment of the present disclosure, one PLL 10 is connected to one multi-phase clock generation circuit 20. However, the receiver circuit 1 according to another embodiment of the present disclosure may include a plurality of multi-phase clock generation circuits 20, and the plurality of multi-phase clock generation circuits 20 may share one PLL 10. In this way, it is possible to reduce the PLL 10, which has a large mounting area, and thus to reduce the overall mounting area.

[0050] In another embodiment of the present disclosure, the number of phase difference detection sections 205 may be increased to multiple.

[0051] 15 is a diagram illustrating an example of a configuration of a clock generation circuit 300 according to some embodiments of the present disclosure. As illustrated in FIG. 15, the clock generation circuit 300 includes a detection unit 301, a conversion unit 302, a comparison unit 303, and a transmission unit 304.

[0052] At the time of initialization of the receiving circuit 1, the detection means 301 detects a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency that is 1 / kth of the normal frequency. The conversion means 302 converts each of the first phase difference and the second phase difference into an analog voltage value. The comparison means 303 compares the two voltage values ​​after conversion by the conversion means 302. The transmission means 304 transmits to the correction circuit a value that minimizes the error, which is the comparison result by the comparison means 303.

[0053] The detection means 301, conversion means 302, comparison means 303, and transmission means 304 can be realized, for example, by using the functions of the phase difference detection unit 205 illustrated in FIG.

[0054] 16 is a diagram showing an example of a processing flow of the clock generation circuit 300 according to some embodiments of the present disclosure. Next, processing performed by the clock generation circuit 300 according to the embodiments of the present disclosure will be described with reference to FIG.

[0055] The detection means 301 detects a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency that is 1 / k of the normal frequency when the receiving circuit 1 is initialized (step S101). The conversion means 302 converts each of the first phase difference and the second phase difference into an analog voltage value (step S102). The comparison means 303 compares the two voltage values ​​after conversion by the conversion means 302 (step S103). The transmission means 304 transmits the comparison result by the comparison means 303, which is a value that minimizes the error, to the correction circuit (step S104).

[0056] The above describes the clock generation circuit 300 according to an embodiment of the present disclosure. The clock generation circuit 300 can generate a clock that is adjusted to an appropriate phase.

[0057] It should be noted that the order of the processes in the embodiments of the present disclosure may be changed as long as appropriate processes are performed.

[0058] Although the embodiments of the present disclosure have been described, the above-mentioned receiving circuit 1, the multi-phase clock generating circuit 20, and other control devices may have a computer system inside. The above-mentioned process steps are stored in a computer-readable recording medium in the form of a program, and the above-mentioned process is performed by the computer reading and executing the program. Specific examples of computers are shown below.

[0059] 17 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in FIG. 17, the computer 5 includes a CPU (Central Processing Unit) 6, a main memory 7, a storage 8, and an interface 9.

[0060] For example, the above-mentioned receiving circuit 1, multi-phase clock generating circuit 20, and other control devices are each implemented in a computer 5. The operations of the above-mentioned processing units are stored in the storage 8 in the form of a program. The CPU 6 reads the program from the storage 8, loads it in the main memory 7, and executes the above-mentioned processing in accordance with the program. The CPU 6 also secures storage areas in the main memory 7 corresponding to the above-mentioned storage units in accordance with the program.

[0061] Examples of the storage 8 include a hard disk drive (HDD), a solid state drive (SSD), a magnetic disk, a magneto-optical disk, a compact disc read only memory (CD-ROM), a digital versatile disc read only memory (DVD-ROM), and a semiconductor memory. The storage 8 may be an internal medium directly connected to the bus of the computer 5, or an external medium connected to the computer 5 via an interface 9 or a communication line. In addition, when the program is distributed to the computer 5 via a communication line, the computer 5 that receives the program may load the program into the main memory 7 and execute the above-mentioned process. In at least one embodiment, the storage 8 is a non-transitory tangible storage medium.

[0062] The program may also realize some of the functions described above. Furthermore, the program may be a file that can realize the functions described above in combination with a program already recorded in the computer system, that is, a so-called differential file (differential program).

[0063] Although some embodiments of the present disclosure have been described, these embodiments are merely examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and modifications may be made to these embodiments without departing from the spirit of the disclosure.

[0064] Note that some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0065] (Appendix 1) A detection means for detecting a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency that is 1 / k of the normal frequency when the device that operates according to the clock is initialized; a conversion means for converting each of the first phase difference and the second phase difference into an analog voltage value; a comparison means for comparing two voltage values ​​converted by the conversion means; a transmitting means for transmitting an output characteristic control signal to a correction circuit with a value that minimizes the error, which is a result of the comparison by the comparing means; A clock generation circuit comprising:

[0066] (Appendix 2) The j is 2, wherein k is 2; 2. The clock generation circuit of claim 1.

[0067] (Appendix 3) When the speed of the clock is switched to a slower speed, The detection means detects the first phase difference and the second phase difference, the transmitting means transmits the output characteristic control signal to the correction circuit; 3. The clock generation circuit of claim 1 or 2.

[0068] (Appendix 4) When the speed of the clock is switched to a slower speed, it means when the speed of the clock is switched to half the speed. 4. The clock generation circuit of claim 3.

[0069] (Appendix 5) Detecting a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency that is k times the normal frequency when the device is initialized according to the clock; converting each of the first phase difference and the second phase difference into an analog voltage value; Comparing the two converted voltage values; transmitting an output characteristic control signal to a correction circuit at a value that minimizes the error as a result of the comparison; A processing method comprising:

[0070] (Appendix 6) The j is 2, wherein k is 2; The processing method described in Appendix 5.

[0071] (Appendix 7) When the speed of the clock is switched to a slower speed, detecting the first phase difference and the second phase difference; sending the output characteristic control signal to the correction circuit; 7. The method of claim 5 or 6,

[0072] (Appendix 8) When the speed of the clock is switched to a slower speed, it means when the speed of the clock is switched to half the speed. The processing method described in Appendix 7.

[0073] (Appendix 9) Detecting a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency that is k times the normal frequency when the device is initialized according to the clock; converting each of the first phase difference and the second phase difference into an analog voltage value, comparing the two converted voltage values, and transmitting an output characteristic control signal having a value that minimizes an error to a correction circuit; A program that causes a computer to execute the following.

[0074] (Appendix 10) The j is 2, wherein k is 2; 9. The program described in Appendix 9.

[0075] (Appendix 11) When the speed of the clock is switched to a slower speed, detecting the first phase difference and the second phase difference; sending the output characteristic control signal to the correction circuit; 11. The program according to claim 9 or 10, which causes a computer to execute the above.

[0076] (Appendix 12) When the speed of the clock is switched to a slower speed, it means when the speed of the clock is switched to half the speed. 12. The program according to claim 11. [Explanation of symbols]

[0077] 1. Receiving circuit 5. Computers 6. CPU 7. Main memory 8. Storage 9. Interface 10...PLL(Phase Locked Loop) 20. Multiphase clock generation circuit 30. Sampling latch 40. Demux 50 Phase detection circuit 201 Input path switching unit 202 4-phase / 8-phase conversion unit 202a, 202b: Buffer 203...8-phase output switching unit 203a...front section 203b...Late stage section (PI (Phase Interpolation) circuit) 204...Control switching unit 205 Phase difference detection section

Claims

1. A first clock; a second clock that is in phase opposite to the first clock; A clock generating circuit to which Upon initialization of a device operating according to the first clock and the second clock, When the first clock and the second clock have a first frequency, A phase difference between the first clock and the second clock is Detecting a first phase difference corresponding to a phase difference j times the minimum phase adjustment amount achievable by the clock data recovery circuit; When the first clock and the second clock have a frequency that is 1 / k of the first frequency, A phase difference between the first clock and the second clock is A second phase difference corresponding to a phase difference (j / k) times the minimum phase adjustment amount is detected. A detection means; a signal having a first voltage magnitude which is an output signal when the first clock and the second clock at the first frequency are used as input differential signals at the timing when the first phase difference is detected; a signal having a second voltage magnitude which is an output signal when the first clock and the second clock having a frequency that is 1 / k of the first frequency at the timing when the second phase difference is detected are used as input differential signals; Output An output means; Comparing the first voltage magnitude signal with the second voltage magnitude signal. Comparison means; Based on the comparison result by the comparison means, a correction circuit for adjusting the first phase difference and the second phase difference, Transmitting a control signal for controlling the first phase difference and the second phase difference A transmitting means; A clock generation circuit comprising:

2. The j is 2, The k is 2.

2. The clock generating circuit according to claim 1.

3. A first clock; a second clock that is in phase opposite to the first clock; A processing method executed by a clock generating circuit to which Upon initialization of a device operating according to the first clock and the second clock, When the first clock and the second clock have a first frequency, A phase difference between the first clock and the second clock is A first phase difference corresponding to a phase difference j times the minimum phase adjustment amount achievable by the clock data recovery circuit is detected. And, When the first clock and the second clock have a frequency that is 1 / k of the first frequency, A phase difference between the first clock and the second clock is A second phase difference corresponding to a phase difference (j / k) times the minimum phase adjustment amount is detected. And, a signal having a first voltage magnitude which is an output signal when the first clock and the second clock at the first frequency at the timing when the first phase difference is detected are used as input differential signals; a signal having a second voltage magnitude which is an output signal when the first clock and the second clock having a frequency that is 1 / k of the first frequency at the timing when the second phase difference is detected are used as input differential signals; Output And, Comparing the first voltage magnitude signal level to the second voltage magnitude signal. And, Based on the comparison results, a correction circuit for adjusting the first phase difference and the second phase difference, Transmitting a control signal for controlling the first phase difference and the second phase difference And, A processing method comprising:

4. The j is 2, The k is 2. The method of claim 3.

5. A program for causing a computer in a clock generating circuit to execute the processing method according to claim 3 or 4.

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