Sparsely Variable Bit-Length Deterministic Pulse Generation for Updating Analog Crossbar Arrays

Abstract

Embodiments are provided for a computer-implemented method, system, and computer program product for updating an analog crossbar array. The embodiments include receiving a represented numerical value for use in a matrix multiplication using pulse generation for the crossbar array and receiving a first bit length for representing the numerical value, the bit length being a configurable bit length. The embodiments also include selecting a pulse position in a pulse sequence having the first bit length for representing the numerical value, performing a calculation using the selected pulse position in the pulse sequence, and updating the crossbar array using the calculation.

Description

[Technical field]

[0001] The present invention relates generally to crossbar arrays implementing neural networks, and more particularly to training neural networks using sparse variable bit-length deterministic pulse generation for updating analog crossbar arrays. [Background technology]

[0002] An artificial neural network (ANN), also known as a neuromorphic and synaptronic system, is a computational system that allows an electronic system to essentially function in a manner similar to biological nervous systems, such as the human brain. In this detailed description, any reference to an ANN is used in its broadest sense to cover a wide range of computer and electronic systems that model biological neural networks, including but not limited to pulsed neural networks (PNNs). Some implementations of ANNs do not utilize the traditional digital model that typically manipulates 0s and 1s. Instead, some implementations of ANNs create connections between processing elements that have roughly equivalent functionality to neurons in a biological brain.

[0003] ANNs are often implemented as relatively large parallel computing systems with many simple processors and many interconnections. Modeling biological nervous systems using ANNs (or PNNs) can contribute to a better understanding of biological functions. Many ANN models attempt to use some of the "organizational" principles believed to be used in the human brain. Modern computer hardware technologies (e.g., VLSI and optics) have made such modeling feasible. ANNs incorporate knowledge from a variety of domains, including neurophysiology, cognitive science / psychology, physics (statistical mechanics), control theory, computer science, artificial intelligence, statistics / mathematics, pattern recognition, computer vision, parallel processing, and hardware (e.g., digital / analog / VLSI / optics).

[0004] Modern ANNs contain a network of artificial neurons (also known as "nodes"). These nodes are connected to each other and are assigned values ​​that represent the strength of their connections. For example, connections can be identified that indicate inhibition (maximum inhibition is minus 1.0) or excitation (maximum excitation is plus 1.0). A higher magnitude value indicates a stronger connection. Each node also has a transfer function built into its design. In a typical ANN, there are three types of neurons: input nodes, hidden nodes, and output nodes.

[0005] Input nodes take in information that can be expressed numerically. The information is represented as an activation value, where each node is given a numerical value, with higher values ​​resulting in greater activation. This information is then passed throughout the network. Activation values ​​are passed from node to node based on connection strengths (weights), inhibition (or excitation), and transfer functions. Each node sums the activation values ​​it receives. Each node then modifies its value based on its transfer function. Activation flows through the input nodes, hidden layers, and until it reaches the output nodes. The output nodes reflect the input to the outside world in a meaningful way.

[0006] There are many types of neural networks, but the two main types are feedforward networks and feedback networks. A feedforward network is a non-recurrent network with an input, an output, and a hidden layer. Signals can only travel in one direction. Input data is passed to a layer of processing elements, which perform a calculation. Each processing element performs a calculation based on a weighted sum of its inputs. The newly calculated value then becomes the new input value given to the next layer. This process continues until all layers have been passed and an output has been determined. A threshold transfer function may be used to quantify the output of the neurons in the output layer.

[0007] A feedback network contains feedback paths, meaning that signals can travel in both directions using loops. All possible connections between neurons are possible. Due to the presence of loops in this kind of network, under certain operations it can be a nonlinear dynamical system that changes continuously until an equilibrium state is reached. Feedback networks are often used in associative memories and optimization problems, where the network seeks the optimal arrangement of interconnected factors.

[0008] In an ANN, the spike generating function can be modeled by a component commonly known as a time encoder or spike generator. Thus, the ability to gain greater knowledge of the biological nervous systems described thus far depends on the development of an ANN that models how neural information is encoded in a recurrent network of spike-type time encoders. Time encoders provide an alternative to both digital and analog encoding by asynchronously integrating the received signal and generating a subsequent set of asynchronous pulse signals. In some configurations of time encoder networks, information about the set of signals input to the network can be extracted from the set of pulses or spikes output from the network. Summary of the Invention

[0009] An embodiment of the present invention is directed to a computer-implemented method of variable bit length pulse generation for updating a crossbar array. A non-limiting example of the computer-implemented method includes receiving a represented numerical value for use in a matrix multiplication using pulse generation for a crossbar array, and receiving a first bit length for representing the numerical value, the bit length being a variable bit length. The computer-implemented method also includes selecting a pulse position in a pulse sequence having the first bit length for representing the numerical value, performing a calculation using the selected pulse position in the pulse sequence by a processor, and updating the crossbar array using the calculation by the processor.

[0010] An embodiment of the present invention is directed to a system for variable bit length pulse generation for updating a crossbar array. A non-limiting example of the system includes a crossbar array having one or more memristor devices and a processor. The processor is configured to receive a represented numerical value to be used for matrix multiplication using pulse generation for the crossbar array, and to receive a bit length for representing the numerical value, the bit length being a variable bit length. The processor is also configured to select a pulse position in a pulse sequence having a bit length for representing the numerical value, perform a calculation using the selected pulse position in the pulse sequence, and update the crossbar array using the calculation, where updating the crossbar array includes changing weights of one or more memristor devices.

[0011] An embodiment of the present invention is directed to a computer program product for variable bit length pulse generation for updating a crossbar array, the computer program product including a computer readable storage medium having program instructions embodied therein. The program instructions are executable by a processor to cause the processor to perform a method. A non-limiting example of the method includes receiving a numerical value to be represented using pulse generation for a crossbar array for use in a matrix multiplication, and receiving a first bit length for representing the numerical value, the bit length being a variable bit length. The method also includes selecting a pulse position in a pulse sequence having the first bit length for representing the numerical value, performing a calculation using the selected pulse position in the pulse sequence by the processor, and updating the crossbar array using the calculation by the processor.

[0012] Further technical features and advantages are realized by the techniques of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, reference is made to the detailed description and drawings. [Brief description of the drawings]

[0013] The particulars of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the claims at the end of the specification. The foregoing and other features and advantages of embodiments of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings.

[0014] [Figure 1] FIG. 2 illustrates input and output connections of a biological neuron modeled using an embodiment of the present invention.

[0015] [Diagram 2] FIG. 2 illustrates a model of the biological neuron shown in FIG. 1 that may be used in connection with embodiments of the present invention.

[0016] [Diagram 3] FIG. 3 shows a model of an ANN incorporating the biological neural model shown in FIG. 2.

[0017] [Figure 4] FIG. 2 shows a block diagram of a known weight update method that may be used in conjunction with an embodiment of the present invention;

[0018] [Diagram 5] FIG. 1 illustrates a block diagram for a computational method that may be used in one or more embodiments of the present invention.

[0019] [Figure 6] FIG. 1 illustrates known equations governing the operation of a passive two-terminal memristive design that may be utilized in connection with embodiments of the present invention.

[0020] [Figure 7] FIG. 13 graphically illustrates a comparison between the switching characteristics of known two-terminal memristors and the non-linear switching characteristics of a two-terminal RPU that may be utilized in conjunction with embodiments of the present invention.

[0021] [Figure 8]FIG. 2 illustrates a crossbar array of a two-terminal, non-linear RPU device according to an embodiment of the present invention, along with a voltage sequence illustrating the operation of the RPU.

[0022] [Figure 9] FIG. 2 illustrates an exemplary 2×2 crossbar array and weight matrix in accordance with one or more embodiments of the present invention.

[0023] [Figure 10] FIG. 13 illustrates multiplication by pulse coincidences to update neural network weights in accordance with one or more embodiments of the present invention.

[0024] [Figure 11] FIG. 2 illustrates a multiplication map and multiplication table in accordance with one or more embodiments of the present invention.

[0025] [Figure 12] FIG. 2 illustrates an algorithm for varying bit lengths and selecting bit positions in a bitstream according to one or more embodiments of the present invention.

[0026] [Figure 13] 1 illustrates a graph and a multiplication map in accordance with one or more embodiments of the present invention.

[0027] [Figure 14] 1 illustrates a graph and a multiplication map in accordance with one or more embodiments of the present invention.

[0028] [Figure 15] FIG. 2 illustrates a flowchart of a method for generating pulses for updating a crossbar array in accordance with one or more embodiments of the present invention.

[0029] [Figure 16] FIG. 1 is a block diagram illustrating an example of a processing system for implementing the teachings herein.

[0030] The figures shown herein are exemplary. There may be many variations to the figures or the operations described herein without departing from the spirit of the invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Also, the term "coupled" and variations thereof describe having a communication path between two elements and do not imply a direct connection between them without an intervening element / connection between them. All of these variations are considered part of this specification.

[0031] In the accompanying drawings and the following detailed description of embodiments of the invention, various elements shown in the figures are provided with two or three digit reference numbers. With few exceptions, the leftmost digit of each reference number corresponds to the figure in which the element is first shown. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternative embodiments of the present invention may be devised without departing from the scope of the present invention. Various connection and positional relationships (e.g., above, below, adjacent, etc.) are described between elements in the following description and drawings. These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, connections between entities may refer to direct or indirect connections, and positional relationships between entities may be direct or indirect positional relationships. Moreover, various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functions not described in detail herein.

[0033] The following definitions and abbreviations may be used for interpretation of the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover an inclusion that is not exclusive. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or device.

[0034] Moreover, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment of the invention described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments of the invention. The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "a plurality" may be understood to include any integer greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" may include both indirect and direct "connected."

[0035] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on equipment available at the time of the filing of this application. For example, "about" can include a range of ±8%, or 5%, or 2% of a given value.

[0036] For the sake of brevity, conventional techniques relating to the manufacture and use of aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for implementing various technical features described herein are well known. Thus, for the sake of brevity, many conventional implementation details are mentioned only briefly herein or omitted entirely without providing details of well-known systems and / or processes.

[0037] Turning now to an overview of the technology more specifically related to the embodiments of the present invention, a description of how a typical ANN operates is now provided with reference to Figures 1, 2 and 3. As described herein above, a typical ANN models the human brain, which contains approximately 100 billion interconnected cells called neurons. Figure 1 shows a simplified diagram of a biological neuron 102 having pathways 104, 106, 108, 110 connecting to upstream inputs 112, 114, downstream outputs 116 and downstream "other" neurons 118, configured and arranged as shown. Each biological neuron 102 sends and receives electrical impulses via pathways 104, 106, 108, 110. The nature of these electrical impulses and how they are processed in the biological neuron 102 is primarily responsible for the overall functioning of the brain. The pathways connecting between biological neurons can be strong or weak. When a given neuron receives an input impulse, it processes the input according to the neuron's function and sends the result of the function to the downstream output, or to downstream "other" neurons, or a combination thereof.

[0038] A biological neuron 102 is modeled in FIG. 2 as a node 202 that includes a mathematical function f(x) represented by the equation shown in FIG. 2. The node 202 takes electrical signals from inputs 212, 214, multiplies each input 212, 214 by the strength of its respective connection path 204, 206, sums the inputs, passes the sum through a function f(x), and generates a result 216 that can be a final output or an input to another node, or both. In this detailed description, an asterisk (*) is used to represent multiplication. A weak input signal is multiplied by a number with a very small connection strength, so the effect of the weak input signal on the function is very small. Similarly, a strong input signal is multiplied by a number with a higher connection strength, so the effect of the strong input signal on the function is larger. The function f(x) is a design choice, and various functions can be used. A typical design choice for f(x) is the hyperbolic tangent function, which takes the previous sum of the function and outputs a number between minus one and plus one.

[0039] FIG. 3 illustrates a simplified ANN model 300 organized as a weighted directional graph, where artificial neurons are nodes (e.g., 302, 308, 316) and weighted directional edges (e.g., m1-m20) connect the nodes. The ANN model 300 is organized such that nodes 302, 304, 306 are input layer nodes, nodes 308, 310, 312, 314 are hidden layer nodes, and nodes 316, 318 are output layer nodes. Each node is connected to all nodes in adjacent layers by connection paths, shown in FIG. 3 as directional arrows with connection strengths m1-m20. Although only one input layer, one hidden layer, and one output layer are shown, in practice multiple input layers, hidden layers, and output layers may be provided.

[0040] Similar to the functioning of the human brain, each input layer node 302, 304, 306 of the ANN 300 receives inputs x1, x2, x3 directly from a source (not shown) without connection strength adjustment and without node summation. Accordingly, y1=f(x1), y2=f(x2), and y3=f(x3), as shown by the equations listed at the bottom of FIG. 3. Each hidden layer node 308, 310, 312, 314 receives its inputs from all input layer nodes 302, 304, 306 with connection strengths associated with the relevant connection paths. Thus, for hidden layer node 308, y4=f(m1*y1+m5*y2+m9*y3), where * denotes multiplication. Similar connection strength multiplication and node summation are performed for hidden layer nodes 310, 312, 314 and output layer nodes 316, 318, as shown by the equations defining functions y5-y9 shown at the bottom of FIG. 3.

[0041] The ANN model 300 "learns" by processing data records one at a time and comparing the record's initial arbitrary classification with the known actual classification of the record. Using a training method known as "backpropagation" (i.e., "backward propagation of error"), errors made in the initial classification of the first record are fed back into the network and used to modify the network's weighted connections for subsequent iterations, and this feedback process continues over and over. During the training phase of the ANN, the correct classification for each record is known, and therefore the output nodes are assigned "correct" values. For example, a node value of "1" (or 0.9) for a node corresponds to the correct class, and a node value of "0" (or 0.1) corresponds to the other. Thus, the network's calculated values ​​for the output nodes can be compared to these "correct" values ​​to calculate an error term for each node (i.e., the "delta" rule). These error terms are then used to adjust the weights in the hidden layer so that in the next iteration, the output values ​​are closer to the "correct" values.

[0042] Although the power consumption may be low, performing offline training can be difficult and resource intensive because a significant number of adjustable parameters (e.g., weights) of the ANN model typically need to be modified during training to match the input-output pairs of the training data. Figure 4 shows a simplified diagram of a typical read-process-write weight update operation in which the CPU / GPU cores (i.e., simulated "neurons") read memory (i.e., simulated "synapses") to perform a weight update processing operation and write the updated weights back to memory. Accordingly, simplifying the cross-point devices of the ANN architecture and prioritizing power saving, offline learning techniques generally means that training speed and training efficiency are not optimized.

[0043] Probabilistic computing is a set of techniques that allows continuous values ​​to be represented as streams of random bits, and complex computations can be calculated by simple bit operations on the streams. Specifically, there are two random and independent bit streams S1 and S2, called probability numbers (i.e. Bernoulli processes), and if the probability of getting a "1" in the first stream is p and the probability of getting a "1" in the second stream is q, then we can take the logical AND of the two streams, as shown in Figure 5. The probability that the output stream contains a "1" is pq. By observing enough output bits and measuring the frequency of "1", it is possible to estimate pq with any precision. Probabilistic computing is often used in the hardware design of neural networks, because the "multiply and multiply" operation is designed to be implemented with a small number of logic gates / transistors.

[0044] However, in some probabilistic techniques, the weights required for the calculation are fed to the systolic array from an external location, and the weight updates are not performed in the array. This only addresses the acceleration of vector-matrix or matrix-matrix multiplication operations that are frequently used during neural network training. However, systolic arrays that do not have local storage cannot perform weight updates in parallel, since the weights are stored in external memory locations. It is necessary to accelerate the weight updates in order to accelerate the overall learning algorithm, as provided by embodiments of the techniques described herein.

[0045] In addition, training an ANN requires a lot of calculations. As the number of nodes increases, the complexity and number of calculations increases, which can lead to further inefficiencies in training speed and accuracy. 2 It is inefficient to send pulses to form the cross product, and b represents the number of bits.

[0046] Turning now to an overview of aspects of the present invention, one or more embodiments of the present invention address the above-mentioned shortcomings of the prior art by providing an efficient neural network training scheme. The techniques of the embodiments of the present invention described herein allow for the selection of an optimal bit length for training the neural network. Also, the bit length can be changed during the neural network training phase. Also, the techniques of the embodiments of the present invention described herein select pulse positions in the pulse sequence based at least in part on the changed bit length to ensure obtaining accurate results while minimizing errors. Errors in the cross-product based update can be introduced by a reduction in the number of pulses, or the placement of the pulses in the pulse sequence, or a combination thereof. Therefore, the selected positions of the pulses in the pulse sequence are very important and need to be strategically selected to maintain the contours shown in the true multiplication map of values ​​even as the bit length is changed.

[0047] The technical effects and advantages of the embodiments of the invention described herein provide an accurate and compact representation of the match detection and updates performed in conventional neural network updates. Additionally, the technical effects and advantages provide an efficient way to encode the multiplication with minimal error using only b bits of the pulse sequence. To optimize the multiplication, an algorithm according to an aspect of the invention provides a minimal representation sufficient to compute the cross product for updating one or more memristors of the crossbar array. Additionally, the algorithm is configured to encode the value for the update using less than b bits. Providing an algorithm to generate pulse positions for values ​​used in matrix multiplication can accelerate the speed and efficiency of training of ANN architectures and also improve overall ANN performance, enabling a wider range of ANN applications.

[0048] The term "memristor" is used to describe a passive two-terminal electrical component whose resistance depends on the history of voltages previously applied to the device. The operation of a memristor is governed by equations [1] and [2] shown in Figure 6, where i is the current passing through the device, v is the voltage applied to the device, g is the conductance value of the device (the inverse of its resistance), s is an internal state variable of the device that controls the conductance value, and f is a function describing the time evolution of the internal state variable s.

[0049] The memristor behavior of a crossbar array according to an embodiment of the present invention is illustrated in FIG. 7. To illustrate the difference between an ideal memristor and a non-ideal non-linear memristor that can be used to implement the described RPU, FIG. 7 is a graph illustrating a comparison between an ideal memristor and the voltage switching behavior of an RPU according to an embodiment of the present invention. The vertical axis of the graph represents the state change of the device at a particular voltage, and the horizontal axis of the graph represents the applied voltage. In an ideal memristor operation, the change in resistance is linearly proportional to the voltage applied to the device. Thus, as soon as any voltage is applied to the memristor, its resistance state changes. This is illustrated by curve 702, which shows that the state change is dramatic even at low voltages.

[0050] For a nonlinear RPU device, such as that shown by curve 704, there is a well-defined set voltage VSET that the device must experience to change its internal resistance state. A bias voltage of 0.5 VSET does not change the internal resistance state. In an embodiment of the present invention, this nonlinear characteristic of the RPU device is exploited to perform the multiplication locally. Assuming f1 is small, applying only 0.5 VSET does not cause the device to change its internal state. Notably, while FIG. 7 shows a positive voltage and a positive change to the resistance state of the RPU device, a similar relationship also exists between a negative voltage and a negative resistance change.

[0051] Turning now to a more detailed description of aspects of the invention, Figure 8 illustrates a two-dimensional (2D) crossbar array 800 performing forward matrix multiplication, backward matrix multiplication and weight updates, according to an embodiment of the invention. The crossbar array 800 is formed from a set of conductive row lines 802, 804, 806 and a set of conductive column lines 808, 810, 812, 814 that intersect the set of conductive row lines 802, 804, 806. The intersections between the set of row lines and the set of column lines are separated by RPUs, which are shown in Figure 8 as resistive elements with adjustable / updateable resistive weights depicted as σ11, σ21, σ31, σ41, σ12, σ22, σ32, σ42, σ13, σ23, σ33, σ43, respectively. For ease of illustration, only one RPU 820 is labeled with reference numerals in Figure 8. In forward matrix multiplication, the conduction state of the RPU (i.e., the stored weights) can be read out by applying a voltage to the RPU and measuring the current passing through it.

[0052] Input voltages V1, V2, and V3 are applied to row lines 802, 804, and 806, respectively. Each column line 808, 810, 812, and 814 sums the currents I1, I2, I3, and I4 generated by each RPU along that particular column line. For example, as shown in FIG. 8, the current I4 generated by column line 814 is according to the equation I4=V1σ41+V2σ42+V3σ43. Thus, the array 800 computes forward matrix multiplication by multiplying the values ​​stored in the RPUs by the row line inputs defined by the voltages V1, V2, and V3. The backward matrix multiplication is very similar. In the backward matrix multiplication, voltages are applied to column lines 808, 810, 812, and 814 and then read out from row lines 802, 804, and 806. For weight updates, which will be described in more detail below, voltages are applied to the column and row lines simultaneously, and all of the conductance values ​​836 stored in the associated RPU devices are updated in parallel. Accordingly, the multiplication and addition operations required to perform the weight updates are performed locally in each RPU 820 of the array 800, using the associated row or column lines of the array 800 in addition to the RPU device itself. Thus, in accordance with an embodiment of the present invention, no read-update-write cycles (as shown in FIG. 4) are required in the array 800.

[0053] Continuing with the diagram of FIG. 8, the operation of a positive weight update method for the RPU 820 and its corresponding weights σ33 at the intersections of the conductive row lines 806 and conductive column lines 812 will now be provided, in accordance with one or more embodiments of the present invention. The nonlinear characteristics of the RPU 820 are used to perform the multiplication operations locally in the RPU 820 using calculations as described below. More specifically, the described method uses the nonlinear switching characteristics of the RPU 820 and the bitstreams 830, 832 to perform the multiplication operations and necessary weight updates locally in the RPU 820 without the need for other circuit elements. Update generator circuits (not shown) are provided at the periphery of the crossbar array 800 and are used as peripheral "translators" to generate the necessary voltage pulses in the form of bitstreams (e.g., 830, 832) that will be applied in parallel to all the RPUs of the 2D crossbar array 800.

[0054] With brief reference to the diagram of FIG. 7, it is assumed that the f1 of the RPU 820 shown in FIG. 8 is very small (e.g., f1=0), which means that the RPU 820 does not change its internal state when only 0.5 VSET is applied. The row voltage sequence or bit stream 830 applied to the row line 806 is shown as a sequence of voltage pulses representing weight updates with either a voltage of zero or a voltage of +0.5 VSET. The column voltage sequence or bit stream 832 applied to the column line 814 is shown as a sequence of voltage pulses also representing weight updates with either a voltage of zero or a voltage of −0.5 VSET. In the example of FIG. 8, 4 / 8 is encoded by the row voltage sequence 830 and 6 / 8 is encoded by the column voltage sequence 832. The exemplary voltage sequence 830, 832 represents a positive resistance change stage of the weight update. After the positive weight update is performed, another set of sequences with the polarity of the respective voltages reversed can be used to update the weights in the negative direction for weights that require such correction.

[0055] Voltage array 834 is the voltage applied to RPU 820 resulting from the difference between row voltage array 830 and column voltage array 832. Voltage array 834 will have three voltage steps: 0V, 0.5VSET, and VSET. However, since the resistance σ43 of RPU 820 changes only for device voltages reaching VSET, a single pulse sent through either the column or row lines will not be sufficient to change the resistance state of RPU 820. If the column line sends a voltage of 0.5VSET and the row line sends a voltage of −0.5VSET, the resulting VSET pulse applied to the associated RPU will incrementally change the resistance value of the device. In response, the voltage pulses applied to RPU 820 take advantage of the nonlinear switching characteristics of RPU 820 to perform a bitwise AND operation (e.g., as shown in FIG. 5) locally at RPU 820. Therefore, the resulting change in the RPU's stored weights (e.g., σ43) is proportional to the product of two numbers (4 / 8*6 / 8=3 / 8) that are “transformed” by the update generator circuitry on the periphery of the crossbar array 800.

[0056] 9, a two-dimensional representation of a crossbar array 900 and corresponding weight matrix w for updating a neural network in accordance with one or more embodiments of the present invention is shown. The crossbar array 900 includes four processing components 910 arranged as shown in FIG. 9. The weight matrix w includes elements w1, w2, w3, and w4. During neural network training, each of the weights corresponding to the processing components may be updated. Also depicted in FIG. 9 is Equation 1 for updating the weight matrix w. As shown in Equation 1, a cross product operation of x and δ is performed to incrementally update the weights in the weight matrix.

[0057] 10 illustrates pulse coincidence multiplication for updating a crossbar array 1000 in accordance with one or more embodiments of the present invention. A pulse sequence of x, δ values ​​determined by algorithm 1200 (described below) is input to the crossbar array 1000, which performs an approximation of the multiplication operation to perform the element-by-element multiplication of a conventional network. Algorithm 1200 defines an exact conversion between the multiplication operation and a selected pulse position within the pulse sequence for the x and δ values.

[0058] FIG. 11 illustrates a true multiplication map (also referred to as an update map) and a granular map resulting from approximating the true multiplication map. It should be understood that the multiplication map described herein refers to a cross-product based update. In general, multiplication is often referred to in relation to a forward / backward pass (i.e., vector-matrix multiplication), but in the embodiments of the invention described herein, multiplication specifically refers to a cross-product based update. The true multiplication map 1110 and true multiplication table have been generated for a 2×2 crossbar array having a resolution b of 2. However, it should be understood that the true multiplication map and table may be generated for any crossbar array having a different resolution b. As shown in map 1130, an approximation has been performed for values ​​of x and δ that provide a granular result. The granular result may be due to incorrect placement of pulses in the pulse sequences representing the values ​​of x and δ. This granular approximation is inappropriate for neural network training and leads to degradation of classification performance.

[0059] FIG. 12 illustrates an algorithm 1200 constructed and arranged in accordance with an embodiment of the present invention to provide a method for determining pulse positions in a pulse sequence for values ​​of x and δ that will provide a compact representation of a true multiplication table. The algorithm 1200 will also produce minimal error and maintain the contours of true multiplication operations necessary to perform efficient weight updates of a neural network. The algorithm 1200 also includes a method for providing a flexible bit length BL, resolution b for x, δ that can be updated during neural network training. For example, if b=2, then x, δ is [0,1]. However, if b=4, then x, δ is [0,0.25,0.5,1]. It should be understood that the value of b is for illustration only and is not intended to be limiting.

[0060] According to an aspect of the invention, algorithm 1200 is a sparse XOR flag compression algorithm for selecting variable bit lengths for training a neural network, according to one or more embodiments of the invention. The compression takes advantage of the placement of multiplication boundaries. For compression ratio > b (with BL smaller than b, where

number

[0061] 13 is a set of graphs and maps for an example implementation for sparse modifiable bit deterministic pulse generation for updating a crossbar array, in accordance with one or more embodiments of the present invention. In this non-limiting example, there are b bins (resolution of x, δ), which indicate that the x and δ values ​​of the weight matrix w can each take on 100 different values. The resolution b is 100, and the selected bit length (BL) is 100 bits. Traditionally, updating weights used in neural networks requires element-wise multiplicative updates for each element (x and δ) to represent different numerical values ​​of x and δ, so b 2 Using the method described in Figure 12, we can achieve a similar result to element-wise multiplication while compressing the 2 The number of bits can be reduced. The method of FIG. 12 allows the resolution b to be selected or changed during neural network training.

[0062] In FIG. 13, graph 1302 represents x values ​​of a weight matrix used in performing updates for a neural network. The x-axis of graph 1302 represents a pulse position in a pulse sequence or a bit position in a bit stream. The y-axis of graph 1302 represents the numerical value of the x values ​​represented in the pulse sequence. The pulse sequence or bit stream can be represented by a series of 1's and 0's. Region 1320 represents a 1 (logic high) and region 1330 represents a 0 (logic low). For example, in graph 1302, the row corresponding to x value 80 indicates the position in the pulse sequence where the numerical value 80 is represented by a pulse provided at the position shown on the x-axis. In another example, the bottom row of graph 1302, which corresponds to the numerical value 0, is represented by 100 0 pulses in the pulse sequence and the top row, which corresponds to a 1, is represented by 100 1's in the pulse sequence.

[0063] The pulse sequences generated for x and delta values ​​are quite different. Thus, the pulse sequence for the delta values ​​is determined to be different from the pulse sequence for the x values ​​and is determined using algorithm 1200 described with reference to Figure 12. In Figure 13, graph 1304 represents pulse position in the pulse sequence versus delta value. As with graph 1302, the x-axis of graph 1304 represents pulse position and the y-axis represents the numerical value of the delta value used in the calculation to update the weights.

[0064] 13, the multiplication map 1306 multiplies each element (x i , δ j ) is multiplied element-wise. True multiplication map 1306 provides the contours corresponding to the element-wise multiplication. In this example, 100 bits for x-values ​​and 100 bits for δ-values ​​are used to represent each numerical value for the matrix multiplication to update the weights of the analog crossbar array, with 10,000 pulses / bit. As the number of bits increases, the complexity and number of calculations increases rapidly.

[0065] Also shown in Fig. 13 is a heat map 1308 generated by taking the cross product of the numerical values ​​of x values ​​represented by the first pulse sequence and the numerical values ​​of δ values ​​represented by the second pulse sequence, where the second pulse sequence of δ values ​​is determined from the algorithm shown in Fig. 12. The heat map 1308 allows intuitive analysis of the closeness between the cross product of the first pulse sequence and the second pulse sequence and the element-by-element multiplication of each element of the weighting matrix w.

[0066] As shown in heat map 1308, the cross product allows for a compact representation of the 10,000 bit per element multiplication using only 100 bits instead of the 10,000 bits required for a true multiplication on each element. An error can be calculated by comparing the multiplication map 1306 and the heat map 1308 and taking the difference between the corresponding values. An error map 1310 can be calculated and presented as shown in FIG. 13. The contours of the heat map 1308 are similar to those shown in the multiplication map 1306, which indicates a representation that provides efficient updates and accurate classification for neural networks using cross products.

[0067] In Fig. 14, various graphs and maps are shown illustrating sparse modifiable compression according to one or more embodiments of the present invention. In this particular configuration, the resolution b is 100 and the bit length is 10. As in Fig. 13, graph 1402 represents the pulse sequence for each x value, and graph 1404 represents the pulse sequence for each δ value used to update the neural network. Regions 1420, 1440 represent 1 (logic high) and regions 1430, 1450 represent 0 (logic low).

[0068] In this example, the bit length was reduced. In one or more embodiments of the present invention, the BL is changed according to algorithm 1200 of FIG. 12 during the training phase. If the BL is selected according to algorithm 1200, the appropriate weight update will be performed in the neural network. More values ​​of x and δ in the true multiplication map will result in shorter BL, so some granularity can be introduced to the heat map. In this example, only 10 choices were provided, but the contours of the heat map are similar, showing minimal error. It should be understood that while the bit length was reduced from 100 to 10, this is a non-limiting example and any other value can be used according to one or more embodiments of the present invention.

[0069] FIG. 15 illustrates a flow chart of a method 1500 for pulse generation to update a crossbar array, according to one or more embodiments of the present invention. The method 1500 can be implemented using a processor as shown in FIG. 4 or the processor described with reference to FIG. 16. It should be understood that any other computing device can be used. The method 1500 begins at block 1502 and proceeds to block 1504, which provides for receiving, by a processor, a numerical value to be used in a matrix multiplication to represent the use of pulse generation for the crossbar array. Block 1506 receives a bit length representing the numerical value, the bit length being a changeable bit length. In one or more embodiments of the present invention, the bit length is updated in a training phase of the neural network. In subsequent calculations, the bit length can be increased or decreased. The bit length provided to the processor is known from the neural network. In other embodiments of the present invention, the bit length can be input or changed by a user at any phase of the training phase of the neural network. Block 1508 selects a pulse position in a pulse sequence having a bit length representing the numerical value. In one or more embodiments of the present invention, the pulse position is determined using the algorithm provided in FIG. 9. A pulse position in the pulse sequence is determined for the δ value. Block 1510 performs a calculation using the selected pulse position in the pulse sequence. A cross product is determined for the first pulse sequence for the δ value of the weight matrix and the second pulse sequence for the x value. The result is used to either add or subtract an increment to adjust the weights for training the neural network. Block 1512 updates the crossbar array using the calculation. In one or more embodiments of the invention, the result is used to adjust the conductance of one or more memristor devices in the crossbar array. Method 1500 ends at block 1514. It should be understood that different or additional order of steps may be included in method 1500 and is not intended to be limited by the steps shown in FIG. 15.

[0070] Referring to FIG. 16, a processing system 1600 for implementing aspects of the present invention in accordance with the teachings described herein is shown. The processing system may be implemented in a processor (CPU / GPU core) such as that shown in FIG. 4. In this embodiment of the present invention, the system 1600 has one or more central processing units (processors) 1601a, 1601b, 1601c, etc. (collectively or generally referred to as processors 1601). In some embodiments of the present invention, each processor 1601 may include a reduced instruction set computer (RISC) microprocessor. The processor 1601 is coupled to a system memory 1614 and various other components via a system bus 1613. A read only memory (ROM) 1602 is coupled to the system bus 1613 and may include a basic input / output system (BIOS) that controls certain basic functions of the system 1600.

[0071] FIG. 16 further illustrates an input / output (I / O) adapter 1607 and a network adapter 1606 coupled to the system bus 1613. The I / O adapter 1607 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 1603 or a tape storage drive 1605, or a combination thereof, or any other similar components. The I / O adapter 1607, the hard disk 1603, and the tape storage device 1605 are collectively referred to herein as mass storage 1604. An operating system 1620 for executing on the processing system 1600 may be stored in the mass storage 1604. The network adapter 1606 interconnects the bus 1613 to an external network 1616, enabling the data processing system 1600 to communicate with other such systems. A screen (e.g., a display monitor) 1615 is connected to the system bus 1613 by a display adapter 1612, which may include a graphics adapter and a video controller to improve performance of graphics-intensive applications. In some embodiments of the invention, adapters 1607, 1606, and 1612 may be connected to one or more I / O buses that are connected to system bus 1613 through an intermediate bus bridge (not shown). Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as Peripheral Component Interconnect (PCI). Additional input / output devices are shown connected to system bus 1613 through user interface adapter 1608 and display adapter 1612. Keyboard 1609, mouse 1610, and speakers 1611 are all interconnected to bus 1613 through user interface adapter 1608, which may include, for example, a super I / O chip that integrates multiple device adapters into a single integrated circuit.

[0072] In an exemplary embodiment of the invention, processing system 1600 includes a graphics processing unit 1630, which is a specialized electronic circuit designed to manipulate and modify memory to accelerate the creation of images in a frame buffer intended for output to a display. In general, graphics processing units 1630 are very efficient at manipulating computer graphics and image processing, and their highly parallel structure makes them more effective than general purpose CPUs at algorithms that process large blocks of data in parallel.

[0073] 16, system 1600 includes processing capability in the form of processor 1601, storage capabilities including system memory 1614 and mass storage 1604, input means such as keyboard 1609 and mouse 1610, and output capabilities including speakers 1611 and display 1615. In some embodiments of the invention, a portion of system memory 1614 and mass storage 1604 collectively stores an operating system for coordinating the functioning of the various components illustrated in FIG.

[0074] The embodiments of the invention described herein improve upon the prior art by determining the bit position in the bit stream to represent each of the numerical values ​​used in the multiplication for neural network training. The embodiments of the invention described herein also improve upon the prior art by allowing the BL to be altered during the training phase of the neural network. The BL can be increased or decreased from an initial BL. The embodiments of the invention described herein also provide for accelerating the training of neural networks using these methods by providing initial values ​​for the neural network before it receives any weight updates.

[0075] The present invention may be a system, method, or computer program product, or combination thereof, integrated at any possible level of technical detail. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0076] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), static random access memories (SRAMs), portable compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves that record instructions, and any suitable combination of the foregoing. Computer-readable storage medium, as used herein, should not be construed as a transitory signal per se, such as electric waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted through wires.

[0077] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium into each computing / processing device, or may be downloaded to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions to a computer-readable storage medium in the respective computing / processing device for storage.

[0078] The computer readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk®, or C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer readable program instructions to personalize the electronic circuitry by utilizing state information of the computer readable program instructions to perform aspects of the present invention.

[0079] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0080] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine whereby the instructions, executed via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions may also be stored in a computer readable storage medium capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer readable storage medium on which the instructions are stored comprises an article of manufacture including instructions for implementing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0081] The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable apparatus, or other device to perform a series of operational steps to create a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / operations specified in one or more blocks of the flowcharts or block diagrams, or both.

[0082] The flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions that includes one or more executable instructions that implement a specified logical function. In some alternative implementations, the functions noted in the blocks may be performed in a different order than that noted in the drawings. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that executes the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0083] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used in this specification is selected to best explain the principles of the embodiments, practical applications of the technology found in the market, or technical improvements thereto, or to enable others skilled in the art to understand the embodiments described herein. According to this specification, the following items are also disclosed. [Item 1] 1. A computer-implemented method for pulse generation for updating an analog crossbar array, the computer-implemented method comprising: receiving, by a processor, numerical values ​​to be used in a matrix multiplication to represent using pulse generation for the crossbar array; receiving, by the processor, a first bit length for representing the numerical value, the first bit length being a variable bit length; selecting, by the processor, a pulse position in a pulse sequence having the first bit length to represent the numerical value; performing, by said processor, a calculation using said selected pulse positions in said pulse sequence; updating, by said processor, said crossbar array using said calculations; A computer-implemented method comprising: [Item 2] selecting a second bit length, said second bit length being different from said first bit length; selecting pulse positions for an updated pulse sequence having said second bit length representing said numerical value; performing subsequent calculations using the selected pulse positions in the updated pulse sequence; updating the crossbar array using the subsequent calculation, where updating the crossbar array includes updating conductance values ​​of one or more memristor devices of the crossbar array based at least in part on the calculation and the subsequent calculation; Item 1. The computer-implemented method of item 1, further comprising: [Item 3] 3. The computer-implemented method of claim 1 or 2, further comprising changing the first bit length to a second bit length during a training phase of the neural network. [Item 4] 4. The computer-implemented method of any one of claims 1 to 3, wherein the calculation comprises performing a cross product operation on the numerical values ​​used in the matrix multiplication and second numerical values ​​used in the matrix multiplication. [Item 5] 5. The computer-implemented method of claim 1, further comprising: generating a heat map, the generated heat map being based at least in part on pulse coincidence counts between a first pulse sequence and a second pulse sequence, at least one of the first pulse sequence or the second pulse sequence including the selected pulse position, and at least one first pulse sequence corresponding to the numerical value and the second pulse sequence corresponding to a second numerical value. [Item 6] Item 6. The computer-implemented method of item 5, further comprising: comparing the generated heat map to a true multiplication map using the selected pulse positions, the true multiplication map performing element-wise multiplication for each element. [Item 7] determining an error between the true multiplication map and the generated heat map; presenting the error between the true multiplication map and the generated heat map; 7. The computer-implemented method of any one of claims 1 to 6, further comprising: [Item 8] 1. A system for implementing pulse generation for updating a crossbar array, the system comprising: a crossbar array having one or more memristor devices; receiving numerical values ​​for use in matrix multiplication to represent using pulse generation for the crossbar array; receiving a bit length for representing the numerical value, the bit length being a configurable bit length; selecting a pulse position in a pulse sequence having said bit length to represent said numerical value; performing a calculation using the selected pulse positions in the pulse sequence; updating the crossbar array using the calculations, the updating of the crossbar array changing weights of the one or more memristor devices; a processor configured to: A system comprising: [Item 9] The processor is selecting a second bit length, said second bit length being different from said bit length; selecting pulse positions for an updated pulse sequence having said second bit length representing said numerical value; performing subsequent calculations using the selected pulse positions in the updated pulse sequence; updating the crossbar array using the subsequent calculation, the updating of the crossbar array being based at least in part on the calculation and the subsequent calculation to update conductance values ​​of one or more memristor devices of the crossbar array. 9. The system according to item 8, configured as follows: [Item 10] 10. The system of claim 8 or 9, wherein the processor is configured to change the bit length to a second bit length during a training phase of the neural network. [Item 11] 11. The system of any one of claims 8 to 10, wherein the calculation comprises performing a cross product operation on a number used in the matrix multiplication and a second number used in the matrix multiplication. [Item 12] 12. The system of any one of claims 8 to 11, wherein the selected pulse position in the pulse sequence is based at least in part on the bit length. [Item 13] 13. The system of claim 8, wherein the processor is further configured to generate a heat map, the generated heat map based at least in part on pulse coincidence counts between a first pulse sequence and a second pulse sequence, and at least one of the first pulse sequence or the second pulse sequence includes the selected pulse position. [Item 14] comparing a true multiplication map to the generated heat map using the selected pulse positions, the true multiplication map performing an element-wise multiplication for each element; determining an error between the true multiplication map and the generated heat map; presenting the error between the true multiplication map and the generated heat map; Item 14. The system of item 13, further comprising: [Item 15] 1. A computer program for pulse generation for updating an analog crossbar array, comprising: The processor: receiving numerical values ​​for use in matrix multiplication to represent using pulse generation for a crossbar array; receiving a bit length for representing the numerical value, the bit length being a configurable bit length; selecting pulse positions in a pulse sequence having said bit length to represent said numerical value; performing a calculation using the selected pulse positions in the pulse sequence; updating the crossbar array using the calculation, the updating of the crossbar array comprising updating a conductance value of one or more memristor devices of the crossbar array based at least in part on the calculation; A computer program that executes the following: [Item 16] The processor includes: selecting a second bit length, said second bit length being different from said bit length; selecting pulse positions for an updated pulse sequence having said second bit length for representing said numerical value; performing subsequent calculations using the selected pulse positions in the updated pulse sequence; updating the crossbar array using the subsequent calculation, the updating of the crossbar array comprising updating conductance values ​​of one or more memristor devices of the crossbar array based at least in part on the calculation and the subsequent calculation; Item 16. The computer program according to item 15, which causes the computer to execute the steps described above. [Item 17] 17. The computer program of item 15 or 16, further comprising causing the processor to execute a procedure of changing the bit length to a second bit length during a training phase of the neural network. [Item 18] 18. The computer program of any one of claims 15 to 17, further comprising causing the processor to perform a procedure of determining a cross product of the first pulse sequence and the second pulse sequence for the neural network. [Item 19] 19. The computer program product of claim 15, further comprising causing the processor to execute a step of generating a heat map, the generated heat map being based at least in part on pulse coincidence counting between a first pulse sequence and a second pulse sequence, at least one of the first pulse sequence or the second pulse sequence including the selected pulse position. [Item 20] The processor includes: comparing a true multiplication map to a heat map generated using the selected pulse positions, the true multiplication map performing an element-wise multiplication for each element; determining an error between the true multiplication map and the generated heat map; presenting the error between the true multiplication map and the generated heat map; 20. The computer program according to any one of items 15 to 19, which causes the computer program to execute the following:

Claims

1. 1. A computer-implemented method for pulse generation for updating an analog crossbar array, the computer-implemented method comprising: receiving, by a processor, numerical values ​​to be used in a matrix multiplication to represent using pulse generation for the crossbar array; receiving, by the processor, a first bit length for representing the numeric value, the first bit length being a variable bit length, the first bit length being less than or equal to a number of possible values ​​of the numeric value; deterministically selecting, by the processor, a pulse position in a pulse sequence having the first bit length to represent the numerical value; performing, by the processor, a calculation using the selected pulse positions in the pulse sequence; updating, by the processor, the crossbar array using the calculations; A computer-implemented method comprising:

2. selecting a second bit length, said second bit length being different from said first bit length; deterministically selecting pulse positions for an updated pulse sequence having the second bit length representing the numerical value; performing subsequent calculations using the selected pulse positions in the updated pulse sequence; updating the crossbar array using the subsequent calculation, where updating the crossbar array includes updating conductance values ​​of one or more memristor devices of the crossbar array based at least in part on the calculation and the subsequent calculation; The computer-implemented method of claim 1 , further comprising:

3. The computer-implemented method of claim 1 or 2, further comprising changing the first bit length to a second bit length during a training phase of a neural network.

4. 4. The computer-implemented method of claim 1, wherein the calculating comprises performing a cross product operation on the numerical values ​​used in the matrix multiplication and a second numerical value used in the matrix multiplication.

5. 5. The computer-implemented method of claim 1, further comprising: generating a heat map, the generated heat map based at least in part on pulse coincidence counts between a first pulse sequence and a second pulse sequence, at least one of the first pulse sequence or the second pulse sequence including the selected pulse position, and at least one first pulse sequence corresponding to the numerical value and the second pulse sequence corresponding to a second numerical value.

6. 6. The computer-implemented method of claim 5, further comprising: comparing the generated heat map to a true multiplication map using the selected pulse positions, the true multiplication map performing an element-wise multiplication for each element.

7. The method of claim 1, further comprising: determining an error between the true multiplication map and the generated heat map; presenting the error between the true multiplication map and the generated heat map; The computer-implemented method of claim 6 , further comprising:

8. 1. A system for implementing pulse generation for updating a crossbar array, the system comprising: a crossbar array having one or more memristor devices; receiving numerical values ​​for use in matrix multiplication to represent using pulse generation for the crossbar array; receiving a bit length for representing the numeric value, the bit length being a configurable bit length, the bit length being equal to or less than a number of possible values ​​of the numeric value; deterministically selecting pulse positions in a pulse sequence having said bit length to represent said numerical value; performing a calculation using the selected pulse positions in the pulse sequence; updating the crossbar array using the calculations, the updating of the crossbar array changing weights of the one or more memristor devices; a processor configured to: A system comprising:

9. The processor, selecting a second bit length, said second bit length being different from said bit length; deterministically selecting pulse positions for an updated pulse sequence having the second bit length representing the numerical value; performing subsequent calculations using the selected pulse positions in the updated pulse sequence; updating the crossbar array using the subsequent calculation, the updating of the crossbar array being based at least in part on the calculation and the subsequent calculation to update conductance values ​​of one or more memristor devices of the crossbar array. The system of claim 8 , configured as follows:

10. 10. The system of claim 8 or 9, wherein the processor is configured to change the bit length to a second bit length during a training phase of a neural network.

11. 11. The system of claim 8, wherein the calculation comprises performing a cross product operation between a number used in the matrix multiplication and a second number used in the matrix multiplication.

12. 12. The system of claim 8, wherein the selected pulse positions in the pulse sequence are based at least in part on the bit length.

13. 13. The system of claim 8, wherein the processor is further configured to generate a heat map, the generated heat map based at least in part on pulse coincidence counts between a first pulse sequence and a second pulse sequence, and at least one of the first pulse sequence or the second pulse sequence includes the selected pulse position.

14. comparing a true multiplication map to the generated heat map using the selected pulse positions, the true multiplication map performing an element-wise multiplication for each element; determining an error between the true multiplication map and the generated heat map; presenting the error between the true multiplication map and the generated heat map; The system of claim 13 further comprising:

15. 1. A computer program for pulse generation for updating an analog crossbar array, comprising: The processor: receiving numerical values ​​for use in matrix multiplication to represent using pulse generation for a crossbar array; receiving a bit length for representing the numeric value, the bit length being a configurable bit length, the bit length being less than or equal to the number of possible values ​​of the numeric value; deterministically selecting a pulse position in a pulse sequence having said bit length to represent said numerical value; performing a calculation using the selected pulse positions in the pulse sequence; updating the crossbar array using the calculation, the updating comprising updating a conductance value of one or more memristor devices of the crossbar array based at least in part on the calculation; A computer program that executes the following:

16. The processor, selecting a second bit length, said second bit length being different from said bit length; deterministically selecting pulse positions for an updated pulse sequence having the second bit length for representing the numerical value; performing subsequent calculations using the selected pulse positions in the updated pulse sequence; updating the crossbar array using the subsequent calculation, the updating of the crossbar array comprising updating conductance values ​​of one or more memristor devices of the crossbar array based at least in part on the calculation and the subsequent calculation; 16. The computer program product of claim 15,

17. 17. A computer program product as claimed in claim 15 or 16, further comprising the processor executing the step of changing the bit length to a second bit length during a training phase of a neural network.

18. 18. The computer program product of claim 15, further comprising the step of: determining a cross product of a first pulse sequence and a second pulse sequence for a neural network.

19. 19. The computer program product of claim 15, further comprising: causing the processor to perform the steps of: generating a heat map, the generated heat map based at least in part on pulse coincidence counts between a first pulse sequence and a second pulse sequence, at least one of the first pulse sequence or the second pulse sequence including the selected pulse position.

20. The processor, comparing a true multiplication map to the generated heat map using the selected pulse positions, the true multiplication map performing an element-wise multiplication for each element; determining an error between the true multiplication map and the generated heat map; presenting the error between the true multiplication map and the generated heat map; 20. The computer program product of claim 19,

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