Mapping conditional execution logic to quantum computing resources

Abstract

Systems, computer-implemented methods, and computer program products are provided that facilitate mapping conditional execution logic to various quantum computing resources. According to one embodiment, the system may include a memory that stores computer-executable components and a processor that executes the computer-executable components stored in the memory. The computer-executable components may include a compiler component that maps logical references to qubit data structures in instructions to a first engine component, and a deployer component that deploys the first engine component to a first block controller component operably connected to the first quantum computing resource, where the first engine component controls the first quantum computing resource based on the instructions.

Description

[Technical field]

[0001] The present disclosure relates to using quantum computing resources, and more particularly, to mapping conditional execution logic to various quantum computing resources. [Background technology]

[0002] Some existing quantum computing development techniques allow developers to develop and implement applications for quantum computing resources using simple operators. A problem with such existing development techniques is that it is difficult to develop applications for a particular quantum computing resource as well as to reuse development efforts to other quantum computing resources. Such challenges may arise because the implementation of various quantum back-end computing resources may differ dramatically in their structure, availability of commands, communication latency between various components, and availability of program resources such as registers. Applications with conditional execution aspects may be particularly difficult to migrate to various resources because they rely on the storage and relaying of information in a particular quantum computing resource.

[0003] Given the challenges discussed above, a problem with such existing quantum computing development techniques is that they can involve complex and time-consuming adaptation of an application for specific quantum back-end computing resources, for example, by requiring a unique compiler for each instance of the application. Summary of the Invention

[0004] The following presents a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, devices, computer-implemented methods, and computer program products that facilitate mapping conditional execution logic to quantum computing resources are described.

[0005] According to an embodiment, a system may include a memory storing computer-executable components and a processor executing the computer-executable components stored in the memory. The computer-executable components may include a compiler component capable of mapping logical references to qubit data structures in instructions to a first engine component, and a deployment component capable of deploying the first engine component to a first block controller component operatively connected to a first quantum computing resource, the first engine component controlling the first quantum computing resource based on the instructions. An advantage of such a system is that it may enable a mapping system for quantum computing applications to more quickly and efficiently develop and deploy applications on one or more quantum computing resources.

[0006] According to another embodiment, the compiler component of the system may further map the logical reference of the instruction to a third engine component operably coupled to a third qubit of a second quantum computing resource, the first quantum computing resource and the second quantum computing resource being quantum computing devices having different structures. An advantage of such a system is that it may enable a quantum state measurement back-end system to more quickly and more efficiently identify a larger number of quantum back-end computing resources from which quantum state measurements can be obtained based on one or more criteria defined by the entity. An advantage of such a system is that it may enable a mapping system for quantum computing applications to more quickly and more efficiently develop and deploy applications on one or more quantum computing resources.

[0007] According to another embodiment, a computer-implemented method may include a system operatively coupled to a processor for mapping logical references to quantum bit data structures in instructions to a first engine component. An advantage of such a system is that it may enable a mapping system for quantum computing applications to more quickly and efficiently develop and deploy applications on one or more quantum computing resources.

[0008] In some embodiments, the computer-implemented method may further include the system deploying the first engine component to a first block controller component operably connected to a first quantum computing resource. In one or more embodiments, the first engine component may control the first quantum computing resource based on the instructions. An advantage of such a system is that it may enable a mapping system for quantum computing applications to more quickly and efficiently develop and deploy applications on one or more quantum computing resources.

[0009] In some embodiments, the computer-implemented method further includes the system deploying a second engine component to the first block controller component and a second block controller component operably connected to a second qubit of the first quantum computing resource, the second engine component controlling the first quantum computing resource based on the second qubit, the first engine component, and the instructions. An advantage of such a system is that it may enable a mapping system for quantum computing applications to more quickly and efficiently develop and deploy applications on one or more quantum computing resources.

[0010] According to another embodiment, a computer program product is provided for facilitating a quantum state measurement back-end process. The computer program product includes a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a processor to facilitate the processor to map conditional execution logic to a quantum computing resource. In this example, the computer program product may include a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a processor to cause the processor to map logical references to qubit data structures in instructions to a first engine component, and to deploy the first engine component to a first block controller component operably connected to a first quantum computing resource, the first engine component controlling the first quantum computing resource based on the instructions. An advantage of such a system is that it may enable a mapping system for quantum computing applications to develop and deploy applications on one or more quantum computing resources more quickly and efficiently.

[0011] In some embodiments, the program instructions are further executable by the processor to cause the processor to utilize a first block controller component operably connected to the first qubit of the first quantum computing resource to facilitate the first engine component controlling the first quantum computing resource further based on the first qubit. An advantage of such a system is that it may enable a mapping system for quantum computing applications to more quickly and efficiently develop and deploy applications on one or more quantum computing resources. [Brief description of the drawings]

[0012] [Figure 1]FIG. 1 illustrates a block diagram of an exemplary, non-limiting system that can facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein.

[0013] [Diagram 2] FIG. 1 illustrates a block diagram of an exemplary, non-limiting system that can facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein. [Diagram 3] FIG. 1 illustrates a block diagram of an exemplary, non-limiting flow diagram that can facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein.

[0014] [Figure 4] FIG. 1 illustrates a block diagram of an exemplary, non-limiting system that can facilitate utilizing distributed processing to facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein.

[0015] [Diagram 5] FIG. 1 illustrates a block diagram of an exemplary, non-limiting system that can facilitate linking various distributed processing resources to achieve benefits including improved performance of conditional execution logic that is mapped to quantum computing resources, according to one or more embodiments described herein.

[0016] [Figure 6] FIG. 1 illustrates a block diagram of an exemplary, non-limiting system that may include a portion of a quantum bit controller that can facilitate access to quantum bits for operation of compiled instructions described herein, in accordance with one or more embodiments.

[0017] [Figure 7A]1 illustrates a block diagram of a non-limiting example of an implementation of an engine component to be deployed within a block controller component according to one or more embodiments.

[0018] [Figure 7B] FIG. 2 illustrates a block diagram of a non-limiting example of an engine component combiner according to one or more embodiments. [Figure 7C] FIG. 2 illustrates a block diagram of a non-limiting example of an engine component combiner according to one or more embodiments.

[0019] [Figure 7D] 1 provides a non-limiting illustration of the operation of an instruction sequencing component according to one or more embodiments. [Figure 7E] 1 provides a non-limiting illustration of the operation of an instruction sequencing component according to one or more embodiments.

[0020] [Figure 8] FIG. 1 illustrates a block diagram of an exemplary, non-limiting system that can facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein.

[0021] [Figure 9] FIG. 1 illustrates a block diagram of an exemplary, non-limiting system that can facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein.

[0022] [Figure 10] FIG. 1 illustrates a block diagram of an exemplary non-limiting operating environment capable of facilitating one or more embodiments described herein.

[0023] [Figure 11]FIG. 1 illustrates a block diagram of an exemplary, non-limiting cloud computing environment in accordance with one or more embodiments of the present disclosure.

[0024] [Figure 12] FIG. 1 illustrates a block diagram of exemplary, non-limiting abstraction model layers in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The following detailed description is illustrative only and is not intended to limit the embodiments and their application or uses, nor is it intended to be bound by any express or implied information presented in the preceding "Background" or "Summary" sections or in the "Description of the Preferred Embodiments" section.

[0026] One or more embodiments will now be described with reference to the drawings. Similar reference numerals are used throughout to refer to similar elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more comprehensive understanding of one or more embodiments. However, it will be apparent that in various instances, one or more embodiments may be practiced without these specific details.

[0027] Quantum computing is generally the use of quantum mechanical phenomena to perform computing and information processing functions. Quantum computing can be viewed in contrast to classical computing, which generally operates on binary values ​​using transistors. That is, while classical computers can operate on bit values ​​of either 0 or 1, quantum computers operate on quantum bits (qubits) that contain superpositions of both 0 and 1, and can entangle multiple qubits and use interference.

[0028] Given the above-mentioned problems with some existing quantum application development and deployment techniques, the present disclosure may be implemented to produce solutions to these problems in the form of systems, computer-implemented methods, and computer program products that can facilitate the use of compiler components that can access organizational data about specific quantum computing resources. An advantage of such systems, computer-implemented methods, and computer program products is that they may be implemented to facilitate the development and distribution of quantum applications among various quantum computing resources.

[0029] In some embodiments, the present disclosure may be implemented to create solutions to the above-mentioned problems in the form of systems, computer-implemented methods, and computer program products that can utilize structural organization data regarding quantum computing resources. A further advantage of such systems, computer-implemented methods, and computer program products is that they may be implemented not only to deploy applications on various quantum computing resources, but also to improve the performance of quantum applications, for example, by assessing aspects such as communication latencies between various components of the quantum computing resources.

[0030] It will be understood that when reference is made herein to an element being "coupled" to another element, this can refer to one or more different types of coupling. For example, when reference is made herein to an element being "coupled" to another element, this can refer to one or more different types of coupling, including, but not limited to, chemical coupling, communicative coupling, capacitive coupling, electrical coupling, electromagnetic coupling, inductive coupling, operational coupling, optical coupling, physical coupling, thermal coupling, and other types of coupling.

[0031] As referred to herein, an entity may include a human being, a client, a user, a computing device, a software application, an agent, a machine learning model, an artificial intelligence, and another entity, it being recognized that such an entity may implement one or more embodiments of the present disclosure described herein.

[0032] 1 illustrates a block diagram of an exemplary, non-limiting system 100 that can facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements and processes employed in each embodiment are omitted.

[0033] In one or more embodiments, system 100 may include a conditional execution logic mapping system 102 coupled to quantum computing resource organization data 150, both of which may be associated with a cloud computing environment. For example, conditional execution logic mapping system 102 may be associated with a cloud computing environment 1150, described below in connection with FIG. 11, and one or more functional abstraction layers (e.g., hardware and software layer 1260, virtualization layer 1270, management layer 1280, and workload layer 1290), described below in connection with FIG.

[0034] Exemplary tasks that may be performed on a cloud computing resource according to one or more embodiments include, but are not limited to, interpreting and utilizing quantum computing resource organization data 150 and compiling jobs into deployable execution logic components. Note that, as described in more detail below, some of the advantageous features of the embodiments described herein include designing and distributing conditional execution logic to execute with very low command latency, such as being deployed to block controller components, described in more detail below. As those skilled in the art will recognize, given the description herein, this low latency can be important due to the coherence times of some of the qubits used by the system.

[0035] The conditional execution logic mapping system 102 and its components (e.g., deployment component 108, compiler component 110, etc.) may employ one or more computing resources of a cloud computing environment 1150, described below in connection with FIG. 11, and one or more functional abstraction layers (e.g., quantum software, etc.), described below in connection with FIG. 12, to perform one or more operations according to one or more embodiments of the present disclosure described herein. For example, the cloud computing environment 1150 and such one or more functional abstraction layers may include one or more classical computing devices (e.g., classical computers, classical processors, virtual machines, servers, etc.), quantum hardware, and quantum software (e.g., quantum computing devices, quantum computers, quantum processors, quantum circuit simulation software, superconducting circuits, etc.), which may be employed by the conditional execution logic mapping system 102 and its components to perform one or more operations according to one or more embodiments of the present disclosure described herein. For example, the conditional execution logic mapping system 102 and its components may employ one or more such classical and quantum computing resources to execute one or more classical and quantum mathematical functions, calculations, and equations, computing and processing of scripts, algorithms, models (e.g., artificial intelligence (AI) models, machine learning (ML) models, etc.), and other operations in accordance with one or more embodiments of the present disclosure described herein.

[0036] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings recited herein is not limited to a cloud computing environment, but rather, embodiments of the invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0037] Cloud computing is a model of service delivery for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal administrative effort or interaction with a service provider. The cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0038] The characteristics are as follows:

[0039] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time and network storage, automatically as needed without requiring human interaction with the provider of the service.

[0040] Broad network access: Capabilities are available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin- or thick-client platforms (eg, cell phones, laptops, and PDAs).

[0041] Pooling of resources: Provider computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically allocated and reallocated according to demand. There is location independence in that consumers generally have no control or knowledge over the exact location of the provided resources, but may be able to specify location at a higher level of abstraction (e.g., country, state, or data center).

[0042] Rapid Elasticity: Capacity can be rapidly and elastically provisioned, sometimes automatically, to quickly scale out, and rapidly released to quickly scale in. The capacity available for provisioning often appears unlimited to the consumer, and any amount can be purchased at any time.

[0043] Measured Services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported to provide transparency to both providers and consumers of the services utilized.

[0044] The service model is as follows:

[0045] Software as a Service (SaaS): The consumer is offered the ability to use a provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer has no management or control over the underlying cloud infrastructure, including networks, servers, operating systems, storage, or even individual application capabilities, possibly with the exception of limited user-specific application configuration settings.

[0046] Platform as a Service (PaaS): The capability offered to a consumer is to deploy applications created or acquired by the consumer, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does control the deployed applications and, in some cases, the application hosting environment configuration.

[0047] Infrastructure as a Service (IaaS): The ability offered to consumers is to provision processing, storage, networking, and other basic computing resources on which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but does control the operating systems, storage, deployed applications, and in some cases, limited control over select networking components (e.g., host firewalls).

[0048] The deployment model is as follows:

[0049] Private Cloud: The cloud infrastructure is operated exclusively for an organization. It may be managed by that organization or a third party and may exist on-premise or off-premise.

[0050] Community Cloud: A cloud infrastructure is shared by several organizations to support a unique community of shared concerns (e.g., mission, security requirements, policies, and compliance considerations). It may be managed by these organizations or a third party and may exist on-premise or off-premise.

[0051] Public Cloud: Cloud infrastructure is made available to the general public or large industry entities and is owned by organizations that sell cloud services.

[0052] Hybrid Cloud: A cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain unique entities but are tied together by standard or proprietary technologies that allow for data and application portability (e.g., cloud bursting to balance load between clouds).

[0053] A cloud computing environment is a service-oriented environment with an emphasis on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0054] As shown in the exemplary embodiment depicted in FIG. 1, the conditional execution logic mapping system 102 may include a memory 104 , a processor 106 , a development component 108 , a compiler component 110 , and a bus 112 .

[0055] It should be appreciated that the embodiments of the present disclosure illustrated in the various figures disclosed herein are for illustrative purposes only, and thus the architecture of such embodiments is not limited to the systems, devices, and components illustrated therein. For example, in some embodiments, the system 100 and the conditional execution logic mapping system 102 may further include various computer elements and computing-based elements described herein in connection with the operating environment 1000 and FIG. 10. In some embodiments, such computer elements and computing-based elements may be used in connection with implementing one or more of the systems, devices, components, and computer-implemented operations illustrated and described in connection with FIG. 1 and other figures disclosed herein.

[0056] The memory 104 may store one or more computer- and machine-readable, writeable, and executable components and instructions that, when executed by the processor 106 (e.g., a classical processor, a quantum processor, etc.), may facilitate the performance of operations defined by the components and instructions. For example, the memory 104 may store computer- and machine-readable, writeable, and executable components and instructions that, when executed by the processor 106, may facilitate the performance of various functions described herein associated with the conditional execution logic mapping system 102, the unfolding component 108, the compiler component 110, and other components associated with the conditional execution logic mapping system 102 as described herein with or without reference to the various figures of this disclosure.

[0057] The memory 104 may include volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), etc.) and non-volatile memory (e.g., read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), etc.), which may employ one or more memory architectures. Further examples of memory 104 are described below with reference to system memory 1016 and FIG. 10. Such examples of memory 104 may be employed to implement any embodiment of the present disclosure.

[0058] The processor 106 may include one or more types of processors and electronic circuits (e.g., classical processors, quantum processors, etc.) that may implement one or more computer- and machine-readable, writable, and executable components and instructions that may be stored in the memory 104. For example, the processor 106 may perform various operations that may be specified by such computer- and machine-readable, writable, and executable components and instructions, including, but not limited to, logic, control, input / output (I / O), and arithmetic. In some embodiments, the processor 106 may include one or more central processing units, multi-core processors, microprocessors, dual microprocessors, microcontrollers, system-on-chips (SOCs), array processors, vector processors, quantum processors, and other types of processors. Further examples of the processor 106 are described below with reference to the processing unit 1014 and FIG. 10. Such examples of the processor 106 may be employed to implement any embodiment of the present disclosure.

[0059] The conditional execution logic mapping system 102, memory 104, processor 106, unfolding component 108, compiler component 110, and any other components of the conditional execution logic mapping system 102 as described herein may be communicatively, electrically, operatively, and optically coupled to one another via a bus 112 to perform the functions of the system 100, the conditional execution logic mapping system 102, and any components coupled thereto. The bus 112 may include one or more memory buses, memory controllers, peripheral buses, external buses, local buses, quantum buses, and other types of buses that may employ a variety of bus architectures. Further examples of the bus 112 are described below with reference to the system bus 1018 and FIG. 10. Such examples of the bus 112 may be employed to implement any embodiment of the present disclosure.

[0060] The conditional execution logic mapping system 102 may include any type of component, machine, device, equipment, apparatus, and appliance, including a processor, and may be capable of effective operational communication with wired and wireless networks. All such embodiments are contemplated. For example, the conditional execution logic mapping system 102 may include server devices, computing devices, general purpose computers, special purpose computers, quantum computing devices (e.g., quantum computers), tablet computing devices, handheld devices, server class computing machines and databases, laptop computers, notebook computers, desktop computers, cell phones, smartphones, consumer appliances and instrumentation, industrial and commercial devices, digital assistants, multimedia Internet-enabled phones, multimedia players, and other types of devices.

[0061] The conditional execution logic mapping system 102 may be coupled (e.g., communicatively, electrically, operatively, optically, etc.) to one or more external systems, sources, and devices (e.g., classical and quantum computing devices, communication devices, etc.) via a data cable (e.g., High Definition Multimedia Interface (HDMI), Recommended Standard (RS) 232, Ethernet cable, etc.). In some embodiments, the conditional execution logic mapping system 102 may be coupled (e.g., communicatively, electrically, operatively, optically, etc.) to one or more external systems, sources, and devices (e.g., classical and quantum computing devices, communication devices, etc.) via a network.

[0062] In some embodiments, such networks may include wired and wireless networks, including, but not limited to, cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs). For example, the conditional execution logic mapping system 102 may map to, or communicate with, any of a variety of networks, including, but not limited to, Wireless Fidelity (Wi-Fi), Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), Enhanced General Packet Radio Service (Enhanced GPRS), 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE), 3rd Generation Partnership Project 2 (3GPP2) Ultra Mobile Broadband (UMB), High Speed ​​Packet Access (HSPA), and other networks. The device may communicate with one or more external systems, sources, and devices, such as computing devices, and vice versa, using virtually any desired wired or wireless technology, including High Speed ​​Passive (HSPA), Zigbee and other 802.XX wireless technologies and legacy telecommunications technologies, BLUETOOTH, Session Initiation Protocol (SIP), ZIGBEE, RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over Low Power Wireless Area Network), Z-Wave, ANT, Ultra Wideband (UWB) standard protocols, and other proprietary and non-proprietary communication protocols.Thus, in such examples, the conditional execution logic mapping system 102 may include hardware (e.g., a central processing unit (CPU), a transceiver, a decoder, quantum hardware, a quantum processor, etc.), software (e.g., a set of threads, a set of processes, running software, a quantum pulse schedule, a quantum circuit, a quantum gate, etc.), or a combination of hardware and software that facilitates communication of information between the conditional execution logic mapping system 102 and external systems, sources, and devices (e.g., computing devices, communications devices, etc.).

[0063] The conditional execution logic mapping system 102 may include one or more computer and machine readable, writeable, and executable components and instructions that, when executed by the processor 106 (e.g., a classical processor, a quantum processor, etc.), can facilitate the performance of operations defined by such components and instructions. Additionally, in numerous embodiments, any component associated with the conditional execution logic mapping system 102, as described herein with or without reference to the various figures of this disclosure, can include one or more computer and machine readable, writeable, and executable components and instructions that, when executed by the processor 106, can facilitate the performance of operations defined by such components and instructions. For example, the unpacking component 108, the compiler component 110, and any other components associated with (e.g., communicatively, electronically, operatively, and optically coupled to and employed by) the conditional execution logic mapping system 102 as disclosed herein can include such computer and machine readable, writeable, and executable components and instructions. As a result, according to numerous embodiments, the conditional execution logic mapping system 102, and any components associated therewith as disclosed herein, may employ a processor 106 to execute such components and instructions that are computer- and machine-readable, writable, and executable to facilitate the performance of one or more operations described herein in connection with the conditional execution logic mapping system 102 and any components associated therewith.

[0064] The conditional execution logic mapping system 102 can facilitate (e.g., via the processor 106) the execution of operations performed by and associated with one or more of its components (e.g., the unfolding component 108, the compiler component 110, etc.). For example, the conditional execution logic mapping system 102 can facilitate (e.g., via the processor 106) the definition of system configurations and programming of functions for quantum computing resources.

[0065] In another example, the conditional execution logic mapping system 102 can facilitate (e.g., via the processor 106) a system operably coupled to a processor to map a logical reference to a qubit data structure in an instruction to a first engine component, and the system to deploy the first engine component to a first block controller component operably connected to a first quantum computing resource, where the first engine component controls the first quantum computing resource based on the instruction. In a variation of this example, the conditional execution logic mapping system 102 can facilitate (e.g., via the processor 106) a system to deploy a second engine component to a second block controller component operably connected to a second qubit of the first quantum computing resource and the first block controller component, where the second engine component controls the first quantum computing resource based on the second qubit, the first engine component, and the instruction.

[0066] In one or more embodiments, the compiler component 110 (e.g., via the processor 106) can map logical references to the qubit data structure in the instruction to the first engine component. Further, the deployment component 108 can deploy the first engine component to a first block controller component operably connected to the first quantum computing resource, where the first engine component controls the first quantum computing resource based on the instruction. According to another embodiment, as described in FIG. 2 below, the compiler component 110 can further map the program logic of the job 225 to a third engine component operably coupled to a third qubit of a second quantum computing resource, where the first quantum computing resource and the second quantum computing resource are quantum computing devices having different structures.

[0067] 2 and 3 illustrate an exemplary, non-limiting flow diagram 300 and block diagram of a system 200 that can facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements and processes employed in each embodiment are omitted.

[0068] In one or more embodiments, system 200 can include compiler component 110, deployment component 108, quantum computing resources 250A-B, and any other components that facilitate the functionality of system 200, as described below. As described further below, compiler component 110 can receive information corresponding to job 225 and organizational data 210A-B.

[0069] Given the above-mentioned problems with some existing approaches to reusing a job (e.g., job 225) for multiple quantum computing resources 250A-B, the present disclosure may be implemented to create a solution to this problem, as shown in FIG. 2 and described below. The approaches described herein may take the form of systems, computer-implemented methods, and computer program products that may compile a job 225 for multiple quantum computing resources 250A-B using a single compiler component 110 (e.g., without using different versions of the compiler component 110 for the different quantum computing resources 250A-B). Once compiled, the deployment component 108 may be instructed by the compiled job 225 to deploy different engine components to different elements of the quantum computing resources 250A-B.

[0070] As one of ordinary skill in the art will appreciate, given the description herein, different characteristics of quantum computing resources may vary from system to system, and these differences currently require compiled instructions to be customized over time to increase the likelihood of uniform functioning across quantum computing resources 250A-B. Exemplary differences between quantum computing resources 250A-B that may affect job deployment include, but are not limited to, the structure and interconnection of various layers (e.g., layers described in Figures 4 and 5 below) that may or may not be included, the location and mapping of registers implemented in the resources, support for conditional logic and extended measurements, and the latency associated with paths between components. Further differences are described with detailed implementation examples described in Figures 6 and 7A-7E below.

[0071] In one example implementation, after deployment of program logic by deployment component 108 on elements of quantum computing resource 250A, compiler component 110 can utilize organizational data 210B to map the program logic of job 225 to engine components operatively coupled to elements of quantum computing resource 250B. An advantage of such a system is that it can enable a mapping system for quantum computing applications to more quickly and efficiently develop and deploy applications on one or more quantum computing resources.

[0072] Figure 3 illustrates an example implementation that may include features that may facilitate the beneficial results described above in Figure 2. For illustrative purposes, the flow diagram of Figure 3 illustrates a conditional abstraction layer that represents general structures and characteristics that may be used to select quantum computing resources that may be used in using some embodiments described herein, for example, to increase the likelihood of successful execution.

[0073] In one or more embodiments, these various different quantum computing resources that may be utilized may be refined through the use of organizational data 210A-B. Thus, as shown in Figure 3, job instructions 310 may be mapped and scheduled 320, at block 325, for a particular quantum computing resource 250A through the use of organizational data 210A. In one implementation, the unique characteristics of the resource may be used to customize the conditional abstraction layer through the use of parameters.

[0074] 4-7E below, in one or more embodiments, once parameterized instructions (e.g., block 325) are generated for a particular quantum computing resource, functionality 345 of the instructions may be distributed to various execution components for execution, e.g., in engine component 340 generated by compiler component 110 and deployed to block controller components by deployment component 108. Thus, in block 350, as outlined above, one or more embodiments may implement job instructions 310 as commands for particular quantum computing resources 250A-B in a variety of ways.

[0075] It should be appreciated that compiling a single representation of a job and facilitating use of the same job on multiple quantum machines can reduce the customization effort required to customize jobs for different machines and improve standardization of deployment to different machines. These and other examples described herein illustrate the reduced computational costs that may result in some circumstances from the use of various embodiments described herein.

[0076] 4 illustrates a block diagram of an exemplary, non-limiting system 400 that can facilitate utilizing distributed processing to facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements and processes employed in each embodiment are omitted.

[0077] 4, one or more embodiments of system 400 may include block controller components 440A-C arranged in a hierarchical structure, qubits 485A-C, and any other components described below that facilitate the functionality of system 200. Block controller components 440A-B may include engine components 480A-B, digital-to-analog converters (DACs) 475A-B, analog-to-digital converters (ADCs) 472A-B, and qubit controllers 470A-B, respectively.

[0078] It should be appreciated that the term block controller component is used throughout this disclosure to denote the deployment of customized program logic to various elements of a destination, e.g., a quantum computing resource. In one or more embodiments, one or more of the block controller components 440A-B may be implemented by a field programmable gate array (FPGA) that receives programming from the deployment component 108 and implements the logic, e.g., as described in FIG. 4 below. This example is non-limiting and other types of program storage may be used to facilitate use of the distributed engine components 480A-B.

[0079] In the example shown in FIG. 4, an exemplary job may be created that tests a condition on a first qubit and applies a quantum gate using a second qubit and a third qubit based on the results of the test. In this example, the components of FIG. 4 described above are part of quantum computing resource 250A described above. Thus, to compile to have the structure of the resource in this example, compiler component 110 identifies organization data 210A. Using organization data 210A, in this example, compiler component selects qubits 485A-C as the reference first qubit, second qubit, and third qubit, respectively, based on, for example, their characteristics and placement within quantum computing resource 250A.

[0080] Because of this selection of qubits, in this example, block controller components 440A-B may be selected by compiler component 110, for example, as these controllers are shown along with other hardware associated with controlling the respective bits. Based on the selection of block controller components 440A-B, in this example, various tasks may be allocated to block controller components 440A-B, and paths may be selected for intermediate data values ​​(e.g., results of tests of the first qubit) and results of specified gates being applied, as described in more detail below.

[0081] After deployment of engine components 480A-B, operation of this exemplary embodiment may begin with engine component 480A utilizing stimulus channel 442A to send data corresponding to a test to DAC 475A and quantum bit controller 470A. Through operation of quantum bit controller 470A, a result is received from quantum bit 485A and converted to digital data by ADC 472A. Execution of the program logic of engine component 480A may resume upon receipt of this digital data, and the result may be interpreted as either a true (1) or false (0) value that may be stored in register 460A. Continuing with this example, the condition bit may be relayed to register 460B at block controller component 440B, either automatically or through operation of the program logic of engine component 480A.

[0082] It should be noted that this relay operation is illustrated in FIG. 4 with two paths between register 460A and register 460B, e.g., a hierarchical route through switch 410, and a direct route (e.g., peer-to-peer connection 405) between the hardware of block controller components 440A-B. In one or more embodiments, the existence of these routes may be stored in organizational data 210A along with the estimated latency of each route. In this example, compiler component 110 evaluated the two routes and selected peer-to-peer connection 405 to relay the result value from register 460A to 460B, and this selection was built into the logic of block controller component 440A. However, if the alternative route through switch 410 had been selected, one or more embodiments may have deployed logic to address the result value in block controller component 440C.

[0083] Continuing with this example, block controller component 440B receives the result value from register 460B by employing program logic deployed by compiler component 110, which determines whether to apply the specified gate by utilizing qubits 485B-C. In this example, when a condition indicates that the gate should be applied, stimulus channel 442B may be triggered to send data corresponding to the application of the gate to DAC 475B and qubit controller 470B. Through operation of qubit controller 470A, the gate is applied and a success indicator is detected by qubit controller 470B. Through operation of logic in engine component 480B, this success indication may be converted to digital data by ADC 472B. To conclude this example, execution of the compiled and deployed exemplary job is completed with the receipt and reporting of successful application of the applied gate.

[0084] It should be appreciated that this example is non-limiting and is intended to illustrate one approach that may be taken to implement the program logic unfolded above.

[0085] FIG. 5 illustrates a block diagram of an exemplary, non-limiting system 500 that can facilitate linking various distributed processing resources to achieve benefits including improved performance of conditional execution logic mapped to quantum computing resources, according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements and processes employed in each embodiment are omitted. In one or more embodiments, the system 500 can include qubits 580A-D, level 1 (L1) qubit (qubit) controllers 570A-D, level 2 (L2) engine components 560A-D, level 3 (L3) engine components 585A-B, and level 4 (L4) engine components 587. Note that in this example, block controller components for the engine components are omitted, along with the DAC or ADC described above in FIG. 4.

[0086] 5 is the selection of locations for deploying engine components 560A-D and the selection of paths that may be evaluated and selected by compiler component 110 to implement a compiled job, e.g., paths that may be used to pass values ​​to various components according to program logic. As an illustration of one or more benefits that may be realized by using some embodiments, an example may be considered in which the only relaying of program values ​​is performed hierarchically, e.g., when a value to be relayed by L2 engine component 560C is relayed not by peer-to-peer connection 505B, but by relaying through L3 engine component 585A, L4 engine component 587, and L3 engine component 585B.

[0087] To avoid this, one or more embodiments can beneficially organize the linkage of engine components in any manner supported by the hardware connections in the quantum computing resource, using connection topologies including, but not limited to, peer-to-peer, interactive mesh, ring, tree, and hierarchical arrangements. It should be noted that while the illustrated example uses a four-tier hierarchy, this arrangement is merely exemplary and other numbers of tiers may be implemented by one or more embodiments. The advantage of such a system is that it may enable a mapping system for quantum computing applications to more quickly and efficiently develop and deploy applications on one or more quantum computing resources, for example, by using the organizational data to compile applications with improved use of the structure of a particular quantum computing resource. Exemplary negative outcomes that may be avoided by using this structural organizational data include congestion points (e.g., choke points) between quantum computing resource elements.

[0088] 5 illustrates a further embodiment in which qubit 580C is labeled as out of service. In existing implementations in which qubits 580A-D are selected for injecting operations, this up-to-date information regarding a particular resource of a quantum computing device would not necessarily be evaluated. In contrast, in one or more embodiments, as described above, the operational status of various components of a quantum computing resource may be included in the organizational data for the resource. This status may range from the example shown (e.g., not in use) to a measure of the performance of the component, such as a measure of processing speed.

[0089] 6 illustrates a block diagram of an exemplary, non-limiting system 600 that may include a portion of a qubit controller that can facilitate access to qubits for manipulation of compiled instructions described herein, according to one or more embodiments. For the sake of brevity, repeated descriptions of similar elements and processes employed in each embodiment are omitted. For example, system 600 includes qubit controller 615B, which acquires channels 630A-C, device layer 612, and qubits 690A-B.

[0090] In one or more embodiments, to facilitate conditional execution of commands based on the value of the qubits, the qubit controllers may have further features that facilitate evaluation of conditions, and various qubit controller actions may be based on this evaluation. For example, system 600 includes two qubit controllers 615A-B, each having an exemplary drive channel (D), measurement channel (M), and U-channel for use with device layer 612. In an implemented feature of one or more embodiments, each of the stimulus channels described above may have a MUX for testing conditions, e.g., conditions 610A-D and 612A-D. In one or more embodiments, this may be implemented to improve performance of conditional execution applications, for example, since the source of the condition bits being tested may change during execution of the circuit. It should be appreciated that this logic may be controlled by compiler component 110 as part of deploying program logic on a particular quantum computing resource.

[0091] In a further feature, to reduce latency in the results measured from the available quantum bits, in one or more embodiments, registers of channels 630A-C may be used for each of acquisition channels 670A-C; for example, quantum bit measurements may be passed into corresponding registers as they are produced, and the register outputs may be routed by program logic directly to stimulus channels within the same quantum bit controller or to other conditional execution logic outside the block controller.

[0092] It should be appreciated that for many of the memory resources described herein (e.g., registers, memory, buffers), the location, performance, latency, size, and availability of such resources may be incorporated into the organizational data used by compiler component 110. Given the description herein, those skilled in the art will recognize these different ways in which such data may be utilized to improve performance, as well as other suggested information that may be used in a similar manner.

[0093] 7A illustrates a block diagram of a non-limiting example implementation 700 of an engine component to be deployed in a quantum computing resource (e.g., in a block controller) according to one or more embodiments. For the sake of brevity, repeated descriptions of similar elements and processes employed in each embodiment are omitted. As shown, the example conditional engine component 790 700 includes receive buffers 720A-C, receive registers 760, result registers 750, combiners 740A-B, combiner specific instruction sequencing components (ISEQ) 724A-B (described in Figures 7D-E below), and transmit channels 710A-C.

[0094] In a non-limiting example shown in FIG. 7A, if one or more embodiments of an engine component described herein have inherent features that can facilitate conditional execution, the engine component may be referred to as a conditional engine component, e.g., conditional engine component 790. It should be noted that while examples of conditional execution are used throughout this disclosure, these are intended to be illustrative only, and embodiments are not limited thereto, e.g., other combinations of programming elements may be used with one or more embodiments. Returning to the conditional execution example described in FIG. 4 above, after a measurement from a qubit is measured, conditional engine component 790 may be used to convert the measurement into a testable condition bit that is distributed to another engine component for conditional use. As described below, additional features may be utilized by one or more embodiments to further improve the performance of the conditional execution process.

[0095] In one or more embodiments, as described above, one way in which the engine component can be configured to programmatically combine and pass qubit values ​​around the system is to use existing commands implemented in some systems. For example, in one or more embodiments, a flat set of global registers and operators that use them. Exemplary operators ("copy" and Boolean functions such as OR, NOR, shift, rotate, etc.) can already move the differentiated binary qubit measurements between registers to facilitate combining them with Boolean functions, for example resulting in single-bit testable conditions. These testable conditions can then be used by the waveform player to determine whether to apply a quantum gate. It should be recognized that incorporating the use of these operators into the operation of the compiler component 110 and unfolder component 108 as described and proposed herein can improve performance, flexibility, and ease of distribution of applications to additional resources. In the following, some elements of an embodiment of the conditional engine component 790 are described.

[0096] The receive buffers 720A-C are described below.

[0097] In an exemplary approach to implementing the bfunc command, in one or more embodiments, at the beginning of a job, binary qubit values ​​may be received by an engine component (e.g., conditional engine component 790) through an array of bits called receive buffers 720A-C. All receive buffers may begin to fill and remain full. In one or more embodiments, the existence and size of receive buffers may be available to compiler component 110 to help improve the operation of the program logic. For example, if more qubit measurement results arrive than the buffers can hold, this may be considered an error, and compiler component 110 may be configured to minimize or eliminate the possibility of this outcome.

[0098] The description of the receive register 760 is as follows:

[0099] The receive buffer values ​​may be concatenated into a single receive register 760 vector for processing by combiners 740A-B, where Boolean functions may be performed. In one or more embodiments, the quantum computing resource may implement this register as a virtual concatenation or a physical concatenation. In a virtual concatenation, one or more embodiments may utilize the receive register 760 as a virtual object, e.g., one cannot use a "copy" command to copy qubit values ​​from receive buffer 720A into receive register 760.

[0100] The description of the result register 750 is as follows:

[0101] In one or more embodiments, as shown, result registers 750 may receive and store the results of combiners 740A-B for further use. In contrast, receive registers 760 may be written by other elements, e.g., qubit controllers and other engine components. In one example, the results may be fed back as inputs into combiners 740A-B to implement a "copy" command or to allow the results of a "bfunc" command to be used by another part of the system. Additionally, as described in FIG. 4 above. They may be the source of bits sent to other blocks, e.g., values ​​relayed using peer-to-peer connections 405, e.g., register 460A relaying values ​​from block controller component 440A to block controller component 440B. In some implementations, the input vectors generated may be the same for all combiners in conditional engine component 790.

[0102] In another embodiment, the receive registers 760 and the result registers 750 may be concatenated and passed into combiners 740A-B, which can execute the "bfunc" command by combining selected receive register 760 inputs into a single binary output. Further details regarding combiners 740A-B are provided in FIG. 7B below.

[0103] 7B-7C illustrate block diagrams of a non-limiting example engine component combiner 702 according to one or more embodiments. The example 702 includes a combiner 740A receiving instruction sequencing information (described in FIGS. 7D-7E below) from an instruction sequencer 789 and providing inputs 783 and outputs 787 to and from other system processes as described above.

[0104] In one or more embodiments, in addition to implementing Boolean functions, as described above, combiners 740A-B may have further features that may be utilized by one or more embodiments to further improve the performance of conditional engine component 790. For example, inputs 783 to combiner 740A may be individually maskable based on settings from compiler component 110. Benefits of this masking capability include the ability to increase processing efficiency by facilitating the selection of a subset of inputs on which combiner 740A operates at a particular time.

[0105] Alternative application of masking: In one or more embodiments, at the start of a job, the contents of all receive buffers 720A-C and result registers 750 may be treated as containing unknown values, e.g., since they may not have been reset between jobs or experimental iterations. In one or more embodiments, organizational data describing the quantum computing resources may include an indication that the initial values ​​from buffers 720A-C and result registers 750 are unknown. Based on this, compiler component 110 may include configuration settings that initially mask inputs coming from these sources, e.g., to prevent unknown values ​​from affecting combiner outputs and the overall result of the job. In one or more embodiments, this mask setting may be received from instruction sequencer 789 as part of the overall sequencing of commands. Further configuration of engine components by compiler component 110 may be enabled in some implementations by the number of combiners in the engine components being selected and set by compiler component 110.

[0106] In a related function of combiners 740A-B, in addition to mask settings, the instruction sequencer can also provide patterns to be applied to masked input values. As with the other settings described above, these patterns are subject to program control that is generated and deployed by compiler component 110.

[0107] Figure 7C provides an example table 703 of binary codes for selecting functions to be performed by combiners 740A-B. The table includes function selection 782 codes with example operations that may be performed by combiners 740A-B. As with mask settings, these function codes may be received from an instruction sequencer 789 as part of the overall sequencing of commands. Further details regarding the instruction sequencing components are provided below in Figures 7D-E.

[0108] 7D-7E provide non-limiting illustrations of the operation of an instruction sequencing component according to one or more embodiments. Figure 7D shows an example 704 of a list 777 of commands for a quantum computing resource, for example, utilizing a hardware control field 774. In one or more embodiments, the compiler 110 can generate lists of this type for use by the instruction sequencer 789 to control program execution.

[0109] In an advantageous implementation of this feature, one or more embodiments may compress this list 777 to a smaller size, e.g., to conserve system resources by limiting processing. In an example 706, FIG. 7E illustrates a resulting compressed list that may be distributed to engine components 480A-B to provide a sequence of instructions. In this example, in the first five cycles of execution of the job, hardware control field 774 is specified by compiling components 110 to be executed over five cycles. In one or more embodiments, prior to distributing information sequencer list 777 as part of the distributed program logic, references to these five sequential hardware control fields may be simplified to compressed 778 entries as shown in FIG. 7D-7E, e.g., by specifying number of cycles 772 (5) and hardware control field 774.

[0110] Certain types of sequencer entries 773 may include a zero (0) value 769 along with a hardware control field 776. In some implementations, this value 769 may execute instructions (e.g., hardware control field 776) that do not need to be specified by compiler component 110. For example, in one or more embodiments, this value 769 may trigger initialization of system data storage resources, for example, to avoid unknown values ​​as noted with the description of combiners 740A-B above. In another example, in one or more embodiments, the value 269 may be used to apply a valid hardware control field during execution of a job. In these examples, the value 269 being zero (0) indicates an indefinite amount of time associated with these processes.

[0111] In one or more embodiments, the functionality of the instruction sequencer 789 may be specifically provided to selected components. For example, to further improve performance in some circumstances, each combiner may have its own instruction sequencer, e.g., ISEQ 742A-B, to facilitate the compiler component 110 scheduling the "copy" and "bfunc" operations when a job is compiled. In other embodiments, additional components that may use the compressed instruction sequencer 789 include registers, including but not limited to, the output registers of the acquisition channels 630A-C, the condition selection multiplexers (e.g., test conditions 610A-D) in the qubit controller, and the transmit register selectors and result register 750 selectors of the transmit channel 710 in the conditional engine component. Although similar in usage, each component may utilize such a sequencer with hardware control fields tailored to the logic managed by the compressed instruction sequencer 789.

[0112] 8 illustrates a flow diagram of an exemplary, non-limiting computer-implemented method 800 that can facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements and processes employed in each embodiment are omitted.

[0113] At 802, computer-implemented method 800 may include a system operably coupled to a processor mapping a logical reference to a qubit data structure in an instruction to a first engine component. For example, in one or more embodiments, method 800 may include a system 100 operably coupled to a processor 106 mapping a logical reference in a job 225 to a qubit data structure in an instruction to a first engine component, e.g., engine component 480A.

[0114] At 804, the computer-implemented method 800 may include the system deploying the first engine component to a first block controller component operably connected to the first quantum computing resource. For example, in one or more embodiments, the method 800 may include the system 100 deploying the engine component 480A to a block controller component 440A operably connected to the quantum computing resource. In one or more embodiments, the conditional execution logic mapping system 102 can provide technical improvements to systems, devices, components, operable steps, and process steps associated with the various technologies identified above. For example, the conditional execution logic mapping system 102 can include mapping a job's logical reference to a qubit data structure in an instruction to a first engine component. An advantage of such a system is that it can enable a mapping system for quantum computing applications to more quickly and efficiently develop and deploy applications on one or more quantum computing resources.

[0115] In some embodiments, method 800 may further include the system deploying the first engine component to a first block controller component operably connected to the first quantum computing resource. In one or more embodiments, the first engine component may control the first quantum computing resource based on the instructions. An advantage of such a system is that it may enable a mapping system for quantum computing applications to more quickly and efficiently develop and deploy applications on one or more quantum computing resources.

[0116] It should be appreciated that the conditional execution logic mapping system 102 provides a new approach driven by relatively new quantum computing technologies, for example, the conditional execution logic mapping system 102 provides a new approach to quantum computing software development and implementation across a variety of quantum computing platforms.

[0117] At least in practical implementations, on a large scale, the conditional execution logic mapping system 102 may employ a combination of hardware and software to solve problems that are highly technical in nature, not abstract, and cannot be implemented as a set of mental acts by a human. In some embodiments, one or more of the processes described herein may be executed by one or more specialized computers (e.g., specialized processing units, specialized classical computers, specialized quantum computers, etc.) to perform defined tasks associated with the various technologies identified above. The conditional execution logic mapping system 102 or components thereof, or both, may be employed to solve new problems that arise through the adoption of advances in the technologies discussed above, quantum computing systems, cloud computing systems, computer architectures, or another technology, or a combination thereof.

[0118] It should be appreciated that in one or more embodiments, the conditional execution logic mapping system 102 may utilize various combinations of electrical components, mechanical components, and circuitry that cannot be replicated in or performed by the human mind. As one of ordinary skill in the art will appreciate, given the description herein, in large-scale practical implementations, these various operations that may be performed by the conditional execution logic mapping system 102 and its components exceed the capabilities of the human mind. For example, the amount of data processed, the speed at which such data is processed, or the type of data processed by the conditional execution logic mapping system 102 over a period of time may be greater, faster, or different than the amount, speed, or type of data that can be processed by the human mind over the same period of time.

[0119] According to some embodiments, the conditional execution logic mapping system 102 may be fully operational (e.g., fully powered on, fully running, etc.) towards the execution of one or more other functions while also performing various operations described herein. It should be appreciated that the simultaneous execution of such multiple operations is beyond the capabilities of the human mind. It should also be appreciated that the conditional execution logic mapping system 102 may include information that cannot be manually obtained by an entity such as a human user. For example, the type, amount, or variety of information included in the conditional execution logic mapping system 102, the deployment component 108, or the compiler component 110, or combinations thereof, may be more complex than information manually obtained by a human user.

[0120] 9 illustrates a flow diagram of an exemplary, non-limiting computer-implemented method 900 that can facilitate mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements and processes employed in each embodiment are omitted.

[0121] At 902, the computer-implemented method 900 may include receiving a job for an identified quantum computing resource. At 904, organizational data for the quantum computing resource may be identified. At 906, job instructions may be compiled based on the organizational data. At 907, engine components generated during compilation may be deployed to block controller components at the identified quantum computing resource. At 907, during execution of the deployed and compiled job, a block controller for a target gate may test a result bit received from a measurement of another controller. At 910, if the condition is false, the gate is not applied, and at 914, if the condition is true (1), the gate specified by the program logic is applied.

[0122] For ease of explanation, the computer-implemented methods are shown and described as a series of acts. It is to be understood and appreciated that the subject innovation is not limited by the acts and the order of acts shown, for example, acts may occur simultaneously in various orders with other acts not shown and described herein. Moreover, not all acts shown may be necessary to implement a computer-implemented method in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that a computer-implemented method may alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, it is to be further appreciated that the computer-implemented methods disclosed hereinafter and throughout this specification may be stored on an article of manufacture to facilitate transporting and transferring such computer-implemented methods to a computer. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0123] To provide a context for various aspects of the disclosed subject matter, Figure 10 and the following description are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. Figure 10 illustrates a block diagram of an exemplary, non-limiting operating environment that may facilitate one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0124] 10, a suitable operating environment 1000 for implementing various aspects of the disclosure may include a computer 1012. The computer 1012 may also include a processing unit 1014, a system memory 1016, and a system bus 1018. The system bus 1018 couples system components including, but not limited to, the system memory 1016 to the processing unit 1014. The processing unit 1014 may be any of a variety of available processors. Dual microprocessors and other multi-processor architectures may also be employed as the processing unit 1014. The system bus 1018 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus or external bus, and a local bus using any of a variety of available bus architectures including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Enhanced ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire® (IEEE 1394), Small Computer System Interface (SCSI).

[0125] The system memory 1016 may also include volatile memory 1020 and non-volatile memory 1022. A basic input / output system (BIOS), containing the basic routines for transferring information between elements within the computer 1012, such as during start-up, is stored in the non-volatile memory 1022. The computer 1012 may also include removable / non-removable, volatile / non-volatile computer storage media. FIG. 10 illustrates, for example, disk storage 1024. The disk storage 1024 may also include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. The disk storage 1024 may also include storage media separate or in combination with other storage media. A removable or non-removable interface, such as an interface 1026, is typically used to facilitate connection of the disk storage 1024 to the system bus 1018. FIG. 10 also illustrates software that acts as an intermediary between users and the basic computer resources described in the preferred operating environment 1000. Such software may include, for example, operating system 1028. Operating system 1028, which may be stored on disk storage 1024, acts to control and allocate resources of the computer 1012.

[0126] System applications 1030 take advantage of the management of resources by operating system 1028 through program modules 1032 and program data 1034, which are stored, for example, in either system memory 1016 or disk storage 1024. It should be appreciated that the present disclosure may be implemented with various operating systems or combinations of operating systems. A user enters commands or information into computer 1012 through input devices 1036. Input devices 1036 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, television tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to processing unit 1014 through system bus 1018 via interface ports 1038. Interface ports 1038 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output devices 1040 use several of the same types of ports as input devices 1036. Thus, for example, a USB port may be used to provide input to the computer 1012 and to output information from the computer 1012 to an output device 1040. Output adapters 1042 are provided to illustrate that there are some output devices 1040, such as monitors, speakers, and printers, among other output devices 1040, that require special adapters. Output adapters 1042 include, by way of example and not limitation, video cards and sound cards that provide a means of connection between the output device 1040 and the system bus 1018. It should be noted that other devices and systems of devices provide both input and output capabilities, such as a remote computer 1044.

[0127] The computer 1012 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1044. The remote computer 1044 can be a computer, a server, a router, a network PC, a workstation, a microprocessor-based appliance, a peer device or other common network node, and typically can include many or all of the elements described relative to the computer 1012. For simplicity, only a memory storage device 1046 is shown with the remote computer 1044. The remote computer 1044 is logically connected to the computer 1012 through a network interface 1048 and is then physically connected via a communication connection 1050. The network interface 1048 encompasses wired and wireless communication networks, such as a local area network (LAN), a wide area network (WAN), a cellular network, and the like. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereon, packet-switched networks, and Digital Subscriber Lines (DSL). Communications connection 1050 refers to the hardware / software employed to connect network interface 1048 to system bus 1018. Although communications connection 1050 is shown internal to computer 1012 for clarity of illustration, it may also be external to computer 1012. The hardware / software for connecting to network interface 1048 may also include, for illustrative purposes only, internal and external technologies such as modems, including ordinary telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0128] Referring now to FIG. 11, an exemplary cloud computing environment 1150 is illustrated. As illustrated, the cloud computing environment 1150 includes one or more cloud computing nodes 1110 with which local computing devices used by cloud consumers may communicate, such as, for example, a personal digital assistant (PDA) or cellular phone 1154A, a desktop computer 1154B, a laptop computer 1154C, and an automobile computer system 1154N. Although not illustrated in FIG. 11, the cloud computing nodes 1110 may further include a quantum platform (e.g., quantum computer, quantum hardware, quantum software, etc.) with which local computing devices used by cloud consumers may communicate. The nodes 1110 may communicate with each other. They may be physically or virtually grouped (not illustrated) in one or more networks, such as a private cloud, a community cloud, a public cloud, or a hybrid cloud, or a combination thereof, as described above. This allows the cloud computing environment 1150 to provide infrastructure, platform, and software as a service without the cloud consumer having to maintain resources on the local computing device. It will be appreciated that the types of computing devices 1154A-N shown in FIG. 11 are intended as examples only, and that the computing node 1110 and cloud computing environment 1150 can communicate with any type of computerized device via any type of network and network-addressable connections (e.g., using a web browser).

[0129]

[0081] Referring now to Figure 12, a set of functional abstraction layers provided by cloud computing environment 1150 (Figure 11) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 12 are intended to be exemplary only, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0130] Hardware and software layer 1260 includes hardware and software components. Examples of hardware components include mainframes 1261, RISC (reduced instruction set computer) architecture based servers 1262, servers 1263, blade servers 1264, storage devices 1265, and networks and networking components 1266. In some embodiments, software components include network application server software 1267, database software 1268, Quantum Platform routing software (not shown in FIG. 12), and Quantum software (not shown in FIG. 12).

[0131] Virtualization layer 1270 provides an abstraction layer from which examples of virtual entities, such as virtual servers 1271 , virtual storage 1272 , virtual networks including virtual private networks 1273 , virtual applications and operating systems 1274 , and virtual clients 1275 , may be provided.

[0132] In one example, management layer 1280 may provide the functionality described below. Resource provisioning 1281 provides dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 1282 provides cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification of cloud consumers and tasks, as well as protection of data and other resources. User portal 1283 provides consumers and system administrators with access to the cloud computing environment. Service level management 1284 provides allocation and management of cloud computing resources such that required service levels are met. Service level agreement (SLA) planning and fulfillment 1285 provides advance preparation and procurement of cloud computing resources in anticipation of future requirements according to SLAs.

[0133] Workload tier 1290 provides examples of functions for which a cloud computing environment may be utilized. Non-limiting examples of workloads and functions that may be provided from this tier include mapping and navigation 1291, software development and lifecycle management 1292, virtual classroom instruction delivery 1293, data analytics processing 1294, transaction processing 1295, and quantum state measurement logic software 1296.

[0134] The present invention may be a system, method, apparatus, and computer program product at any conceivable level of technical detail of integration. The computer program product may include one or more computer-readable storage media having computer-readable program instructions for causing a processor to perform aspects of the present invention. A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may include portable computer diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), static random access memories (SRAMs), portable compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves that record instructions, and any suitable combination of the foregoing. Computer-readable storage medium, as used herein, should not be construed as being, itself, a transitory signal, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or an electrical signal transmitted through a wire.

[0135] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium into each computing / processing device, or may be downloaded to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, and a wireless network. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing / processing device. The computer readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk® or C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to perform aspects of the invention.

[0136] Aspects of the present invention are described herein with reference to flowchart illustrations and block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and block diagrams, and combinations of blocks in the flowchart illustrations and block diagrams, can be implemented by computer readable program instructions. These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing apparatus create means for implementing the functions / acts specified in one or more blocks of the flowcharts and block diagrams. These computer readable program instructions, which can direct computers, programmable data processing apparatus, and other devices to function in a particular manner, can also be stored on a computer readable storage medium, such that the computer readable storage medium having the instructions stored thereon includes an article of manufacture including instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and block diagrams. The computer readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable apparatus, or other device to perform a series of operable acts to produce a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowcharts and block diagrams.

[0137] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may be performed in a different order than that noted in the figures. For example, depending on the functionality involved, two blocks shown in succession may actually be executed substantially simultaneously, or these blocks may be executed in reverse order in some cases. It will also be noted that each block of the block diagrams and flowchart diagrams, and combinations of blocks in the block diagrams and flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or acts, or a combination of dedicated hardware and computer instructions.

[0138] Although the subject matter has been described above in the general context of computer-executable instructions for computer program products running on one computer and multiple computers, those skilled in the art will appreciate that the present disclosure may also be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and implement particular abstract data types. Those skilled in the art will also appreciate that the computer-implemented methods of the present invention may be practiced with other computer system configurations, including single-processor or multi-processor computer systems, minicomputing devices, mainframe computers, as well as computers, handheld computing devices (e.g., PDAs, phones), and microprocessor-based or programmable consumer or industrial electronic devices, etc. The illustrated aspects may be practiced in a distributed computing environment where tasks are performed by remote processing devices linked through a communications network. However, some, but not all, aspects of the present disclosure may be practiced on stand-alone computers. In a distributed computing environment, program modules may be located in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components may be executed from a memory that may include or consist of one or more distributed memory units. As used herein, the terms "memory" and "memory unit" are interchangeable. Furthermore, one or more embodiments described herein may execute computer-executable component code in a distributed manner (e.g., multiple processors combine or cooperate to execute code from one or more distributed memory units). As used herein, the term "memory" may encompass a single memory or memory unit in one location, or multiple memories or memory units in one or more locations.

[0139] As used herein, terms such as "component," "system," "platform," and "interface" can refer to and include computer-related entities or entities related to an operable machine having one or more specific functions. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and a computer. By way of example, both an application running on a server and the server can be a component. One or more components can reside within a process and thread of execution, and some components can be localized on one computer and distributed among two or more computers. In another example, each component can execute from various computer-readable media having various data structures stored thereon. These components can communicate via local and remote processes, such as according to such signals having one or more data packets (e.g., data from one component interacting with another component in a network such as the Internet with local systems, distributed systems, and other systems via signals). As another example, a component may be a device having specific functionality provided by mechanical parts operated by electrical or electronic circuitry operated by a software or firmware application executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application.As yet another example, a component may be a device that provides a unique functionality without mechanical parts through electronic components, which may include a processor or other means for executing software or firmware that provides at least part of the functionality of the electronic component. In an aspect, a component may emulate an electronic component via a virtual machine, for example, in a cloud computing system.

[0140] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any of the natural and inclusive permutations. That is, if X employs A, if X employs B, or if X employs both A and B, then "X employs A or B" is valid under any of the above-mentioned examples. In addition, the articles "a" and "an" as used in this specification and the accompanying drawings should generally be construed to mean "one or more" unless otherwise specified or clear from the context that they are intended to refer to the singular form. As used herein, the terms "example" and "exemplary" are utilized to mean serving as an example, illustration, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as "example" and "exemplary" should not necessarily be construed as preferred or advantageous over other aspects or designs, nor is it intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0141] As employed herein, the term "processor" may refer to substantially any computing processing unit or device, including, but not limited to, a single-core processor, a single processor with software multithreading execution capability, a multi-core processor, a multi-core processor with software multithreading execution capability, a multi-core processor with hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space usage or enhance the performance of user equipment. A processor may be implemented as a combination of computing processing units. In this disclosure, terms such as "memory," "storage," "data store," "data storage," "database," and substantially any other information storage component associated with the operation and functionality of a component are utilized to refer to a "memory component" entity embodied in a "memory" or memory-containing component. It should be recognized that memory and memory components described herein may be either volatile or non-volatile memory, or may include both volatile and non-volatile memory.By way of example, and not limitation, non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include, for example, a RAM that may act as external cache memory. By way of example, and not limitation, RAM is available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of the systems or computer-implemented methods herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0142] The foregoing includes only examples of systems and computer-implemented methods. Of course, for purposes of describing this disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art can recognize that many further combinations and permutations of the present disclosure are possible. Moreover, to the extent that terms such as "including," "having," and "possessing" are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a manner similar to the term "comprising" when interpreted as such when employed as a transitional term in the claims.

[0143] Although the description of various embodiments has been presented for illustrative purposes, the description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will become apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements to the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. According to this specification, the following items are also disclosed. [Item 1] A memory for storing computer executable components; a processor for executing the computer-executable components stored in the memory; A system comprising: The computer-executable components are: a compiler component that maps logical references to qubit data structures in the instructions to a first engine component; a deployment component that deploys the first engine component to a first block controller component operably connected to a first quantum computing resource, the first engine component controlling the first quantum computing resource based on the instructions; Including, system. [Item 2] The system of item 1, wherein the first block controller component is operably connected to a first quantum bit of the first quantum computing resource, and the first engine component controls the first quantum computing resource further based on the first quantum bit. [Item 3] 3. The system of claim 2, wherein the first engine component is operably linked to the first quantum bit via a quantum bit controller coupled to the first quantum bit, the quantum bit controller interfaces with the first quantum bit by sending analog signals to the first quantum bit and receiving analog signals from the first quantum bit. [Item 4] The system of any one of claims 1 to 3, dependent on claim 2, wherein the first engine component further conditionally controls the first quantum computing resource based on a value of the first quantum bit. [Item 5] 5. The system of claim 4, wherein the compiler component further maps the logical references of the instruction to a third engine component operably coupled to a second block controller component of a second quantum computing resource, the first quantum computing resource and the second quantum computing resource having different structures. [Item 6] 6. The system of claim 5, wherein the compiler component selects the third engine component based on second organizational data for the second quantum computing resource, the second organizational data including a structure of the engine component of the second quantum computing resource. [Item 7] 7. The system of any one of claims 1 to 6, wherein based on the instructions, the deployment component further deploys a second engine component to a second block controller component operably connected to a second quantum bit of the first quantum computing resource and to the first block controller component, and the second engine component controls the first quantum computing resource based on the second quantum bit, the first engine component, and the instructions. [Item 8] Based on the first organizational data, the compiler component is: further mapping execution of the instructions to the first engine component and the second engine component; configuring the first engine component to access a first element of the first quantum computing resource, the first organizational data including first organizational data describing the first element of the first quantum computing resource; 8. The system according to item 7. [Item 9] 9. The system of claim 8, wherein the instructions further include a further logical reference to a register that stores a result of measuring the first quantum bit, and the first element includes the register. [Item 10] The system of any one of items 1 to 9, dependent on item 7, wherein the first organizational data further includes a latency value corresponding to a duration for completing communication of program values ​​between the first block controller component and the second block controller component, and based on the latency value, the deployment component deploys the second engine component to the second block controller component and the first engine component of a second quantum computing resource. [Item 11] The system of any one of items 1 to 10, dependent on item 7, wherein the first engine component and the second engine component of the first quantum computing resource are operatively linked to each other in a hierarchical structure based on first organizational data. [Item 12] The system of any one of claims 1 to 11, wherein the deployment component further deploys a fourth engine component to a fourth execution controller component, and the fourth engine component controls the first quantum computing resource to execute default instructions without mapping by the compiler component. [Item 13] 1. A computer-implemented method comprising: a system operatively coupled to the processor mapping a logical reference to the qubit data structure in the instruction to a first engine component; deploying the first engine component to a first block controller component operably connected to a first quantum computing resource, the first engine component controlling the first quantum computing resource based on the instructions; A computer-implemented method comprising: [Item 14] deploying a second engine component to the first block controller component and a second block controller component operably connected to a second qubit of the first quantum computing resource, the second engine component controlling the first quantum computing resource based on the second qubit, the first engine component, and the instructions, Item 14. The computer-implemented method of item 13, further comprising: [Item 15] the system further mapping execution of the instructions to the first engine component and the second engine component based on first organizational data; configuring the first engine component to access a first element of the first quantum computing resource, the first organizational data including first organizational data describing the first element of the first quantum computing resource; Item 15. The computer-implemented method of item 14, further comprising: [Item 16] Item 16. The computer-implemented method of item 15, wherein the instructions further include a logical reference to a register that stores a result of measuring the first quantum bit, and the first element includes the register. [Item 17] The computer-implemented method of any one of items 13 to 16, dependent on item 15, wherein the first organizational data further includes a latency value corresponding to a duration for completing communication of program values ​​between the first block controller component and the second block controller component, and based on the latency value, the deployment component deploys the second engine component to the second block controller component and the first engine component of a second quantum computing resource. [Item 18] 1. A computer program product that facilitates mapping conditional execution logic to a quantum computing resource, the computer program product comprising program instructions executable by a processor, the program instructions causing the processor to: Mapping a logical reference to the qubit data structure in the instruction to a first engine component; deploying the first engine component on a first block controller component operably connected to a first quantum computing resource, the first engine component controlling the first quantum computing resource based on the instructions; A computer program that performs the following: [Item 19] 20. The computer program product of claim 18, wherein the first block controller component is operably connected to a first quantum bit of the first quantum computing resource, and the first engine component controls the first quantum computing resource further based on the first quantum bit. [Item 20] 20. The computer program product of claim 19, wherein the first engine component further conditionally controls the first quantum computing resource based on a value of the first quantum bit.

Claims

1. A memory for storing computer executable components; a processor for executing the computer-executable components stored in the memory; A system comprising: The computer executable components include: a compiler component that maps logical references to qubit data structures in instructions to a first engine component; a deployment component that deploys the first engine component to a first block controller component operably connected to a first quantum computing resource, the first engine component controlling the first quantum computing resource based on the instructions; Including, the first block controller component is operably connected to a first qubit of the first quantum computing resource, and a resultant value received from the first qubit is sent to a second block controller component operably connected to a second qubit of the first quantum computing resource. system.

2. The system described in claim 1, wherein the first engine component controls the first quantum computing resource further based on the first quantum bit.

3. 3. The system of claim 2, wherein the first engine component is operably linked to the first qubit via a qubit controller coupled to the first qubit, the qubit controller interfacing with the first qubit by sending analog signals to and receiving analog signals from the first qubit.

4. 4. The system of claim 2 or 3, wherein the first engine component is further configured to conditionally control the first quantum computing resource based on a value of the first quantum bit.

5. The system of claim 4 , wherein the compiler component further maps the logical references of the instruction to a third engine component operably coupled to a third block controller component of a second quantum computing resource, the first quantum computing resource and the second quantum computing resource having different structures.

6. 6. The system of claim 5, wherein the compiler component selects the third engine component based on second organizational data for the second quantum computing resource, the second organizational data including a structure of an engine component of the second quantum computing resource.

7. 7. The system of claim 1, wherein based on the instructions, the deployment component further deploys a second engine component to the second block controller component and the first block controller component, the second engine component controlling the first quantum computing resource based on the second qubit, the first engine component, and the instructions.

8. Based on the first organizational data, the compiler component: further mapping execution of the instructions to the first engine component and the second engine component; Configuring the first engine component to access a first element of the first quantum computing resource, the first organizational data including first organizational data describing the first element of the first quantum computing resource. The system of claim 7.

9. 10. The system of claim 8, wherein the instructions further include a further logical reference to a register that stores a result of measuring the first quantum bit, and the first element comprises the register.

10. 10. The system of claim 7, wherein the first organizational data further comprises a latency value corresponding to a duration for completing communication of program values ​​between the first block controller component and the third block controller component, and wherein based on the latency value, the deployment component deploys the first engine component and the second engine component to the third block controller component of a second quantum computing resource.

11. 11. The system of claim 7, wherein based on first organizational data, the first engine component and the second engine component of the first quantum computing resource are operatively linked to each other in a hierarchical structure.

12. 12. The system of claim 1, wherein the deployment component further deploys a fourth engine component to a fourth execution controller component, the fourth engine component controlling the first quantum computing resource to execute default instructions without mapping by the compiler component.

13. 1. A computer-implemented method, comprising: a system operatively coupled to the processor mapping a logical reference to the qubit data structure in the instruction to a first engine component; The system deploys the first engine component on a first block controller component operably connected to a first quantum computing resource, the first engine component controlling the first quantum computing resource based on the instructions; the system transmitting a resultant value received from a first qubit of the first quantum computing resource to a second block controller component of the first quantum computing resource, the first qubit being operably connected to the first block controller component and the second block controller component being operably connected to a second qubit; A computer-implemented method comprising:

14. deploying a second engine component to the second block controller component and to the first block controller component, the second engine component controlling the first quantum computing resource based on the second qubit, the first engine component, and the instructions. The computer-implemented method of claim 13 further comprising:

15. the system further mapping execution of the instructions to the first engine component and the second engine component based on first organizational data; configuring the first engine component to access a first element of the first quantum computing resource, the first organizational data including first organizational data describing the first element of the first quantum computing resource; The computer-implemented method of claim 14 further comprising:

16. 16. The computer-implemented method of claim 15, wherein the instructions further include a logical reference to a register that stores a result of measuring a first quantum bit, and the first element includes the register.

17. 17. The computer-implemented method of claim 15, wherein the first organizational data further includes a latency value corresponding to a duration for completing communication of a program value between the first block controller component and a third block controller component of a second quantum computing resource, and based on the latency value, a deployment component deploys the first engine component and the second engine component to the third block controller component of the second quantum computing resource.

18. 1. A computer program product that facilitates mapping conditional execution logic to a quantum computing resource, the computer program product comprising program instructions executable by a processor, the program instructions causing the processor to: Mapping a logical reference to the qubit data structure in the instruction to a first engine component; deploying the first engine component on a first block controller component operably connected to a first quantum computing resource, the first engine component controlling the first quantum computing resource based on the instructions; transmitting a resultant value received from a first qubit of the first quantum computing resource to a second block controller component of the first quantum computing resource, the first qubit being operably connected to the first block controller component and the second block controller component being operably connected to a second qubit; A computer program that performs the following:

19. The computer program of claim 18, wherein the first engine component controls the first quantum computing resource further based on the first quantum bit.

20. 20. The computer program product of claim 19, wherein the first engine component is further configured to conditionally control the first quantum computing resource based on a value of the first quantum bit.

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