Differential amplifier, semiconductor device, and offset cancellation method

Abstract

To accelerate data reading speed while suppressing influence of an offset voltage of a differential amplifier.SOLUTION: A differential amplifier includes: a current source which is connected to a first power supply, and whose supply current capacity is a first current; an active element pair which is connected to the current source, and outputs an output signal pair after amplifying a signal inputted to an input terminal pair; a load element pair whose power supply voltage is connected to a second power supply different from the first power supply, and which outputs the output signal pair to an output terminal pair; a capacitance element pair inserted between an external input terminal pair and the input terminal pair; a switching element pair for charging the capacitance element pair so that a voltage converted from the offset voltage of the input terminal pair to an input voltage is generated at the capacitance element pair, by shorting corresponding terminals between the output terminal pair and the input terminal pair; and a current control circuit for controlling the current which can be supplied from the current source is controlled to a second current larger than the first current, at the time of performing the charge.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a differential amplifier, a semiconductor device, and an offset cancellation method. [Background technology]

[0002] Data is read from a memory in a semiconductor device by converting data stored in a memory cell into a weak potential difference from a reference potential, and then differentially amplifying this potential difference using a differential amplifier (sense amplifier). Meanwhile, differential amplifiers are designed with symmetry in mind so that no offset voltage occurs, but there is manufacturing variation in the characteristics of the pair of transistors that make up the differential amplifier, and a slight offset voltage exists at the input terminal pair of the differential amplifier. The presence of this offset voltage prevents the above-mentioned potential difference from being accurately input to the differential amplifier, leading to data read errors, so it is necessary to suppress the effects of the offset voltage as much as possible.

[0003] As a means for suppressing the effect of the offset voltage of a differential amplifier, for example, a digital offset cancellation mechanism is known, as described in Patent Document 1. This digital offset cancellation mechanism holds the detection result of the offset voltage in a latch circuit, and compensates for the offset by turning on and off a compensating constant current source via the operation of the latch circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-086111 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above digital offset cancellation mechanism, in order to improve the accuracy of offset voltage compensation, it is necessary to increase the number of latch circuits and constant current sources. In this case, not only does the circuit area increase according to the number of latch circuits, etc., but the time required for offset voltage compensation at the time of product shipment becomes longer, and the test cost increases. Therefore, it is becoming difficult to meet the demand for further speedup of data readout in the market.

[0006] In view of the above circumstances, there is a demand for a technique that can increase the speed of data reading while suppressing the effect of the offset voltage of the differential amplifier. [Means for solving the problem]

[0007] A differential amplifier according to one embodiment includes a current source connected to a first power supply having a first current that can be supplied; an active element pair connected to the current source, amplifying a signal input to an input terminal pair and outputting an output signal pair; a load element pair connected to a second power supply whose power supply voltage is different from the first power supply, and outputting the output signal pair to an output terminal pair; a capacitive element pair inserted between an external input terminal pair and the input terminal pair; a switching element pair that performs an offset cancellation operation to charge the capacitive element pair so that a voltage that is converted from an offset voltage of the input terminal pair into an input voltage is generated in the capacitive element pair by shorting corresponding terminals between the output terminal pair and the input terminal pair; and a current control circuit that controls the current that can be supplied by the current source to be a second current that is larger than the first current when performing the offset cancellation operation. Effect of the Invention

[0008] According to one embodiment, it is possible to increase the speed of data reading while suppressing the effect of the offset voltage of the differential amplifier. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a semiconductor memory device. [Diagram 2] FIG. 2 shows a configuration of a sense amplifier according to a reference technology. [Diagram 3] 4 is a timing chart for a sense amplifier according to a reference technique. [Figure 4] FIG. 2 is a diagram showing a configuration of a sense amplifier according to the first embodiment. [Diagram 5] 4 is a timing chart in the sense amplifier according to the first embodiment. [Figure 6] FIG. 11 is a diagram for explaining an offset cancel operation. [Figure 7] FIG. 13 is a diagram for explaining a precharge operation. [Figure 8] FIG. 13 is a diagram for explaining a sense operation. [Figure 9] FIG. 11 is a diagram showing a configuration of a sense amplifier according to a second embodiment. [Figure 10] 11 is a timing chart in the sense amplifier according to the second embodiment. [Figure 11] FIG. 11 is a diagram showing a configuration of a sense amplifier according to a third embodiment. [Figure 12] FIG. 13 is a diagram showing the relationship between the discharge time and the sense amplifier input voltage difference. [Figure 13] FIG. 11 is a diagram showing the operation time of a sense amplifier. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] From now on, the embodiments will be described. Note that each embodiment described below is an example for realizing the present invention, and does not limit the technical scope of the present invention. In addition, in each embodiment described below, components having the same function are given the same reference numerals, and repeated description thereof will be omitted unless particularly necessary.

[0011] The scope of application of the present application is not limited to a specific semiconductor device, but can be applied to various semiconductor devices that use a sense amplifier (differential amplifier) ​​to read data. Here, as an example, a case where the present application is applied to a semiconductor memory device will be described.

[0012] (Configuration of Semiconductor Memory Device) The configuration of the semiconductor memory device will be described.

[0013] 1 is a diagram showing a schematic configuration of a semiconductor memory device 1. As shown in FIG. 1, the semiconductor memory device 1 includes a memory array 2, a plurality of amplifier blocks 3, an address decoder 4, a word line driver 5, and a timing controller 6.

[0014] The memory array 2 is a group of memory cells in which many memory cells MC11 to MCnm are arranged in a two-dimensional matrix. One bit line pair is connected to the memory cells arranged in one column. Also, one word line is connected to the memory cells arranged in one row. A memory cell from which data is to be read is specified by selecting the bit line pair of that memory cell and then selecting the word line of that memory cell. The memory array 2 is managed by dividing it into multiple memory blocks. A memory block is a collection of multiple memory cells arranged in a certain number of columns.

[0015] There are a plurality of amplifier blocks 3, and each amplifier block 3 is responsible for one memory block. Each amplifier block 3 has a column decoder 7, a sense amplifier 8, and a reference signal generator 9.

[0016] The address decoder 4 is connected to the column decoder 7 and the word line driver 5, and controls the column decoder 7 and the word line driver 5 in order to select a target memory cell from which data is to be read.

[0017] The column decoder 7 is connected to a plurality of bit lines. Under the control of the address decoder 4, the column decoder 7 selects a bit line connected to a target memory cell from among the plurality of bit lines.

[0018] The word line driver 5 is connected to a plurality of word lines. The word line driver 5 selects a word line connected to a target memory cell from among the plurality of word lines under the control of the address decoder 4. When reading data from a target memory cell, the word line driver 5 activates the selected word line and connects the bit line of the target memory cell selected by the column decoder 7 to the data input path DIN1 of the sense amplifier 8.

[0019] The reference signal generator 9 has a reference signal line REF and outputs a reference voltage Vref to the reference signal line REF. The reference voltage Vref is used to generate a reference current signal to be compared with a current signal read from a bit line BL of a target memory cell when reading data stored in the target memory cell. The reference signal line REF is connected to a data input path DIN2 of the sense amplifier 8.

[0020] The timing controller 6 is connected to the sense amplifier 8. The timing controller 6 outputs a signal group MSr for operating the sense amplifier 8 to the sense amplifier 8. The timing controller 6 outputs each signal constituting the signal group MSr at a voltage corresponding to an "H (high)" level, an "L (low)" level, or a level between "H" and "L", and controls the switching timing of these outputs.

[0021] The sense amplifier 8 has a built-in differential amplifier circuit (not shown in FIG. 1). The sense amplifier 8 is connected to a column decoder (also called a column selector) 7 and also to a reference signal generator 9. A bit line BL connected to a target memory cell selected by the column decoder 7 is connected to a data input path DIN1 of the differential amplifier circuit. A reference signal line REF of the reference signal generator 9 is connected to a data input path DIN2 of the differential amplifier circuit. The sense amplifier 8 is also connected to a timing controller 6. The sense amplifier 8 receives control from the timing controller 6 regarding the timing and level of a signal group MSr required for operating the sense amplifier 8.

[0022] (Reference technology) A sense amplifier according to a reference technology will be described below. This sense amplifier according to the reference technology is a sense amplifier that serves as a reference (base) or comparative example for the configurations of the embodiments described below.

[0023] Reference Technology Sense Amplifier Construction FIG. 2 is a diagram showing the configuration of a sense amplifier according to the reference technology. The sense amplifier 8A shown in FIG. 2 is a CMOS current mirror type differential sense amplifier. The sense amplifier 8A is an example of a sense amplifier in which a capacitive element, i.e., a capacitor, which holds a voltage that compensates for the offset voltage, is provided at the input stage. The offset voltage is a voltage that occurs due to the difference in characteristics of a pair of transistors connected to the input stage of the sense amplifier. In this embodiment, the offset voltage refers to the difference voltage between the gate threshold voltage required for one of the pair of transistors to be "on" and the gate threshold voltage required for the other of the pair of transistors to be "on."

[0024] 2, the sense amplifier 8A includes PMOS transistors 11 to 16, NMOS transistors 17 to 18, capacitors 19 and 20, switches 21 to 22, and a differential amplifier 23. A power supply VDD1 is connected to the sense amplifier 8A. In FIG. 2, characteristic current flows are indicated by dashed arrows.

[0025] In this specification, power supply VDDn (n=integer) refers to a power supply whose voltage is VDDn, and power supply VCCn (n=integer) refers to a power supply whose voltage is VCCn. In each embodiment, voltage VDDn=voltage VDD, and voltage VCCn=voltage VCC. Power supply VSS has a power supply voltage lower than power supply VDDn, for example, the ground voltage of a sense amplifier.

[0026] The PMOS transistors 11 and 13 and the NMOS transistor 17 are connected in series between the path of the power supply VDD1 and the path of the power supply VSS. The PMOS transistors 12 and 14 and the NMOS transistor 18 are connected in series between the path of the power supply VDD1 and the path of the power supply VSS. The power supply voltage of the power supply VSS is generally lower than the power supply voltage of the power supply VDD1, and is, for example, the ground voltage of the sense amplifier 8A.

[0027] The PMOS transistors 11 and 12 form a pair of transistors on the P-channel side of the sense amplifier 8A, and the NMOS transistors 17 and 18 form a pair of transistors on the N-channel side of the sense amplifier 8A.

[0028] The gates of the PMOS transistors 13 and 14 both receive a signal SAEN. When the signal SAEN is at "H" level, the PMOS transistors 13 and 14 are turned "off", and the circuit above the PMOS transistors 13 and 14 in terms of operating voltage (hereinafter sometimes simply referred to as "above") and the circuit below the PMOS transistors 13 and 14 in terms of operating voltage (hereinafter sometimes simply referred to as "below") are disconnected. In other words, these circuits stop operating as a differential amplifier. Conversely, when the signal SAEN is at "L" level, the PMOS transistors 13 and 14 are turned "on", and the circuit above the PMOS transistors 13 and 14 and the circuit below the PMOS transistors 13 and 14 are connected. In other words, these circuits function as a differential amplifier.

[0029] The gate of the NMOS transistor 17 and the gate of the NMOS transistor 18 are connected to a common node. Here, this connection point is referred to as a node NG0. The gate and source of the NMOS transistor 17 are connected to each other. As a result, the NMOS transistors 17 and 18 form a current mirror configuration.

[0030] The sources of the PMOS transistors 11 and 12 are connected to a common node. This connection point is referred to as node COM. A path of the power supply VDD1 is connected to node COM via a tail current source TCS. The tail current source TCS has a limit to the amount of current it can pass, and the maximum current is the tail current Ibias.

[0031] The capacitor 19 is connected between the data input path DIN1 to which the bit line BL is connected and the gate of the PMOS transistor 11. The PMOS transistor 15 is connected between the path of a power supply VDD2 (an example of a "fifth power supply" in this application) and the data input path DIN1 connected to the bit line BL, and its gate receives a signal OCEN. The capacitor 20 is connected between the data input path DIN2 to which a reference signal line REF is connected and the gate of the PMOS transistor 12. The PMOS transistor 16 is connected between the path of the power supply VDD2 and the data input path DIN2 connected to the reference signal line REF, and its gate receives a signal OCEN.

[0032] The node OT1 is a node that connects the PMOS transistor 13 and the NMOS transistor 17. The node OT2 is a node that connects the PMOS transistor 14 and the NMOS transistor 18.

[0033] The switch 21 is connected between a node PG1 connected to the gate of the PMOS transistor 11 and a node OT1, and has an enable terminal that receives a signal OSEN. The switch 22 is connected between a node PG2 connected to the gate of the PMOS transistor 12 and a node OT2, and has an enable terminal that receives the signal OSEN. The switches 21 and 22 are "on" or conductive when the signal OSEN received by their enable terminals is at an "L" level.

[0034] One input terminal of the differential amplifier 23 is connected to a node OT1 between the PMOS transistor 13 and the NMOS transistor 17. The other input terminal of the differential amplifier 23 is connected to a node OT2 between the PMOS transistor 14 and the NMOS transistor 18. The enable terminal of the differential amplifier 23 receives a signal SAE2. The differential amplifier 23 outputs an output signal to the output terminal OUT when the signal SAE2 received by the enable terminal is at an “H” level.

[0035] The PMOS transistor 15 is connected between the path of the power supply VDD2 and the data input path DIN1, and its gate receives a signal OCEN. Similarly, the PMOS transistor 16 is connected between the path of the power supply VDD2 and the data input path DIN2, and its gate receives a signal OCEN. When the signal OCEN becomes "L" level, the PMOS transistors 15 and 16 are turned "on", and the data input paths DIN1 and DIN2 are precharged to the potential of the power supply VDD2 and initialized.

[0036] Sense Amplifier Operation According to Reference Technology The operation of the sense amplifier 8A according to the reference technique will now be described.

[0037] 3 is a timing chart of a sense amplifier based on the reference technology. The timing chart shows the time changes in the levels of the main signals received by the sense amplifier and the time changes in the potentials of the main terminals, nodes, or paths in the sense amplifier.

[0038] The operation of the sense amplifier 8A according to the reference technology can be divided into an offset cancel operation, a precharge operation, and a sense operation. The sense operation includes a part or all of the discharge operation. The operation period of the sense amplifier 8A can be divided into an offset cancel operation period Phase-OC, a precharge operation period Phase-PC, and a sense operation period Phase-SA. However, the offset cancel operation and the precharge operation are performed in parallel in part or in whole. Therefore, the offset cancel operation period Phase-OC and the precharge operation period Phase-PC overlap in part or in whole. In addition, the states of the sense amplifier 8A can be divided into a standby state, an offset cancel operation state, a precharge operation state, and a sense operation state.

[0039] The offset cancel operation is an operation of preparing in advance so that the offset voltage of the sense amplifier 8A is cancelled during the sense operation of the sense amplifier 8A. Specifically, it is an operation of charging the capacitors 19, 20 so that the voltage obtained by converting the offset voltage of the sense amplifier 8A into the input voltage of the data input paths DIN1, DIN2 is stored in the capacitors 19, 20 as a voltage difference. The precharge operation is a preparation operation before the sense operation, and is an operation of charging the bit line BL and the reference signal line REF connected to the data input paths DIN1, DIN2 so that the data input paths DIN1, DIN2 become a predetermined voltage. The sense operation is an operation of comparing weak signals input to the data input paths DIN1, DIN2 with each other, amplifying the difference, and outputting it as a data value that can be read by an analog circuit.

[0040] First, the offset operation in the offset cancel operation period Phase-OC will be described.

[0041] 3, at time t1, the sense amplifier 8A is in a standby state before entering an offset operation. At time t1, the signals SAEN and OCEN are both at the “H” level. Also, the signal SAE2 is at the “L” level.

[0042] At time t1, since the signal SAEN is at "H" level, the potential of the gates of the PMOS transistors 13 and 14 is at "H" level, and the PMOS transistors 13 and 14 are "off". This separates the circuit below the PMOS transistors 13 and 14 from the circuit above, making it possible to reduce unnecessary current consumption. Furthermore, since the signal OCEN is at "H" level, the switches 21 and 22 are "off". Therefore, the nodes PG1 and PG2 are in a floating state. Furthermore, the PMOS transistors 15 and 16 are "off", and the operation of precharging the data input paths DIN1 and DIN2 to the power supply VDD1 has not yet been performed.

[0043] At time t2, the signals SAEN and OCEN each switch from the "H" level to the "L" level, and the signal SAE2 maintains the "L" level. At this timing t2, the sense amplifier 8A starts the offset cancel operation and the precharge operation.

[0044] At time t2, the signal SAEN is at the "L" level, so that the potentials of the gates of the PMOS transistors 13 and 14 are at the "L" level, turning the PMOS transistors 13 and 14 "on." This connects the circuits above and below the PMOS transistors 13 and 14.

[0045] A current can be supplied from the path of the power supply VDD1 to the node COM, which is the common source of the PMOS transistors 11 and 12. In addition, since the signal OCEN is at the "L" level, the switches 21 and 22 are "ON". That is, a current flows from the node COM through the PMOS transistor 11, the PMOS transistor 13, the node OT1, the switch 21, and the node PG1 to the capacitor 19, and charging of the capacitor 19 begins. In addition, a current flows from the node COM through the PMOS transistor 12, the PMOS transistor 14, the node OT2, the switch 22, and the node PG2 to the capacitor 20, and charging of the capacitor 20 begins. That is, the offset cancellation operation begins.

[0046] The NMOS transistors 17 and 18 form a current mirror configuration and function as a pair of load elements for allowing a pair of output signals, which are the differential amplification of the pair of input signals on the data input paths DIN1 and DIN2, to appear at nodes OT1 and OT2.

[0047] As a result, the capacitors 19 and 20 are charged so that the voltage Vos, which is the offset voltage of the sense amplifier 8A converted into the input voltage to the data input paths DIN1 and DIN2, appears as a difference between the terminal voltage of the capacitor 19 and the terminal voltage of the capacitor 20. At this time, the only path for supplying current to the node COM is the path from the power supply VDD1. The amount of current that the tail current source TCS from the power supply VDD1 can supply is generally small, and in this embodiment, it is limited to a maximum of the tail current Ibias×100%. Accordingly, the charging current to the capacitors 19 and 20 is also limited, and the offset cancellation time tOC required for the offset cancellation operation tends to be relatively long.

[0048] At time t2, the signal OCEN is at the "L" level, so that the PMOS transistors 15 and 16 are turned "on" and a precharge operation from the power supply VDD2 to the data input paths DIN1 and DIN2 (the external input terminal pair of the bit line BL and the reference signal line REF) is started. The potential of the data input paths DIN1 and DIN2 gradually increases from time t2, and reaches the power supply voltage VDD of the power supply VDD2 at time t3 after the elapse of the precharge time tPC required for precharging the data input paths DIN1 and DIN2.

[0049] Therefore, during the offset cancel operation period Phase-OC, not only the offset cancel operation but also the precharge operation of the data input paths DIN1 and DIN2 is performed in parallel.

[0050] The offset cancel operation is completed at time t4, which can be roughly estimated based on, for example, the capacitances of the capacitors 19 and 20, the amount of current supplied from the node COM, and the resistance components of the conduction path.

[0051] Next, the sense operation in the sense operation period Phase-SA will be described. Time t5 is set as the time after a predetermined small time has elapsed from time t4. At time t5, the signal OCEN switches from the "L" level to the "H" level, and the signal SAEN maintains the "L" level. As a result, the sense amplifier 8A switches from the offset cancel operation to the sense operation.

[0052] At time t5, the signal OCEN goes to the "H" level, turning the PMOS transistors 15 and 16 "off." This cuts off the path from the power supply VDD2, i.e., the path used to precharge the data input paths DIN1 and DIN2. Also, at time t5, the signal OCEN is at the "H" level, so the switches 21 and 22 are also turned "off." This cuts off the path from the power supply VDD1 to charge the capacitors 19 and 20.

[0053] When the sense operation starts, the charges precharged in the data input paths DIN1 and DIN2 are gradually discharged according to the read data, and the potentials of the data input paths DIN1 and DIN2 decrease accordingly. The potentials of the nodes PG1 and PG2 also decrease due to the effect of coupling with the capacitors 19 and 20.

[0054] Time t6 is set to the time when a discharge time tDC, which is considered necessary for an accurate signal to be output to the output terminal OUT of the differential amplifier 23, has elapsed from time t5. At time t6, the signal SAE2 switches from the "L" level to the "H" level, and the signal OCEN maintains the "H" level. This activates the differential amplifier 23. As a result, the differential amplifier 23 outputs a voltage obtained by differentially amplifying the potential difference between the data input paths DIN1 and DIN2 to the output terminal OUT. That is, a potential corresponding to the data of the memory cell at the selected address appears at the output terminal OUT of the differential amplifier 23.

[0055] Time t7 is set as the time when a predetermined minute time required for the output of the output terminal OUT to be determined has elapsed from time t6. At time t7, the signal SAEN switches from "L" level to "H" level, and the signal SAE2 switches from "H" level to "L" level. As a result, the gate potential of the PMOS transistors 13 and 14 becomes "H" level, and the PMOS transistors 13 and 14 are turned "off". In addition, the potential of the enable terminal of the differential amplifier 23 becomes "L" level, and the differential amplifier 23 is inactivated. At this time, the output terminal OUT of the differential amplifier 23 is in a state where an accurate signal is output, and it becomes possible to read the signal of the output terminal OUT, that is, to read the data of the selected memory cell. After time t7, the sense amplifier 8A enters a standby state again and prepares for the next data read operation.

[0056] Time t8 is a time after a certain time has elapsed from time t7. At time t8, the data input paths DIN1 and DIN2 and the nodes PG1 and PG2 are reset.

[0057] In this sense amplifier 8A, the capacitors 19 and 20 are charged with a tail current Ibias from a tail current source TCS from a power supply VDD1 so that a voltage Vos obtained by converting the offset voltage of the sense amplifier 8A into an input voltage appears as a differential voltage. After that, in a state in which the offset voltage of the sense amplifier 8A is cancelled by the capacitors 19 and 20, the signal of the bit line BL and the signal of the reference signal line REF input to the data input paths DIN1 and DIN2 are differentially amplified, thereby realizing a sense operation.

[0058] In addition, in order to compensate for the offset voltage of the sense amplifier, capacitors 19 and 20 whose charging voltage is continuously variable are provided, so that the accuracy of offset cancellation is high. Furthermore, due to the above-mentioned sensing operation, a differentially amplified signal between the signal of the bit line BL and the signal of the reference signal line REF appears at nodes OT1 and OT2, and the signals at nodes OT1 and OT2 are further differentially amplified by the differential amplifier 23 and output. Therefore, the comparison resolution of the signals input to the data input paths DIN1 and DIN2 is high.

[0059] However, it is generally difficult to increase the amount of current supplied from the power supply VDD1 in terms of operating current and amplification sensitivity, and the amount of tail current Ibias is limited. Therefore, the offset cancellation time tOC, which is the time it takes for the capacitors 19 and 20 to be charged, tends to be relatively long, and it takes a long time to read data.

[0060] (Embodiment 1) A sense amplifier according to the first embodiment will be described. The sense amplifier according to the first embodiment is an improved example of the sense amplifier according to the reference technology. As described above, the reference technology has the advantages of high accuracy of offset cancellation and high comparative resolution of signals input to the data input paths DIN1 and DIN2. On the other hand, in the configuration of the reference technology, the amount of current supplied from the path of the power supply VDD1 generally cannot be made large, and the amount of current of the tail current Ibias is limited. Therefore, the offset cancellation time tOC, which is the time until the capacitors 19 and 20 are charged, tends to be relatively long, and it takes time to read data. In view of such circumstances, the present inventors have created the configuration of the sense amplifier described below. The sense amplifier according to the first embodiment is configured to improve the charging ability of the capacitor, shorten the offset cancellation time tOC so that the offset cancellation time tOC is equal to or less than the precharge time tPC, and realize a shortening of the overall operating time of the sense amplifier.

[0061] Configuration of the Sense Amplifier According to the First Embodiment 4 is a diagram showing a configuration of a sense amplifier according to embodiment 1. The sense amplifier according to embodiment 1 is an example of the following "differential amplifier" in this application.

[0062] The differential amplifier includes a current source (CS) connected to a first power supply (VDD1) having a first current (Ibias) that can be supplied, a pair of active elements (PMOS transistors 11, 12) that are connected to the current source and that amplify a signal input to a pair of input terminals (PG1, PG2) and output a pair of output signals, a pair of load elements (NMOS transistors 17, 18) that are connected to a second power supply (VSS) whose power supply voltage is different from that of the first power supply and that output the pair of output signals to a pair of output terminals (OT1, OT2), and a pair of capacitive elements (capacitors 19, a switching element pair (switches 21, 22) that performs an offset cancellation operation of charging the pair of capacitance elements so that a voltage (Vos) obtained by converting the offset voltage of the input terminal pair into an input voltage is generated in the pair of capacitance elements by shorting corresponding terminals between the output terminal pair and the input terminal pair; and a current control circuit (PMOS transistor 38) that controls the current that can be supplied from the current source to a second current (the supplyable current of VDD1+the supplyable current of VDD3) that is larger than the first current when the offset cancellation operation is performed.

[0063] The differential amplifier also includes a precharge circuit (PMOS transistors 15 and 16) that connects a fifth power supply (VDD2) to the external input terminal pair and precharges the external input terminal pair to the potential of the fifth power supply, and while the precharge operation is being performed by the precharge circuit (PMOS transistors 15 and 16 are on), the offset cancellation operation is performed (PMOS transistor 38, switches 21 and 22, and NMOS transistor 36 are turned on), and then the offset cancellation operation is stopped (PMOS transistor 38, switches 21 and 22, PMOS transistors 15 and 16, and NMOS transistor 36 are turned off), and after the offset cancellation operation is stopped, the precharge operation is stopped (PMOS transistors 15 and 16 are turned off), a discharge operation of the external input terminal pair is started, and an operation of reading an output based on the output signal pair is enabled to be started.

[0064] The sense amplifier 8B shown in Fig. 4 is a sense amplifier configured to reduce the offset cancellation time tOC, which is the time it takes for the capacitors 19 and 20 to be charged, compared to the sense amplifier 8A according to the reference technology. Compared to the sense amplifier 8A, the sense amplifier 8B further includes NMOS transistors 31-36, PMOS transistors 38 and 39, a power supply VDD3 (an example of the "third power supply" in this application), and an inverter (inverting logic circuit) 25. Note that in Fig. 4, the characteristic current flow is indicated by dashed arrows on the configuration diagram of the sense amplifier 8B.

[0065] The NMOS transistor 31 is connected between the node PG1 and the path of the power supply VSS, and its gate receives a signal SAEN. The NMOS transistor 32 is connected between the node PG2 and the path of the power supply VSS, and its gate receives a signal SAEN. When the signal SAEN is at the "H" level, the NMOS transistors 31 and 32 (an example of an "initialization circuit" in this application) are "on", i.e., conductive, and the potentials of the nodes PG1 and PG2 become the level of the potential of the power supply VSS (an example of a "second power supply" in this application), and are initialized. The power supply voltage of the power supply VSS is generally lower than the power supply voltage of the power supply VDD1, and is, for example, the ground voltage of the sense amplifier 8B.

[0066] The PMOS transistor 37 is connected between the path of the power supply VDD1 (an example of the "first power supply" in this application) and the node COM serving as the current source CS (an example of the "current source" in this application), and its gate receives a signal BIAS. When the signal BIAS is at the "L" level, the PMOS transistor 37 is "on", i.e., conductive, and the power supply VDD1 is connected to the node COM. The PMOS transistor 38 is connected between the node COM and a power supply VDD3 different from the power supply VDD1, and its gate receives a signal OCEN. When the signal OCEN is at the "L" level, the PMOS transistor 38 is "on", i.e., conductive, and the power supply VDD3 is connected to the node COM. In other words, when the signal BIAS is at the "L" level and the signal OCEN is at the "L" level, the path for supplying current to the node COM includes not only the path from the power supply VDD1 but also the path from the power supply VDD3.

[0067] In this embodiment, the current from the path of the power supply VDD1 is limited to a maximum of the tail current Ibias×100% by setting the signal BIAS to a potential between the "H" level and the "L" level. On the other hand, the power supply VDD3 can pass a current larger than that of the power supply VDD1. The power supply VDD3 has the same power supply voltage as the power supply VDD1, for example, and can pass a current of the tail current Ibias×300% or more.

[0068] A PMOS transistor 39 and a parallel circuit of NMOS transistors 33 and 34 (an example of a "pair of elements through which a current flows" in this application) are connected in series between the path of the power supply VDD1 and the path of the power supply VSS. The gate of the PMOS transistor 39 receives a signal BIAS. The gates of the NMOS transistors 33 and 34 are connected to a node AB1 which is a connection point between the PMOS transistor 39 and the parallel circuit of the NMOS transistors 33 and 34.

[0069] When the signal BIAS switches from the "H" level to a level between "H" and "L", the PMOS transistor 39 and the parallel circuit of the NMOS transistors 33 and 34 are turned "on". As a result, current starts to flow from the power supply VDD1 to the PMOS transistor 39 and the parallel circuit of the NMOS transistors 33 and 34, and the node AB1 maintains a constant potential so that the saturated tail current Ibias flows.

[0070] When the signal BIAS switches from a level between "H" and "L" to the "H" level, the PMOS transistor 39 and the parallel circuit of the NMOS transistors 33 and 34 are turned "off." This causes the current flowing through the PMOS transistor 39 and the parallel circuit of the NMOS transistors 33 and 34 to decrease and eventually reach zero.

[0071] The connection point between the gate of the NMOS transistor 17 and the gate of the NMOS transistor 18 is the node NG0. The NMOS transistor 35 is connected between the node OT1 and the node NG0, and its gate receives the signal SAE1. The NMOS transistor 36 is connected between the node NG0 and the node AB1, and its gate receives the signal obtained by inverting the signal SAE1 by the inverter 25. When the signal SAE1 becomes the "H" level, the NMOS transistor 35 is turned "on" and the NMOS transistor 36 is turned "off", so that the node NG0 and the node OT1 are connected. As a result, the NMOS transistors 17 and 18, which are a pair of N-channel transistors, form a current mirror circuit.

[0072] On the other hand, when the signal SAE1 goes to the "L" level, the NMOS transistor 35 is turned "off" and the NMOS transistor 36 is turned "on", connecting the node NG0 to the node AB1. As a result, the NMOS transistors 17 and 18, together with the parallel circuit of the NMOS transistors 33 and 34, form a current mirror circuit.

[0073] In this way, the NMOS transistors 35, 36 and the inverter 25 constitute a load control circuit (an example of the “load control circuit” in this application) that switches the configuration of the current mirror circuit of the NMOS transistors 17, 18 by switching the connection destination of the gates of the NMOS transistors 17, 18, which are a load element pair, as necessary.

[0074] <Operation of the Sense Amplifier According to the First Embodiment> The operation of the sense amplifier 8B according to the first embodiment will be described. FIG. 5 is a timing chart in the sense amplifier according to the first embodiment.

[0075] The operation of the sense amplifier 8B according to the first embodiment can be divided into an offset cancel operation, a precharge operation, and a sense operation. The sense operation includes a part or all of the discharge operation. The operation period of the sense amplifier 8B can be divided into an offset cancel operation period Phase-OC, a precharge operation period Phase-PC, and a sense operation period Phase-SA. However, the offset cancel operation and the precharge operation are performed in parallel in part or in whole. Therefore, the offset cancel operation period Phase-OC and the precharge operation period Phase-PC overlap in part or in whole.

[0076] The states of the sense amplifier 8B can be divided into a standby state, an offset cancel operation state, a precharge operation state, and a sense operation state. The states of the sense amplifier 8B are switched in the following order: standby state, offset cancel operation state (precharge operation state), sense operation state, and standby state. Switching between these states is controlled by the switching timing of "H" and "L" of each signal output from a timing controller 6 (an example of a "state control circuit" in this application).

[0077] The offset cancel operation is an operation of preparing in advance so that the offset voltage of the sense amplifier 8B is cancelled during the sense operation of the sense amplifier 8B. Specifically, it is an operation of charging the capacitors 19, 20 so that the voltage obtained by converting the offset voltage of the sense amplifier 8B into the input voltage of the data input paths DIN1, DIN2 is stored in the capacitors 19, 20 as a voltage difference. The precharge operation is a preparation operation before the sense operation, and is an operation of charging the data input paths DIN1, DIN2 so that these paths become a predetermined voltage. The sense operation is an operation of comparing weak signals input to the data input paths DIN1, DIN2 with each other, amplifying the difference, and outputting it as a data value that can be read by an analog circuit.

[0078] First, the offset cancel operation in the offset cancel operation period Phase-OC will be described.

[0079] As shown in Fig. 5, time t1 is the standby state time before entering the offset cancel operation. At time t1, the signals SAEN and OCEN are both at "H" level, and the signals SAE1 and SAE2 are both at "L" level. The signal BIAS maintains a level between "H" and "L" during the period in which data read is repeated.

[0080] At time t1, since the signal SAEN is at the "H" level, the potential of the gates of the PMOS transistors 13 and 14 is at the "H" level, and the PMOS transistors 13 and 14 are "off". When the PMOS transistors 13 and 14 are "off" and not conducting, the circuit below the PMOS transistors 13 and 14 is disconnected, and unnecessary current consumption can be reduced. Since the signal SAEN is at the "H" level, the potential of the gates of the NMOS transistors 31 and 32 is at the "H" level, and the NMOS transistors 31 and 32 are "on". Since the signal OCEN is at the "H" level, the switches 21 and 22 are "off". Therefore, the potentials of the nodes PG1 and PG2 are at the level of the potential of the power supply VSS, and are in an initialized state. Since the signal OCEN is at the "H" level, the PMOS transistors 15 and 16 are "off", and the operation of precharging the data input paths DIN1 and DIN2 to the power supply voltage VDD of the power supply VDD2 is not performed.

[0081] Here, the potentials of the nodes PG1 and PG2 are initialized to the potential level of the power supply VSS, so that the PMOS transistors 11 and 12 are "on," and when the offset cancellation operation starts, the current flow through the PMOS transistors 11 and 12 is not hindered.

[0082] At time t2, the signals SAE1 and SAE2 each maintain the "L" level, but the signals SAEN and OCEN each switch from the "H" level to the "L" level, causing the sense amplifier 8B to enter an offset cancel operation and a precharge operation.

[0083] FIG. 6 is a diagram for explaining the offset cancel operation. In FIG. 6, the characteristic current flow is indicated by a dashed arrow on the configuration diagram of the sense amplifier 8B. Since the signal SAEN is at the "L" level at time t2, the potential of the gates of the NMOS transistors 31 and 32 becomes "L" level, and the NMOS transistors 31 and 32 become "OFF". The potential of the gates of the PMOS transistors 13 and 14 becomes "L" level, and the PMOS transistors 13 and 14 become "ON". Since the signal SAE1 is at the "L" level, the potential of the gate of the NMOS transistor 35 is at the "L" level, and the NMOS transistor 35 becomes "OFF". On the other hand, the potential of the gate of the NMOS transistor 36 is at the "H" level, and the NMOS transistor 36 becomes "ON". In other words, the node NG0 becomes connected to the node AB1.

[0084] Furthermore, since the signal BIAS is at a level between "H" and "L", the PMOS transistor 39 and the parallel circuit of the NMOS transistors 33 and 34 are "ON". A current starts to flow from the power supply VDD1, and at time tA, the node AB1, i.e., the node NG0, maintains a constant potential such that a saturated current Ibias flows.

[0085] Furthermore, since the signal OCEN is at the "L" level, the switches 21 and 22 are turned "ON." That is, a current flows from the node COM, which is the common source of the PMOS transistors 11 and 12, to the node PG1 via the PMOS transistor 11 and the switch 21, and the capacitor 19 is charged. Also, a current flows from the node COM to the node PG2 via the PMOS transistor 12 and the switch 22, and the capacitor 20 is charged.

[0086] When the capacitors 19 and 20 are charged as described above, the capacitors 19 and 20 are charged so that the voltage Vos obtained by converting the offset voltage of the sense amplifier 8B into an input voltage appears as a difference between the terminal voltage of the capacitor 19 and the terminal voltage of the capacitor 20. At this time, the path for supplying current to the node COM includes not only the path from the power supply VDD1 through the PMOS transistor 37, but also the path from the power supply VDD3 through the PMOS transistor 38. Therefore, the charging current to the capacitors 19 and 20 becomes large, charging is performed at a higher speed, and the offset cancellation time tOC required for offset cancellation can be shortened.

[0087] At this time, the potentials of the nodes PG1 and PG2 are initialized to the potential level of the power supply VSS. Therefore, when the offset cancel operation starts after this, there is an effect of not hindering the current flow through the PMOS transistors 11 and 12. In other words, this operation contributes to further shortening the offset cancel time tOC.

[0088] Furthermore, the NMOS transistors 17 and 18 form a current mirror circuit together with the parallel circuit of the NMOS transistors 33 and 34. This configuration serves to match the operating points of the NMOS transistors 17 and 18 in the sense operation period following the offset cancel operation period. The sum of the currents flowing through the NMOS transistors 17 and 18 is set to be equivalent to the tail current Ibias from the power supply VDD1 (for example, 50% to 150% of Ibias).

[0089] With such settings, it is possible to equally control the current flowing through the PMOS transistors 11 and 12 when the offset cancel operation is completed at time t3 and the current flowing through the PMOS transistors 11 and 12 when the sense operation is completed. By equally controlling the current flowing through the PMOS transistors 11 and 12 when the offset cancel operation is completed and the current flowing through the PMOS transistors 11 and 12 when the sense operation is completed, it is possible to perform offset cancellation with high precision.

[0090] The mirror ratio of this current mirror is set so that 50% of the tail current Ibias flows through each of the NMOS transistors 17 and 18. In this embodiment, the transistor sizes of the pair of transistors are set so that 50% of the tail current Ibias flows through each of the NMOS transistors 17 and 18.

[0091] 7 is a diagram for explaining the precharge operation, in which dashed arrows indicate characteristic current flows on a configuration diagram of the sense amplifier 8B.

[0092] The PMOS transistors 15 and 16 are turned “on”, and the data input paths DIN1 and DIN2 are precharged from the power supply VDD1. The potential of the data input paths DIN1 and DIN2 gradually rises from time t2 and reaches the power supply voltage VDD of the power supply VDD2 at time t3 after the precharge time tPC has elapsed.

[0093] Therefore, during the offset cancel operation period, not only the offset cancel operation but also the precharge operation of the data input paths DIN1, DIN2 and the operation of matching the operating points of the NMOS transistors 17, 18 during the sense operation period are performed in parallel. Also, the current flowing through the capacitors 19, 20 due to the offset cancel operation also flows through the data input paths DIN1, DIN2 via the capacitors 19, 20. Therefore, the offset cancel operation supports the precharge operation, and the precharge time tPC required for precharge is further shortened. In this way, the sense amplifier 8B performs a very efficient operation.

[0094] Next, the sense operation in the sense operation period Phase-SA will be described. As shown in Fig. 5, at time t4, the signals OCEN and SAE1 each switch from the "L" level to the "H" level, the signals SAEN and SAE2 each maintain the "L" level, and the signal BIAS maintains a level between "H" and "L". Depending on the levels of these signals, the sense amplifier 8B switches from the offset cancel operation to the sense operation.

[0095] The timing of time t4 is set to the time when the precharge time tPC required for completing the precharge of the data input path DIN1 (bit line BL) and DIN2 (reference signal line REF) has elapsed from time t2. The time required for offset cancellation, that is, the offset cancellation time tOC required for the charging of the capacitors 19 and 20 to be completed, can be made smaller than the precharge time tPC required for precharging (tOC≦tPC) by adjusting the amount of current through the path via the PMOS transistor 38. Therefore, the precharge time tPC is dominant in the time from the start of the offset cancellation operation to the start of the sense operation.

[0096] Fig. 8 is a diagram for explaining the sense operation. In Fig. 8, activated elements are marked with a circle (○) and inactivated elements are marked with a cross (×) on the configuration diagram of the sense amplifier 8B, and characteristic current flows are indicated by dashed arrows.

[0097] At time t4 (time t5), the signal OCEN goes to the "H" level, so that the PMOS transistors 15 and 16 are turned "off" as shown in FIG. 8, and the path from the power supply VDD2 to the data input paths DIN1 and DIN2 is cut off. In addition, the PMOS transistor 38 is turned "off", and the path from the power supply VDD3 to the node COM, which is the current supply source, is cut off. As a result, the current supply to the node COM, which is the current source CS, is only the tail current Ibias from the power supply VDD1 through the PMOS transistor 37 by the tail current source TCS. In addition, the switches 21 and 22 are also turned "off". With this connection configuration, the path for charging the capacitors 19 and 20 from the power supply VDD3 is cut off.

[0098] Furthermore, when the signal SAE1 goes to the "H" level, the NMOS transistor 35 is turned "on" and the NMOS transistor 36 is turned "off", so that the NMOS transistors 17 and 18, which are a pair of N-channel transistors, form a current mirror configuration with the node OT1 as the gate potential. With the above connection configuration, the sense amplifier 8B has a circuit configuration equivalent to that of the sense amplifier 8A, which is a differential sense amplifier. With this connection configuration, a sense operation is possible in a state where the voltage Vos has already been applied during the offset cancellation operation period Phase-OC. In other words, the sense amplifier 8B is able to perform a highly accurate sense operation while ensuring the offset cancellation effect.

[0099] When the sense operation starts, the charges precharged in the data input paths DIN1 and DIN2 are gradually discharged according to the read data, and the potentials of the data input paths DIN1 and DIN2 decrease accordingly. The potentials of the nodes PG1 and PG2 also decrease due to the coupling effect with the capacitors 19 and 20.

[0100] As shown in FIG. 5, time t6 is the time after the discharge time tDC of the data input paths DIN1 and DIN2 has elapsed from time t4. At time t6, the signal SAE2 switches from the "L" level to the "H" level, the signal SAEN and the signal BIAS maintain the "L" level, and the signal OCEN and the signal SAE1 maintain the "H" level. Due to these signal levels, the enable terminal of the differential amplifier 23 becomes the "L" level, and the differential amplifier 23 is activated. As a result, the differential amplifier 23 outputs a voltage obtained by differentially amplifying the potential difference between the data input paths DIN1 and DIN2 to the output terminal OUT. That is, a potential corresponding to the memory data at the selected address appears at the output terminal OUT of the differential amplifier 23.

[0101] Time t7 is set to the time after time t6 when the time required for the output of the differential amplifier 23 to stabilize has elapsed. At time t7, the signals SAEN and BIAS switch from the "L" level to the "H" level, the signal OCEN maintains the "H" level, and the signals SAE1 and SAE2 switch from the "H" level to the "L" level. This ends the sense operation. A potential corresponding to the data of the memory cell at the selected address is determined and appears at the output terminal OUT of the differential amplifier 23. After that, data is read from the device connected to the output terminal OUT of the differential amplifier 23. After time t7, the sense amplifier 8A enters the standby state again to prepare for the next data read operation.

[0102] Time t8 is a time after a certain time has elapsed from time t7. At time t8, the data input paths DIN1 and DIN2 and the nodes PG1 and PG2 are reset.

[0103] According to such a sense amplifier 8B, the capacitors 19 and 20 are charged by a current flowing from the node COM, which is a current supply source, so that the voltage Vos obtained by converting the offset voltage of the sense amplifier 8A into an input voltage appears as a differential voltage. At this time, the node COM is supplied with a current not only from the path from the power supply VDD1 but also from the path from the power supply VDD3. That is, the amount of current that can be supplied from the node COM to the capacitors 19 and 20 can be made larger than the tail current Ibias that can be supplied by the power supply VDD1. Such an increase in the supply current allows the capacitors 19 and 20 to be charged at a higher speed, and the offset cancellation time tOC can be significantly shortened. It is preferable that the amount of current that can be supplied by the power supply VDD3 is larger than the current that can be supplied by the power supply VDD1.

[0104] The charges precharged in the data input paths DIN1 and DIN2 are gradually discharged in accordance with the read data, and the potentials of the data input paths DIN1 and DIN2 decrease accordingly. The potentials of the nodes PG1 and PG2 also decrease due to the effect of coupling with the capacitors 19 and 20.

[0105] In addition, in order to compensate for the offset voltage of the sense amplifier, capacitors 19 and 20 whose charging voltage is continuously variable are provided, so that the accuracy of offset cancellation is high. Furthermore, due to the above-mentioned sensing operation, a differentially amplified signal between the signal of the bit line BL and the signal of the reference signal line REF appears at nodes OT1 and OT2, and the signals at nodes OT1 and OT2 are further differentially amplified by the differential amplifier 23 and output. Therefore, the comparison resolution of the signals input to the data input paths DIN1 and DIN2 is high.

[0106] In this way, the sense amplifier 8B according to embodiment 1 is able to reduce the effects of the offset voltage of the sense amplifier by using an offset cancellation mechanism, while shortening the offset cancellation time tOC and also the precharge time tPC, thereby enabling faster data readout.

[0107] (Embodiment 2) A sense amplifier according to embodiment 2 will be described. The sense amplifier according to embodiment 2 is an improved example of the sense amplifier according to embodiment 1. The sense amplifier according to embodiment 2 has a configuration suitable for the case where the offset cancel time tOC is longer than the precharge time tPC. Specifically, the sense amplifier according to embodiment 2 is configured to stop the precharge operation and start the discharge operation before the offset cancel operation is completed, thereby realizing a reduction in the overall operation time of the sense amplifier.

[0108] Configuration of the Sense Amplifier According to the Second Embodiment 9 is a diagram showing a configuration of a sense amplifier according to embodiment 2. The sense amplifier according to embodiment 2 is an example of the following "differential amplifier" in this application.

[0109] The differential amplifier includes a current source (CS) connected to a first power supply (VDD1) having a first current (Ibias) that can be supplied, a pair of active elements (PMOS transistors 11, 12) that are connected to the current source and that amplify a signal input to a pair of input terminals (PG1, PG2) and output a pair of output signals, a pair of load elements (NMOS transistors 17, 18) that are connected to a second power supply (VSS) whose power supply voltage is different from that of the first power supply and that output the pair of output signals to a pair of output terminals (OT1, OT2), and a pair of capacitive elements (capacitors 19, a switching element pair (switches 21, 22) that performs an offset cancellation operation of charging the pair of capacitance elements so that a voltage (Vos) obtained by converting the offset voltage of the input terminal pair into an input voltage is generated in the pair of capacitance elements by shorting corresponding terminals between the output terminal pair and the input terminal pair; and a current control circuit (PMOS transistor 38) that controls the current that can be supplied from the current source to a second current (the supplyable current of VDD1+the supplyable current of VDD3) that is larger than the first current when the offset cancellation operation is performed.

[0110] The differential amplifier also includes a precharge circuit (PMOS transistors 15, 16, 41 to 44) that connects a fifth power supply (VDD2) to the external input terminal pair and precharges the external input terminal pair to the potential of the fifth power supply. During a period in which the precharge circuit is performing a precharge operation (PMOS transistors 15, 16, 43, 44 are on, and PMOS transistors 41, 42 are off), the differential amplifier performs the offset cancel operation (PMOS transistor 38, switches 21, 22, and NMOS transistor 36 are on, and NMOS transistor 37 is off). and turns off PMOS transistors 38, 41, 42, and NMOS transistor 35), thereby enabling the start of an operation to read an output based on the output signal pair.

[0111] The precharge circuit also includes a second switching element pair (PMOS transistors 41, 42) connected between the capacitive element pair and the external input terminal pair, a third switching element pair (PMOS transistors 15, 16) connected between a connection point pair between the capacitive element pair and the second switching element pair and the fifth power supply, and a fourth switching element pair (PMOS transistors 43, 44) connected between a connection point pair between the second switching element pair and the external input terminal pair and a sixth power supply, and stops the precharge operation and starts the discharge operation by transitioning from a state in which the second switching element pair is inactivated and the third and fourth switching element pairs are activated to a state in which the fourth switching element pair is inactivated.

[0112] 9 is a sense amplifier configured to perform part of the offset cancel operation in parallel with the discharge operation, as compared with the sense amplifier 8B according to the first embodiment. With this configuration, even if the current Ibias from the path passing through the PMOS transistor 37 cannot be made large and it is assumed that the offset cancel is completed later than the precharge, the overall operation time of the sense amplifier can be shortened. Compared with the sense amplifier 8B, the sense amplifier 8C further includes PMOS transistors 41-44 and a power supply VDD4 (an example of the "sixth power supply" in this application).

[0113] The PMOS transistor 41 is connected between the data input path DIN1 and the capacitor 19, and its gate receives the inverted signal OCE of the signal OCEN. The PMOS transistor 42 is connected between the data input path DIN2 and the capacitor 20, and its gate receives the inverted signal OCE of the signal OCEN. The node N1 is the connection point between the PMOS transistor 15 and the capacitor 19. The node N2 is the connection point between the PMOS transistor 16 and the capacitor 20. The PMOS transistor 43 is connected between the power supply VDD4 and the node DIN1, and its gate receives the signal PCEN. The PMOS transistor 44 is connected between the power supply VDD and the node DIN2, and its gate receives the signal PCEN.

[0114] When both the signals OCEN and PCEN are at the "L" level, the offset cancel operation, which is the operation of charging the capacitors 19 and 20, and the operation of precharging the path on the bit line BL side and the path on the reference signal line REF side are performed in parallel.

[0115] At a timing when it is considered that the precharge is completed, the signal PCEN is switched to the "H" level while the signal OCEN remains at the "L" level. Then, the PMOS transistors 43 and 44 are turned "off", the precharge operation is stopped, and the discharge operation of the path on the bit line BL side and the path on the reference signal line REF side is started. After that, at a timing when it is considered that the offset cancel is also completed, the signal OCEN is switched to the "H" level. This also turns "off" the PMOS transistors 15 and 16, and the offset cancel operation is also stopped.

[0116] <Operation of the Sense Amplifier According to the Second Embodiment> The operation of the sense amplifier 8C according to the second embodiment will be described.

[0117] FIG. 10 is a timing chart of the sense amplifier according to the second embodiment. The operation of the sense amplifier 8C according to the second embodiment can be divided into an offset cancel operation, a precharge operation, and a sense operation. The sense operation includes a part or all of the discharge operation. The operation period of the sense amplifier 8C can be divided into an offset cancel operation period Phase-OC, a precharge operation period Phase-PC, and a sense operation period Phase-SA. However, the offset cancel operation and the precharge operation are performed in parallel in part or in whole. Therefore, the offset cancel operation period Phase-OC and the precharge operation period Phase-PC overlap in part or in whole. The state of the sense amplifier 8C can be divided into a standby state, an offset cancel operation state, a precharge operation state, and a sense operation state.

[0118] The offset cancel operation is an operation of preparing in advance so that the offset voltage of the sense amplifier 8C is cancelled during the sense operation of the sense amplifier 8C. Specifically, it is an operation of charging the capacitors 19, 20 so that the voltage obtained by converting the offset voltage of the sense amplifier 8C into the input voltage of the data input paths DIN1, DIN2 is stored in the capacitors 19, 20 as a voltage difference. The precharge operation is a preparation operation before the sense operation, and is an operation of charging the data input paths DIN1, DIN2 so that these paths become a predetermined voltage. The sense operation is an operation of comparing weak signals input to the data input paths DIN1, DIN2 with each other, amplifying the difference, and outputting it as a data value that can be read by an analog circuit.

[0119] First, the offset cancel operation in the offset cancel operation period Phase-OC will be described.

[0120] 10, at time t1, the signals SAEN, OCEN, and PCEN are all at the “H” level, and the signals SAE1 and SAE2 are all at the “L” level. The signal BIAS maintains a level between “H” and “L” during the period in which data read is repeated.

[0121] At time t1, the signal SAEN is at the “H” level, so the potentials of the gates of the PMOS transistors 13 and 14 are at the “H” level and the PMOS transistors 13 and 14 are “off.” This separates the circuits below the PMOS transistors 13 and 14, making it possible to reduce unnecessary current consumption.

[0122] Furthermore, since the signal SAEN is at "H" level, the potentials of the gates of the NMOS transistors 31 and 32 are at "H" level, and the NMOS transistors 31 and 32 are "ON". Furthermore, since the signal OCEN is at "H" level, the switches 21 and 22 are "OFF". Therefore, the potentials of the nodes PG1 and PG2 are at the level of the potential of the power supply VSS, and are in the initialized state.

[0123] Moreover, since the signals OCEN and PCEN are at the "H" level, the PMOS transistors 15, 16, 43, and 44 are "off," and the operation of precharging the data input paths DIN1 and DIN2 from the power supplies VDD2 and VDD4 is not performed.

[0124] At time t2, the signals SAE1 and SAE2 each maintain the "L" level, but the signals SAEN, OCEN, and PCEN each switch from the "H" level to the "L" level, causing the sense amplifier 8C to enter an offset cancel operation and a precharge operation.

[0125] At time t2, since the signal SAEN is at "L" level, the potentials of the gates of the NMOS transistors 31 and 32 become "L" level, and the NMOS transistors 31 and 32 are turned "OFF". The potentials of the gates of the PMOS transistors 13 and 14 become "L" level, and the PMOS transistors 13 and 14 are turned "ON". Since the signal SAE1 is at "L" level, the potential of the gate of the NMOS transistor 35 is at "L" level, and the NMOS transistor 35 is turned "OFF". On the other hand, the potential of the gate of the NMOS transistor 36 is at "H" level, and the NMOS transistor 36 is turned "ON". In other words, the node NG0 is connected to the node AB1.

[0126] Also, since the signal BIAS is at a level between "H" and "L", the PMOS transistor 39 and the parallel circuit of the NMOS transistors 33 and 34 are turned "ON", and a current starts to flow from the path of the power supply VDD1, gradually increases, and finally a saturated tail current Ibias flows. At the same time, the potential of the node AB1, i.e., the node NG0, gradually decreases from the potential of the power supply VDD1, reaches a certain constant potential at time tA, and then maintains that potential.

[0127] Furthermore, since the signals OCEN and PCEN are both at the "L" level, the switches 21 and 22 are turned "ON." That is, a current flows from the node COM, which is the common source of the PMOS transistors 11 and 12, to the node PG1 via the PMOS transistor 11 and the switch 21, and the capacitor 19 is charged. Also, a current flows from the node COM to the node PG2 via the PMOS transistor 12 and the switch 22, and the capacitor 20 is charged.

[0128] As a result, the capacitors 19 and 20 are charged so that the voltage Vos obtained by converting the offset voltage of the sense amplifier 8C into an input voltage appears as a difference between the terminal voltage of the capacitor 19 and the terminal voltage of the capacitor 20. At this time, the path of the current supply to the node COM serving as the current source CS includes not only the path from the power supply VDD1 through the PMOS transistor 37, but also the path from the power supply VDD3 through the PMOS transistor 38. Therefore, the charging current to the capacitors 19 and 20 becomes large, charging is performed at a higher speed, and the offset cancellation time tOC required for offset cancellation can be shortened.

[0129] Furthermore, the NMOS transistors 17 and 18 form a current mirror circuit together with the parallel circuit of the NMOS transistors 33 and 34. This serves to match the operating points of the NMOS transistors 17 and 18 in the sense operation period following the offset cancel operation period.

[0130] Furthermore, the sum of the currents flowing through the NMOS transistors 17 and 18 is set to be approximately equal to the tail current Ibias from the tail current source TCS from the power supply VDD1, for example, 50% to 150% of Ibias. More preferably, the sum of the currents flowing through the NMOS transistors 17 and 18 is set to the tail current Ibias x 100%. This makes it possible to control the currents flowing through the PMOS transistors 11 and 12 to be approximately equal in both the offset cancel operation state and the sense operation state, enabling offset cancellation to be performed with high precision.

[0131] The mirror ratio of this current mirror is preferably set so that 50% of the tail current Ibias flows through each of the NMOS transistors 17 and 18. In this embodiment, the transistor sizes of the pair of transistors are set so that 50% of the tail current Ibias flows through each of the NMOS transistors 17 and 18.

[0132] Since the signals OCEN and PCEN are at the "L" level, the PMOS transistors 15, 16, 43, and 44 are turned "on," and the PMOS transistors 41 and 42 are turned "off." As a result, the data input paths DIN1 and DIN2 are precharged from the power supplies VDD2 and VDD4, and the potentials of the data input paths DIN1 and DIN2 gradually increase from time t2, and reach the power supply voltage VDD at time t3 after the precharge time tPC has elapsed.

[0133] During the offset cancel operation period, not only the offset cancel operation but also the precharge operation of the data input paths DIN1, DIN2 and the operation of matching the operating points of the NMOS transistors 17, 18 during the sense operation period are performed in parallel.

[0134] In this embodiment, it is assumed that the current that can be supplied from the power supplies VDD1 and VDD3 used for the offset cancel operation cannot be made sufficiently large. In this case, there is a limit to the shortening of the time required to complete the offset cancel operation. Therefore, as shown in FIG. 10, it is assumed that the time t3 at which the offset cancel operation (charging of the capacitors 19 and 20) is completed will be later than the time t4 at which the precharge operation is completed.

[0135] Therefore, at time t4 when the precharge operation is considered to be completed, the signal PCEN is switched from "L" to "H". When the signal PCEN becomes "H", the PMOS transistors 43 and 44 are turned "off". That is, the paths from the capacitors 19 and 20 to the data input paths DIN1 and DIN2 are cut off, and the precharge operation to the data input paths DIN1 and DIN2 is stopped.

[0136] However, since the signal OCEN remains at the "L" level, the potentials of the nodes N1 and N2, which are the input terminals of the capacitors 19 and 20, are maintained at the power supply voltage VDD of the power supply VDD2. The PMOS transistor 38 is also "on". As a result, a charging current flows from the power supplies VDD1 and VDD3 to the capacitors 19 and 20, and the offset cancel operation continues. On the other hand, for the data input paths DIN1 and DIN2, the discharge operation starts after the precharge operation stops. In other words, the period of the precharge operation is shortened, and the discharge operation is started before the offset cancel operation is completed. In other words, the discharge operation is performed in parallel with the offset cancel operation without waiting for the offset cancel operation to be completed.

[0137] By performing this operation, even when there is insufficient current available from power supply VDD1 or power supply VDD3 and it is difficult to sufficiently shorten the time required for the offset cancellation operation, it is possible to shorten the overall operation time of sense amplifier 8C.

[0138] Time t5 is set as a time after a certain time has elapsed from time t3. At time t5, the signal OCEN goes to the "H" level, the PMOS transistors 15 and 16 go "off", the PMOS transistors 41 and 42 go "on", and the switches 21 and 22 go "off". Also, at time t5, the signal SAE1 goes from "L" to the "H" level, the NMOS transistor 35 goes "on", and the NMOS transistor 36 goes "off". As a result, the gates of the NMOS transistors 17 and 18, which are a load element pair, are connected to each other to form a current mirror circuit. Also, the gates of the NMOS transistors 17 and 18 are disconnected from the node AB1. When this connection state is formed, the operating state of the sense amplifier 8C becomes the sense operating state, and the sense operation starts.

[0139] The sense operation in the subsequent sense operation period Phase-SA is similar to that of the sense amplifier 8B, and therefore will not be described.

[0140] According to the sense amplifier 8C, the capacitors 19 and 20 are charged by a current flowing from the node COM, which is a current supply source, so that the voltage Vos, which is the offset voltage of the sense amplifier 8C converted into an input voltage, appears as a differential voltage. At this time, the node COM is supplied with a current not only from the path from the power supply VDD1 but also from the path from the power supply VDD3. In other words, the amount of current that can be supplied from the node COM to the capacitors 19 and 20 can be made larger than the current that can be supplied by the power supply VDD1.

[0141] This enables the capacitors 19 and 20 to be charged at a higher speed, and the offset cancellation time tOC to be significantly shortened. It is preferable that the amount of current that the power supply VDD3 can supply is greater than the amount of current that the power supply VDD1 can supply.

[0142] The charges precharged in the data input paths DIN1 and DIN2 are gradually discharged in accordance with the read data, and the potentials of the data input paths DIN1 and DIN2 decrease accordingly. The potentials of the nodes PG1 and PG2 also decrease due to the effect of coupling with the capacitors 19 and 20.

[0143] In addition, in order to compensate for the offset voltage of the sense amplifier, capacitors 19 and 20 whose charging voltage is continuously variable are provided, so that the accuracy of offset cancellation is high. Furthermore, due to the above-mentioned sensing operation, a differentially amplified signal between the signal of the bit line BL and the signal of the reference signal line REF appears at nodes OT1 and OT2, and the signals at nodes OT1 and OT2 are further differentially amplified by the differential amplifier 23 and output. Therefore, the comparison resolution of the signals input to the data input paths DIN1 and DIN2 is high.

[0144] Furthermore, even if the offset cancel time tOC is longer than the precharge time tPC, the discharge operation can be started without waiting for the offset cancel operation, thereby achieving a reduction in the overall operating time of the sense amplifier 8C.

[0145] In this way, the sense amplifier 8C according to embodiment 2 is able to reduce the effects of the offset voltage of the sense amplifier by using an offset cancellation mechanism, while shortening the offset cancellation time tOC and also the precharge time tPC, thereby enabling faster data readout.

[0146] (Embodiment 3) A description will now be given of a sense amplifier according to embodiment 3. The sense amplifier according to embodiment 3 is an example which is further improved compared to the sense amplifiers of the above two embodiments.

[0147] Configuration and Operation of Sense Amplifier According to Third Embodiment Fig. 11 is a diagram showing the configuration of a sense amplifier according to embodiment 3. Note that Fig. 11 shows, as an example, an application of the improved technique of embodiment 3 to embodiment 1.

[0148] 11, the capacitors 19 and 20 also function as decoupling between the data input path DIN1 and node PG1 and between the data input path DIN2 and node PG2. Therefore, it becomes possible to use different voltages for the power supply used to precharge the data input paths DIN1 and DIN2 and the power supply for the circuit performing the sense operation.

[0149] 11, the sense amplifier 8D according to the third embodiment has a configuration in which the power supply used for precharging the data input paths DIN1 and DIN2 is changed to a power supply VCC1 (an example of the "fourth power supply" in this application) whose power supply voltage is higher than VDD2, as compared with the sense amplifiers 8A to 8C according to the above-mentioned reference techniques to the second embodiment. For example, the power supply voltage of the power supply VDD2 is 1 [V], and the power supply voltage of the power supply VCC1 is 1.5 [V].

[0150] According to the sense amplifier 8D having the above configuration, by using a higher voltage power supply for precharging, the current when precharging the data input paths DIN1, DIN2 can be increased, and the precharge time tPC can be further shortened.

[0151] <Relationship between discharge time and input voltage difference of sense amplifier> Fig. 12 is a diagram showing the relationship between the discharge time and the sense amplifier input voltage difference, in which the horizontal axis indicates the discharge time tDC of the data input paths DIN1 and DIN2, and the vertical axis indicates the input voltage difference of the sense amplifier.

[0152] The following formula (1) is a formula for calculating the discharge time tDC of the data input paths DIN1 and DIN2.

[0153] tDC=(C / ΔI0)×(ΔV0+Vos) …(1) ΔV0: Minimum input differential voltage required for sense operation (when Vos=0V) Vos: Sense amplifier specific offset voltage (voltage converted into input voltage) C: Parasitic capacitance when discharging bit lines, etc. ΔI0: Difference current between memory cell current Icell and reference current Iref

[0154] As can be seen from FIG. 12 and the above formula, when the voltage Vos is voltage Vos(a), the input voltage difference of the sense amplifier required for the sense operation (the voltage difference between the data input paths DIN1 and DIN2) is ΔV0+ΔVos(a). The discharge time tDC(a) required for the input voltage difference of the sense amplifier to become ΔV0+ΔVos(a) is (C / ΔI0)×(ΔV0+Vos(a)). On the other hand, when the voltage Vos is voltage Vos(b) which is smaller than the voltage Vos(a), the input voltage difference of the sense amplifier required for the sense operation (the voltage difference between the data input paths DIN1 and DIN2) is ΔV0+ΔVos(b). The discharge time tDC(b) required for the input voltage difference of the sense amplifier to become ΔV0+ΔVos(b) is (C / ΔI0)×(ΔV0+Vos(b)).

[0155] From the above, it can be seen that the smaller the voltage Vos, the shorter the discharge time tDC required for the sense operation. In other words, as the accuracy of offset cancellation improves and the offset improvement amount increases, the discharge time tDC due to the memory cell current Icell is shortened, and the improvement amount of the discharge time tDC increases.

[0156] <Effect of Reducing Operation Time of Sense Amplifier According to Each Embodiment> The sense amplifiers 8B and 8C of the first and second embodiments not only have an offset cancellation mechanism, but also have a mechanism for increasing the amount of current that can be supplied to the capacitors 19 and 20 for offset cancellation. Therefore, the sense amplifiers 8B and 8C can shorten the discharge time tDC and can shorten the offset cancellation time tOC compared to the sense amplifier 8A.

[0157] In the sense amplifiers 8B and 8C of the first and second embodiments, the precharge operation and the offset cancel operation are performed in parallel, and a larger current is supplied to charge the capacitor in the offset cancel operation. Therefore, in the sense amplifiers 8B and 8C, the path of the current supplied to precharge the data input paths DIN1 and DIN2 includes not only the path through the PMOS transistors 15 and 16, but also the path through the capacitors 19 and 20, which enables the precharge time tPC to be further shortened.

[0158] In addition, the sense amplifier 8D of the third embodiment has a configuration in which the power supply used for precharging the data input paths DIN1 and DIN2 is the power supply VCC1, the power supply voltage of which is the voltage VCC higher than the voltage VDD. Therefore, in the sense amplifier 8D, the amount of current flowing in the precharge operation can be further increased, and the precharge time tPC can be further shortened.

[0159] Overall Operation Time of Sense Amplifiers According to Reference Technology and Various Embodiments Fig. 13 is a diagram showing the operation time of a sense amplifier. In the bar graph shown in Fig. 13, the horizontal axis indicates the operation time required for the operation of the sense amplifier, and the vertical axis indicates the type of the sense amplifier. The operation time of the sense amplifier includes a precharge time tPC, an offset cancel time tOC, and a discharge time tDC, and blocks (boxes) representing times corresponding to operations that can be performed in parallel are written vertically in parallel.

[0160] 13, the first graph from the top corresponds to the case of a sense amplifier without an offset cancellation function. The second graph from the top corresponds to the case of a sense amplifier 8A with an offset cancellation mechanism according to the reference technology. The third graph from the top corresponds to the case of a sense amplifier according to embodiment 1. Moreover, the fourth graph from the top corresponds to the case of a sense amplifier according to embodiment 2.

[0161] In the case of a sense amplifier that does not have an offset cancellation mechanism, the effect of the offset voltage cannot be suppressed, and the discharge time tDC becomes relatively long as described above.

[0162] Next, in the case of the sense amplifier 8A based on the reference technology, since it has an offset cancellation mechanism, it is possible to suppress the effect of the offset voltage, and the discharge time tDC is shortened. On the other hand, since the current that charges the capacitors 19 and 20 is limited to the tail current Ibias from the power supply VDD1, the offset cancellation time tOC is relatively longer than the precharge time tPC. Therefore, there is room for further shortening of the overall operating time of the sense amplifier.

[0163] Next, in the case of the sense amplifier 8B according to the first embodiment, since it has an offset cancellation mechanism, the discharge time tDC is shortened similarly to the sense amplifier 8A. Also, since the current that charges the capacitors 19 and 20 is not only the tail current Ibias from the power supply VDD1 but also the current from the power supply VDD3, the offset cancellation time tOC is shortened to be equal to or shorter than the precharge time tPC. Therefore, the overall operation time of the sense amplifier is significantly shortened.

[0164] Next, in the case of the sense amplifier 8C according to the second embodiment, since it has an offset cancel mechanism, the discharge time tDC is shortened in the same way as the sense amplifier 8A. On the other hand, when the current for charging the capacitors 19 and 20 cannot be sufficiently secured, the precharge current is increased to shorten the precharge time tPC. At the same time, the discharge operation is started before the offset operation is completed and is partially executed in parallel to cover the increased offset cancel time tOC. This makes it possible to make the overall operating time of the sense amplifier almost the same as that of the sense amplifier 8B.

[0165] (Embodiment 4) A semiconductor device including each of the sense amplifiers is also an embodiment of the present application. Specifically, for example, the semiconductor device includes a plurality of memory cells (memory cells MCnm of the memory array 2), a selection circuit (address decoder 4) that selects one of the plurality of memory cells, a reference signal generator 9 that generates a reference signal and outputs it to a reference signal line (REF), and any one of the differential amplifiers (sense amplifiers 8A to 8D), in which the bit line (BL) of the memory cell selected by the selection circuit is connected to one terminal of the external input terminal pair (DIN1, DIN2) of the differential amplifier, and the reference signal line (REF) is connected to the other terminal of the external input terminal pair. (Embodiment 5) A method for canceling an offset of a sense amplifier is also an embodiment of the present application. Specifically, for example, the offset canceling method cancels an offset voltage of an input terminal pair of a sense amplifier (differential amplifier), in which the sense amplifier (differential amplifier) ​​includes a current source connected to a first power supply having a first current as a current that can be supplied, an active element pair connected to the current source and amplifying a signal input to the input terminal pair to output an output signal pair, a load element pair connected to a second power supply having a power supply voltage different from the first power supply and outputting the output signal pair to the output terminal pair, and a capacitive element pair inserted between an external input terminal pair and the input terminal pair, and includes a step of performing an offset canceling operation of charging the capacitive element pair so that a voltage obtained by converting the offset voltage of the input terminal pair into an input voltage is generated in the capacitive element pair by shorting corresponding terminals between the output terminal pair and the input terminal pair, and a step of controlling the current that can be supplied by the current source to be a second current larger than the first current when performing the offset canceling operation.

[0166] Although various embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments, and various modified examples are included. Furthermore, the above-mentioned embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those having all of the configurations described. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. All of these belong to the scope of the present invention. Furthermore, the numerical values ​​and the like included in the text and figures are merely examples, and the effect of the present invention is not impaired even if different ones are used. [Explanation of symbols]

[0167] 1...Semiconductor memory device (semiconductor device) 2...Memory array (multiple memory cells) 3. Amplifier block 4...Address decoder (selection circuit) 5...Word line driver 6...Timing controller 7...Column decoder 8, 8A, 8B, 8C, 8D...Sense amplifier (differential amplifier) 9...Reference signal generator 11~16, 37~39, 41~44...PMOS transistors 17, 18, 31 to 36...NMOS transistors 19,20…Capacitor 21,22…Switch 23...Differential amplifier 25…Inverter PG1, PG2...Input terminal pair DIN1, DIN2...Data input path VDD1...Power supply (first power supply) VDD2…Power supply (5th power supply) VDD3...Power supply (third power supply) VDD4…Power supply (6th power supply) VCC1…Power supply (fourth power supply) VSS...Power supply (second power supply) BL...Bit line REF...Reference signal line

Claims

1. A differential amplifier, a current source connected to a first power supply capable of supplying a first current; a pair of active elements connected to the current source, amplifying a signal input to the pair of input terminals and outputting a pair of output signals; a load element pair connected to a second power supply whose power supply voltage is different from the first power supply, for outputting the output signal pair to an output terminal pair; a pair of capacitance elements inserted between an external input terminal pair and the input terminal pair; a switching element pair that performs an offset cancellation operation of charging the capacitance element pair so that a voltage obtained by converting an offset voltage of the input terminal pair into an input voltage is generated in the capacitance element pair by shorting corresponding terminals between the output terminal pair and the input terminal pair; a current control circuit that controls a current that can be supplied by the current source to a second current that is greater than the first current when performing the offset cancel operation; an initialization circuit connected to the second power supply and initializing the input terminal pair to a potential of the second power supply before starting the offset canceling operation; a state control circuit that controls circuits or elements constituting the differential amplifier so that the state of the differential amplifier is switched in the following order: a standby state, an offset cancel operation state, a sense operation state, and the standby state; the initialization circuit initializes the input terminal pair to the potential of the second power supply during the standby state, and is disconnected from the input terminal pair during a state other than the standby state; the current control circuit controls the current that the current source can supply to the second current during the offset cancel operation state, and controls the current that the current source can supply to the first current during the sense operation state. Differential amplifier.

2. A differential amplifier, a current source connected to a first power supply capable of supplying a first current; a pair of active elements connected to the current source, amplifying a signal input to the pair of input terminals and outputting a pair of output signals; a load element pair connected to a second power supply whose power supply voltage is different from the first power supply, for outputting the output signal pair to an output terminal pair; a pair of capacitance elements inserted between an external input terminal pair and the input terminal pair; a switching element pair that performs an offset cancellation operation of charging the capacitance element pair so that a voltage obtained by converting an offset voltage of the input terminal pair into an input voltage is generated in the capacitance element pair by shorting corresponding terminals between the output terminal pair and the input terminal pair; a current control circuit that controls a current that can be supplied by the current source to a second current that is greater than the first current when performing the offset cancel operation; an initialization circuit connected to the second power supply and initializing the input terminal pair to a potential of the second power supply before starting the offset canceling operation; a state control circuit that controls circuits or elements constituting the differential amplifier so that the state of the differential amplifier is switched in the following order: a standby state, an offset cancel operation state, a sense operation state, and the standby state; a load control circuit that controls a sum of currents flowing through the load element pair during the offset cancel operation state to be 50% to 150% of the first current. Differential amplifier.

3. A current source connected to a first power supply, the first power supply having a first current that can be supplied; a pair of active elements connected to the current source, amplifying a signal input to the pair of input terminals and outputting a pair of output signals; a load element pair connected to a second power supply whose power supply voltage is different from the first power supply, for outputting the output signal pair to an output terminal pair; a pair of capacitance elements inserted between an external input terminal pair and the input terminal pair; a switching element pair that performs an offset cancellation operation of charging the capacitance element pair so that a voltage obtained by converting an offset voltage of the input terminal pair into an input voltage is generated in the capacitance element pair by shorting corresponding terminals between the output terminal pair and the input terminal pair; a current control circuit that controls a current that can be supplied by the current source to a second current that is greater than the first current when performing the offset cancel operation; An element pair through which a current flows; a load control circuit that switches a connection destination of the load element pair so that the load element pair and the element pair form a current mirror circuit when performing the offset cancellation operation. Differential amplifier.

4. A current source connected to a first power supply, the first power supply having a first current that can be supplied; a pair of active elements connected to the current source, amplifying a signal input to the pair of input terminals and outputting a pair of output signals; a load element pair connected to a second power supply whose power supply voltage is different from the first power supply, for outputting the output signal pair to an output terminal pair; a pair of capacitance elements inserted between an external input terminal pair and the input terminal pair; a switching element pair that performs an offset cancellation operation of charging the capacitance element pair so that a voltage obtained by converting an offset voltage of the input terminal pair into an input voltage is generated in the capacitance element pair by shorting corresponding terminals between the output terminal pair and the input terminal pair; a current control circuit that controls a current that can be supplied by the current source to a second current that is greater than the first current when performing the offset cancel operation; a precharge circuit that connects a fifth power supply to the pair of external input terminals and precharges the pair of external input terminals to a potential of the fifth power supply, performing the offset cancel operation during a period in which the precharge operation is being performed by the precharge circuit; Next, the offset cancel operation is stopped, after the offset cancel operation is stopped, the precharge operation is stopped and a discharge operation of the external input terminal pair is started; enabling initiation of an output read operation based on the output signal pair; Differential amplifier.

5. A current source connected to a first power supply, the first power supply having a first current that can be supplied; a pair of active elements connected to the current source, amplifying a signal input to the pair of input terminals and outputting a pair of output signals; a load element pair connected to a second power supply whose power supply voltage is different from the first power supply, for outputting the output signal pair to an output terminal pair; a pair of capacitance elements inserted between an external input terminal pair and the input terminal pair; a switching element pair that performs an offset cancellation operation of charging the capacitance element pair so that a voltage obtained by converting an offset voltage of the input terminal pair into an input voltage is generated in the capacitance element pair by shorting corresponding terminals between the output terminal pair and the input terminal pair; a current control circuit that controls a current that can be supplied by the current source to a second current that is greater than the first current when performing the offset cancel operation; a precharge circuit that connects a fifth power supply to the pair of external input terminals and precharges the pair of external input terminals to a potential of the fifth power supply, performing the offset cancel operation during a period in which the precharge operation is being performed by the precharge circuit; during the offset cancel operation, stopping the precharge operation and starting a discharge operation of the external input terminal pair; After the discharge operation is started, the offset cancel operation is stopped; enabling initiation of an output read operation based on the output signal pair; Differential amplifier.

6. 6. The differential amplifier according to claim 5, The precharge circuit includes: a second switching element pair connected between the capacitance element pair and the external input terminal pair; a third switching element pair connected between the fifth power supply and a connection pair of the capacitance element pair and the second switching element pair; a fourth switching element pair connected between a sixth power supply and a connection point pair between the second switching element pair and the external input terminal pair, transitioning from a state in which the second switching element pair is inactivated and the third and fourth switching element pairs are activated to a state in which the fourth switching element pair is inactivated, thereby stopping the precharge operation and starting the discharge operation; Differential amplifier.

7. 4. The differential amplifier according to claim 3, the current control circuit connects a third power supply, the third power supply having a current supply path different from that of the first power supply, to the current source when performing the offset cancellation operation. Differential amplifier.

8. 4. The differential amplifier according to claim 3, a precharge circuit for connecting a fourth power supply having a power supply voltage higher than that of the first power supply to the pair of external input terminals and precharging the pair of external input terminals to a potential of the fourth power supply; Differential amplifier.

9. 4. The differential amplifier according to claim 3, The power supply voltage of the second power supply is the ground voltage of the differential amplifier. Differential amplifier.

10. A plurality of memory cells; A selection circuit that selects one of the plurality of memory cells; a reference signal generator that generates a reference signal and outputs the reference signal to a reference signal line; A differential amplifier according to any one of claims 1 to 9, a bit line of the memory cell selected by the selection circuit is connected to one terminal of the pair of external input terminals of the differential amplifier, and the reference signal line is connected to the other terminal of the pair of external input terminals; Semiconductor device.

11. 1. An offset cancellation method for canceling an offset voltage of an input terminal pair of a differential amplifier, comprising: The differential amplifier comprises: a current source connected to a first power supply capable of supplying a first current; a pair of active elements connected to the current source, amplifying a signal input to the pair of input terminals and outputting a pair of output signals; a load element pair connected to a second power supply whose power supply voltage is different from the first power supply, for outputting the output signal pair to an output terminal pair; a pair of capacitance elements inserted between an external input terminal pair and the input terminal pair; An element pair through which a current flows; A load control circuit, a step of performing an offset cancellation operation in which corresponding terminals between the output terminal pair and the input terminal pair are short-circuited, by the differential amplifier, to charge the capacitance element pair so that a voltage obtained by converting an offset voltage of the input terminal pair into an input voltage is generated in the capacitance element pair; a step of controlling a current that can be supplied by the current source to be a second current that is larger than a first current when the differential amplifier performs the offset cancellation operation; the load control circuit switches a connection destination of the load element pair so that the load element pair and the element pair form a current mirror circuit when performing the offset cancellation operation. Offset cancellation method.

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