Image Sensor

Abstract

To provide a solid imaging element with a high function of holding a potential, including a thin film transistor with stable electric characteristics.SOLUTION: By initializing a signal charge accumulation unit of a solid imaging element to a cathode potential of a photoelectric conversion element, a reset transistor is omitted. By using a thin film transistor with an off current of 1×10-13A or less including an oxide semiconductor layer as a transfer transistor of the solid imaging element, the potential of the signal charge accumulation unit is maintained constant and the dynamic range can be improved. By using a silicon semiconductor that can manufacture a complementary metal oxide semiconductor element in a peripheral circuit, a semiconductor device of high speed and low consumption power can be manufactured.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device including a field-effect transistor using an oxide semiconductor. Regarding.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A technique for constructing thin-film transistors using a semiconductor thin film formed on a substrate having an insulating surface. Thin-film transistors are used in display devices such as liquid crystal televisions. Silicon-based semiconductor materials have been publicly known as semiconductor thin films that can be used in thin-film transistors. However, oxide semiconductors are attracting attention as another material.

[0004] As an oxide semiconductor material, zinc oxide or a material containing zinc oxide is known. , the carrier (electron) concentration is 10 18 / cm 3 In amorphous oxides (oxide semiconductors) Thin film transistors formed thereon are disclosed in Patent Documents 1 to 3. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165527 A [Patent Document 2] JP 2006-165528 A [Patent Document 3] JP 2006-165529 A Summary of the Invention [Problem to be solved by the invention]

[0006] On the other hand, solid-state imaging devices require excellent electrical characteristics while having a structure similar to that of a display device. Generally, field-effect transistors using SOI substrates or bulk single crystal silicon substrates are used. It is used in.

[0007] However, even field-effect transistors using single-crystal silicon do not have ideal electrical properties. For example, the off-state current (also called leakage current) is It is not so small that it can be called zero. Also, silicon has a relatively large change in temperature characteristics. The off-state current is particularly prone to change. When configuring a semiconductor device, it is necessary to ensure that a sufficient potential retention period can be secured without being affected by the surrounding environment. Therefore, the development of devices with even lower off-state currents is desirable.

[0008] In view of this, one embodiment of the disclosed invention is a semiconductor device having stable electrical characteristics (for example, an extremely reduced off-state current). The present invention aims to provide a solid-state imaging device including a thin film transistor having a . [Means for solving the problem]

[0009] One embodiment of the present invention is a photoelectric conversion element and an amplifier transistor formed using a silicon semiconductor. A solid-state image pickup device having a pixel in which a transfer transistor is formed of an oxide semiconductor. Regarding the imaging element.

[0010] In addition, in the oxide semiconductor according to one embodiment of the present invention, impurities that serve as electron donors (donors) are removed. By removing the SiO2, it is possible to obtain an intrinsic or substantially intrinsic semiconductor having a higher energy density than a silicon semiconductor. -The gap is big.

[0011] That is, one embodiment of the present invention is to remove hydrogen or OH groups contained in an oxide semiconductor. The hydrogen concentration in the oxide semiconductor was measured by secondary ion mass spectrometry (SIMS). Minimum value of 5 for econdary ion mass spectroscopy ×10 19 / cm 3 Less than or equal to 5×10 18 / cm 3 Less than or equal to 5×1, more preferably 0 17 / cm 3 or less, or 1×10 16 / cm 3 less than 1×10 1 4 / cm 3 Less than 1 x 10 12 / cm 3 The channel of the oxide semiconductor film is A solid-state imaging device having thin film transistors in which regions are formed is constructed.

[0012] The energy gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, and more preferably or 3 eV or more, and impurities such as hydrogen that form donors are reduced as much as possible, and the carrier concentration 1×10 14 / cm 3 Less than or equal to 1×10 12 / cm 3 Make it as follows.

[0013] Such a highly purified oxide semiconductor is used for the channel formation region of a thin film transistor. This results in a normally-off electrical characteristic, and at drain voltages from 1V to 10V, Its off-state current is 1×10 -13 A or less, or 100aA / μm (μm is the thin film transistor The current is preferably 10 aA / μm or less, and more preferably 1 aA / μm or less. m or less.

[0014] One embodiment of the present invention disclosed in this specification is a semiconductor device including: a signal charge storage section electrically connected to the photoelectric conversion element section via a transfer transistor; a gate electrode of the charge storage unit and an amplifying transistor, The channel formation region of the amplifier transistor is made of an oxide semiconductor. The pixel forming region is a semiconductor device having a pixel portion formed of a silicon semiconductor. be.

[0015] The amplifying transistor may also be formed of a thin film transistor using an oxide semiconductor. Further, the pixel section may be provided with a selection transistor. The peripheral circuitry is made of bulk transistors using silicon semiconductors, and is complementary metal-oxide semiconductor (CMOS). A transistor configuration is preferred.

[0016] Another embodiment of the present invention disclosed in this specification is a photoelectric conversion element portion and a photoelectric conversion element electrically connected to the photoelectric conversion element portion. a transfer transistor electrically connected to the transfer transistor; a signal charge storage section and an amplifying transistor electrically connected to the signal charge storage section; The transfer transistor is turned on to transfer the signal charge storage section to the photoelectric conversion element section. The photoelectric conversion element is initialized to a cathode potential, the photoelectric conversion element is reverse biased, and light is irradiated onto the photoelectric conversion element. The potential of the signal charge storage section is changed by turning off the transfer transistor. A semiconductor device that holds a potential and outputs a signal from an amplifying transistor according to the potential of a signal charge storage section. A method of operating a semiconductor device.

[0017] Conventional CMOS (Complementary Metal Oxide Semiconductor) The image sensor operates the reset transistor to In the above embodiment, the potential of the signal charge storage unit is initialized. The reset transistor is initialized to the cathode potential of the conversion element (photodiode). It is possible to adopt a configuration that omits the motor.

[0018] In this specification, the terms "electrode" and "wiring" are used to define the functions of these components. For example, an "electrode" is sometimes used as part of a "wiring." "Wiring" is sometimes used as a part of "electrode". The term also includes cases where a plurality of "electrodes" or "wirings" are integrally formed.

[0019] In addition, the substrate used for the "SOI substrate" is not limited to semiconductor substrates such as silicon wafers, but can also be glass. This also includes non-semiconductor substrates such as silicon substrates, quartz substrates, sapphire substrates, and metal substrates. The term "SOI substrate" broadly includes those that have a layer of semiconductor material on an insulating substrate. Furthermore, in this specification and the like, the term "semiconductor substrate" refers only to a substrate made of semiconductor material. The term "substrate" refers not only to a semiconductor material but also to any substrate that includes a semiconductor material. "SOI substrates" are also included in the "semiconductor substrates". Effect of the Invention

[0020] According to one embodiment of the present invention, a reset transistor is omitted and an oxide semiconductor device having an extremely small off-current is provided. By using a thin film transistor using a nitride semiconductor as the transfer transistor, The potential of the peripheral circuit is kept constant, improving the dynamic range. By using silicon semiconductors, which can be used to create complementary transistors, the operation is fast and the power consumption is low. The semiconductor device may be a power semiconductor device. [Brief description of the drawings]

[0021] [Figure 1] FIG. 2 is a cross-sectional view illustrating a configuration of a pixel of a solid-state imaging element. [Diagram 2] FIG. 2 is a cross-sectional view illustrating a configuration of a pixel of a solid-state imaging element. [Diagram 3] FIG. 2 is a cross-sectional view illustrating a configuration of a pixel of a solid-state imaging element. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a solid-state imaging element. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a solid-state imaging element. [Figure 6] FIG. 13 shows Vg-Id characteristics of a thin film transistor including an oxide semiconductor. [Figure 7] A photo of a thin-film transistor that uses an oxide semiconductor. [Figure 8] FIG. 13 shows Vg-Id characteristics (temperature characteristics) of a thin film transistor including an oxide semiconductor. [Figure 9] FIG. 1 is a longitudinal sectional view of an inverted staggered thin film transistor including an oxide semiconductor. [Figure 10] FIG. 10 is an energy band diagram (schematic diagram) taken along the line A-A' of FIG. [Figure 11] 10 is an energy band diagram (schematic diagram) in the B-B' cross section shown in Figure 9, (A) showing the state in which a positive potential (+VG) is applied to the gate (G1), and (B) showing the state in which a negative potential (-VG) is applied to the gate (G1). [Figure 12] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 13]2 is a diagram illustrating the configuration of a pixel of a solid-state imaging element. [Figure 14] 3A and 3B are diagrams for explaining the operation of a pixel of a solid-state imaging element. [Figure 15] FIG. 2 is a diagram illustrating the operation of a photodiode. [Figure 16] 2 is a diagram illustrating the configuration of a pixel of a solid-state imaging element. [Figure 17] 3A and 3B are diagrams for explaining the operation of a pixel of a solid-state imaging element. [Figure 18] 2 is a diagram illustrating the configuration of a pixel of a solid-state imaging element. [Figure 19] 3A and 3B are diagrams for explaining the operation of a pixel of a solid-state imaging element. [Figure 20] 2 is a diagram illustrating the configuration of a pixel of a solid-state imaging element. [Figure 21] 3A and 3B are diagrams for explaining the operation of a pixel of a solid-state imaging element. [Figure 22] 2 is a diagram illustrating the configuration of a pixel of a solid-state imaging element. [Figure 23] 3A and 3B are diagrams for explaining the operation of a pixel of a solid-state imaging element. [Figure 24] FIG. 2 is a diagram for explaining the configuration of a solid-state imaging element. [Diagram 25] 3A and 3B are diagrams illustrating configurations of a reset terminal driver circuit and a transfer terminal driver circuit. [Figure 26] FIG. 2 is a diagram illustrating a configuration of a vertical output line driver circuit. [Figure 27] FIG. 1 is a diagram showing an example of a shift register and a buffer circuit. [Figure 28] FIG. 2 is a cross-sectional view illustrating a configuration of a pixel of a solid-state imaging element. [Figure 29] 2 is a diagram illustrating the configuration of a pixel of a solid-state imaging element. [Diagram 30] 3A and 3B are diagrams for explaining the operation of a pixel of a solid-state imaging element. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in the following manner. The present invention is not limited to the above-described embodiment. In the structure, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. and the repeated explanation will be omitted.

[0023] In each figure described in this specification, the size of each component, region, thickness of layer, etc. may be exaggerated for clarity and are not necessarily limited to that scale. do not have.

[0024] In this specification, the terms "first", "second", "third", etc. are used in order to avoid confusion of components. The order is not limited to the order. For example, "first" can be appropriately replaced with "second" or "third", etc.

[0025] (Embodiment 1) One aspect of the present invention is a metal-insulator-semiconductor device, so-called MIS (Metal Insulator Semiconductor) A semiconductor device using a MOSFET. An element that uses a thin film semiconductor in the channel forming region is called a thin film transistor, and An element that uses bulk semiconductor in the formation region is called a bulk transistor. (Silicon on Insulator) The semiconductor layer formed on the substrate is a thin film. However, in this specification, the transistor formed with the semiconductor layer is one of bulk transistors. The seeds are:

[0026] An example of a pixel of a solid-state imaging device including a thin film transistor according to one embodiment of the present invention will be described below. In the present embodiment, as an example, a thin film transistor of a pixel in a solid-state imaging device is described. A thin-film transistor is connected to a photoelectric conversion element and a silicon semiconductor. The bulk transistor formed on the solid-state image sensor will be described. Each element, such as a photoelectric conversion element, a transistor, and wiring, is connected to the input of an electrical signal. This refers to a group of elements that are composed of elements for outputting an image.

[0027] As shown in the cross-sectional view of FIG. 28(A), the pixel is formed by a lens 600 formed on the surface side of the substrate, a camera Incident light is received by a photoelectric conversion element 608 through a color filter 602 and an interlayer insulating film 606. However, as shown in the area enclosed by the dotted line, A part of the optical path may be blocked by a part of the wiring layer 604. As shown in FIG. 6, a lens 610 and a color filter 612 are formed on the rear surface of the substrate to reflect incident light. A structure that allows the electric conversion element 618 to receive light efficiently may be used.

[0028] Also, when it is stated that A and B are connected, it means that A and B are electrically connected. This includes the case where A and B are directly connected to each other, and the case where A and B are directly connected to each other. The object is assumed to be an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). do.

[0029] An example of a pixel portion of a solid-state imaging device according to an embodiment of the present invention is shown in a cross-sectional view in FIG. In the example in which a thin film transistor made of an oxide semiconductor is used as the transistor 101, 131 is an n-channel bulk transistor formed on a single crystal silicon substrate 100. The photoelectric conversion element 110 is a photodiode including an n-type region 112 and a thin p-type region 114. It forms a diode and is connected to the source electrode 104 of the transfer transistor 101 . In addition, a signal charge storage section 116 (floating transistor) is provided below the drain electrode of the transfer transistor 101. The transfer transistor 101 is formed of an oxide semiconductor. The amplifier transistor 131 has a top-gate structure in which the conductor layer serves as a channel region. An n-channel bulk transistor including n-type regions 132a and 132b and a gate electrode 138. The gate electrode 138 of the amplifying transistor 131 is connected to a signal charge storage It is electrically connected to the stack portion 116 .

[0030] In the structure of FIG. 1, the gate insulating layer 136 of the bulk transistor is a thin-film transistor. The signal charge storage section 116 also serves as a base insulating layer for the transfer transistor 101, which is a gate. The gate insulating layer 136 serves as a dielectric to form a capacitance. The insulating layer 118 functions as part of the interlayer insulating layer of the bulk transistor.

[0031] Thin film transistors that use an oxide semiconductor in the channel formation region are, for example, top-gate type. However, a bottom gate type such as an inverted staggered structure may also be used. Since it is necessary to irradiate the transfer transistor 10 with light, a part of the source electrode of the transfer transistor 101 is photoelectrically connected to the In the example shown, the source electrode is connected to the light receiving portion of the conversion element 110, but the source electrode is made of a transparent conductive material. Alternatively, the state of connection with the photoelectric conversion element 110 may be changed. For example, as shown in FIG. A transistor 201 having a source electrode 204 made of a light-transmitting conductive material is placed on the transfer transistor. If used as a transistor, it can be connected to a part or the entire light receiving surface of the photoelectric conversion element 210. In addition, as shown in FIG. 2B, in order to ensure a light path to the photoelectric conversion element 310, A low-resistance metal layer is used as the source electrode 304 and the drain electrode 306, and a transparent conductive material layer The transistor 301 is a transfer transistor. It may also be used.

[0032] The photodiode formed as the photoelectric conversion element is made on a p-type single crystal silicon substrate (in the case of SOI). In this example, an n-type region is formed on a p-type single crystal silicon layer, and a thin p-type region is formed on top of it. A so-called buried photodiode is formed. A p-type region is formed on the surface of the photodiode. This can reduce noise caused by dark current generated on the surface.

[0033] Although the above embodiment shows an example in which a single crystal semiconductor substrate is used, a substrate having an SOI structure may also be used. The structure of the bulk transistor is not limited to this. The LDD (Lightly Doped Drain) structure and the source / drain region A structure in which low resistance silicide or the like is formed in a part of the structure may also be used.

[0034] In addition, a selection transistor electrically connected to the amplification transistor 131 is provided in the pixel section. The amplifier transistor and the selection transistor may be made of a silicon semiconductor or an oxide semiconductor. However, the amplifier transistor can be made of either a conductor or a It is preferable to form the transistor from a bulk transistor using a silicon semiconductor layer having a high efficiency.

[0035] In addition, an insulating layer is provided on the upper part of the bulk transistor, and a thin film transistor is provided on the insulating layer. For example, a transfer transistor formed of a thin film transistor can be replaced with a bulk transistor. If the amplifier transistor is placed on top of the amplifier, the surface area of ​​the transistor required for one pixel can be reduced. The product is about 1 / 2 to 2 / 3, which allows for improved integration and an increased light receiving area for the photodiode. This can reduce noise. Figure 3 shows an example of this. A conversion element 510 and an amplifying transistor 531 formed of a bulk transistor are formed, and an insulating A transfer transistor 501 formed of a thin film transistor is provided on the upper layer via an insulating film 541. This is an example in which the manufacturing processes for the photoelectric conversion element, bulk transistor, and thin film transistor are separated. However, the process for forming the signal charge storage portion 516 can be easily controlled. It is preferable to provide a capacitive electrode 540 .

[0036] Here, one embodiment of the present invention includes a thin film transistor including an oxide semiconductor layer. In addition, the solid-state imaging element CMOS (Complementary Metal Oxide A common component of Xide Semiconductor image sensors is the reset switch. The feature of this sensor is that it does not use a reset transistor. The potential of the signal charge storage section is initialized by operating the set transistor. However, in one aspect of the present invention, the signal charge storage unit is initialized to the cathode potential of the photodiode. First, the photodiode is forward biased and the transfer transistor is turned on. Then, the signal charge storage section has the same potential as the cathode of the photodiode. When the photodiode is reverse biased and light is irradiated onto it, the potential of the signal charge storage section is discharged. At this point, the transfer transistor is turned off and the amplifier transistor is turned on according to the held potential. A signal can be output by a register.

[0037] By combining the thin film transistors and bulk transistors described above, By improving the potential retention function of the charge storage section, a pixel section of a solid-state image sensor with a wide dynamic range is formed. However, in order to realize one embodiment of the present invention, an extremely small off-state current is required. It is preferable to use a thin film transistor having a low resistance. Next, a method for manufacturing the thin film transistor will be described.

[0038] One embodiment of the present invention is a bulk transistor using a single crystal silicon semiconductor, and has extremely high electrical characteristics. By combining thin film transistors using oxide semiconductors with excellent image quality, Therefore, the present invention relates to a method for manufacturing a thin film transistor using an oxide semiconductor. A detailed explanation will be given focusing on the above.

[0039] As an example, a method for fabricating the structure shown in FIG. 1 will be described with reference to the cross-sectional views shown in FIGS. A single crystal silicon substrate 100 is separated by an insulating film 140 (also called a field oxide film). The element formation region is formed. The element isolation region is formed by the LOCOS method (Local Oxidation ation of Silicon) method and STI method (Shallow Trench Isolation) method Isolation) etc. can be used.

[0040] Here, the substrate is not limited to a single crystal silicon substrate, but may be SOI (Silicon on Insul A substrate such as a photodiode may also be used.

[0041] In this embodiment, a buried photodiode and an n-channel bulk transistor are Since this is a structure that uses a p-type single crystal silicon substrate, a p-well is formed. If this is done, an n-type single crystal silicon substrate can also be used.

[0042] Next, a gate insulating layer 136 is formed so as to cover the element forming region. For example, a heat treatment is performed. The surface of the element formation region provided on the single crystal silicon substrate 100 is oxidized. A silicon film can be formed. Also, after forming a silicon oxide film by thermal oxidation, In addition, the surface of the silicon oxide film is nitrided by a nitriding process, so that the silicon oxide film can be It may be formed of a laminated structure of a silicon film and a silicon oxynitride film.

[0043] As another method, for example, the surface of the element formation region provided on the single crystal silicon substrate 100 is The gate insulating layer 13 is then subjected to oxidation or nitridation by high density plasma treatment. The layer 6 can be made of a silicon oxide film or a silicon nitride film. After oxidizing the surface of the element formation area by Zuma treatment, high-density plasma treatment is performed again. In this case, the oxidized layer may be in contact with the surface of the element formation region. A silicon film is formed, a silicon oxynitride film is formed on the silicon oxide film, and a gate insulating film is formed on the silicon oxide film. The edge layer 136 is a film in which a silicon oxide film and a silicon oxynitride film are laminated.

[0044] Next, a conductive layer is formed to cover the gate insulating layer 136. Here, the conductive layer 138a and The conductive layer 138b is formed by stacking the conductive layers 138a and 138b in order. Of course, the conductive layer may be a single layer or a stack of two or more layers. It may be formed in a layer structure.

[0045] The conductive layers 138a and 138b may be made of tantalum (Ta), tungsten (W), titanium ( Ti), Molybdenum (Mo), Aluminum (Al), Copper (Cu), Chromium (Cr), Ni Elements selected from Nb, etc., or alloy materials containing these elements as main components, or It can be formed from compound materials. It can also be formed from a metal nitride film made by nitrifying these elements. Other examples include polycrystalline silicon doped with impurity elements such as phosphorus. The semiconductor material may also be used.

[0046] Here, the conductive layer 138a is formed using tantalum nitride, and the conductive layer 138b is formed thereon. In addition, the conductive layer 138a is provided as a stacked layer using tungsten. A single layer or a laminated film selected from tungsten nitride, molybdenum nitride, or titanium nitride is used. The conductive layer 138b is a single layer or a laminated film selected from tantalum, molybdenum, and titanium. can be used.

[0047] Next, the laminated conductive layers 138a and 138b are selectively etched away. As a result, conductive layers 138a and 138b are left on a portion above the gate insulating layer 136. , and a gate electrode 138 is formed.

[0048] Next, a resist mask is selectively formed so as to cover areas other than the element formation area. The n-type region 1 is then doped with an impurity element using the mask and gate electrode 138 as a mask. 32a and 132b are formed. Here, an n-channel bulk transistor is formed. Therefore, the impurity elements used are phosphorus (P) and arsenic (As), which are n-type impurity elements. etc. can be used.

[0049] Next, a resist mask is selectively applied to create a photodiode, which is a photoelectric conversion element. First, phosphorus (P) or arsenic (As), which are impurity elements that give n-type conductivity, are added to form a p-type single crystal. After the p-n junction is formed by introducing boron, an impurity element that gives the p-type, into a crystalline silicon substrate, (B) is introduced into the surface layer of the n-type region to form a buried photodiode. can be done.

[0050] At this stage, the bulk transistor shown on the right side of Figure 4(A) and the photodiode shown on the left side The structure is completed.

[0051] Next, a method for manufacturing a thin film transistor having an oxide semiconductor layer as a channel region will be described. .

[0052] In this embodiment, a bulk transistor already provided on a single crystal silicon substrate 100 is A thin film transistor is formed on the gate insulating layer 136 of the thin film transistor. The undercoat film can also serve as the gate insulating layer of the bulk transistor. Alternatively, an insulating layer may be formed using a material other than silicon, and a base film may be laminated thereon.

[0053] The insulating layer in contact with the oxide semiconductor layer is a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or a silicon nitride layer. It is preferable to use an oxide insulating layer such as an aluminum layer or an aluminum oxynitride layer. The method for forming the insulating film may be a plasma CVD method, a sputtering method, or the like. In order to prevent a large amount of hydrogen from being contained in the insulating layer, it is necessary to form an insulating layer by sputtering. is preferred.

[0054] An example in which a silicon oxide layer is formed as an insulating layer by a sputtering method will be described. The silicon substrate 100 is transferred to a processing chamber, and is then immersed in a sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed. A silicon target is used to form an insulating layer on a single crystal silicon substrate 100. The single crystal silicon substrate 100 may be at room temperature or may be heated. It's fine.

[0055] For example, quartz (preferably synthetic quartz) is used as a target, the substrate temperature is 108° C., and the substrate The distance between the target and the source (TS distance) was set to 60 mm, the pressure was set to 0.4 Pa, and the high frequency power supply was set to 1 .5kW, oxygen and argon (oxygen flow rate 25sccm:argon flow rate 25sccm = 1: 1) A silicon oxide layer is formed by RF sputtering in a 100 nm atmosphere. In addition, silicon is used as a target for forming the silicon oxide layer instead of quartz. In this case, oxygen or a mixture of oxygen and argon is used as the sputtering gas. This is done using gas.

[0056] In this case, it is preferable to form the insulating layer while removing residual moisture from within the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the insulating layer.

[0057] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 O) and other compounds containing hydrogen atoms are exhausted, and the insulating layer formed in the processing chamber is The concentration of impurities can be reduced.

[0058] The sputtering gas used to deposit the insulating layer does not contain impurities such as hydrogen, water, hydroxyl groups, or hydrides. It is possible to use high-purity gas in which substances have been removed to concentrations on the order of ppm or ppb. preferable.

[0059] The sputtering method uses a high-frequency power supply as the sputtering power source, while the RF sputtering method uses a DC power supply. There are two types of sputtering: DC sputtering and pulsed DC sputtering, which uses a pulsed bias. The sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit conductive films. It is used when:

[0060] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0061] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0062] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0063] The insulating layer may have a laminated structure. For example, from the substrate side, a silicon nitride layer, a silicon oxynitride layer, A nitride insulating layer such as an aluminum nitride layer, an aluminum nitride layer, or an aluminum nitride oxide layer and the oxide A laminated structure with a nitride insulating layer may also be used.

[0064] For example, a spatula containing high-purity nitrogen from which hydrogen and moisture have been removed is used between the silicon oxide layer and the substrate. A target gas is introduced and a silicon nitride layer is formed using a silicon target. In the same manner as for the silicon oxide layer, the silicon nitride layer is formed while removing the residual moisture in the processing chamber. It is preferable to coat the substrate with a film.

[0065] When forming a silicon nitride layer, the substrate may be heated during film formation.

[0066] When a silicon nitride layer and a silicon oxide layer are laminated as an insulating layer, the silicon nitride layer and the oxide layer Silicon layers can be deposited in the same process chamber using a common silicon target. First, nitrogen-containing sputtering gas is introduced to the silicon target mounted in the processing chamber. A silicon nitride layer is formed using a sputter gas containing oxygen. The silicon oxide layer is formed by replacing the silicon target with the silicon nitride layer. Since the silicon nitride layer and the silicon oxide layer can be formed successively without exposure to the atmosphere, It is possible to prevent impurities such as hydrogen and moisture from being adsorbed onto the surface.

[0067] Next, a thin film having a thickness of 2 nm or more and a thickness of 200 nm or more is deposited on the insulating layer (on the gate insulating layer 136 in this embodiment). An oxide semiconductor film having a thickness of 1 nm or less is formed.

[0068] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor film as much as possible, As a pretreatment for film formation, the single crystal silicon substrate 100 is preheated in a preheating chamber of the sputtering device. It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate. The exhaust means provided in the preheating chamber is preferably a cryopump. This pre-heating can be omitted. This may be performed before the deposition of the edge layer 118, or after the deposition of the source and drain electrodes that will be formed later. This may be performed before the conductive layer is formed.

[0069] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma It is preferable to perform reverse sputtering to generate ions, and to remove dust adhering to the surface of the insulating layer. Reverse sputtering is a method in which a voltage is applied to the substrate side using an RF power source in an argon atmosphere. This is a method of modifying the surface by bombarding the substrate with ionized argon. Alternatively, nitrogen, helium, oxygen, etc. may be used.

[0070] The oxide semiconductor film is formed by a sputtering method. The In-Sn-Ga-Zn-O film, which is a material of the ternary metal oxide, and the In-Ga-Zn- O film, In-Sn-Zn-O film, In-Al-Zn-O film, Sn-Ga-Zn-O film, A In-Ga-Zn-O films, Sn-Al-Zn-O films, and binary metal oxides such as In-Zn -O film, Sn-Zn-O film, Al-Zn-O film, Zn-Mg-O film, Sn-Mg-O film, An In-Mg-O film, an In-O film, an Sn-O film, a Zn-O film, or the like can be used. The oxide semiconductor film may contain SiO2.

[0071] The oxide semiconductor film is InMO3(ZnO) m Use a thin film represented by (m>0) Here, M is one or more selected from Ga, Al, Mn and Co. Metal element. For example, M is Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. InMO3(ZnO) m An oxide semiconductor film having a structure represented by (m>0) Among them, oxide semiconductors with a structure containing Ga as M are called In-Ga-Zn-O oxide semiconductors. and the thin film is also called an In-Ga-Zn-O film.

[0072] In this embodiment, an oxide semiconductor film is grown using an In-Ga-Zn-O based metal oxide target. The oxide semiconductor film is formed by a sputtering method using a rare gas (typically, argon). ) atmosphere, oxygen atmosphere, or a mixture of these atmospheres by sputtering. It is possible.

[0073] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Using high-purity gas in which impurities have been removed to concentrations on the order of ppm or ppb It is preferable that

[0074] A target containing zinc oxide as the main component for forming an oxide semiconductor film by a sputtering method is used. For example, a target of a metal oxide having a composition ratio of In2O3: Use a metal oxide target with a Ga2O3:ZnO=1:1:1 [molar ratio] In addition, the metal oxide ternary phase of In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] was A fill rate of the metal oxide target is preferably 90% or more and 100% or less. The filling rate is 95% or more and 99.9% or more. By using a metal oxide target with a high filling rate, As a result, the formed oxide semiconductor film becomes a dense film.

[0075] The oxide semiconductor film is formed by holding the substrate in a treatment chamber that is kept in a reduced pressure state and removing residual moisture in the treatment chamber. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the oxygen, and the metal oxide is sputtered onto the target. In order to remove residual moisture in the treatment chamber, It is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, It is preferable to use a titanium sublimation pump. A cryopump with a cold trap may be used. The treatment chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor film formed in the treatment chamber is exhausted, The concentration of impurities in the film can be reduced. Good too.

[0076] An example of the deposition conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, Pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, oxygen and argon (oxygen flow rate 15 scc m: Argon flow rate 30sccm) atmosphere is applied. Note that pulse direct current (DC ) power supply reduces the amount of powdery material (also called particles or dust) that is generated during film formation. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less in thickness. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be appropriately selected depending on the application.

[0077] Next, the oxide semiconductor film is formed into an island shape by a first photolithography step and an etching step. The oxide semiconductor layer 102 is then processed into an oxide semiconductor layer 102 (see FIG. 4B).

[0078] Note that a resist mask for forming an island-shaped oxide semiconductor layer is formed by an ink-jet method. If the resist mask is formed by the inkjet method, no photomask is required. In addition, the etching of the oxide semiconductor film is performed by dry etching. Either etching or wet etching may be used, or both may be used.

[0079] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0080] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing added sulfur, etc. can be used.

[0081] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0082] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide water: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO-07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0083] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium, etc. contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials, we can make effective use of resources and reduce costs. do.

[0084] In order to etch into the desired shape, the etching conditions (etching solution, The etching time, temperature, etc. are adjusted appropriately.

[0085] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 102 by etching.

[0086] In this embodiment, nitrogen, helium, neon, or arsenic is added to the oxide semiconductor layer 102. The first heat treatment is performed under a rare gas atmosphere such as argon. The temperature of the first heat treatment is 400° C. or higher. The temperature is set to 750° C. or less, and preferably 400° C. or more and less than the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the equipment, and the oxide semiconductor layer was heated to 450° C. in a nitrogen atmosphere. Heat treatment is performed for 1 hour at 100°C. When the temperature is lowered from the heat treatment temperature, the atmosphere is switched to oxygen. The oxide semiconductor layer 102 may be dehydrated or dehydrogenated by the first heat treatment. It can be done.

[0087] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Annealing) equipment, LRTA (Lamp Ra pid Thermal Annealing (RTA) equipment The LRTA device is a halogen laser annealing (HLTA) device. lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure nato The exposure to light (electromagnetic waves) emitted from lamps such as lithium lamps and high-pressure mercury lamps can cause The GRTA device is a device that uses high-temperature gas to heat materials. The gases include rare gases such as argon, or nitrogen, which can be treated by heat treatment. An inert gas that does not react with the material is used.

[0088] For example, the first heat treatment is performed by heating an inert gas to a high temperature of 650° C. or more and 700° C. or less. The substrate is then moved into the inert gas chamber and heated for a few minutes. GRTA can be used to heat the gas out. GRTA allows high-temperature heating in a short time. It becomes possible.

[0089] In the first heat treatment, the atmosphere is nitrogen, helium, neon, argon, or the like. It is preferable that the gas does not contain water, hydrogen, etc. Alternatively, the purity of the atmospheric gas is 6 N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. impure The concentration of the substance is 1 ppm or less, preferably 0.1 ppm or less. Oxygen is used as the atmospheric gas. When used, it is preferable that it has a similar purity.

[0090] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, In some cases, the crystallization rate is 90% or more, resulting in a microcrystalline or polycrystalline layer. In some cases, the oxide semiconductor layer is microcrystalline, or 80% or more of the oxide semiconductor layer is microcrystalline. Depending on the conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor layer containing no crystalline components may be obtained. In some cases, it becomes a conductor layer. In addition, microcrystals (grain size 1 nm or more) are present in the amorphous oxide semiconductor. In the case where the oxide semiconductor layer is a mixture of There are also cases where this is the case.

[0091] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. It can also be performed on semiconductor films.

[0092] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer is formed. After the formation of the oxide semiconductor layer, a source electrode and a drain electrode are laminated on the oxide semiconductor layer. After forming a gate insulating layer on the drain electrode, the above-mentioned step may be performed.

[0093] Next, the photodiode upper layer is removed by a second photolithography step and an etching step. An opening is formed in the insulating layer so as to reach the p-type region of the oxide semiconductor layer 102. The conductive layer may be formed by sputtering or vacuum deposition. is selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. The above elements, or alloys containing the above elements, or alloy films of combinations of the above elements Manganese, magnesium, zirconium, beryllium, yttrium, etc. The metal conductive layer may be made of one or more of the following materials: It may be a single layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon A single-layer structure of the film, a two-layer structure of a titanium film laminated on an aluminum film, a titanium film and its titanium The aluminum film is layered on top of the titanium film, resulting in a three-layer structure. In addition, titanium, tantalum, tungsten, molybdenum, etc. are used in combination with aluminum. A film made of a single or a combination of elements selected from the group consisting of chromium, neodymium, and scandium; An alloy film or a nitride film may also be used.

[0094] Next, a resist mask is formed on the conductive layer in a third photolithography process. Etching is performed to form the source electrode 104 and the drain electrode 106 of the thin film transistor. After the formation of the source electrode, the resist mask is removed (see FIG. 4(C)). If the end of the drain electrode is tapered, the coverage of the gate insulating layer laminated thereon is improved. Therefore, it is preferable.

[0095] In this embodiment, the source electrode 104 and the drain electrode 106 are formed by sputtering. A titanium film is formed to a thickness of 150 nm.

[0096] Note that when the conductive layer is etched, part of the oxide semiconductor layer 102 is removed. The respective materials and etching conditions are set so as not to expose the insulating layer underneath. Adjust appropriately.

[0097] In this embodiment, a titanium film is used as the conductive layer, and an In-GaAs film is used as the oxide semiconductor layer 102. Using a-Zn-O oxide semiconductor, ammonia hydrogen peroxide (NH3H2O) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0098] Note that in the third photolithography step and the etching step, the oxide semiconductor layer 102 In some cases, only a portion of the oxide semiconductor layer is etched, resulting in a groove (a recess). In addition, a resist mask for forming the source electrode 104 and the drain electrode 106 is formed by ink. If the resist mask is formed by the inkjet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0099] In the third photolithography process, ultraviolet light or KrF laser is used for exposure when forming the resist mask. The lower ends of adjacent source electrodes on the oxide semiconductor layer 102 are The width of the gap between the lower end of the drain electrode and the channel of a thin film transistor to be formed later. When performing exposure with a channel length L of less than 25 nm, the channel length L is determined by the channel length L. Extreme ultraviolet rays have extremely short wavelengths of up to several tens of nanometers. The resist mask is formed in the second photolithography process using the ultraviolet light. Line exposure has high resolution and a large depth of focus. It is also possible to set the channel length L of the transistor to 10 nm or more and 1000 nm or less. This allows for faster operation and, because the off-current is extremely small, it is also possible to reduce power consumption. can.

[0100] Next, on the insulating layer, the oxide semiconductor layer 102, the source electrode 104 and the drain electrode 106 A gate insulating layer 118 is formed (see FIG. 5(A)). The gate insulating layer 118 is also deposited and becomes a part of the interlayer insulating film.

[0101] Here, the oxide semiconductor ( Since the gate oxide semiconductor (highly purified oxide semiconductor) is extremely sensitive to the interface state and interface charge, The interface between the gate insulating layer and the highly purified oxide semiconductor is important. The insulating layer (GI) is required to be of high quality.

[0102] For example, high-density plasma CVD using microwaves (2.45 GHz) produces dense, highly insulating materials. This is preferable because it allows the formation of a high-quality insulating layer with high pressure. The close contact between the gate insulating layer and the semiconductor substrate reduces the interface state density and improves the interface characteristics. Of course, it is possible to form a high-quality insulating layer as a gate insulating layer. If so, other film formation methods such as sputtering and plasma CVD can be applied. In addition, the film quality of the gate insulating layer and the interface characteristics with the oxide semiconductor are improved by heat treatment after film formation. In any case, the film quality as the gate insulating layer must be good. Of course, it is necessary to reduce the interface state density with the oxide semiconductor and form a good interface. That's good.

[0103] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias and thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, The bond with the main component of is broken by a strong electric field (B: bias) and high temperature (T: temperature), and the generated The dangling bonds induce a shift in the threshold voltage (Vth). In one embodiment of the present invention, impurities, particularly hydrogen, water, and the like, are removed as much as possible from an oxide semiconductor. By improving the interface characteristics with the gate insulating layer, a stable thin film transistor is obtained even when a BT test is performed. This makes it possible to obtain transistors.

[0104] In this embodiment, the gate insulating layer 118 is formed by using microwaves (2.45 GHz). The high density plasma CVD apparatus used here is: 1×10 11 / cm 3 This refers to a device that can achieve a plasma density of 3k or higher. A microwave power of 1000 W to 6 kW is applied to generate plasma, and an insulating layer is formed.

[0105] The chamber is filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gas as material gases. A gas is introduced, and high-density plasma is generated under a pressure of 10 Pa to 30 Pa to deposit an insulating layer on the substrate. After that, the supply of monosilane gas was stopped, and the nitrous oxide ( The surface of the insulating layer may be subjected to plasma treatment by introducing at least nitrogen (N2O) and a rare gas. The plasma treatment performed on the surface of the insulating layer by introducing nitrogen oxide (N2O) and rare gases is The insulating layer that has undergone the above process has a thin film thickness, e.g., less than 100 nm. It is an insulating layer that can ensure reliability even if the insulating layer is heated.

[0106] When forming the gate insulating layer 118, monosilane gas (SiH4) and nitrogen are introduced into the chamber. The flow ratio of nitrogen oxide (N2O) should be in the range of 1:10 to 1:200. The rare gases introduced into the bar are helium, argon, krypton, xenon, etc. Among them, it is preferable to use argon, which is inexpensive.

[0107] In addition, the insulating layer obtained by the high density plasma CVD apparatus can form a layer of a constant thickness. In addition, the insulating layer obtained by the high-density plasma CVD device allows precise control of thin layer thickness.

[0108] The insulating layer obtained through the above process is different from the insulating layer obtained using conventional parallel plate PECVD equipment. The film quality is significantly different, and when comparing the etching rates using the same etchant, In this case, the insulation layer obtained by the parallel plate type PECVD apparatus is enhanced by 10% or more or 20% or more. The etching speed is slow, and the insulating layer obtained using a high-density plasma CVD apparatus can be said to be a dense layer.

[0109] In this embodiment, the gate insulating layer 118 is formed by a high density plasma CVD apparatus. 0 nm silicon oxynitride layer (SiO x N y Also called, where x>y>0).

[0110] As another method, a silicon oxide layer, a nitrogen layer, etc. are formed by using a plasma CVD method or a sputtering method. A silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer is formed by a single layer. Note that the gate insulating layer 118 may be formed as a single layer or a stacked layer. In order to prevent the gate insulating layer 118 from being broken down, it is also preferable to form the gate insulating layer 118 by sputtering. When forming a silicon oxide layer by sputtering, a silicon target is used. A quartz target or a quartz target is used, and oxygen or a mixture of oxygen and argon is used as the sputtering gas. This is done using a mixed gas.

[0111] The gate insulating layer 118 is formed by insulating the source electrode 104 and the drain electrode 106 with a silicon oxide layer. A silicon nitride layer may be laminated. For example, a silicon nitride layer may be laminated as the first gate insulating layer. A silicon oxide layer (SiO x (x>0)) and the first A second gate insulating layer having a thickness of 50 nm or more is formed on the gate insulating layer by sputtering. Silicon nitride layer of less than 1 nm (SiN y (y>0)) is laminated to form a gate of 100 nm thickness. It may also be an insulating layer.

[0112] Next, a resist mask is formed by a fourth photolithography process and selectively etched. 10. The gate insulating layer 118 is then partially etched to remove a portion of the gate insulating layer 118 to expose the source region of the bulk transistor. Then, openings are formed that reach the n-type regions 132a and 132b that will become the n-type regions or drain regions (FIG. 5( See B). )

[0113] Next, a conductive layer is formed on the gate insulating layer 118 in which the opening is formed, and then a fifth photolithography is performed. The gate electrode 108 and the wiring layers 152 and 153 are formed by a lithography process. The resist mask may be formed by an inkjet method. When the method is used for formation, no photomask is used, and therefore the manufacturing cost can be reduced.

[0114] The gate electrode 108 and the wiring layers 152 and 153 are made of molybdenum, titanium, chromium, or tantalum. Metallic materials such as tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. An alloy material containing these as main components can be used to form a single layer or a laminated layer.

[0115] For example, a laminated structure in which the gate electrode 108 and the wiring layers 152 and 153 are two layers is Two-layer laminate structure with a layer of molybdenum laminated on a layer of aluminum, or molybdenum laminated on a layer of copper A two-layer structure with a copper layer and a titanium nitride layer or a tantalum nitride layer on a copper layer. Preferably, the titanium nitride layer and the molybdenum layer are laminated to form a two-layer structure. The laminated structure is a tungsten layer or a tungsten nitride layer, and an aluminum and silicon layer. A titanium nitride layer or titanium layer is laminated with an alloy of aluminum and titanium or an alloy of aluminum and titanium. It is preferable that the gate electrode is formed using a light-transmitting conductive layer. Examples of the conductive layer having light-transmitting properties include a light-transmitting conductive oxide. It can be done.

[0116] In this embodiment, the gate electrode 108 and the wiring layers 152 and 153 are formed by sputtering. A titanium film is formed to a thickness of 150 nm.

[0117] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment, the heating is performed at a temperature of 00° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. After forming a protective insulating layer and a planarizing insulating layer on the thin film transistor and the bulk transistor, You may go.

[0118] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed by maintaining a constant heating temperature or by heating from room temperature to 100 Repeat heating to a temperature of 200°C or higher and cooling from the heating temperature to room temperature several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. If the heat treatment is carried out under reduced pressure, the heating time can be shortened.

[0119] Through the above steps, an oxide semiconductor layer in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. A thin film transistor can be formed (see FIG. 5(C)). The transistor can be applied as a transfer transistor 101, and the bulk transistor can be applied as an amplification It can be applied as the transistor 131.

[0120] In addition, a protective insulating layer 142 and a thin film transistor (not shown) are formed on the thin film transistor and the bulk transistor. For example, a silicon oxide layer may be used as the protective insulating layer 142. Silicon layer, silicon nitride layer, silicon oxynitride layer, silicon oxynitride layer, or aluminum oxide layer The aluminum layer can be formed as a single layer or a stacked layer.

[0121] The planarizing insulating layer may be made of polyimide, acrylic, benzocyclobutene, or polyamide. In addition to the above organic materials, organic materials having heat resistance such as epoxy can be used. Low-k materials, siloxane resins, PSG (phosphorus glass), BP SG (silicon boron glass) can be used. A planarizing insulating layer may be formed by laminating a plurality of insulating films.

[0122] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. In addition, the organic group may have a fluoro group.

[0123] The method for forming the flattening insulating layer is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. Spin coating, dip coating, spray coating, droplet ejection (inkjet, screen Printing methods such as inkjet printing, offset printing, etc., doctor knife, roll coater, A tool such as a ten coater or a knife coater can be used.

[0124] When the oxide semiconductor film is formed as described above, residual moisture in the atmosphere is removed, The concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. This makes it possible to stabilize the compound semiconductor film.

[0125] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, It is possible to provide a semiconductor device having stable electrical characteristics and high reliability.

[0126] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0127] (Embodiment 2) One embodiment of the present invention is a method for manufacturing a semiconductor device that functions as a carrier donor (or acceptor) in an oxide semiconductor. By removing all possible impurities to extremely low levels, the resulting semiconductor is intrinsic or substantially intrinsic. The present embodiment is a conductor, and the oxide semiconductor is applied to a thin film transistor. In this embodiment, the measured values ​​of the off-state current in an evaluation element (also called a TEG) will be described below.

[0128] In Fig. 6, 200 thin-film transistors with L / W = 3 μm / 50 μm are connected in parallel. The initial characteristics of a 3μm / 10000μm thin-film transistor are shown. A top view of the above is shown in FIG. 7(A), and a partially enlarged view of the above is shown in FIG. 7(B). The area enclosed by the dotted line is a thin-film transistor with L / W=3μm / 50μm and Lov=1.5μm. In order to measure the initial characteristics of the thin-film transistor, the substrate temperature was set to room temperature and The source-drain voltage (hereinafter referred to as drain voltage or Vd) is set to 10 V. The gate voltage (hereafter referred to as gate voltage or Vg) was changed from -20V to +20V. The change in the source-drain current (hereinafter referred to as drain current or Id) when In other words, the Vg-Id characteristics were measured. In FIG. 7, Vg was set in the range of -20V to +5V. As shown in Fig.

[0129] As shown in FIG. 6, a thin-film transistor with a channel width W of 10,000 μm has a Vd of 1 V and At 10V, the off-state current is 1×10 -13 [A] or less, and the measuring instrument (semiconductor The resolution of the meter analyzer (Agilent 4156C; Agilent) (1 00fA).

[0130] That is, the above thin film transistor exhibits normally-off electrical characteristics and operates at a voltage ranging from 1 V to 10 At a drain voltage of V, the off-state current per 1 μm of channel width is 100 aA / μm or more. preferably 10 aA / μm or less, and more preferably 1 aA / μm or less. It can be done.

[0131] A method for manufacturing the thin film transistors that were measured will be described.

[0132] First, a silicon nitride layer is formed as a base layer on a glass substrate by a CVD method. A silicon oxynitride layer was formed on the silicon oxynitride layer as a gate electrode by a sputtering method. A tungsten layer was then formed on the gate electrode by selectively etching the tungsten layer. was formed.

[0133] Next, a 100 nm thick silicon oxynitride film was formed on the gate electrode as a gate insulating layer by the CVD method. A layer was formed.

[0134] Next, an In-Ga-Zn-O metal oxide target is deposited on the gate insulating layer by sputtering. The thickness of the film was 50 mm. Here, the oxide semiconductor layer was selectively etched to form an island. A shaped oxide semiconductor layer was formed.

[0135] Next, the oxide semiconductor layer was subjected to a first etching treatment in a clean oven under a nitrogen atmosphere at 450° C. for 1 hour. Heat treatment was carried out.

[0136] Next, a titanium layer (thickness 150 nm) was formed on the oxide semiconductor layer as a source electrode and a drain electrode. The titanium layer was selectively etched to form a solenoid. The channel length L of each thin film transistor is 3 μm. With a channel width of 50 μm and 200 pieces in parallel, the L / W ratio is 3 μm / 10,000. The thickness was set to μm.

[0137] Next, an oxide semiconductor layer was formed by reactive sputtering as a protective insulating layer. A silicon oxide layer was formed to a thickness of 300 nm. The silicon oxide layer, which was a protective layer, was selectively etched. The gate electrode, the source electrode, and the drain electrode were then subjected to etching to form openings. A second heat treatment was carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0138] Then, before measuring the Vg-Id characteristics, the device was heated at 150° C. for 10 hours.

[0139] Through the above steps, a bottom gate type thin film transistor was fabricated.

[0140] As shown in Figure 6, the off-current of the thin-film transistor is 1×10 -13 [A] is the level This is because the hydrogen concentration in the oxide semiconductor layer can be sufficiently reduced in the above manufacturing process. The hydrogen concentration in the oxide semiconductor layer is 5×10 19 atoms / cm 3 Hereinafter, preferably 5×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 or less, or 1×10 16 / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer is Secondary ion mass spectrometry (SIMS) This is done using ectroscopy.

[0141] Although an example using an In-Ga-Zn-O-based oxide semiconductor has been shown, the present invention is not limited thereto and other Oxide semiconductor materials such as In-Sn-Zn-O, Sn-Ga-Zn-O, Al -Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, In-Sn-O system, Using Sn-Zn-O, Al-Zn-O, In-O, Sn-O, Zn-O, etc. In addition, as the oxide semiconductor material, I, which contains 2.5 to 10 wt% Al, can be used. Uses n-Al-Zn-O system or In-Zn-O system with 2.5-10wt% Si mixed in It is also possible.

[0142] In addition, the carrier concentration of the oxide semiconductor layer measured by a Hall meter is 5×10 14 / cm 3 Less than or equal to 5×1012 / cm 3 More preferably, the carrier concentration of silicon is Degree 1.45×10 10 / cm 3 That is, the oxide semiconductor layer The carrier concentration can be made as close to zero as possible.

[0143] In addition, the channel length L of the thin film transistor can be set to 10 nm or more and 1000 nm or less. This enables the circuit to operate at higher speeds, and the extremely small off-state current allows for even lower power consumption. It can also be electrified.

[0144] In addition, when the thin film transistor is in an off state, the oxide semiconductor layer can be regarded as an insulator. It is possible to carry out calculations.

[0145] Next, the temperature characteristics of the off-current of the thin film transistor manufactured in this embodiment are evaluated. The temperature characteristics are important for the environmental resistance of the final product in which the thin-film transistor is used, as well as for maintaining the performance. It is important to take into consideration that the smaller the change, the better. increases.

[0146] The temperature characteristics are measured using a thermostatic chamber at -30℃, 0℃, 25℃, 40℃, 60℃, 80℃, and 100℃. The substrate on which the thin film transistors were formed at temperatures of 120°C and 150°C was kept at a constant temperature. The drain voltage was set to 6V and the gate voltage was changed from -20V to +20V to measure the Vg-Id characteristics. Obtained.

[0147] Figure 8(A) shows the Vg-Id characteristics measured at each of the above temperatures, which are overlaid. The area of ​​the off-state current surrounded by the dotted line is shown in enlarged form in Figure 8(B). The rightmost curve shown is taken at -30℃, the leftmost curve is taken at 120℃, and the other curves are taken at other temperatures. The curve lies between them. The on-current has almost no temperature dependence. As is clear from the enlarged view of Fig. 8(B), the current is constant except for the gate voltage of about 20V. The resolution of the measuring instrument is close to 1×10 at all temperatures. -12 [A] or less, depending on temperature. In other words, even at a high temperature of 120°C, the off-state current is 1×10 -12 [A] Considering that the channel width W is 10000 μm, the off-current is It turns out to be very small.

[0148] Highly purified oxide semiconductor In thin film transistors using ZnO or ZnO, the temperature dependence of the off-current is almost nonexistent. As shown in the band diagram of FIG. 10A, the oxide semiconductor is highly purified, The conductivity type approaches the intrinsic type and the Fermi level is located in the center of the forbidden band, so there is no temperature dependence. This is because the oxide semiconductor energy is 3 eV or more. This is also due to the extremely small number of thermally excited carriers. The domain is in a degenerate state, which is why there is no temperature dependence. The operation of the transistor is mostly due to carriers injected into the oxide semiconductor from the degenerate source region. Since there is almost no temperature dependence of the carrier density, the above characteristics (temperature dependence of off-current) The extremely low off-state current can be explained by the following This will be explained using a diagram.

[0149] 9 is a vertical cross-sectional view of an inverted staggered thin film transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on an electrode (GE1) via a gate insulating film (GI), A source electrode (S) and a drain electrode (D) are provided thereon.

[0150] FIG. 10 is an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. 0(A) shows the case where the voltage between the source and drain is equipotential (VD=0V), as shown in Fig. 1. 0(B) shows the case where a positive potential (VD>0) is applied to the drain.

[0151] FIG. 11 is an energy band diagram (schematic diagram) in the cross section taken along line BB' in FIG. FIG. 11(A) shows the state where a positive potential (+VG) is applied to the gate (G1). This shows the on-state where carriers (electrons) flow between the drains. Also, FIG. 11(B) shows A negative potential (-VG) is applied to the gate (G1), and the transistor is in the off state (minority carrier This indicates the case where the current does not flow.

[0152] Figure 12 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0153] Conventional oxide semiconductors are generally n-type, and the Fermi level (EF) in this case is It is located away from the intrinsic Fermi level (Ei) in the center of the gap and closer to the conduction band. In addition, some of the hydrogen in an oxide semiconductor acts as a donor, which is one of the reasons why the semiconductor becomes n-type. It is known that...

[0154] In contrast, in an oxide semiconductor according to one embodiment of the present invention, hydrogen, which is an n-type impurity, is introduced into the oxide semiconductor. It is removed from the body and highly purified so that impurities other than the main component of the oxide semiconductor are minimal. By doing so, it is considered to be intrinsic (i type), or it is considered to be intrinsic. Instead of adding impurities to make it i-type, impurities such as hydrogen and water are removed as much as possible to achieve high purity. The feature of the method is to make the semiconductor into an i-type (intrinsic) semiconductor or to make it close to the i-type. Therefore, the Fermi level (EF) can be made equal to the intrinsic Fermi level (Ei). can.

[0155] When the band gap (Eg) of an oxide semiconductor is 3.15 eV, the electron affinity (χ) is The specification of titanium (Ti) that constitutes the source and drain electrodes is 4.3 eV. The charge function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, At the interface between the two layers, no Schottky barrier is formed for electrons.

[0156] That is, the work function of the metal (φ M ) and the electron affinity (χ) of the oxide semiconductor are equal, When a person comes into contact with the material, an energy band diagram (schematic diagram) like that shown in FIG. 10(A) is displayed.

[0157] In FIG. 10(B), black circles (●) represent electrons. When a positive potential is applied to the drain, The electrons cross the barrier (h) and are injected into the oxide semiconductor, where they flow toward the drain. In this case, the barrier height (h) changes depending on the gate voltage and the drain voltage. When a gate voltage is applied, the barrier height in FIG. 10(A) The barrier height (h) is smaller than half the band gap (Eg).

[0158] At this time, the electrons injected into the oxide semiconductor pass through the oxide semiconductor as shown in FIG. In addition, in FIG. 11(B), when a negative potential is applied to the gate electrode (G1), Since the number of holes, which are minority carriers, is essentially zero, the current flows to an almost limitless extent.

[0159] For example, if the channel width W of a thin-film transistor is 1×10 4 μm and the channel length L is 3 μm. Even if the device is small, the off-state current at room temperature is 10 -13 A or less, and the subthreshold swing A switching value (S value) of 0.1 V / dec. (gate insulating film thickness 100 nm) can be obtained.

[0160] The intrinsic carrier density of silicon semiconductor is 1.45×10 10 / cm 3 (300K), Carriers exist even at room temperature. This is because thermally excited carriers exist even at room temperature. Furthermore, the band gap of silicon semiconductor is 1.12e V, so transistors using silicon semiconductors have a large off-state current that depends on temperature. This will fluctuate.

[0161] Therefore, rather than simply applying an oxide semiconductor with a wide band gap to a transistor, By purifying the oxide semiconductor to the maximum extent possible so that it contains no impurities other than the main component, Carrier concentration is 1×10 14 / cm 3 Less than or equal to 1×10 12 / cm 3 It will be as follows By doing so, there are almost no thermally excited carriers at practical operating temperatures, and the source The transistor can be operated only by electrons injected from the side. , off current is 1×10-13 A or less, and the off-state current is almost It is possible to obtain a transistor that operates extremely stably with almost no change.

[0162] The technical idea of ​​one embodiment of the present invention is to form an oxide semiconductor by inversion without adding impurities. By removing impurities such as water and hydrogen that are unintentionally present in the oxide semiconductor, The purpose of the purification is to remove water or hydrogen that creates donor levels, and then At the same time, oxygen is supplied to the oxide semiconductor that is in an oxygen-deficient state, so that the oxide semiconductor itself Its special feature is that it highly purifies the body.

[0163] Even immediately after deposition, oxide semiconductors are 20 / cm 3 Hydrogen at this level is detected by SIMS (secondary ion This is observed by mass spectrometry. The water or hydrogen that creates the donor level is intentionally removed, and then water or By compensating for the oxygen that is simultaneously reduced as hydrogen is removed, the oxide semiconductor can be highly One of the technical concepts is to purify the material and make it into an electrically i-type (intrinsic) semiconductor.

[0164] As a result, the less hydrogen there is, the better, and the fewer carriers there are in the oxide semiconductor. The less the better. When used in thin film transistors, oxide semiconductors carry current. Rather than intentionally having carriers as a gate electrode, the carriers in the oxide semiconductor are eliminated. This causes the gate to become insulated and acts as a passageway for carriers (electrons) supplied from the source. It is what is known as a highly purified i-type (intrinsic) semiconductor.

[0165] As a result, by making the oxide semiconductor have no or very few carriers, T The technical idea of ​​one aspect of the present invention is to reduce the off-current of the FT. The hydrogen concentration is 5×10 19 / cm 3 Less than or equal to 5×10 18 / c m 3 Less than 5×10, more preferably 17 / cm 3 Less than or equal to 1×10 16 / cm 3 and the carrier density is less than 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 The following is required:

[0166] As a result, the oxide semiconductor functions as a path, and the oxide semiconductor itself is a carrier. The i-type (intrinsic) is highly purified so that it does not or barely supplies arsenic. The rear is supplied by the source and drain.

[0167] Therefore, the lower the off-current, the better, and the drain voltage should be between 1 and 10 V. The transistor characteristics when a voltage is applied are 100aA / μm (channel width W=1 current per μm), preferably 10 aA / μm or less, and more preferably 1 aA / μm or less. It is characterized by being less than m.

[0168] By using thin film transistors with extremely low off-state current, memory circuits (memory elements) and the like can be realized. When a semiconductor device is fabricated, the off-current is small and there is almost no leakage, so the potential retention time is long, This makes it possible to retain stored data for a long period of time.

[0169] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0170] (Embodiment 3) The operation of a solid-state imaging element including a thin film transistor according to one embodiment of the present invention will be described.

[0171] The solid-state imaging element is CMOS (Complementary Metal Oxide The image sensor stores a potential in the signal charge storage area. The signal is output to the vertical output line via an amplification transistor. So, if there is leakage current in the reset transistor and / or the transfer transistor, The signal charge storage section is charged or discharged by the current. When the potential of the signal charge storage section changes, the potential of the amplifier transistor also changes, and the potential This resulted in a discrepancy in the values, which resulted in degradation of the captured image.

[0172] In this embodiment, the thin film transistor shown in the first and second embodiments is used as a CMOS image sensor. The effect of the operation when the transistor is applied to the transfer transistor of the sensor will be described. As described above, in one embodiment of the present invention, the reset transistor can be omitted. Either thin-film transistors or bulk transistors can be used for the amplification transistors. good.

[0173] FIG. 29 is a diagram showing an example of a pixel configuration of a conventional CMOS image sensor. A photodiode 1002 which is a conversion element, a transfer transistor 1004, a reset transistor The matrix is ​​made up of a resistor 1006, an amplifier transistor 1008, and various wiring. A number of such sensors are arranged in a rectangular shape to form a sensor.

[0174] Here, the photodiode 1002 is connected to the source side of the transfer transistor 1004. The drain side of the transfer transistor 1004 is connected to a signal charge storage section 1010 (FD: forward charge storage section). The signal charge storage section 1010 has a relay. The source of the set transistor 1006 and the gate of the amplification transistor 1008 are connected. In other configurations, a selection transistor is connected to the amplification transistor. .

[0175] Next, the operation will be described with reference to the timing chart in Fig. 30. First, when the power supply voltage Then, a reset pulse is input to the gate of the reset transistor 1006. The signal charge storage section 1010 receives a reset voltage. The reset transistor 1006 is then turned off and the signal charge storage The integrated circuit 1010 is held at the potential of the reset power supply. Next, the transfer transistor 1004 is turned on. When the signal charge accumulation unit 1010 is turned on, a current flows from the signal charge accumulation unit 1010 to the photodiode. The potential of 1010 drops. When the transfer transistor 1004 is turned off, The potential is stored in the signal charge storage section 1010. Then, the potential is The signal is then output to the vertical output line 1120. After that, the supply of the power supply voltage to the power supply terminal is cut off. The signals are output in this order.

[0176] FIG. 13 is a diagram showing an example of a pixel configuration of a CMOS image sensor according to an embodiment of the present invention. The pixel includes a photodiode 1002, which is a photoelectric conversion element, a transfer transistor 1004, , an amplifier transistor 1008 and various wirings, and multiple The sensor is formed by these elements. In one embodiment of the present invention, the reset transistor is omitted. It is characterized by:

[0177] Here, the photodiode 1002 is connected to the source side of the transfer transistor 1004. A signal charge storage section 1010 is formed on the drain side of the transfer transistor 1004. The gate of the amplifier transistor 1008 is connected to the signal charge storage section 1010. .

[0178] Next, the operation will be described with reference to the timing chart in Fig. 14. First, when the power supply voltage is applied to the power supply terminal, Then, when the potential (RST1) of the reset signal line 1040 becomes high level, The photodiode 1002 is forward biased and the cathode of the photodiode 1002 is The forward voltage (Vf Next, the potential of the transfer switch line 1050 becomes high level. When the transfer transistor 1004 is turned on, the potential (FD) of the signal charge storage unit 1010 becomes The potential of the cathode of the photodiode 1002 is then applied to the reset signal line 1001 (period T1). When the potential (RST1) of the photodiode 1002 becomes low level, the anode of the photodiode 1002 The potential of the photodiode becomes low level, and the photodiode 1002 is reverse biased. Here, a current corresponding to the light irradiated on the photodiode 1002 is generated. The potential of the signal charge storage section 1010 becomes low. The potential of the transfer switch line 1050 becomes low level, and the transfer transistor When the signal charge storage section 1010 turns off, the potential at the time of turning off the signal charge storage section 1010 is held. (period T3). Here, almost no leakage current flows through the transfer transistor 1004. For example, the potential (FD) of the signal charge storage section 1010 is held until the next transistor operation. Then, the signal is output to the vertical output line 1120 via the amplification transistor 1008. The power supply voltage to the power terminal is cut off. The signals are output in this order.

[0179] In other words, the reset transistor can be omitted, and the transfer transistor 1 can be omitted. In the thin film transistor of the oxide semiconductor having an extremely low off-state current shown in the first and second embodiments, By applying the thin film transistor, the relay from the signal charge storage unit 1010 through the thin film transistor It is possible to almost completely eliminate the break current, and an extremely high potential is maintained during the holding period of the above-mentioned period T3. The function can be activated.

[0180] Next, the operation of the photodiode 1002 will be described with reference to FIG. When not illuminated, the diode exhibits the same voltage-current characteristics as a normal diode (see Figure 15). When light is irradiated, especially when reverse bias is applied, the A large current flows (curve B in Figure 15). The movement of the photodiode operating point is shown in Figure 13. The operation of the reset signal line 1040 and the transfer transistor 100 will be described. When 4 is off, there is no current path through the photodiode 1002, so when light is irradiated The cathode of the photodiode 1002 is located at point c in FIG. When the potential of 40 becomes high level, the photodiode 1002 becomes forward biased, and The cathode of the diode is lower than the reset potential by the forward voltage of the photodiode. When the transfer transistor 1004 is turned on, the signal charge storage section 1010 The potential of the reset signal line 1040 becomes the same as that of the cathode of the diode 1002. When it goes low, the photodiode 1002 is reverse biased, which is point d in FIG. When light is irradiated onto the photodiode 1002, a signal charge is generated from the signal charge storage section 1010. A discharge current flows through the transfer transistor 1004 to the photodiode 1002, and a signal The potential of the charge storage unit 1010 drops. When the transfer transistor 1004 is turned off, The discharge stops, and if the operating point in Figure 15 at that time is e, the potential difference between operating points d and e is is the potential difference of the signal obtained by discharging the photodiode 1002.

[0181] Next, the operation when the amplification transistor and each signal line are shared among a plurality of pixels will be described. Figure 16 shows that each pixel has a transfer transistor, an amplifier transistor, and a photodiode. In the basic form, the reset signal line, the transfer switch line, and the vertical output line are connected to the pixels. be.

[0182] The operation of the basic type will be explained according to the timing chart in Figure 17. The first line is driven as follows: First, when the potential (RST1) of the first reset signal line 1240 becomes high level, the first The first photodiode 1212 becomes forward biased, and the cathode of the first photodiode 1212 The forward voltage ( Next, the potential of the first transfer switch line 1250 (TRF When 1) becomes high level, the first transfer transistor 1214 is turned on, and the signal charge storage section The potential (FD) of 1210 becomes the same as the cathode of the first photodiode 1212. Next, when the potential (RST1) of the first reset signal line 1240 becomes low level, At this time, the anode of the first photodiode 12 is at a low level potential. The first photodiode 1212 is reverse biased. A current according to the first photodiode 1212 and the first transfer transistor 1214 The potential (FD) of the signal charge storage section 1210 is lowered by the discharge. When the potential (TRF1) of the switch line 1250 becomes low level, the first transfer transistor 121 4 is turned off and the current path is cut off, so the potential (FD) of the signal charge storage section 1210 is maintained. This potential is output to the vertical output line 1220 via the first amplification transistor 1218. Then, the second line is driven, and so on.

[0183] Figure 18 differs from the basic form above in that it has an amplifier transistor, a reset transistor, and a The figure shows a vertical 4-pixel shared type configuration that uses the same signal line. This allows for miniaturization by reducing the pixel area, and noise reduction by expanding the light receiving area of ​​the photodiode. The drain side of the transfer transistor of each of the four vertical pixels is electrically The signal charge storage section 1410 is connected to the amplifier. The gate of transistor 1408 is connected.

[0184] The operation of the vertical 4-pixel sharing type will be described with reference to the timing chart in FIG. In the driving, when the potential (RST1) of the first reset signal line 1461 becomes high level, The first photodiode 1412 becomes forward biased, and the first photodiode 1412 The cathode of the photodiode is higher than the high level potential of the first reset signal line 1461. The potential is lowered by the forward voltage (Vf). When the potential (TRF1) becomes high level, the first transfer transistor 1414 turns on and the signal The potential (FD1) of the signal charge storage unit 1410 is connected to the cathode of the first photodiode 1412. Next, the potential (RST1) of the first reset signal line 1461 becomes low level. When the first photodiode is turned on, the anode of the photodiode is turned on. The first photodiode 1412 is reverse biased. A current corresponding to the incident light flows through the first photodiode 1412 and the first transfer transistor. The electric potential (FD1) of the signal charge storage section 1410 decreases due to the discharge. When the potential (TRF1) of the first transfer switch line 1451 becomes low level, the first transfer transistor The transistor 1414 is turned off and the current path is cut off, so the potential ( This potential is supplied to the vertical output line FD1 via the first amplifying transistor 1408. Output to 1470.

[0185] To drive the second line, first, the potential (RST1) of the first reset signal line 1461 is set to a high level. When the second photodiode 1422 becomes positive, the second photodiode 1422 becomes forward biased. The cathode of the photodiode 1422 is at a higher potential than the high level potential of the first reset signal line 1461. The potential drops by the forward voltage (Vf) of the diode. Next, the second transfer switch When the potential (TRF2) of the line 1452 becomes high level, the second transfer transistor 1424 is turned on, and the potential (FD1) of the signal charge storage unit 1410 is Next, the potential of the first reset signal line 1461 (RST1) becomes When the potential becomes low, the anode of the photodiode becomes low. The second photodiode 1422 is reverse biased. A current corresponding to the light irradiated to the second photodiode 1422 is generated by the second photodiode 1422 and the second The potential (FD1) of the signal charge storage section 1410 is discharged. When the potential (TRF2) of the second transfer switch line 1452 becomes low level, The transfer transistor 1424 of the signal charge storage unit 142 is turned off and the current path is cut off. The potential (FD1) of the output terminal 10 is maintained. This potential is supplied to the first amplifier transistor 1408. and outputs it to the vertical output line 1470.

[0186] To drive the third line, first, the potential (RST1) of the first reset signal line 1461 is set to a high level. When the third photodiode 1432 becomes positive, the third photodiode 1432 becomes forward biased. The cathode of the photodiode 1432 is at a higher potential than the high level potential of the first reset signal line 1461. The potential drops by the forward voltage (Vf) of the diode. Next, the third transfer switch When the potential (TRF3) of the line 1453 becomes high level, the third transfer transistor 1434 is turned on, and the potential (FD1) of the signal charge storage unit 1410 is Next, the potential of the first reset signal line 1461 (RST1) becomes When the potential becomes low, the anode of the photodiode becomes low. The third photodiode 1432 is reverse biased. A current corresponding to the light irradiated to the third photodiode 1432 is generated by the third photodiode 1432 and the third The potential (FD1) of the signal charge storage section 1410 is discharged. When the potential (TRF3) of the third transfer switch line 1453 becomes low level, The transfer transistor 1434 of the signal charge storage unit 143 is turned off and the current path is cut off. The potential (FD1) of the output terminal 10 is maintained. This potential is supplied to the first amplifier transistor 1408. and outputs it to the vertical output line 1470.

[0187] To drive the fourth line, first, the potential (RST1) of the first reset signal line 1461 is set to a high level. When the fourth photodiode 1442 becomes positive, the fourth photodiode 1442 becomes forward biased. The cathode of the photodiode 1442 is at a higher potential than the high level potential of the first reset signal line 1461. The potential drops by the forward voltage (Vf) of the diode. Next, the fourth transfer switch When the potential (TRF4) of the line 1454 becomes high level, the fourth transfer transistor 1444 is turned on, and the potential (FD1) of the signal charge storage unit 1410 is Next, the potential of the first reset signal line 1461 (RST1) becomes When the potential becomes low, the anode of the photodiode becomes low. The fourth photodiode 1442 is reverse biased. A current corresponding to the light irradiated to the fourth photodiode 1442 is generated by the fourth photodiode 1442 and the fourth A current flows through the transfer transistor 1444, and the potential (FD1) of the signal charge storage unit 1410 is discharged. When the potential (TRF4) of the fourth transfer switch line 1454 becomes low level, Then, the fourth transfer transistor 1444 turns off, and the current path is cut off, so that the signal charge accumulation The potential (FD1) of the output terminal 1410 is maintained. This potential is supplied to the first amplifying transistor 1408. The driving of the 5th to 8th lines is as follows: The potential of the second reset signal line becomes high level, and the pixels are similarly driven sequentially.

[0188] Figure 20 shows a pixel sharing configuration different from that of Figure 18, with two pixels in each direction. The vertical and horizontal four-pixel shared type uses the same transistors as the reset signal line and amplification transistor. As with the shared pixel type, miniaturization is achieved by reducing the pixel area by reducing the number of transistors and wiring. In addition, noise can be reduced by increasing the light receiving area of ​​the photodiode. The drain side of the transfer transistor of each of the four pixels is electrically connected. In the signal charge storage section 1510, an amplifying transistor is formed. The gates of star 1508 are connected.

[0189] The operation of the vertical / horizontal 4-pixel shared type will be described with reference to the timing chart in FIG. The driving of the first reset signal line 1561 is performed by first setting the potential (RST1) of the first reset signal line 1561 to a high level. Then, the first photodiode 1512 becomes forward biased, and the first photodiode 15 The cathode of 12 is a photodiode that is connected to the high level potential of the first reset signal line 1561. Next, the potential of the first transfer switch line 1551 is lowered by the forward voltage (Vf) of the When the potential (TRF1) of the first transfer transistor 1514 becomes high level, the first transfer transistor 1514 turns on, The potential (FD1) of the signal charge storage unit 1510 is will have the same potential.

[0190] Next, when the potential (RST1) of the first reset signal line 1561 becomes low level, The anode of the diode falls to a low level potential. At this time, the first photodiode 15 12 is reverse biased. Here, the light irradiated to the first photodiode 1512 is A current according to the first photodiode 1512 and the first transfer transistor 1514 The potential (FD1) of the signal charge storage section 1510 is lowered by the discharge. When the potential (TRF1) of the switch line 1551 becomes low level, the first transfer transistor 15 14 is turned off and the current path is cut off, so the potential (FD1) of the signal charge storage unit 1510 is maintained. This potential is output to the vertical output line 1570 via the first amplifying transistor 1508. To exert effort.

[0191] Next, when the potential (RST1) of the first reset signal line 1561 becomes high level again, The second photodiode 1522 becomes forward biased, and the second photodiode 1522 The cathode is connected to the high level potential of the first reset signal line 1561, and the forward direction of the photodiode is The potential of the second transfer switch line 1552 is lowered by the forward voltage (Vf). When (TRF2) becomes high level, the second transfer transistor 1524 turns on and the signal The potential (FD1) of the charge storage unit 1510 is the same as the cathode of the second photodiode 1522. It becomes an electric potential.

[0192] Next, when the potential (RST1) of the first reset signal line 1561 becomes low level, The anode of the diode is at a low level potential. At this time, the second photodiode 152 2 is reverse biased. Here, in response to the light irradiated to the second photodiode 1522, The current flows through the second photodiode 1522 and the second transfer transistor 1524. The potential (FD1) of the signal charge storage unit 1510 is lowered by the discharge. When the potential (TRF2) of the transfer line 1552 becomes low level, the second transfer transistor 1524 is turned off and the current path is cut off, so the potential (FD1) of the signal charge storage unit 1510 is maintained. This potential is output to the vertical output line 1570 via the first amplification transistor 1508. By these two operations, the outputs of the pixels in the first line are output in sequence to the vertical output line 1570.

[0193] To drive the second line, first, the potential (RST1) of the first reset signal line 1561 is set to a high level. When the third photodiode 1532 becomes positive, the third photodiode 1532 becomes forward biased. The cathode of the photodiode 1532 is connected to the high level potential of the first reset signal line 1561. The potential drops by the forward voltage (Vf) of the diode. Next, the third transfer switch line When the potential (TRF3) of 1553 becomes high level, the third transfer transistor 1534 The potential (FD1) of the signal charge storage unit 1510 is It has the same potential as the cathode.

[0194] Next, when the potential (RST1) of the first reset signal line 1561 becomes low level, The anode of the diode falls to a low level potential. At this time, the third photodiode 15 The third photodiode 1532 is reverse biased. A current according to the third photodiode 1532 and the third transfer transistor 1534 The electric potential (FD1) of the signal charge storage section 1510 is lowered by the discharge. When the potential (TRF3) of the switch line 1553 becomes low level, the third transfer transistor 15 34 is turned off and the current path is cut off, so the potential (FD1) of the signal charge storage unit 1510 is maintained. This potential is output to the vertical output line 1570 via the first amplifying transistor 1508. To exert effort.

[0195] Next, when the potential (RST1) of the first reset signal line 1561 becomes high level again, The fourth photodiode 1542 becomes forward biased, and the fourth photodiode 1542 The cathode is connected to the high level potential of the first reset signal line 1561, and the forward direction of the photodiode is The potential of the fourth transfer switch line 1554 is lowered by the forward voltage (Vf). When (TRF4) becomes high level, the fourth transfer transistor 1544 is turned on, and the signal The potential (FD1) of the charge storage unit 1510 is the same as the cathode of the fourth photodiode 1542. It becomes an electric potential.

[0196] Next, when the potential (RST1) of the first reset signal line 1561 becomes low level, The anode of the diode is at a low level potential. At this time, the fourth photodiode 154 2 is reverse biased. Here, the light irradiated to the fourth photodiode 1542 A current corresponding to the input signal is supplied to the fourth photodiode 1542 and the fourth transfer transistor 1544. The potential (FD1) of the signal charge storage unit 1510 is lowered by the discharge. When the potential (TRF4) of the switch line 1554 becomes low level, the fourth transfer transistor 154 4 is turned off and the current path is cut off, so the potential (FD1) of the signal charge storage unit 1510 is maintained. This potential is output to the vertical output line 1570 via the first amplification transistor 1508. By these two operations, the output of the pixels on the second line is output in sequence to the vertical output line 1570. Next, the potential of the second reset signal line becomes high level, and similarly, driving is performed sequentially. cormorant.

[0197] FIG. 22 shows the reset signal line, transfer switch, and This is a shared transfer switch line type in which the line and the amplification transistor are used together. The pixel area is reduced by sharing the transfer switch line. By miniaturizing the device by shrinking the size of the chip and by expanding the light receiving area of ​​the photodiode, noise can be reduced. For four pixels that are vertically and horizontally adjacent, the drain side of the transfer transistor of each pixel The signal charge storage section is electrically connected to the amplifier transistor. The gates of the two transfer transistors are connected. The transistors share the transfer switch line, so that the transfer It is characterized by having transistors that operate simultaneously.

[0198] The operation of the shared transfer switch line type will be described with reference to the timing chart in FIG. The driving of the second and third lines is performed by first resetting the potential (RST1) of the first reset signal line 1665 and When the potential (RST2) of the second reset signal line 1666 becomes high level, the first photodiode The first photodiode 1612 and the third photodiode 1632 are forward biased, and the first photodiode The cathodes of the first reset diode 1612 and the third photodiode 1632 are connected to the first reset The photodiode is turned on by the high level potential of the signal line 1665 and the second reset signal line 1666. The potential drops by the forward voltage (Vf) of the diode.

[0199] Next, when the potential (TRF1) of the first transfer switch line 1751 becomes high level, The transfer transistor 1614 is turned on, and the potential (FD1) of the first signal charge storage section 1610 becomes The potential becomes the same as that of the cathode of the first photodiode 1612, and the second signal charge storage unit 1 The potential of 620 (FD2) becomes the same as the cathode of the third photodiode 1612. Next, the potential (RST1) of the first reset signal line 1665 and the potential (RST2) of the second reset signal line 16 When the potential of 66 (RST2) becomes low level, the anode of the photodiode becomes low level. At this time, the first photodiode 1612 and the third photodiode 1613 632 is reverse biased. Here, the first photodiode 1612 and the third photodiode A current corresponding to the light irradiated on the diode 1632 is generated by the first photodiode 1612. , a third photodiode 1632, a first transfer transistor 1614 and a third transfer transistor The potential (FD1) of the first signal charge storage section 1610 and the potential (FD2) of the second signal charge storage section 1610 are The potential (FD2) of the signal charge storage unit 1620 is lowered by discharging. When the potential (TRF1) of 1751 becomes low level, the first transfer transistor 1614 and The third transfer transistor 1634 is turned off and the current path is cut off, so that the first signal charge storage The potential (FD1) of the second signal charge accumulation section 1610 and the potential (FD2) of the second signal charge accumulation section 1620 are maintained. These potentials are supplied to the first vertical output line 1616 via the first amplifying transistor 1618. 675, and then through a second amplification transistor 1628 to a second vertical output line 1676. Output.

[0200] Next, the potential (RST1) of the first reset signal line 1665 and the potential (RST2) of the second reset signal line When the potential (RST2) of 1666 becomes high level, the second photodiode 1622 and The second photodiode 162 and the fourth photodiode 1642 are forward biased, and the second photodiode 162 The cathodes of the second and fourth photodiodes 1642 are connected to the first reset signal line 1665 and The forward voltage (V The potential drops by f).

[0201] Next, when the potential (TRF2) of the second transfer switch line 1572 becomes high level, The transfer transistor 1624 and the fourth transfer transistor 1644 are turned on, and the first signal current The potential (FD1) of the charge storage section 1610 is the same as the cathode of the second photodiode 1622. The potential (FD2) of the second signal charge storage unit 1620 becomes the potential of the fourth photodiode The potential of the first reset signal line 1665 (RS When the potential (RST1) of the second reset signal line 1666 and the potential (RST2) of the second reset signal line 1666 become low, At this time, the anode of the second photodiode 1 becomes a low level potential. The second photodiode 622 and the fourth photodiode 1642 are reverse biased. The fourth photodiode 1622 and the fourth photodiode 1642 generate a current in response to light irradiated thereon. The current passes through the second photodiode 1622, the fourth photodiode 1642, the second transfer transistor 1644, and the The first signal charge storage unit The potential (FD1) of the first signal charge storage section 1610 and the potential (FD2) of the second signal charge storage section 1620 are discharged. When the potential (TRF2) of the second transfer switch line 1572 becomes low level, The second transfer transistor 1624 and the fourth transfer transistor 1644 are turned off, and the current path Since the potential of the first signal charge storage section 1610 (FD1) and the potential of the second signal charge storage section 1610 (FD2) are blocked, The potential (FD2) of the storage section 1620 is maintained. 1618 to the first vertical output line 1675, and the second amplification transistor 1628 The first and second vertical output lines 1676 are output via these two operations. The output of the second pixel is output to a first vertical output line 1675 and a second vertical output line 1676 in order. do.

[0202] Next, the driving of the third and fourth lines will be described. First, the third reset signal line 16 The potential (RST3) of the fourth reset signal line 1667 and the potential (RST4) of the fourth reset signal line 1668 are high. At this time, the fifth photodiode 1652 and the seventh photodiode 1672 The fifth photodiode 1652 and the seventh photodiode 167 are forward biased. The cathode of the second reset signal line 1667 and the high of the fourth reset signal line 1668 are connected to the cathode of the third reset signal line 1667 and the high of the fourth reset signal line 1668. This potential is lower than the level potential by the forward voltage (Vf) of the photodiode.

[0203] Next, when the potential (TRF3) of the third transfer switch line 1753 becomes high level, the fifth transfer The seventh transfer transistor 1654 and the seventh transfer transistor 1674 are turned on, and the second signal charge The potential (FD2) of the storage section 1620 and the potential (FD3) of the third signal charge storage section 1630 are The same as the cathode of the fifth photodiode 1652 and the seventh photodiode 1672 Next, the potential (RST3) of the third reset signal line 1667 and the potential (RST4) of the fourth reset signal line 1668 are When the potential (RST4) of the signal line 1668 becomes low level, the anode of the photodiode At this time, the fifth photodiode 1652 and the seventh photodiode The fifth photodiode 1652 and the fifth photodiode 1672 are reverse biased. The current corresponding to the light irradiated to the seventh photodiode 1672 is output to the fifth photodiode 1673. a seventh photodiode 1652, a seventh photodiode 1672, a fifth transfer transistor 1654, and The potential (FD2) of the second signal charge storage unit 1620 flows to the transfer transistor 1674 of The potential (FD3) of the third signal charge storage section 1630 decreases due to discharge. When the potential (TRF3) of the transfer switch line 1753 becomes low level, the fifth transfer transistor The seventh transfer transistor 1654 and the seventh transfer transistor 1674 are turned off, and the current path is cut off. The potential (FD2) of the second signal charge storage unit 1620 and the potential of the third signal charge storage unit 1630 (FD3) is held. This potential is fed to the second vertical output line via the second amplifying transistor. 1676, and then output to the first vertical output line 1675 via the third amplification transistor. do.

[0204] Next, the potential (RST3) of the third reset signal line 1667 and the potential (RST4) of the fourth reset signal line When the potential (RST4) of 1668 becomes high level, the sixth photodiode 1662 and The eighth photodiode 1682 and the sixth photodiode 166 The cathodes of the second and eighth photodiodes 1682 are connected to the reset signal lines 1667 and The forward voltage (Vf ) the potential drops by

[0205] Next, when the potential (TRF4) of the fourth transfer switch line 1754 becomes high level, the sixth transfer The eighth transfer transistor 1664 and the eighth transfer transistor 1684 are turned on, and the second signal charge The potential (FD2) of the storage section 1620 and the potential (FD3) of the third signal charge storage section 1630 are The same as the cathode of the sixth photodiode 1662 and the eighth photodiode 1682 Next, the potential (RST3) of the third reset signal line 1667 and the potential (RST4) of the fourth reset signal line 1668 are When the potential (RST4) of the signal line 1668 becomes low level, the anode of the photodiode At this time, the sixth photodiode 1662 and the eighth photodiode The diode 1682 is reverse biased. Here, the sixth photodiode 1662 and A current corresponding to the light irradiated to the eighth photodiode 1682 is output to the sixth photodiode 1683. a sixth photodiode 1662, an eighth photodiode 1682, a sixth transfer transistor 1664, and The potential of the second signal charge storage unit 1620 (FD2 The potential (FD3) of the third signal charge storage section 1630 and the potential (FD4) of the fourth signal charge storage section 1630 are lowered by the discharge. When the potential (TRF4) of the transmission switch line 1754 becomes low level, the sixth transfer transistor The second transfer transistor 1664 and the eighth transfer transistor 1684 are turned off, and the current path is cut off. The potential of the first signal charge storage section 1620 (FD2) and the potential of the third signal charge storage section 1630 ( This potential is supplied to the second vertical output line 1 through the second amplifying transistor. 676, and then output to the first vertical output line 1675 via the third amplification transistor. These two operations cause the output of the pixels on the third and fourth lines to be output to the second vertical output line 167 in order. 6 and the first vertical output line 1675. Thereafter, the operations are carried out in this order.

[0206] FIG. 24 is a diagram of the entire CMOS image sensor. A reset terminal drive circuit 2020 and a transfer terminal drive circuit 2040 are arranged on both sides of the transistor 2100. In FIG. 24, the driving circuits are arranged on both sides of the pixel matrix 2100. The driver circuit may be disposed. In addition, a vertical line may be provided for outputting a signal from the driver circuit. A vertical output line driving circuit 2060 is arranged in the vertical direction. The transmission terminal driver circuit 2040 is a driver circuit that outputs two values, low and high, and is therefore In this way, the shift register 2200 and the buffer circuit 2300 can be combined to operate the device. These driving circuits can be constructed with bulk transistors or thin film transistors. However, bulk transistors using silicon semiconductors that can form complementary transistors are also used. It is preferable to use a stencil.

[0207] The vertical output line driving circuit 2060 includes a shift register 2210 and a buffer 2211 as shown in FIG. The vertical output lines can be configured by the circuit 2310 and the analog switch 2400. 2120 is selected by an analog switch 2400, and a video signal is sent to a video output line 2500. The analog switch 2400 is connected to the shift register 2210 and the buffer circuit 2310. The vertical output line driver circuit 2060 is a bulk transistor. Although it can be constructed of thin film transistors, it is possible to form complementary transistors. It is preferable to use a bulk transistor using a silicon semiconductor.

[0208] Figure 27 shows an example of a shift register and a buffer circuit. A shift register 2220 composed of a shifter and a buffer 2221 composed of an inverter. This is an example of a shift register and a buffer circuit 2320. The shift register and the buffer circuit are not limited to this circuit. Instead, the reset terminal driver circuit 2020, the transfer terminal driver circuit 2040, and the vertical output line driver The operating circuit 2060 is not limited to the above configuration.

[0209] The solid-state imaging device according to the above embodiment is applicable to various electronic devices (including gaming machines). For example, digital cameras, digital video cameras, mobile phones, portable games, etc. The present invention can be used in electronic devices having a means for acquiring image information, such as a mobile phone, a portable information terminal, etc. do.

[0210] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0211] 100 Single crystal silicon substrate 101 Transfer transistor 102 Oxide semiconductor layer 104 Source electrode 106 Drain electrode 108 Gate electrode 110 Photoelectric conversion element 114 p-type region 116 Signal charge storage section 118 Gate Insulation Layer 131 Amplifying transistor 136 Gate Insulation Layer 138 Gate electrode 140 Insulating film 142 Protective insulation layer 152 Wiring layer 154 Wiring 132a n-type region 138a Conductive layer 138b Conductive layer 201 Transistor 204 Source Electrode 210 Photoelectric conversion element 301 Transistor 304 Source Electrode 305 Buffer Layer 306 Drain electrode 310 Photoelectric conversion element 112 n-type region 450 under nitrogen atmosphere 501 Transfer transistor 510 Photoelectric conversion element 516 Signal charge storage section 531 Amplifying Transistor 540 Capacitive electrode 541 Insulating film 600 Lens 602 Color Filter 604 Wiring layer 606 Interlayer insulating film 608 Photoelectric conversion element 610 Lens 612 Color Filter 618 Photoelectric conversion element 1002 Photodiode 1004 Transfer transistor 1006 Reset transistor 1008 Amplifying transistor 1010 Signal charge storage section 1040 Reset signal line 1050 Transfer switch line 1120 Vertical output line 1210 Signal charge storage section 1212 Photodiode 1214 Transfer transistor 1218 Amplifying transistor 1220 vertical output line 1240 Reset signal line 1250 Transfer Switch Line 1408 Amplifying transistor 1410 Signal charge storage section 1412 Photodiode 1414 Transfer transistor 1422 Photodiode 1424 Transfer transistor 1432 Photodiode 1434 Transfer transistor 1442 Photodiode 1444 Transfer transistor 1451 Transfer Switch Line 1452 Transfer Switch Line 1453 Transfer Switch Line 1454 Transfer Switch Line 1461 Reset signal line 1470 vertical output line 1508 Amplifying transistor 1510 Signal charge storage section 1512 Photodiode 1514 Transfer transistor 1522 Photodiode 1524 Transfer transistor 1532 Photodiode 1534 Transfer transistor 1542 Photodiode 1544 Transfer transistor 1551 Transfer Switch Line 1552 Transfer Switch Line 1553 Transfer Switch Line 1554 Transfer Switch Line 1561 Reset signal line 1570 Vertical output line 1572 Transfer Switch Line 1610 Signal charge storage section 1612 Photodiode 1614 Transfer transistor 1618 Amplifying transistor 1620 Signal charge storage section 1622 Photodiode 1624 Transfer transistor 1628 Amplifying transistor 1630 Signal charge storage section 1632 Photodiode 1634 Transfer transistor 1642 Photodiode 1644 Transfer transistor 1652 Photodiode 1654 Transfer transistor 1662 Photodiode 1664 Transfer transistor 1665 Reset signal line 1666 Reset signal line 1667 Reset signal line 1668 Reset signal line 1672 Photodiode 1674 Transfer transistor 1675 vertical output line 1676 vertical output line 1682 Photodiode 1684 Transfer transistor 1751 Transfer Switch Line 1753 Transfer Switch Line 1754 Transfer switch line 2000 pixels 2020 Reset terminal drive circuit 2040 Transfer terminal drive circuit 2060 Vertical output line driver circuit 2100 pixel matrix 2120 each vertical output line 2200 Shift Register 2210 Shift Register 2220 Shift Register 2300 Buffer circuit 2310 Buffer circuit 2320 Buffer circuit 2400 Analog Switch 2500 video output line

Claims

1. An image sensor including a plurality of circuits arranged in a matrix, each circuit including a first photodiode to a fourth photodiode, a first transfer transistor to a fourth transfer transistor, an amplifier transistor, and a capacitor, a cathode of the first photodiode is electrically connected to a gate of the amplifying transistor via the first transfer transistor; a cathode of the second photodiode is electrically connected to a gate of the amplifying transistor via the second transfer transistor; a cathode of the third photodiode is electrically connected to a gate of the amplifying transistor via the third transfer transistor; a cathode of the fourth photodiode is electrically connected to a gate of the amplification transistor via the fourth transfer transistor; The gate of the amplifying transistor is always electrically connected to the capacitor, a first conductive layer having a function as an electrode of the capacitance and a second conductive layer having a function as a gate of the first transfer transistor are disposed in the same layer in a cross-sectional view; when viewed in a cross section, the first conductive layer and the second conductive layer are disposed on an insulating film having a region to become a gate insulating film of the first transfer transistor, the insulating film being opposite to a side on which a single crystal silicon substrate on which the first photodiode is formed is disposed; a third conductive layer electrically connected to one of the source and drain of the first transfer transistor and electrically connected to the gate of the amplification transistor, the third conductive layer overlapping the source region or the drain region of the amplification transistor; the third conductive layer overlaps with the first conductive layer; The plurality of circuits include a first output line and a second output line arranged in each column, Among the plurality of circuits, a first circuit and a second circuit included in the same column are arranged adjacent to each other in the column direction, one of a source and a drain of the amplifying transistor included in the first circuit is electrically connected to a wiring to which a power supply voltage is supplied; one of a source and a drain of the amplifying transistor included in the second circuit is electrically connected to the one wiring; the other of the source and the drain of the amplifying transistor included in the first circuit is electrically connected to the first output line; the other of the source and the drain of the amplifying transistor included in the second circuit is electrically connected to the second output line; Image sensor.

2. An image sensor including a plurality of circuits arranged in a matrix, each circuit including a first photodiode to a fourth photodiode, a first transfer transistor to a fourth transfer transistor, an amplifier transistor, and a capacitor, a cathode of the first photodiode is electrically connected to a gate of the amplifying transistor via the first transfer transistor; a cathode of the second photodiode is electrically connected to a gate of the amplifying transistor via the second transfer transistor; a cathode of the third photodiode is electrically connected to a gate of the amplifying transistor via the third transfer transistor; a cathode of the fourth photodiode is electrically connected to a gate of the amplification transistor via the fourth transfer transistor; The gate of the amplifying transistor is always electrically connected to the capacitor, a first conductive layer having a function as an electrode of the capacitance and a second conductive layer having a function as a gate of the first transfer transistor are disposed in the same layer in a cross-sectional view; when viewed in cross section, the first conductive layer and the second conductive layer are arranged to overlap a single crystal silicon substrate on which the first photodiode is formed, via an insulating film having a region that becomes a gate insulating film of the first transfer transistor; a third conductive layer electrically connected to one of the source and drain of the first transfer transistor and electrically connected to the gate of the amplification transistor, the third conductive layer overlapping the source region or the drain region of the amplification transistor; the third conductive layer overlaps with the first conductive layer; The plurality of circuits include a first output line and a second output line arranged in each column, Among the plurality of circuits, a first circuit and a second circuit included in the same column are arranged adjacent to each other in the column direction, one of a source and a drain of the amplifying transistor included in the first circuit is electrically connected to a wiring to which a power supply voltage is supplied; one of a source and a drain of the amplifying transistor included in the second circuit is electrically connected to the one wiring; the other of the source and the drain of the amplifying transistor included in the first circuit is electrically connected to the first output line; the other of the source and the drain of the amplifying transistor included in the second circuit is electrically connected to the second output line; Image sensor.

3. In claim 1 or 2, the third conductive layer comprises copper; Image sensor.

Images