How to measure high resistivity test samples

Abstract

To measure the resistance area product of a high resistivity layer with a microscopic multi-terminal probe, the high resistivity layer is sandwiched between two conductive layers. Multiple electrode configurations / positions are used to perform three voltage or resistance measurements. An equivalent electrical circuit model / three-layer model is used to determine the resistance area product as a function of the three measurements.

Description

[Technical field]

[0001] The present disclosure relates to measuring / determining electrical properties, such as resistance area product, of multi-layer test specimens, such as semiconductor wafers. Specifically, the present disclosure includes measuring / determining the resistance area product of layers that have high resistivity (i.e., are poor conductors). [Background technology]

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to European Patent Application No. 21207514, filed November 10, 2021, and U.S. Patent Application No. 63 / 192102, filed May 24, 2021, the disclosures of which are incorporated herein by reference.

[0003] It is desirable to perform electrical property measurements using a microscopic multi-terminal probe, which has multiple contact probes for contacting the test sample so that a current is injected into the test sample, with a pitch between the contact probes in the micrometer range. However, it can be difficult to establish an electrical connection between the contact probes and the high resistivity layer. Using a microscopic probe is also not possible because the probe contact terminals are too large or may damage the sample.

[0004] It is known, for example in Patent Document 1, to measure a tunnel junction using a microscopic multi-terminal probe and determine the electrical characteristics of the tunnel junction by an equivalent circuit model. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 6,927,569 Summary of the Invention [Problem to be solved by the invention]

[0006] However, such test samples are three-layer test samples, and therefore not test samples with a bottom conductive layer and a top insulating / high resistivity layer. Furthermore, the tunnel junction test samples are not test samples with a high resistivity layer, since there is no ohmic electron transport in the tunnel barrier. [Means for solving the problem]

[0007] To achieve the goal of measuring the resistance area product of a high resistivity layer of a test sample using a microscopic multi-terminal probe, a conductive top layer is added to the test sample on top of the high resistivity layer so that the test sample has a three-layer structure with the high resistivity layer sandwiched between the top conductive layer and the bottom conductive layer. The resistance area product is determined using an equivalent circuit model that has as inputs the value of the injected current and the measured voltage or resistance.

[0008] A first aspect of the present disclosure is a method for determining an electrical property, such as a resistance area product, of a multi-layer test sample. The multi-layer test sample has a bottom layer (e.g., a wafer substrate) constituting a conductive or semi-conductive layer, an interfacial layer, and a top layer constituting a conductive or semi-conductive layer. The interfacial layer is arranged between the bottom layer and the top layer, has a smaller electrical conductivity than the bottom layer and the top layer, and has a thickness such that the interfacial layer constitutes a substantially ohmic conductor and electron transport through the interfacial layer by quantum tunneling is negligible (e.g., is less than 1% of the total electron transport through the interfacial layer). This electron transport through the interfacial layer may be obscured by measurement noise. The method includes providing a test sample, providing a microscopic multi-terminal probe having a set of contact probes for contacting the top layer, contacting the top layer with the set of contact probes, and measuring a plurality of voltages or resistances for each of a plurality of contact probe spacings. One pair of contact probes is used for each resistance or voltage measurement. A model is provided for determining the resistance area product of the interfacial layer. The model takes multiple voltages or resistances as inputs and returns as output the resistor-area product, which is determined by the model.

[0009] The top layer may be provided by depositing it on top of the interface layer / high resistivity layer if it is not already provided so that a microscopic multi-terminal probe can be placed on the top conductive layer and electrical contact can be established. The top layer may be a metallic or semiconducting layer. The top layer may also be referred to as the top electrode.

[0010] The interface layer / high resistivity layer may be, for example, an oxide layer on top of the wafer, or a material such as High-k, Indium Gallium Zinc Oxide (IGZO) or a Phase Change Material (PCM). Other materials are possible.

[0011] For an ohmic conductor, the current through it is directly proportional to the voltage across it (i.e., it obeys Ohm's law). The tunnel barrier is not an ohmic conductor. However, electron transport by quantum mechanical tunneling cannot be ruled out, meaning that it is negligible for the material to be measured and becomes smaller as the measurement noise increases. Therefore, the signal-to-noise ratio in the measurement is too low to be measured.

[0012] Contact probes are also known as pins / electrodes. A contact probe may have each probe tip / end of the probe arranged along a line with an equal spacing / pitch between each tip (e.g., collinear equidistant probes).

[0013] Specifically, three different pin / contact probe configurations may be used: for example, for a first current injection / measurement, the two outermost pins may be used to inject current and the two innermost pins may be used to measure voltage.

[0014] For a second current injection, the two outer left pins may be used to inject current and the two outer right pins may be used to measure voltage.

[0015] For a third current injection, the outermost pin may be used together with the center pin to inject current (ie, with the voltage pin in between).

[0016] For three measurements to be mathematically independent, a probe with at least five pins may be used. [Brief description of the drawings]

[0017] For a complete understanding of the nature and objectives of the present disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which: [Figure 1] FIG. 1 illustrates an exemplary wafer having three layers. [Figure 2a] FIG. 2 shows the configuration of the current and voltage pins of the probe. [Figure 2b] FIG. 2 shows the configuration of the current and voltage pins of the probe. [Figure 2c] FIG. 2 shows the configuration of the current and voltage pins of the probe. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The present disclosure will now be described in more detail below by way of examples. However, the present disclosure may be embodied in forms different from those shown below, and should not be construed as being limited to the examples set forth herein. Rather, any examples are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0019] Figure 1 shows a wafer 10 having three layers. A top layer 12 may be tungsten and is deposited on an interface layer 14, which is the layer to be measured. A wafer substrate 16 constitutes the bottom layer.

[0020] In general, the top layer 12 should be easily contacted with a metallic material such as Ru, W, or TiN. The sheet resistance of the top layer 12 may be three times larger than the sheet resistance of the bottom layer or electrode. This sheet resistance may provide the desired measurement results.

[0021] The bottom layer may be the wafer substrate 16 or may be a layer on top of the wafer substrate 16. The bottom layer may be formed of Ru, W, TiN, or doped Si. The interface layer 14 is 1000 ohm μm 2 For example, the interface layer 14 may have a resistance area area of ​​10 Megaohms μm 2 , 100 Megaohms μm 2 , or 1000 Megaohms μm 2 It may be larger than.

[0022] To provide the desired measurement results, the interface layer 14 may have a thickness greater than 2 nm and a conductivity less than 10 times that of the bottom or top layers 12. Other resistor area products, thicknesses, and conductivities are possible. These are merely examples.

[0023] Standard microscopic four-terminal measurements on such material stacks provide the sheet resistance, which in a three-layer model is a combination of the sheet resistances of the top and bottom layers and the resistance area product (RA) of the interfacial layers. These parameters define the transport length (designated L or λ), which is the characteristic lateral length scale for current transport in the sample.

[0024] Depending on the ratio of probe pitch to L, the results of a four-point probe measurement can be substantially different. Typically, a small probe pitch will primarily probe the top layer, and a large probe pitch will primarily probe the parallel resistance of the top and bottom layers.

[0025] Measurements over a range of probe pitches near λ are required to accurately target the properties of all three layers.

[0026] In one embodiment, the value of L is in the range between 100 μm and 300 μm (micrometers). If either the top or bottom layer of the stack has a resistance multiple (e.g., >5) of another, a measurement with a 1000 μm pitch will have low sensitivity to the high resistance layer. In addition, such a measurement will also have low sensitivity to high resistance interface layers. Therefore, such a measurement may be unreliable for monitoring process variations in a multilayer stack unless all layers have similar resistance.

[0027] Figures 2a-2c show three separate configurations of probe current and voltage pins. Here, only four pins are shown. The voltmeter is shown as a single circle circuit symbol and the current source is shown as a double circle circuit symbol. Each contact probe / pin is shown as a rectangular arrow circuit symbol. Although four probes / pins are shown, more or less probes / pins are possible. In one example, more than four probes / pins are used.

[0028] The probes may have a distance between adjacent contact probes of at least 4 μm, although other dimensions are possible. In one example, the probes have a distance between the two outermost contact probes of less than 3 mm.

[0029] In what follows, it is assumed that no in-plane current flows in the interface layer, which is equivalent to an interface layer that has high resistivity and is thin compared to the top and bottom layers. The bottom layer should be more than 100 times more conductive than the interface layer for the assumptions presented below to hold and be usable.

[0030] When the probe is engaged with a multi-layer sample, it will measure the combination of the resistance of the bottom layer (Rb) and the top layer (Rt) and the resistance area product of the interface (RA=ρ*t), where ρ and t are the resistivity and thickness of the interface layer, respectively.

[0031] In one example, the contact probes may be placed on a conductive or semiconductive layer or on contact pads connected to a conductive or semiconductive layer, which may be in the top layer 12.

[0032] For collinear equidistant probes (ie, probes with all electrodes on one line and equally spaced), the resistance measured in the A, B and C configurations is governed by the following model:

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number

number

[0033] R A R is the resistance measured by the probe in the configuration shown in Figure 2a. B R is the resistance measured by the probe in the configuration shown in Figure 2b. C is the resistance measured by the probe in the configuration shown in Figure 2c.

[0034] K0(x) is the Bessel function of the second kind of order 0, s is the electrode pitch, and λ is the characteristic length given by:

number

[0035] The resistor area product is related to the sheet resistance as follows:

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[0036] The model may then be numerically solved for the resistance area product (RA) of the interface layer. Thus, the resistance area product of the interface layer is determined as a function of the resistance measurements. Alternatively, instead of inputting the measured resistance, values ​​of the injected current and the measured voltage may be input, since resistance is a voltage versus current.

[0037] In one embodiment, injecting a first current is injected into the test sample by a first pair of contact probes of the set of contact probes. A second current is injected into the test sample by a second pair of contact probes of the set of contact probes. A third current is injected into the test sample by a third pair of contact probes of the set of contact probes. The first pair of contact probes, the second pair of contact probes, and the third pair of contact probes have distances therebetween. These distances may be the same or different depending on the probes that make up the pairs.

[0038] The controller may be coupled to the probe and in electrical communication with the probe. The controller typically comprises a programmable processor that is programmed in software and / or firmware to perform the functions described herein, along with appropriate digital and / or analog interfaces for coupling to other elements of the system. Alternatively or additionally, the controller may comprise hardwired and / or programmable hardware logic circuitry that performs at least some of the functions of the controller. In practice, the controller may comprise multiple interconnected control units with appropriate interfaces for receiving and outputting signals as described herein. Program code or instructions for the controller to implement the various methods and functions disclosed herein may be stored in a readable storage medium, such as a memory in the controller or a separate memory.

[0039] Although the present disclosure has been described with respect to one or more particular embodiments, it will be understood that other embodiments of the present disclosure may be made without departing from the scope of the present disclosure. Accordingly, the present disclosure is intended to be limited only by the scope of the appended claims and their reasonable interpretation.

Claims

1. 1. A method for determining electrical properties of a multi-layer test specimen, comprising: Providing the multi-layer test specimen, the multi-layer test specimen comprising: A bottom layer constituting the first conductive or semiconductive layer; An interface layer, and a top layer constituting a second conductive or semiconductive layer, the interface layer being arranged between the bottom layer and the top layer, the interface layer having a smaller electrical conductivity than the bottom layer and the top layer, the interface layer having a thickness such that the interface layer constitutes a substantially ohmic conductor and such that electron transport through the interface layer by quantum tunneling is negligible compared to the total electron transport through the interface layer; and providing a microscopic multi-terminal probe, the microscopic multi-terminal probe having a set of contact probes for contacting the top layer; contacting the top layer with the set of contact probes; measuring a plurality of voltages or resistances for each of a plurality of spacings of the contact probes, a pair of contact probes being used for each resistance or voltage measurement; providing a model for determining a resistance-area product of the interface layer, the model receiving the plurality of voltages or resistances as inputs and returning the resistance-area product as an output; determining the resistor-area product according to the model; A method comprising:

2. The method of claim 1 , wherein the electron transport through the interface layer by quantum tunneling is obscured by measurement noise.

3. The method of claim 1 , wherein the electron transport through the interfacial layer by quantum tunneling is less than 1% of the total electron transport through the interfacial layer.

4. injecting a first current into the test sample using a first pair of contact probes of the set of contact probes, the first pair of contact probes having a first distance therebetween; injecting a second current into the test specimen using a second pair of contact probes of the set of contact probes, the second pair of contact probes having a second distance therebetween; injecting a third current into the test specimen using a third pair of contact probes of the set of contact probes, the third pair of contact probes having a third distance therebetween; The method of claim 1 further comprising:

5. 10. The method of claim 1, further comprising the step of placing the set of contact probes on the second conductive or semiconductive layer or on contact pads connected to the second conductive or semiconductive layer.

6. The method of claim 1 , wherein the set of contact probes includes more than four contact probes.

7. The method of claim 1 , wherein the first conductive or semiconductive layer comprises a wafer substrate.

8. The method of claim 1 , wherein the semiconductive layer in the bottom layer is a wafer substrate.

9. The interface layer has a resistance of 1000 ohm μm ２ The method of claim 1 , wherein the resistor-area product is greater than

10. The resistor area product is 10 megaohms μm ２ The method of claim 9 , wherein the

11. The method of claim 1 , wherein the microscopic multi-terminal probe has a distance between adjacent contact probes of at least 4 μm.

12. The method of claim 11 , wherein the microscopic multi-terminal probe has a distance between the two outermost ones of the contact probes of less than 3 mm.

13. The method of claim 1 , wherein the interface layer has a thickness greater than 2 nm.

14. The method of claim 1 , wherein the interfacial layer has a conductivity that is less than 10 times that of the bottom layer or the top layer.

15. The method of claim 1 , wherein the model constitutes an electrical equivalent circuit of the first conductive or semiconductive layer, the interface layer, and the second conductive or semiconductive layer.

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