Quantum bit control method and quantum computer

Abstract

To selectively perform a two-quantum bit logic gate operation on two quantum bits that have a gate in common.SOLUTION: When performing a two-quantum bit operation on a plurality of quantum bit pairs via a plurality of barrier transistors that are controlled collectively, a method of controlling a quantum bit selectively performs a two-quantum bit operation on a desired quantum bit pair selected from the plurality of quantum bit pairs by selectively performing one-quantum bit on a quantum bit selected from the plurality of quantum bit pairs.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The present invention relates to a method for controlling integrated quantum bits. [Background technology]

[0002] Quantum computers are attracting attention because they are capable of faster information processing than existing computers. Whereas existing computers only handle the binary values ​​of 0 and 1, quantum computers are characterized by their ability to handle superposition states of these two values. Quantum operations are realized by performing appropriate operations on each quantum bit or two quantum bits. In computer science, it is known that any operation can be realized by combining two types of one-qubit operations (one quantum gate operation) and one type of two-qubit operation (two quantum gate operation).

[0003] Semiconductor quantum bits are quantum bits born from the silicon semiconductor engineering that underpins our modern information society. Semiconductor quantum bits use electrostatic effects to capture a single electron and associate the spin direction of that electron with a value of 0 or 1. There are two methods for integrating semiconductor quantum bits: one is to provide each quantum bit with an individual gate electrode for electron capture, and the other is to arrange the quantum bits in an array using a common gate electrode for multiple quantum bits.

[0004] The former method remains merely an idea due to the difficulty of wiring, while the latter has been demonstrated. Regarding the latter, Patent Document 1 proposes expanding quantum bits to two dimensions. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-27142 Summary of the Invention [Problem to be solved by the invention]

[0006] As mentioned in the background art, the common gate electrode type quantum processor can increase integration, but at the cost of individual controllability of quantum bits due to the common gate electrode. To perform calculations on a quantum computer, it is necessary to be able to execute two types of one-qubit logic gates and one type of two-qubit logic gate on the quantum processor.

[0007] However, in a quantum processor using a common gate electrode, a two-qubit logic gate cannot be selectively implemented for two or more qubits. A swap logic gate (SWAP gate), which swaps the states of two qubits, is a typical two-qubit logic gate. The operation performed by the SWAP gate operation is called the swap logic operation.

[0008] In a quantum processor using a common gate electrode, it is not possible to perform an exchange logic gate on one quantum bit pair, but instead the exchange logic gate is applied to multiple quantum bit pairs simultaneously.

[0009] Thus, in a quantum processor using the common gate electrode method, it is difficult to provide the logic gates required by a quantum computer, and this is a problem that must be solved in order for it to function as a quantum computer.

[0010] Therefore, an object of the present invention is to selectively perform a two-qubit logic gate operation on two qubits that have a gate in common. [Means for solving the problem]

[0011] A preferred aspect of the present invention is a method for controlling quantum bits, in which, when a two-qubit operation is performed on multiple pairs of quantum bits using multiple barrier transistors controlled collectively, a single-qubit operation is selectively performed on a quantum bit selected from the multiple pairs of quantum bits, thereby selectively performing a two-qubit operation on a desired quantum bit pair selected from the multiple pairs of quantum bits.

[0012] Another preferred aspect of the present invention is a quantum computer comprising a quantum processor, a drive unit for driving the quantum processor, and a computer for controlling the quantum processor and the drive unit, and performing a quantum gate operation on a quantum bit, wherein the quantum processor comprises transistors for performing the quantum gate operation, the transistors have a gate electrode shared by each of a plurality of transistors, and the quantum gate operation is controlled by an electrical signal applied to the gate electrode and microwave irradiation, and at least one of the computer and the drive unit has a function of decomposing a desired quantum gate operation into element quantum gate operations, and the desired quantum gate operation is realized by performing the element quantum gate operation on the quantum bit. Effect of the Invention

[0013] This makes it possible to selectively perform two-qubit logic gate operations on two qubits that have a gate in common. [Brief description of the drawings]

[0014] [Figure 1] Diagram of a quantum bit that uses the electron spin state. [Diagram 2] Three-view diagram of the basic structure of an electron spin quantum bit semiconductor device. [Diagram 3] Circuit diagram of a quantum processor consisting of electron spin qubits using a common gate system. [Figure 4] A conceptual diagram of a quantum computer. [Diagram 5] Diagram of the state of a qubit before and after an inversion logic gate. [Figure 6A] An illustration of how to implement an inversion logic gate on a quantum processor. [Figure 6B] A diagram explaining the principle of quantum bit resonant reaction. [Figure 6C] FIG. 1 is a graph illustrating the principle of controlling the resonance frequency of a quantum bit. [Figure 6D] A diagram explaining the principle of applying a magnetic field to a quantum bit by controlling the current. [Figure 6E] A diagram showing the principle of how a magnetic field can be selectively applied to a qubit in a two-dimensional plane. [Figure 7] Flow diagram of the implementation procedure for an inversion logic gate. [Figure 8] Diagram of the state of a qubit before and after a switching logic gate. [Figure 9] An illustration of how to implement a switching logic gate on a quantum processor. [Figure 10] A flow diagram of the implementation procedure of a switched logic gate. [Figure 11] Diagram of the qubit states before and after an equivalent two-qubit logic gate. [Figure 12] Quantum circuit diagram illustrating how to realize an equivalent two-qubit logic gate. [Figure 13] Circuit diagram of a quantum processor illustrating how an equivalent two-qubit logic gate can be realized. [Figure 14] Quantum circuit diagram illustrating alternative realizations of equivalent two-qubit logic gates. [Figure 15] 1 is a flow diagram illustrating an alternative realization of an equivalent two-qubit logic gate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The following describes the embodiments in detail with reference to the drawings. However, the present invention should not be interpreted as being limited to the description of the embodiments shown below. It is easily understood by those skilled in the art that the specific configuration of the present invention can be changed without departing from the concept or purpose of the present invention.

[0016] In the configuration of the invention shown below, the same parts or parts with similar functions are designated by the same reference numerals in different drawings, and duplicated explanations may be omitted. When there are multiple elements with the same or similar functions, they may be explained with different suffixes. However, there may be cases where the suffixes are omitted.

[0017] The designations "first," "second," "third," and the like in this specification are used to identify components and do not necessarily limit the number, order, or content. Furthermore, numbers for identifying components are used in different contexts, and a number used in one context does not necessarily indicate the same configuration in another context. Furthermore, a component identified by a certain number does not prevent consideration of the function of a component identified by another number.

[0018] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings, etc. may not show the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings, etc.

[0019] As will be described in detail in the following embodiment, one example of the embodiment realizes the required logic gate equivalently by combining multiple operations. Two-qubit operations are realized by turning on the inter-qubit coupling in a qubit pair. An integrated structure of semiconductor qubits (hereinafter referred to as a qubit array) can simultaneously turn on / off the inter-qubit coupling strength in multiple qubit pairs. In each qubit pair, the coupling between the qubits acts to exchange the states of the qubits (hereinafter referred to as a swap). Repeating a swap twice is equivalent to doing nothing. However, if another operation is inserted between the swaps, the original state cannot be restored. Using this, two-qubit operations are performed only on a specific qubit pair. EXAMPLES

[0020] 1 to 11 are diagrams for explaining the first embodiment.

[0021] Figure 1 shows an example of an electron spin or hole spin state and the value associated with it. Symbol 101, consisting of a circle and arrow in the figure, is a stylized image of electron spin. In this way, electron spin is expressed as a vector. The base of the vector is the downward spin state (down state) and upward spin state (up state), and for example, each is associated with the numerical values ​​1 and 0.

[0022] Controlling electron spin, for example by changing the spin state associated with a numerical value from an up state to a down state, is the operation of a quantum computer. A distinctive feature of quantum bits is their ability to create a superposition of up and down states. Dealing with superpositions of 0 and 1 is one of the features of quantum computers.

[0023] Figure 2 shows three-orthographic views of the basic physical structure of a semiconductor quantum bit, showing the top surface of the substrate, the A-A' cross section, and the B-B' cross section.

[0024] The semiconductor quantum bit is composed of gate electrodes 201-1 to 201-5, an insulating layer 202, and a semiconductor layer 203. This structure is similar to that of an electrostatic effect transistor. A voltage is applied to gate electrode 201 to trap electrons in semiconductor layer 203 by the electrostatic effect. These electrons are used as quantum bits. Conversely, electrons can also be expelled by applying a negative voltage.

[0025] Electrons are arranged in an orderly manner by combining trapping and expulsion. Electrons are trapped in the valley of electrostatic potential 204 in Fig. 2. During two-qubit operations, the height of the potential hill separating the two electrons is controlled by the voltage applied to gate electrode 201-3, thereby controlling the quantum bit.

[0026] 3 is a diagram showing how a quantum processor 304 is described as a transistor circuit. This circuit diagram shows how the transistors that make up the quantum processor are arranged on a two-dimensional plane, and is described using three types of transistors 301 to 303. The transistors in each row and column of the matrix in FIG. 3 have a device structure as shown in FIG. 2.

[0027] For the sake of explanation, each line that makes up the matrix is ​​numbered as 13 rows x 9 columns as shown in the figure to explain its position. The number of rows and columns is just an example and has no particular meaning. Rows are numbered 1 to 13 from the top, and columns are numbered 1 to 9 from the left.

[0028] The two-terminal transistor 301 represents a transistor for trapping electrons. The black dots in the two-terminal transistor 301 in the figure represent electrons. The two-terminal transistor 301 has two terminals and one gate, and traps a single electron.

[0029] The four-terminal transistor 302 also represents a transistor for trapping electrons, but its channel is connected in four directions: up, down, left, and right. In other words, it has four terminals and one gate. This four-way connection makes it possible to configure the quantum processor in Figure 3 in two dimensions. The black dots in the four-terminal transistor 302 in the figure represent electrons.

[0030] The barrier transistor 303 represents a transistor for removing electrons. This transistor corresponds to 201-3 in Fig. 2, and a two-qubit operation is executed by changing the gate voltage of this transistor.

[0031] 3 are common gate lines for the barrier transistor 303. In FIG. 2, these correspond to the gate electrode 201-3.

[0032] Columns 2 and 8 in Fig. 3 are channel paths of the four-terminal transistor 302 and the barrier transistor 303. In Fig. 2, they correspond to the semiconductor layer 203. The rows and columns of the channel paths are connected, and the four-terminal transistor 302 is connected to channels in four directions.

[0033] 3 are common gate lines for the two-terminal transistor 301. In FIG. 2, these correspond to the gate electrode 201-3.

[0034] 3 are common gate lines for the barrier transistor 303. In FIG. 2, these correspond to the gate electrode 201-3.

[0035] 3 are common gate lines for the four-terminal transistor 302. In FIG. 2, these correspond to the gate electrode 201-3.

[0036] 3 are channel paths of the two-terminal transistor 301, the four-terminal transistor 302, and the barrier transistor 303. These correspond to the semiconductor layer 203 in FIG.

[0037] As is well known, the semiconductor layer 203 is maintained at a predetermined voltage to operate the transistors. Also, the row and column gate lines are separated.

[0038] In addition to using these three types of transistors, the features of Figure 3 are that the transistors share gate electrodes 305 and 306. This arrangement of transistors sharing the gate electrodes enables a two-dimensional arrangement of the quantum processor. Note that the arrangement of the transistors in Figure 3 is merely one example.

[0039] Fig. 4 shows a configuration diagram of an entire quantum computer system including the quantum processor of Fig. 3. The quantum computer system includes the quantum processor 304 described in Fig. 3.

[0040] The quantum computer system is equipped with a microwave antenna 402 necessary for controlling the quantum processor 304. A driving unit 401 is provided as a circuit for driving the quantum processor 304 and the antenna 402. The driving unit 401 is controlled by an ordinary computer 403. The computer 403 instructs the quantum processor 304 to perform a desired quantum operation according to a program. A communication path 404 is provided between the driving unit 401 and the computer 403.

[0041] The method by which the quantum processor performs quantum operations using the above structure and configuration will be described below, divided into one-qubit operations (Figs. 5 to 7) and two-qubit operations (Figs. 8 to 12). First, an example of a one-qubit operation will be described.

[0042] Figure 5 describes the changes in the state of electrons and the state of quantum bits before and after a one-qubit operation. There are various known one-qubit operations, such as an inversion gate (X gate) and a phase rotation gate (Z gate). An inversion gate, which is an example of a one-qubit operation, is an operation that changes the initial state from 0 to 1, and from 1 to 0. In other words, it is an operation that inverts the state of a quantum bit (an inversion operation).

[0043] 6A is a diagram for explaining the operation of the quantum processor 304 during one quantum bit operation. For the sake of explanation, the positions of the lines constituting the matrix are explained by assigning numbers of 13 rows and 9 columns as shown in the figure. The numbers of rows and columns are merely examples and have no particular meaning.

[0044] The quantum bit to be operated on is the quantum bit one to the right and one below from the upper left corner indicated by the white circle (the intersection of 6 rows and 4 columns). When operating on one quantum bit, voltage is applied to the left and right, top and bottom lines of the gate electrode line (V x1+ , V x1- , V y1+ , V y1- ) A current is passed through the gate electrode. Then, microwaves 601 are irradiated from antenna 402 to the quantum bit.

[0045] In this example, specifically, to change the quantum state of two-terminal transistors 301 at the intersections of six rows and four columns, a voltage is applied to each terminal of the common gate line of four-terminal transistors 302 in the fifth row and the common gate line of barrier transistors 303 in the seventh row, causing a current to flow in the direction of the arrow. Also, a voltage is applied to each terminal of the common gate line of barrier transistors 303 in three columns and the common gate line of barrier transistors 303 in the fifth column, causing a current to flow in the direction of the arrow.

[0046] As a result, the quantum bit in the circulating current is irradiated with microwaves 601, enabling selective single quantum bit operation. The principle by which selective gate operation on a single quantum bit becomes possible will be described in detail below.

[0047] The state of a quantum bit can be controlled by microwaves. However, the quantum bit will flip its state in response to the microwaves only if the quantum bit's resonant frequency matches the microwave frequency. This resonant response to frequency is one of the characteristics of quantum bits.

[0048] Fig. 6B is a principle diagram explaining the principle of the resonant reaction of a quantum bit. By utilizing this principle, as shown in Fig. 6B, if there are two quantum bits and their respective resonant frequencies are f1 and f2, it is possible to selectively invert the state of only the quantum bit with the resonant frequency f1 by irradiating microwaves with frequency f1. In this way, by controlling the irradiated microwaves and the resonant frequency of the quantum bits, it is possible to enable selective gate operation constituting the quantum computer of the embodiment.

[0049] FIG. 6C is a graph illustrating the principle of controlling the resonance frequency of a quantum bit. This resonance frequency can be controlled by a magnetic field applied to the quantum bit. FIG. 6C illustrates the relationship between the magnetic field applied to the quantum bit and the resonance frequency of the quantum bit. By utilizing this relationship, when it is desired to perform selective gate operation of quantum bits, that is, when it is desired to create a difference in the resonance frequency between quantum bits, this can be realized by applying a magnetic field to the quantum bit to be controlled.

[0050] Figure 6D is a diagram explaining the principle of applying a desired magnetic field to a quantum bit by controlling the current. When there are two wires, A and B, on either side of the quantum bit, currents I1 and I2 in opposite directions are passed through each wire. In this way, in the region 611 between the two wires, the magnetic fields B1 and B2 generated by the currents reinforce each other, while in the other regions 610 and 612, the magnetic fields weaken each other. This makes it possible to selectively apply a magnetic field to the quantum bit in the diagram.

[0051] Fig. 6E expands Fig. 6D to show a method for selectively applying a magnetic field to quantum bits in a two-dimensional plane. In this case, by passing a current through wiring that is laid out vertically and horizontally, it is possible to selectively apply a magnetic field to quantum bits in an area 6000 shown by a dotted line in the figure.

[0052] Figure 7 is a flowchart describing the flow of one quantum bit operation. The initial state is a state in which an appropriate constant voltage is applied to each gate voltage (S701).

[0053] Next, a voltage is applied to both ends of each gate electrode so that a current flows through the gate electrode (S702).

[0054] Next, microwaves are applied (S703). After a certain period of time has passed, the microwave application is stopped (S704). After that, the gate voltage is returned to its original state so that no current flows through the gate electrode (S705). Note that during this series of steps, the voltage applied to cause current to flow through the gate electrode is allowed to fluctuate.

[0055] We will now discuss the algebraic description of one-qubit operations realized by the above configuration and method. Quantum logic gates can be described using linear algebra. In other words, they can be expressed as matrices. As a prerequisite, the two bit states, 0 and 1, are described by the vectors of Equation 1 and Equation 2, respectively.

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[0058] Equation 3 is the mathematical description of the quantum logic gate (inverter gate) corresponding to Figure 5. Other kinds of one-qubit operations can also be described in matrix form.

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[0060] The quantum logic gate of formula 3 is shown as a matrix, but it can be decomposed into multiple matrix operations. For example, the quantum logic gate of formula 3 can be decomposed into the quantum logic gates of formulas 4 to 7. Formulas 4 to 7 are all operations that, when executed twice in succession as shown in formula 8, result in the one-qubit gate of formula 3. Each operation can be generated by adjusting the microwave irradiation time and phase.

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[0066] Next, we will describe two-qubit operations. Various types of two-qubit operations are also known. Here, we will present the method of the controlled phase rotation gate (CZ gate) as an example. To do this, we will first explain the non-selective exchange logic gate (SWAP gate) for the CZ gate.

[0067] Figure 8 shows the state of electrons and the state of quantum bits before and after the operation of a SWAP gate, a typical two-qubit operation. A SWAP gate is a quantum logic gate that acts on two quantum bits, and swaps the states of the two quantum bits. This SWAP gate only swaps states, and does not swap two electrons.

[0068] Figure 9 is a diagram explaining the operation of a quantum processor when using a SWAP gate. The quantum bits to be used with the SWAP gate are the pair of quantum bits one to the right and one below from the top left corner (the intersection of 6 rows and 4 columns) and the pair of quantum bits two to the right and two below from the top left corner (the intersection of 6 rows and 6 columns), both of which are indicated by white circles.

[0069] To operate the SWAP gate for this quantum bit, the voltage of the gate electrode of the barrier transistor separating these two quantum bits is changed to Vx for a certain period of time. The feature of this calculation method is that it also affects quantum bit pairs other than those mentioned above (all of the two-terminal transistors 301 on the lines in columns 4 and 6).

[0070] For example, the same operation is performed on the quantum bit one to the right of the upper left corner of the quantum processor (the intersection of row 3, column 4) and the quantum bit two to the right (the intersection of row 3, column 6). This is because the gate electrodes of the transistors separating the quantum bit pairs (the line in the fifth column) are shared. In other words, this SWAP gate is not selective for the desired quantum bit pair, but is a non-selective quantum logic gate for multiple quantum bit pairs. This is a characteristic of a quantum processor with shared gates.

[0071] Figure 10 is a flowchart describing the flow of a non-selective SWAP quantum bit operation. In the initial state, an appropriate constant voltage is applied to each gate electrode (S1001). Next, a voltage is applied to the gate electrode (S1002). After a certain period of time has passed, the gate voltage is returned to its original state (S1003).

[0072] The following describes an algebraic description of the two-qubit operation realized by the above configuration and method. As a premise, the two-bit states 00, 01, 10, and 11 are described by the vectors of Equations 9 to 12, respectively.

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[0077] Equation 13 is the mathematical description of the SWAP gate corresponding to FIG.

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[0079] An example of two-qubit operations is also described in Patent Document 1, for example. For the sake of later explanation, an example is shown in which the quantum logic gate of formula 13 is decomposed into multiple quantum logic gates. Here, a quantum logic gate equivalent to half of the quantum logic gate of formula 13 is explained. The quantum logic gate of formula 14 can be realized by adjusting the time applied to the gate electrode, and when it is operated twice as in formula 15, it becomes equivalent to formula 13.

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[0082] The SWAP qubit operation, which acts on multiple qubit pairs simultaneously due to the commonality of gate electrodes, has an obstacle when used for quantum operations. Below, we explain an example in which multiple quantum logic gates are combined to effectively perform selective two-qubit operations on two qubit pairs.

[0083] Figure 11 shows the quantum bit states before and after the action of a selective quantum logic gate that is effectively realized. This quantum logic gate is a quantum logic gate that changes the quantum phase of the right quantum bit TB (hereinafter referred to as the first quantum bit (target bit)) depending on the state of the left quantum bit CB (hereinafter referred to as the second quantum bit (control bit)). In the case of a CZ gate, the first quantum bit is made to act as a phase rotation gate (Z gate) only when the second quantum bit is 1. The algebraic description is as shown in Equation 16.

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[0085] Figure 12 shows a method for realizing the quantum logic gate of Figure 11. A-1 shows a CZ gate as a gate procedure diagram. A-2 is the procedure for actually realizing this. The quantum logic gate of A-1 can be effectively realized by combining and using the 1-qubit and 2-qubit quantum logic gates already explained.

[0086] In the example of Figure 12, the quantum logic gate of the CZ gate is realized by combining the quantum logic gates of Equations 4 to 7 and 14. Although the inversion gate and SWAP gate are previously decomposed into multiple quantum logic gates, it is believed that subdividing the operations will improve the degree of freedom to create any operation by combination.

[0087] In this embodiment, for quantum bits that do not perform quantum operations among the quantum bits that share a gate, half the operation of the SWAP gate in formula 14 is performed four times as a two-qubit gate. Since this is equivalent to applying the SWAP gate twice, the quantum bits return to their original state, that is, it acts as an identity operator (I gate) and the result does not change. The quantum bits also return to their original state when an operation equivalent to applying the SWAP gate an even number of times is performed. It does not have to be equivalent to applying the SWAP gate twice, for example, half the operation of the SWAP gate can be performed eight times, as long as it is equivalent to applying the SWAP gate an even number of times.

[0088] Of the qubits that share a gate, the qubit that performs the quantum operation must also perform half the operation of the SWAP gate in Equation 14 four times as a two-qubit gate like the other qubits due to the structure of the device. However, for the qubit that performs the quantum operation, a one-qubit operation is performed on the first qubit (target bit). The one-qubit operation can be selectively executed using the method described in Figure 6.

[0089] FIG. 13 shows the case where a CZ quantum gate is selectively performed on the quantum bit pair of Q3 and Q4.

[0090] FIG. 14 shows quantum operations performed on each of the quantum bits Q1 to Q8 when selectively performing a CZ quantum gate.

[0091] FIG. 15 is a flow chart showing the process performed by the quantum circuit of FIG. 13 in order to perform the quantum operation of FIG.

[0092] When a voltage of Vx is applied to gate electrode 1301 of barrier transistor 303 in Fig. 13 to operate a √S quantum gate, this quantum gate operates on four quantum bit pairs: Q1 and Q2, Q3 and Q4, Q5 and Q6, and Q7 and Q8. This non-selectivity is due to the common gate electrode and is unavoidable structurally.

[0093] However, when a series of quantum gates are applied as shown in Fig. 14, √S is applied four times to Q1 and Q2, Q5 and Q6, and Q7 and Q8, respectively. According to Equation 15 and Equation 13, this is equivalent to no quantum gates being applied, so this series of quantum gates is equivalent to only applying it to Q3 and Q4 as shown in Fig. 14. In this way, it is possible to apply two-qubit operations only to the desired qubit pair.

[0094] As described above, the ability to perform one-qubit operations and selective two-qubit operations enables arbitrary qubit operations even in a quantum processor with a common wiring system.

[0095] The equivalent conversion operation may be instructed by the computer 403 in Fig. 4, or may be instructed by the driving unit 401. Note that there are electrons and holes as carriers in semiconductors. Holes may be used instead of electrons.

[0096] According to the above embodiment, it is possible to realize an energy-efficient quantum computer, which consumes less energy, reduces carbon emissions, prevents global warming, and contributes to the realization of a sustainable society. [Explanation of symbols]

[0097] 101...Electron spin or quantum bit 201 Gate electrode 202: Insulating layer 203 Semiconductor layer 204...Electrostatic potential 205...Insulator 301...Two-terminal transistor 302...4-terminal transistor 303 Barrier transistor 304 Quantum Processor 401 Drive unit 402 Microwave antenna 403...Computer 404...Communication path 601...Microwave

Claims

1. A quantum computer comprising a quantum processor and a microwave antenna, The quantum processor includes: a plurality of transistors for performing quantum gate operations on the plurality of semiconductor qubits; a plurality of common gate lines each having a gate electrode common to each of the plurality of transistors; Equipped with applying a magnetic field to the semiconductor quantum bit to be calculated by passing a current through the plurality of common gate lines located to the left and right or above and below the semiconductor quantum bit to be calculated; The microwave antenna irradiates microwaves onto the semiconductor quantum bit. A quantum computer characterized by:

2. applying a magnetic field to the semiconductor quantum bit of the operation target by passing current through the plurality of common gate lines located to the left and right and above and below the semiconductor quantum bit of the operation target; 2. The quantum computer of claim 1.

3. A magnetic field is applied to the semiconductor quantum bit to control a resonant frequency of the semiconductor quantum bit, thereby performing selective gate operation of the semiconductor quantum bit.

2. The quantum computer of claim 1.

4. applying a magnetic field to the semiconductor quantum bit by passing currents in opposite directions through the common gate lines located on both sides of the semiconductor quantum bit to be calculated; 2. The quantum computer of claim 1.

5. flowing currents in opposite directions through the common gate lines located on the left and right of the semiconductor quantum bit to be operated on; applying a magnetic field to the semiconductor quantum bit by passing currents in opposite directions through the plurality of common gate lines located above and below the semiconductor quantum bit to be operated on; 3. The quantum computer according to claim 2.

6. A driving unit that drives the quantum processor and the microwave antenna, and a general computer that controls the quantum processor and the driving unit, 2. The quantum computer of claim 1.

7. At least one of the conventional computer and the driver has a function of decomposing a desired quantum gate operation into elementary quantum gate operations; A desired quantum gate operation is realized by performing the elementary quantum gate operation on the semiconductor quantum bit.

7. The quantum computer according to claim 6.

8. When performing quantum gate operations on a plurality of pairs of the semiconductor quantum bits by the plurality of transistors, performing a first elementary quantum gate operation on a first pair of semiconductor quantum bits selected from the plurality of pairs of semiconductor quantum bits to realize a first quantum gate operation; performing a second elementary quantum gate operation on a second pair of semiconductor quantum bits selected from the plurality of pairs of semiconductor quantum bits to realize a second quantum gate operation; The quantum computer of claim 7.

9. The application of a magnetic field to any one of the plurality of semiconductor quantum bits is performed by a current flowing through a gate electrode that two-dimensionally surrounds the semiconductor quantum bit. The quantum computer of claim 1 .

10. A quantum bit control method for performing quantum bit operations on a plurality of semiconductor quantum bits by using a plurality of common gate lines having gate electrodes in common, comprising: When performing a one-qubit operation on a semiconductor quantum bit selected from the plurality of semiconductor quantum bits, applying a magnetic field to the selected semiconductor quantum bit by passing a current through the common gate lines located to the left and right or above and below the selected semiconductor quantum bit; Irradiating the semiconductor quantum bit with microwaves; A method for controlling a quantum bit.

11. When performing a one-qubit operation on a semiconductor quantum bit selected from the plurality of semiconductor quantum bits, applying a magnetic field to the selected semiconductor quantum bit by passing current through the common gate lines located to the left, right, top and bottom of the selected semiconductor quantum bit; The method for controlling a quantum bit according to claim 10.

12. When performing a one-qubit operation on a semiconductor quantum bit selected from the plurality of semiconductor quantum bits, flowing currents in opposite directions through the common gate lines located on the left and right of the selected semiconductor quantum bit; applying a magnetic field to the semiconductor quantum bit by passing currents in opposite directions through the common gate lines located above and below the selected semiconductor quantum bit; The method for controlling a quantum bit according to claim 10.

13. When performing a two-qubit operation on a pair of semiconductor qubits selected from the plurality of semiconductor qubits, performing an even number of exchange logic operations on the semiconductor quantum bit pair, and performing a further one-qubit operation on at least one quantum bit of the semiconductor quantum bit pair; The method for controlling a quantum bit according to claim 10.

14. By decomposing one exchange logic operation into a plurality of two-qubit operations and executing the same, the exchange logic operation is effectively performed twice.

14. The method of claim 13, wherein the quantum bit is a quantum bit.

15. By decomposing one exchange logic operation into a plurality of two-qubit operations and executing the same, the exchange logic operation is effectively performed twice.

15. The method of claim 14, wherein the quantum bit is a quantum bit.

16. The one-qubit operation is a decomposition of an inversion operation.

14. The method of claim 13, wherein the quantum bit is a quantum bit.

17. A two-qubit operation is selectively performed on the selected semiconductor qubit pair by controlling a controlled phase rotation gate operation.

17. The method of claim 16, wherein the quantum bit is a quantum bit.

18. performing a first elementary quantum gate operation on a first pair of semiconductor quantum bits selected from the plurality of semiconductor quantum bits to realize a first quantum gate operation; performing a second elementary quantum gate operation on a second pair of semiconductor quantum bits selected from the plurality of semiconductor quantum bits to realize a second quantum gate operation; The first element quantum gate operation is a decomposition of a SWAP gate operation for the first semiconductor quantum bit pair and a decomposition of a one-qubit gate operation for any quantum bit of the first semiconductor quantum bit pair; The second element quantum gate operation is a decomposition of a SWAP gate operation for the second semiconductor quantum bit pair, and the second quantum gate operation does not change the state of the second semiconductor quantum bit pair.

14. The method of claim 13, wherein the quantum bit is a quantum bit.

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