Quantum operation device and method for manufacturing the same

Abstract

A quantum computing device (10) comprises: a first substrate (30) having a through-hole (32A, 32B); a qubit element (20) formed on a first surface (S1) of the substrate (30); a cover (50) covering the first surface (S1) side of the first substrate (30); and a second substrate (40) provided on a second surface (S2) side of the first substrate (30) opposite the first surface (S1) side, and closing an opening end of the through-hole (32A, 32B) on the second surface (S2) side. A sealed space (51) surrounding the qubit element (20) and communicating with the through-hole (32A, 32B) is provided between the first surface (S1) and the cover (50).

Description

[Technical field]

[0001] The disclosed technology relates to a quantum processing device and a method for manufacturing a quantum processing device. [Background technology]

[0002] The following techniques are known as techniques related to quantum computing devices. For example, a technique is known in which a confinement layer is bonded to a substrate on which a quantum bit element is formed, and a sealed vacuum cavity is formed between the confinement layer and the substrate.

[0003] Stacked quantum computing devices are also known in which a first chip contains superconducting qubits and is coupled to a second chip that contains one or more wiring layers and qubit control and qubit readout elements integrated with a lossy dielectric. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2019-532520 [Patent Document 2] Special Publication No. 2020-511794 Summary of the Invention [Problem to be solved by the invention]

[0005] A quantum bit element (Qubit) that constitutes a quantum computing device is known to use a transmon. The transmon has a configuration in which a superconducting Josephson element and a capacitor are connected in parallel, and performs quantum computing using nonlinear energy. Since the transmon operates with extremely small energy, it is easily affected by noise from the outside world. The time that the transmon can continue quantum computing is called the coherence time. The coherence time is sensitively affected by the state around the transmon. For example, if a dielectric such as an oxide film exists around the transmon, the coherence time will be shortened due to dielectric loss. For this reason, it is common not to form an insulating film such as a protective film on the surface of the transmon. A quantum computing device that includes a quantum bit element is kept at an extremely low temperature in a vacuum chamber, but adsorbates that are adsorbed in the atmosphere and cause decoherence will remain cooled as they are. Since the coherence time is shortened by adsorbates adsorbed on the surface of the quantum bit element, it is necessary to always keep the surface of the quantum bit element clean.

[0006] The disclosed technique aims to keep the surface of a quantum bit element clean in a quantum computing device. [Means for solving the problem]

[0007] The quantum computing device according to the disclosed technique includes a first substrate having a through hole, a quantum bit element formed on a first surface of the substrate, a cover covering the first surface side of the first substrate, and a second substrate provided on a second surface side of the first substrate opposite to the first surface side and closing an open end of the through hole on the second surface side. A sealed space is provided between the first surface and the cover, surrounding the quantum bit element and communicating with the through hole. Effect of the Invention

[0008] According to the disclosed technique, it is possible to keep the surface of a quantum bit element clean in a quantum computing device. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view illustrating an example of a configuration of a quantum processing device according to an embodiment of the disclosed technique. [Diagram 2] FIG. 1 is a diagram illustrating an example of a circuit configuration of a quantum bit element according to an embodiment of the disclosed technique. [Diagram 3] FIG. 1 is a diagram illustrating an example of a connection configuration between quantum bit elements according to an embodiment of the disclosed technique. [Figure 4] 1 is a diagram illustrating an example of a circuit configuration of a resonator according to an embodiment of the disclosed technique. [Diagram 5] 1 is a schematic cross-sectional view showing an example of a configuration of a quantum processing device according to an embodiment of the disclosed technique. [Figure 6] 10A and 10B are plan views showing an example of a form of a seal member that forms a joint between a cover and a first substrate according to an embodiment of the disclosed technique. [Figure 7] 1A and 1B are plan views showing examples of configurations of a sealing member and a conductive pad according to an embodiment of the disclosed technique; [Figure 8] 1 is a plan view showing an example of an arrangement of through vias, sealing members, control electrodes, and bumps on a first substrate according to an embodiment of the disclosed technique. [Figure 9] 1 is a plan view showing an example of an arrangement of through vias, conductive pads, and bumps on a second substrate according to an embodiment of the disclosed technique. [Figure 10] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 11] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 12] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 13] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 14] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 15] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 16] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 17] 1 is a schematic cross-sectional view showing an example of a configuration of a quantum processing device according to an embodiment of the disclosed technique. [Figure 18] 10A and 10B are plan views showing an example of a form of a seal member that forms a joint between a cover and a first substrate according to an embodiment of the disclosed technique. [Figure 19] 1 is a schematic cross-sectional view showing an example of a configuration of a quantum processing device according to an embodiment of the disclosed technique. [Figure 20] 10A and 10B are plan views showing an example of a form of a seal member that forms a joint between a cover and a first substrate according to an embodiment of the disclosed technique. [Figure 21] 1 is a plan view showing an example of a pattern of a capacitor provided on a path of an inter-bit wiring according to an embodiment of the disclosed technique; [Figure 22] 1 is a schematic cross-sectional view showing an example of a configuration of a quantum processing device according to an embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and duplicated descriptions will be omitted.

[0011] [First embodiment] 1 is a plan view showing an example of a configuration of a quantum processing device 10 according to an embodiment of the disclosed technique. The quantum processing device 10 has a quantum bit element (Qubit) 20, a resonator 21, and a readout electrode 22 provided on a first substrate 30.

[0012] The quantum bit element 20 is an element that forms a coherent two-level system using superconductivity. FIG. 2 is a diagram showing an example of a circuit configuration of the quantum bit element 20. The quantum bit element 20 performs quantum operations using nonlinear energy, and is configured to include a transmon quantum bit circuit in which a superconducting Josephson element 201 and a capacitor 202 are connected in parallel. The superconducting Josephson element 201 is configured to include a pair of superconductors that exhibit superconductivity at a temperature equal to or lower than a predetermined critical temperature, and an extremely thin insulator having a thickness of about several nm sandwiched between the pair of superconductors. The superconductor may be, for example, aluminum, and the insulator may be, for example, aluminum oxide. As shown in FIG. 3, in the quantum operation device 10, a plurality of quantum bit elements 20 are connected to other adjacent quantum bit elements 20 via inter-bit wiring 24. A capacitor 23 is provided on the path of the inter-bit wiring 24. As a result, each of the quantum bit elements 20 creates a quantum entangled state with the other adjacent quantum bit element 20 to perform quantum operations.

[0013] The resonator 21 interacts with the quantum bit element 20 to read out a bit signal indicating the state of the quantum bit element 20. The resonator 21 is connected to the quantum bit element 20 via a capacitor (not shown). FIG. 4 is a diagram showing an example of a circuit configuration of the resonator 21. The resonator 21 includes a resonance circuit in which a superconducting inductor 211 and a capacitor 212 are connected in parallel. The read electrode 22 is an electrode connected to the resonator 21 and used to extract the bit signal read out by the resonator 21 to the outside.

[0014] Fig. 5 is a schematic cross-sectional view showing an example of the configuration of the quantum processing device 10. Note that the resonator 21 (see Fig. 1) is omitted in Fig. 5. Fig. 4 shows only the peripheral configuration of one quantum bit element 20. The quantum processing device 10 has a configuration in which a first substrate 30, a second substrate 40, and a cover 50 are stacked.

[0015] The quantum bit element 20 is mounted on the first surface S1 of the first substrate 30. No insulating film that causes dielectric loss is provided on the surface of the quantum bit element 20. The resonator 21, not shown in FIG. 5, may be mounted on the first surface S1 of the first substrate 30. The first substrate 30 is provided with through vias 31A and 31B. The through vias 31A and 31B include through holes 32A and 32B that penetrate the first substrate 30, respectively, and conductive films 33A and 33B that cover the inner walls of the through holes 32A and 32B. The conductive films 33A and 33B have portions that extend to the first surface S1 of the first substrate 30 and the second surface S2 opposite to the first surface S2.

[0016] The through via 31A is used to supply a ground potential to the first substrate 30 and the cover 50. The through via 31B functions as a readout electrode 22. A control electrode 37 to which a quantum bit control signal for controlling the quantum bit element 20 is supplied is provided on the second surface S2 of the first substrate 30. The control electrode 37 is disposed directly below the quantum bit element 20 mounted on the first surface S1, and the quantum bit control signal supplied to the control electrode 37 is transmitted to the quantum bit element 20 via the base material of the first substrate 30.

[0017] An insulator or a semiconductor can be used as the base material of the first substrate 30, and silicon, for example, can be preferably used. The conductive films 33A, 33B and the control electrode 37 constituting the through vias 31A, 31B are preferably made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature. For example, Nb (niobium) can be preferably used as such a metal.

[0018] The cover 50 covers the first surface S1 side of the first substrate 30. The cover 50 forms a sealed space 51 around the quantum bit element 20 and the readout electrode 22. A recess for forming the sealed space 51 may be formed in the portion of the cover 50 facing the quantum bit element 20 and the readout electrode 22. The sealed space 51 communicates with the through holes 32A and 32B. The sealed space 51 is preferably a vacuum. By making the sealed space 51 a vacuum, it is possible to suppress the adsorption of a substance to the quantum bit element 20 without forming a protective film that causes dielectric loss on the surface of the quantum bit element 20, and the surface of the quantum bit element 20 can be kept always clean. Note that the vacuum is not limited to a complete vacuum, and includes a low pressure state that can substantially suppress the adsorption of a substance to the quantum bit element 20.

[0019] 6 is a plan view showing an example of the form of a seal member 60 forming a joint between the cover 50 and the first substrate 30. The cover 50 is joined to the first substrate 30 via a ring-shaped seal member 60 that surrounds the outer periphery of the quantum bit element 20 and the readout electrode 22. By joining the cover 50 to the first substrate 30 via the ring-shaped seal member 60, a sealed state is realized in the sealed space 51.

[0020] The cover 50 is preferably made of a conductor, and is preferably made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature. For example, Al (aluminum) can be suitably used as a material for the cover 50. The cover 50 is joined to the through via 31A to which the ground potential is supplied via a bump 52. This allows the potential of the cover 50 to be fixed at the ground potential, and makes it possible to block noise coming from the outside and noise radiated from the quantum bit element 20 and the like. The seal member 60 and the bump 52 are preferably made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature. For example, In (indium) can be suitably used as such a metal. The seal member 60 and the bump 52 are joined to the cover 50 via a conductive film 53 that is made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature, such as Nb (niobium). It is also possible to use a material for the cover 50 in which a metal film that exhibits superconductivity is provided on the surface of an insulator or semiconductor.

[0021] The second substrate 40 is provided on the second surface S2 side of the first substrate 30. The second substrate 40 has through vias 41A, 41B, and 41C, and conductive pads 44A, 44B, and 44C connected to these through vias. The through vias 41A, 41B, and 41C are configured to include through holes 42A, 42B, and 42C that penetrate the second substrate 40, respectively, and conductive films 43A, 43B, and 43C that cover the inner walls of these through holes.

[0022] The conductive pad 44A is connected to the control electrode 37 via the bump 45. The quantum bit control signal is input from the rear surface of the second substrate 40 (the surface opposite to the bonding surface with the first substrate 30) and is supplied to the control electrode 37 via the through via 41A, the conductive pad 44A, and the bump 45.

[0023] The conductive pad 44B is connected to the through via 31A of the first substrate 30 via the sealing member 71. The ground potential is input from the rear surface of the second substrate 40 and supplied to the various elements formed on the first substrate 30 and the cover 50 via the through via 41B, the conductive pad 44B, the sealing member 71, and the through via 31A.

[0024] The conductive pad 44C is connected to the through via 31B (read electrode 22) of the first substrate 30 via a sealing member 72. A read control signal for reading out a bit signal indicating the state of the quantum bit element 20 is input from the rear surface of the second substrate 40 and supplied to the through via 31B (read electrode 22) via the through via 41C, the conductive pad 44C and the sealing member 72. The bit signal read out from the quantum bit element 20 is taken out to the outside by following a path opposite to the path of the read control signal. The second substrate 40 is joined to the first substrate 30 via the bumps 45 and the sealing members 71 and 72.

[0025] 7 is a plan view showing an example of the configuration of the sealing members 71, 72 and the conductive pads 44B, 44C. The sealing members 71, 72 each have a ring-like shape surrounding the outer periphery of the open end on the second surface S2 side of the through holes 32A, 32B constituting the through vias 31A, 31B of the first substrate 30. The through electrodes 31A, 31B are joined to the conductive pads 44B, 44C via the sealing members 71, 72, respectively, so that the open ends on the second surface S2 of the through holes 32A, 32B are blocked. This makes the sealed space 51 communicating with the through holes 32A, 32B completely sealed. That is, a vacuum state is maintained in the sealed space 51.

[0026] An insulator or a semiconductor can be used as the base material of the second substrate 40, and for example, silicon can be preferably used. The sealing members 71, 72 and the bump 45, as well as the conductive films 43A, 43B, 43C and the conductive pads 44A, 44B, 44C are preferably each composed of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature. For example, In (indium) can be preferably used as the metal constituting the sealing members 71, 72 and the bump 45. For example, Nb (niobium) can be preferably used as the metal constituting the conductive films 43A, 43B, 43C and the conductive pads 44A, 44B, 44C.

[0027] The material of the second substrate 40 may be an insulator or a semiconductor. For example, silicon can be suitably used as the material of the second substrate 40. The sealing members 71, 72 and the bumps 45 are preferably made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature. For example, In (indium) can be suitably used as such a metal. The conductive films 43A, 43B, 43C and conductive pads 44A, 44B, 44C constituting the through vias 41A, 41B, 41C are preferably made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature. For example, Nb (niobium) can be suitably used as such a metal.

[0028] Fig. 8 is a plan view showing an example of an arrangement of the sealing member 60, the through vias 31A, 31B and the associated sealing members 71, 72, the control electrode 37 and the associated bump 45 on the first substrate 30. Fig. 9 is a plan view showing an example of an arrangement of the through vias 41A, 41B, 41C, the conductive pads 44A, 44B, 44C, and the bump 45 on the second substrate 40.

[0029] An example of a manufacturing method for the quantum processing device 10 will be described below with reference to Figs. 10 to 16. First, a first substrate 30 is prepared. For example, a silicon substrate can be used as the first substrate 30. Next, a resist (not shown) is formed on the surface of the first substrate 30, and the resist is patterned. Using the patterned resist as a mask, through-holes 32A and 32B are formed in the first substrate 30 by, for example, deep RIE (Reactive Ion Etching) (Fig. 10).

[0030] Next, a conductive film 33 made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined critical temperature, such as Nb (niobium), is formed by sputtering on the first surface S and the second surface S2 of the first substrate 30. The inner walls of the through holes 32A and 32B are also covered with the conductive film 33 (FIG. 11).

[0031] Next, the conductive film 33 is patterned by photolithography and dry etching. This forms the through vias 31A and 31B and the control electrode 37. The through via 31B functions as the read electrode 22. Furthermore, a quantum bit element 20 including a superconducting Josephson element is formed on the first surface S1 of the first substrate 30 using Al or the like (FIG. 12).

[0032] Next, the cover 50 is prepared. The cover 50 is preferably made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined critical temperature, such as Al (aluminum). A recess may be formed in the cover 50 at a portion facing the quantum bit device 20 and the readout electrode 22. A ring-shaped seal member 60 is formed on the cover 50 at a portion surrounding the outer periphery of the quantum bit device 20 and the readout electrode 22, via a conductive film 53. A bump 52 is formed on the cover 50 at a portion corresponding to the through via 31A, via the conductive film 53. The seal member 60 and the bump 52 are preferably made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined critical temperature, such as In (indium). The conductive film 53 is preferably made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined critical temperature, such as Nb (niobium) (FIG. 13).

[0033] Next, the cover 50 and the first substrate 30 are accommodated in a vacuum chamber (not shown). Thereafter, oxides on the surfaces of the seal member 60 and the bumps 52 are removed by surface treatment such as Ar ion milling in the vacuum chamber. Next, the first substrate 30 and the cover 50 are heated in a state of being in close contact with each other in the vacuum chamber. The heating temperature is determined according to the melting points of the seal member 60 and the bumps 52. When the seal member 60 and the bumps 52 are made of, for example, In (indium), the heating temperature is preferably 100°C or higher and 150°C or lower. As a result, the seal member 60 and the bumps 52 melt, the first substrate 30 and the cover 50 are bonded together, and a sealed space 51 communicating with the through holes 32A and 32B is formed around the quantum bit element 20 and the readout electrode 22. The cover 50 is bonded to the first substrate 30 via the ring-shaped seal member 60, thereby realizing a sealed state in the sealed space 51 (FIG. 14).

[0034] Next, the second substrate 40 is prepared. For example, a silicon substrate can be used as the second substrate 40. Next, the through vias 41A, 41B, 41C and the conductive pads 44A, 44B, 44C are formed on the second substrate 40. The formation procedure is the same as the formation procedure of the through vias 31A, 31B on the first substrate 30. Next, the bump 45 is formed on the surface of the conductive pad 44A. Furthermore, the sealing members 71, 72 are formed on the surfaces of the conductive pads 44B, 44C. The sealing members 71, 72 each have a ring-like shape surrounding the outer periphery of the opening end on the second surface S2 side of the through holes 32A, 32B. The sealing members 71, 72 and the bump 45 are preferably made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined critical temperature, such as In (indium). (FIG. 15).

[0035] Next, the laminate of the cover 50 and the first substrate 30 and the second substrate 40 are housed in a vacuum chamber. Thereafter, oxides on the surfaces of the seal members 71, 72 and the bumps 45 are removed by surface treatment such as Ar ion milling. Next, a surface treatment gas such as vapor HF gas is introduced into the sealed space 51 from the through holes 32A, 32B in the vacuum chamber to remove oxides and the like on the surface of the quantum bit element 20. This cleans the surface of the quantum bit element 20 without damaging the quantum bit element 20.

[0036] Next, the first substrate 30 and the second substrate 40 are heated in a vacuum chamber while being in close contact with each other. The heating temperature is determined according to the melting points of the seal members 71, 72 and the bumps 45. When the seal members 71, 72 and the bumps 45 are made of, for example, In (indium), the heating temperature is preferably 100°C or higher and 150°C or lower. As a result, the seal members 71, 72 and the bumps 45 melt, and the first substrate 30 and the second substrate 40 are bonded together. The through electrodes 31A, 31B are bonded to the conductive pads 44B, 44C via the seal members 71, 72, respectively, and thus the opening ends of the through holes 32A, 32B on the second surface S2 are blocked. As a result, the sealed space 51 communicating with the through holes 32A, 32B is completely sealed. That is, a vacuum state is maintained in the sealed space 51 (FIG. 16).

[0037] As described above, the quantum computing device 10 includes the first substrate 30 on which the quantum bit element 20 is mounted on the first surface S1, the cover 50 covering the first surface S1 side of the first substrate 30, and the second substrate 40 provided on the second surface S2 side of the first substrate 30. The first substrate 30 includes the through vias 31A and 32B including the through holes 32A and 32B and the conductive films 33A and 33B. The cover 50 forms a sealed space 51 around the quantum bit element 20 that communicates with the through holes 32A and 32B. The opening ends of the through holes 32A and 32B on the second surface S2 are closed by the second substrate 40. According to the quantum computing device 10 according to the disclosed technology, the sealed space 51 is kept sealed, so that the surface of the quantum bit element 20 can be kept clean. That is, it is possible to suppress the adsorption of a substance to the surface of the quantum bit element 20, and it is possible to avoid a shortening of the coherence time caused by the adsorbed substance.

[0038] In addition, the second substrate 40 is joined to the first substrate 30 via ring-shaped seal members 71 and 72 that surround the outer periphery of the open ends of the through holes 32A and 32B, and the cover 50 is joined to the first substrate 30 via a ring-shaped seal member 60 that surrounds the sealed space 51. This allows the sealed space 51 to be in a completely sealed state and to be maintained in a vacuum state. This makes it possible to almost completely prevent the adsorption of substances to the surface of the quantum bit element 20.

[0039] The second substrate 40 has conductive pads 44A, 44B, and 44C electrically connected to the through vias 31A and 31B provided in the first substrate 30, and through vias 41A, 41B, and 41C electrically connected to these conductive pads. By using the second substrate 40 as a rewiring layer in this manner, the wiring and the quantum bit elements 20 can be integrated at a high density, which contributes to the miniaturization of the quantum processing device 10.

[0040] In the above embodiment, Al (aluminum), Nb (niobium) and In (indium) are exemplified as metals that exhibit superconductivity at temperatures equal to or lower than a predetermined critical temperature. However, metals such as NbN (niobium nitride), Ta (tantalum), TaN (tantalum nitride) and TiN (titanium nitride) can also be used.

[0041] [Second embodiment] Fig. 17 is a schematic cross-sectional view showing an example of the configuration of a quantum processing device 10A according to the second embodiment of the disclosed technique. Note that the resonator 21 and the readout electrode 22 are omitted from Fig. 17. Fig. 17 also shows only the peripheral configuration of one quantum bit element 20.

[0042] The quantum processing device 10A has a structure in which a first substrate 30, a second substrate 40, and a cover 50 are laminated, similarly to the quantum processing device 10 according to the first embodiment. The cover 50 covers the first surface S1 side of the first substrate 30 while forming a sealed space 51 around the quantum bit element 20. The second substrate 40 is provided on the second surface S2 side of the first substrate 30, and closes the opening ends on the second surface S2 side of each of the through holes constituting the through vias 31P, 31Q, 31R, and 31S provided in the first substrate 30. Although not shown in FIG. 17, a plurality of quantum bit elements 20 are mounted on the first surface S1 of the first substrate 30. The sealed spaces 51 are formed so as to be separated from each other for each quantum bit element 20.

[0043] 18 is a plan view showing an example of the form of a seal member 60 forming a joint between the cover 50 and the first substrate 30. The cover 50 is joined to the first substrate 30 via a ring-shaped seal member 60 surrounding the outer periphery of each quantum bit element 20. By joining the cover 50 to the first substrate 30 via the ring-shaped seal member 60, a sealed state is realized in the sealed space 51. The sealed spaces 51 provided for each quantum bit element 20 are separated from each other by the seal member 60.

[0044] Each of the multiple quantum bit elements 20 mounted on the first surface S1 of the first substrate 30 is connected to the other adjacent quantum bit elements 20 via the bit-to-bit wiring 24. In the quantum computing device 10A according to the present embodiment, a part of the bit-to-bit wiring 24 is provided on the first substrate 30, and another part of the bit-to-bit wiring 24 is provided on the second substrate 40. FIG. 18 shows a part of the bit-to-bit wiring 24 provided on the first substrate 30. As shown in FIGS. 17 and 18, a part of the bit-to-bit wiring 24 that intersects with the seal member 60 is provided on the second substrate 40, and the other part of the bit-to-bit wiring 24 is provided on the first surface S1 of the first substrate 30. That is, the bit-to-bit wiring 24 is detouring to the second substrate 40 at the part that intersects with the seal member 60. The portion of the bit-to-bit wiring 24 provided on the first substrate 30 (hereinafter referred to as the first portion) and the portion provided on the second substrate 40 (the second portion) are connected to each other via through vias 31P, 31Q, 31R, and 31S.

[0045] 17 indicates the path of a bit signal from the quantum bit element 20 to another adjacent quantum bit element (not shown). For example, the bit signal output from the quantum bit element 20 is transmitted to the other adjacent quantum bit element (not shown) via the first part of the inter-bit wiring 24, the through via 31P, the second part of the inter-bit wiring 24, the through via 31Q, and the first part of the inter-bit wiring 24.

[0046] According to the quantum computing device 10 of this embodiment, the sealed spaces 51 are formed separately for each quantum bit element 20. As a result, even if the vacuum state cannot be maintained in one sealed space 51, it is possible to maintain the vacuum state in the other sealed spaces 51. In other words, compared to the case where a plurality of quantum bit elements 20 are vacuum-sealed together, the effect of the vacuum being broken can be reduced.

[0047] On the other hand, when providing a seal member 60 surrounding the outer periphery of each of the multiple quantum bit elements 20, it is necessary to arrange the inter-bit wiring 24 so as not to come into contact with the seal member 60. According to the quantum computing device 10A of this embodiment, the portion of the inter-bit wiring 24 that intersects with the seal member 60 is bypassed to the second substrate 40, so that contact between the inter-bit wiring 24 and the seal member 60 is avoided.

[0048] [Third embodiment] FIG. 19 is a schematic cross-sectional view showing an example of the configuration of a quantum operation device 10B according to the third embodiment of the disclosed technology. In FIG. 19, the resonator 21 and the readout electrode 22 are omitted. Also, FIG. 19 shows only the peripheral configuration of one quantum bit element 20. FIG. 20 is a plan view showing an example of the form of a seal member 60 forming a joint between the cover 50 and the first substrate 30. The quantum operation device 10B according to this embodiment is different from the quantum operation device 10A according to the second embodiment described above in that all parts of the bit wiring 24 are provided on the first substrate 30. In the quantum operation device 10B according to this embodiment, an insulator 80 is provided at the intersection between the seal member 60 and the bit wiring 24 to separate the seal member 60 and the bit wiring 24. That is, the insulator 80 is sandwiched between the seal member 60 and the bit wiring 24, thereby preventing the seal member 60 from contacting the bit wiring 24. According to the quantum processing device 10B of this embodiment, a through via for diverting the bit-to-bit wiring 24 to the second substrate 40 is not necessary.

[0049] FIG. 21 is a plan view showing an example of a pattern of the capacitor 23 provided on the path of the inter-bit wiring 24. The capacitor 23 may have a comb-shaped pattern as exemplified in FIG. 21. The insulator 80 provided at the intersection of the sealing member 60 and the inter-bit wiring 24 may be provided at a position overlapping the capacitor 23. This allows the parasitic capacitance of the insulator 80 to be incorporated into the capacitor 23, making the design easier. The capacitor 23 may be arranged outside the area surrounded by the sealing member 60, and one capacitor 23 may be provided for two quantum bit elements 20 adjacent to each other.

[0050] [Fourth embodiment] 22 is a schematic cross-sectional view showing an example of the configuration of a quantum processing device 10C according to the fourth embodiment of the disclosed technology. The quantum processing device 10C according to the fourth embodiment has a configuration in which structures 90A and 90B each including a cover 50, a first substrate 30, and a second substrate 40 are stacked. The structures 90A and 90B each have the same configuration as the quantum processing device 10 according to the first embodiment described above. The structures 90A and 90B are stacked by bonding the covers 50 together. The second substrate 40 is disposed on the top layer and the bottom layer of the quantum processing device 10C, respectively.

[0051] The quantum computing device 10C according to this embodiment makes it possible to densely integrate the quantum bit elements 20. In addition, since the second substrates 40 are disposed in the uppermost and lowermost layers, wiring for accessing the quantum bit elements 20 can be drawn out in two directions, making it possible to access the quantum bit elements 20 from two directions. [Explanation of symbols]

[0052] 10, 10A, 10B, 10C quantum computing device 20 qubit elements 23 Capacitor 24 Bit-to-bit wiring 30 First substrate 31A, 31B, 31C, 31P, 31Q, 31R Through Via 32A, 32B through hole 33A, 33B Conductive film 41A, 41B, 41C Through Via 44A, 44B, 44C Conductive pads 50 Cover 60, 71, 72 Seal members 80 Insulator 90A, 90B Structure

Claims

1. a first substrate having a through hole; a quantum bit device formed on a first surface of the substrate; a cover that covers the first surface side of the first substrate; a second substrate provided on a second surface side of the first substrate opposite to the first surface side, the second substrate closing an open end of the through hole on the second surface side; a sealed space is provided between the first surface and the cover, the sealed space surrounding the quantum bit element and communicating with the through hole. Quantum computing device.

2. The second substrate is joined to the second surface of the first substrate via a ring-shaped seal member that surrounds the outer periphery of the opening end. The quantum computing device according to claim 1 .

3. The cover is joined to the first surface of the first substrate via a ring-shaped seal member that surrounds the sealed space. The quantum computing device according to claim 1 or 2.

4. The enclosed space is a vacuum. The quantum computing device according to claim 1 .

5. the first substrate has a through via including a conductive film covering the through hole and an inner wall of the through hole; The second substrate has a conductive pad electrically connected to the through via, and a through via electrically connected to the conductive pad. The quantum computing device according to any one of claims 1 to 4.

6. a plurality of the quantum bit elements are formed on the first surface of the first substrate; The sealed spaces are formed so as to be separated from each other for each of the plurality of quantum bit elements. The quantum computing device according to claim 1 .

7. At least a part of the inter-bit wiring that connects adjacent quantum bit element pairs is provided on the second substrate. The quantum computing device according to claim 6.

8. the cover is joined to the first surface of the first substrate via a ring-shaped seal member surrounding each of the sealed spaces; A portion of the bit-to-bit wiring that intersects with a ring-shaped seal member surrounding each of the sealed spaces is provided on the second substrate. The quantum computing device according to claim 7.

9. an inter-bit wiring that connects adjacent pairs of quantum bit elements is provided on the first surface of the first substrate; the cover is joined to the first surface of the first substrate via a ring-shaped seal member surrounding each of the sealed spaces; An insulator is provided at an intersection between the sealing member and the inter-bit wiring to separate the sealing member and the inter-bit wiring. The quantum computing device according to claim 6.

10. a capacitor provided on a path of the bit line; The intersection and the insulator are provided at positions overlapping the capacitor. The quantum computing device according to claim 9 .

11. A plurality of structures each including the cover, the first substrate, and the second substrate are stacked. The quantum computing device according to any one of claims 1 to 10.

12. The ring-shaped seal member surrounding the outer periphery of the open end is made of a metal that exhibits superconductivity. The quantum computing device according to claim 2 .

13. The conductive film and the conductive pad are configured to contain a metal that exhibits superconductivity. The quantum computing device according to claim 5 .

14. forming a through hole in a first substrate; forming a quantum bit device on a first surface of the first substrate; a step of bonding a cover covering a side of the first surface of the first substrate to the first surface of the first substrate; a step of bonding a second substrate to a second surface of the first substrate opposite to the first surface, the second substrate closing an open end of the through hole on the second surface side; Including, 11. A method for manufacturing a quantum computing device, comprising: a step of bonding the cover to the first surface, wherein an enclosed space is formed between the first surface and the cover, the enclosed space surrounding the quantum bit element and communicating with the through hole.

15. The second substrate is bonded to the second surface of the first substrate via a ring-shaped seal member that surrounds the outer periphery of the opening end. The method of claim 14.

16. The cover is joined to the first surface of the first substrate via a ring-shaped seal member that surrounds the sealed space. The method according to claim 14 or 15.

17. The step of bonding the cover to the first substrate and the step of bonding the second substrate to the first substrate are performed in a vacuum. The method according to any one of claims 14 to 16.

18. The method further includes the step of cleaning a surface of the quantum bit element by introducing a gas through the open end of the through hole after the step of bonding the cover to the first substrate and before the step of bonding the second substrate to the first substrate. The method according to any one of claims 14 to 17.

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