Apparatus and method for intelligent prediction of processor idle time - Patents.com

Abstract

To provide an apparatus and method for intelligent prediction of the processor idle time.SOLUTION: A machine-learning (ML) scheme runs a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on the time of day and / or the system telemetry. The ML gives a High Water Mark (HWM) number of dirty cache lines (DLs) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DLs for notification of low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.SELECTED DRAWING: Figure 2

Description

[Background technology]

[0001] Optimizing the decision for the processor to enter low power states such as S0i4 (e.g., Dynamic Random Access Memory (DRAM) off state in a two-level memory configuration) makes the entry cost and / or restart cost of those low power states higher. The break-even point can be on the order of minutes. Delays in entering S0i4 or incorrect entry (with exiting within minutes) can result in wasted energy and battery life, which can affect the user's Hours of Battery Life (HoBL) experience. [Brief description of the drawings]

[0002] The disclosed embodiments will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which should not be construed to limit the disclosure to specific embodiments, but are merely for purposes of illustration and understanding. [Figure 1] 1 illustrates a high-level computing architecture operable to intelligently predict idle time to reduce entry energy costs associated with deep sleep states, according to some embodiments. [Diagram 2] 1 illustrates a flowchart of an architecture for intelligently predicting idle time to reduce entry energy cost, according to some embodiments. [Diagram 3] 1 illustrates a method for intelligently predicting idle time by training a machine learning algorithm, according to some embodiments. [Figure 4] 1 illustrates a method for intelligently predicting idle time by using inference, according to some embodiments. [Diagram 5]In accordance with various embodiments, a smart appliance or computer system or SoC (System on Chip) having apparatus and / or software for intelligently predicting idle time to reduce entry energy cost is illustrated. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0003] The power policy of the memory subsystem controlled by the power agent algorithm (e.g., pCode firmware running on the power control unit (PCU)) may use heuristics to construct a one-size-fits-all decision to infer whether the user of the processor will remain in Modern Connected Standby (ModCS) or if the user plans to wake the processor soon. In this case, the power agent algorithm considers history as an indication of the future. Modern Standby or ModCS is an extension of Windows 8.1 Connected Standby. ModCS is just one example and various embodiments are applicable to other low power idle mechanisms.

[0004] The power agent algorithm detects when a user of the processor has been in the ModCS for a long enough time and determines if an entry cost is justified based on the number of dirty cache lines in the system cache. Examples of system caches include a last level (LL) cache in a one level memory (1LM) mode configuration, or a DRAM cache in a two level memory (2LM) mode configuration.

[0005] However, the power agent algorithm described above cannot predictively fine-tune its decision based on an individual user's personal or behavioral patterns, and therefore cannot fine-tune the entry decision for the processor user. This results in cases of incorrect entry and missed opportunities. The power agent algorithm may also require the processor to remain in the PC10 power state for some time before deciding to enter the S0i3 or S0i4 state. In some cases where the power agent algorithm decides to enter the S0i4 state after the S0i3 state, this decision results in wasted energy for the time spent in the S0i3 state, when a predictive S0i4 state entry would have allowed for a longer time in a lower power state, and further wasted energy in exiting the S0i3 state and re-entering the S0i4 state. Although embodiments are described with reference to the S0ix state, the embodiments are also applicable to other low power states, such as those described with reference to the Advanced Configuration and Power Interface (ACPI) specification embodied in version 6.3 released in January 2019.

[0006] Here, the S0ix state, where 'x' is a number, represents an Intel® SoC (System on a Chip) being in an idle standby power state. The S0ix state shuts down parts of the SoC when they are not being used. For example, S0i4 turns off the Dynamic Random Access Memory (DRAM) in a two-level memory configuration. S0i4 is a deeper sleep state compared to S0i3. The S0ix state is triggered when certain conditions within the SoC are achieved. For example, when certain components of the computing system are in a low power state, the SoC may decide to enter a particular deeper power state. In the deepest power state (e.g., S0i4), the SoC consumes the least amount of power.

[0007] Some embodiments use higher level machine learning (ML) running in the software driver stack (e.g., ML-based Dynamic Platform Thermal Framework driver or DPTF-ML driver) to learn user habits of entering low power states, e.g., ModCS, and duration as a function of time of day and system telemetry. ML provides the High Water Mark (HWM) number of dirty cache lines as a hint to the power agent. The power agent algorithms of various embodiments use these hints and the actual number of dirty cache lines in the system to inform low power state entry decisions, e.g., entry decisions in S0i4 vs. S0i3.

[0008] There are numerous technical advantages of various embodiments. For example, the power agent algorithm or scheme produces significant battery life savings for customers during low power states, such as ModCS standby states. The power agent algorithm or scheme of various embodiments allows for reduced computing platform costs because the scheme allows computing platforms to use lower or deeper power states (e.g., ModCS power states) with less expensive DRAM dual in-line memory modules (DIMMs) than can be achieved with more expensive low power double data rate (LPDDR) DIMMs. Other technical advantages become apparent from the various embodiments and figures.

[0009] In the following description, numerous details are set forth in order to provide a more thorough description of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. Also, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present disclosure.

[0010] It should be noted that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths and / or may have arrows at one or both ends to indicate the main direction of information flow. Such indications are not intended to be limiting. Rather, the lines are used to aid in easy understanding of a circuit or logic unit in connection with one or more exemplary embodiments. The signals represented are dictated by design needs or preferences, and may in fact have one or more signals that may travel in either direction and may be implemented with any suitable type of signaling scheme.

[0011] Throughout the specification and in the claims, the term "connected" means a direct connection, such as an electrical, mechanical or magnetic connection, between the things that are connected, without any intermediate devices.

[0012] The term "coupled" means a direct or indirect connection, such as, for example, a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices.

[0013] The term "adjacent" as used herein generally refers to the position of one thing next to (e.g., immediately adjacent or in close proximity with one or more things between them) or abutting (e.g., adjoining) another thing.

[0014] The term "circuit" or "module" may refer to one or more passive and / or active components configured to cooperate with each other to provide a desired functionality.

[0015] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on".

[0016] The term "scaling" generally refers to converting a design (schematics and layout) from one process technology to another, which may then be reduced in layout area. In some cases, scaling may also enlarge a design from one process technology to another, which may then be enlarged in layout area. The term "scaling" generally refers to making layouts and devices smaller or larger within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up, i.e., scaling down or up, respectively) signal frequencies relative to another parameter, such as power supply levels. The terms "substantially," "close," "approximately," "near," and "about" generally refer to within ±10% of a target value.

[0017] Unless otherwise noted, the use of ordinal adjectives "first," "second," "third," etc. to describe a common object is intended merely to indicate that different instances of a similar object are being referred to, and is not intended to imply that the objects so described must be in a given sequence, temporally, spatially, in ranking, or in any other way.

[0018] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0019] In the specification and claims, where present, the terms "left," "right," "front," "rear," "top," "bottom," "upper," "lower," and the like are used for descriptive purposes and are not necessarily used to describe permanent relative positions.

[0020] It is noted that elements of a figure having the same reference number (or name) as elements of another figure may operate or function in a similar manner as described, but are not limited to such.

[0021] For purposes of the embodiments, the transistors in the various circuit and logic blocks described herein are metal oxide semiconductor (MOS) transistors or their derivatives, with MOS transistors including drain, source, gate, and bulk terminals. Transistors and / or MOS transistor derivatives also include tri-gate and FinFET transistors, gate-all-around cylindrical transistors, tunneling FETs (TFETs), square wire or rectangular ribbon transistors, ferroelectric FETs (FeFETs), or other devices that implement transistor functions, such as carbon nanotube or spintronic devices. The symmetrical source and drain terminals of a MOSFET are, in other words, equal terminals and are used interchangeably herein. On the other hand, a TFET device has asymmetrical source and drain terminals. One skilled in the art will appreciate that other transistors, such as bipolar junction transistors (BJT PNP / NPN), BiCMOS, CMOS, etc., may also be used without departing from the scope of the disclosure.

[0022] FIG. 1 illustrates a high-level computing architecture 100 operable to intelligently predict idle time to reduce entry energy costs associated with deep sleep states, according to some embodiments. The architecture 100 is a simplified version of the system-on-chip (SoC) of FIG. 5. In some embodiments, the architecture 100 includes a SoC 101, a kernel 102 (e.g., an operating system), applications 103, software drivers 104, and external memory 105. The SoC 101 may include multiple intellectual property (IP) blocks, such as processor cores, voltage regulators (VRs), caches, etc. In some embodiments, the SoC 101 includes power management logic 101a that executes code 101b (referred to herein as pCode) to manage power for the SoC 101 and the architecture 100. The SoC 101 may also include memory 101c. The memory 101c may be a first, second, third, and / or last level cache. In some embodiments, memory 101c is not a cache memory but a larger storage for storing data than a cache. A processor core may access memory 101c, for example, if data is not found in the cache(s). In some embodiments, SoC 101 is further coupled to external memory 105, for example, a DIMM.

[0023] In some embodiments, the driver 104 includes a stack of drivers (e.g., one or more drivers) that implement a higher ML scheme for dynamic tuning of parameters (e.g., idle time prediction). The ML scheme learns the user habits of entering low power states, e.g., ModCS, and durations that depend on time of day (TOD), day of week (DOW), calendar busy and free time slots, and other system telemetry. The ML provides a high water mark (HWM) number of dirty cache lines as a hint to the power management unit 101a to decide which power state (e.g., S0i3 or S0i4) to enter. The power management unit 101a (also referred to as a power agent) executes algorithms using proprietary or OEM (original equipment manufacturer) accessible software code, e.g., pCode, to analyze these hints and the actual number of dirty cache lines in the system and inform a low power state entry decision, e.g., S0i4 vs. S0i3 entry decision. Thus, the architecture 100 enters a power state that results in higher power savings under the usage conditions of the SoC. For example, based on telemetry information, the ML scheme predicts the idle duration of the SoC 101 and, depending on the duration, places the SoC 101 in a sleep mode from which most of the energy savings derives. Thus, the architecture 100 may delay entry into the S0i4 state or erroneous entry into a power state that will be exited in a short time.

[0024] 2 illustrates a flowchart 200 of an architecture for intelligently predicting idle time to reduce entry energy costs associated with deep sleep states, according to some embodiments. Flowchart 200 illustrates functional blocks that may be hardware, software, or a combination thereof. These various blocks are executed sequentially, in parallel, or out of order to generate a decision to enter a particular power state.

[0025] In some embodiments, the architecture for intelligently predicting idle time includes a machine learning (ML) scheme driver 201 used to train an ML model for dynamic tuning, an ML scheme driver 202 used for inference, a register that stores system telemetry information 203, a time stamp counter (TSC) 204, a register that stores an HWM 205, a pCode 101b that determines the decision for the lower state, a tag cache 206, and a register that stores the number of dirty lines 207. In some embodiments, the ML scheme driver 201 has software, hardware, or a combination thereof. For example, the ML scheme driver 201 has or has access to multipliers and adders that train the ML model and generate an output based on the trained weights (or coefficients) and inputs (e.g., telemetry inputs). In some embodiments, the ML scheme driver 201 performs machine learning using one or more of logistic regression, random forest, or neural network.

[0026] In some embodiments, the ML scheme driver 202 assumes trained weights and infers an output (e.g., an entry hint) based on the input (e.g., telemetry information). In this case, the output is generated much faster because the ML model by the driver 201 is already trained (e.g., the weights are already determined). In some embodiments, the ML scheme driver 202 comprises software, hardware, or a combination thereof. For example, the ML scheme driver 202 comprises or has access to multipliers and adders that train the ML model and generate the output based on the trained weights (or coefficients) and the input (e.g., telemetry input).

[0027] In some embodiments, system telemetry 203 has instructions and mechanisms for training the ML algorithms. For example, system telemetry 203 has access to an unlimited number of user behaviors that are used as inputs for ML drivers 201 and 202. In some embodiments, system telemetry 203 logs user ModCS entry and / or exit history and time-in-state (e.g., time spent in a particular power state) in a scratchpad space (e.g., memory) for training the ML algorithms whenever a training run is made. In some embodiments, the time-in-state is a predictor variable that is used as feedback in the training phase. In some instances, the time-in-state may not be used in inference. In some embodiments, the log in the scratchpad is an event that can be a trigger to start the ML training algorithm by driver 201 (or to start the ML inference algorithm by driver 202). When training, weights are modified to achieve the desired results. In some embodiments, system telemetry 203 can use data from the foreground application at the time of entry and / or exit. In some embodiments, system telemetry 203 can use data from the user calendar, such as data indicating free, busy, out of office, etc., to predict user behavior for a particular time of day (TOD) or day of week (DOW), and thus the duration of standby time in a particular power state. Telemetry information is not limited to the above examples. Other information desirable to assist ML scheme driver 201 / 202 in determining when to enter which power state can also be used.

[0028] In general, traditional software control algorithms are overly complex and energy intensive due to the large number of inputs to the ML algorithm. The ML algorithm adapts over time to specific user habits and behaviors. In some embodiments, the ML algorithm uses one or more of logistic regression, random forest, or neural network to train the weights. In some embodiments, the ML algorithm 201 / 202 runs in real time. In some embodiments, the ML algorithm 201 / 202 runs in response to events, not in real time. For example, the ML algorithm 201 / 202 runs on the user's system triggered by changes in the telemetry events mentioned above. In another example, the ML algorithm 201 / 202 runs infrequently on the user's system and trains on the history of telemetry recorded over the period. In some embodiments, the ML algorithm 201 runs as part of the ModCS entry flow to update the ML network, which then performs inference by the ML algorithm 202. In some embodiments, the training of the ML algorithm 201 is offloaded to the cloud (or server) based on user telemetry.

[0029] Upon exiting a low power case (e.g., ModCS), in some embodiments, the ML driver 201 reads the time stamp counter (TSC) 204 and provides time in state (TIS) information to the ML algorithm 201. The TSC 204 is a register (e.g., a 64-bit register) in an x86 processor. The TSC 204 can be accessed using the kern.timecounter.invariant_tsc flag on FreeBSD or the constant_tsc flag in / proc / cpuinfo on Linux. The TSC ticks at the nominal frequency of the processor (e.g., the cores of the SoC 101), regardless of the actual CPU core clock frequency due to turbo or power saving states. Thus, the TSC ticks count the passage of time, not the number of CPU clock cycles that have elapsed. In some embodiments, in addition to or instead of the TSC 204, the ML scheme driver 201 uses higher resolution counters available through the Windows API, such as QueryPerformanceCounter and QueryPerformanceFrequency.

[0030] In various embodiments, the ML scheme driver 201 reads the dirty line count in a dirty line scratch pad (e.g., memory area) and feeds back the prediction error to the ML algorithm 201 based on the time in state information, the watermark 205, and / or the DL number 207. A dirty cache line generally refers to data in a cache that is modified relative to the copy of the data in the main memory 101c or 104. A cache line has a dirty bit asserted to indicate that the contents of the cache line are different from what is currently in the operational memory. The dirty line (DL) number indicates the number of cache lines that have modified data compared to the corresponding data in the main memory.

[0031] In various embodiments, upon entering a power state (e.g., ModCS entry), the power agent 101a (or suitable microcontroller) executes pCode 101b (or other software) or executes hardware and / or software functions that compare the current dirty lines from the tag cache 206 to the HWM 205 established by the ML driver 202. The tag cache 206 is the requested memory location. Data is generally transferred between the memory 105 and the cache. Data is transferred in fixed-sized blocks called cache lines or cache blocks. When a cache line is copied from memory to the cache, a cache entry is created. The cache entry will contain the copied data and the requested memory location (i.e., the tag cache 206).

[0032] The HWM 205 is stored in a register accessible by the drivers 201 and / or 202. The HWM 205 indicates a count or threshold level of dirty cache lines that dictates whether the SoC 101 should enter a particular power state. As the ML scheme 201 or 202 runs over time (e.g., throughout the day), it will keep updating the scratch pad with the latest HWM 205. This HWM 205 threshold is periodically compared to the current dirty cache line count to predict which power state (e.g., S0i3 or Soi4) should be entered.

[0033] For example, pCode101b compares HWM205 with the number of dirty lines in DRAM and makes a simple decision to enter S0i4 or S0i3. For example, if the number of dirty lines in DRAM is greater than HWM205, pCode101b places SoC101 or the computing system in S0i3 state to mitigate the entry energy cost of flushing those dirty lines, otherwise it places SoC101 or the computing system in S0i4 state because the predicted in-state time for ModCS is expected to be long enough to offset the energy cost of entry. After comparing HWM205 with the current DL number, pCode101b updates the registers that store TSC204 and / or TIS. TSC204 is later used to calculate TIS to feed to ML scheme 201. In some embodiments, after comparing HWM205 with the current DL number, pCode101b provides its decision to ML driver 201. In some embodiments, pCode 101b also updates the count of the number of dirty DRAM lines for future training / learning by the ML scheme driver 201.

[0034] In some embodiments, upon exiting a power state (e.g., exiting from ModCS), pCode 101b writes a timestamp counter 204 to a scratchpad register to calculate the time in state and provides it to the ML algorithm 201. The ML algorithm 201 then uses the timestamp to predict the time in state for future entries.

[0035] 3 illustrates a method 300 for intelligently predicting idle time by training a machine learning algorithm, according to some embodiments. Although the blocks are shown in a particular order, the order can be changed. For example, some blocks are performed in parallel with other blocks and some are performed before others.

[0036] At block 301, system telemetry logic 203 gathers telemetry information from various sources to predict user behavior in response to entering a standby mode, such as modern standby. For example, system telemetry logic 203 identifies foreground applications at the time of entry and / or exit of a power state, calendar information indicating when a user of the SoC is free, busy, out of the office, etc., battery information (e.g., charging and / or discharging patterns), time of day, and / or day of the week. The telemetry information is provided to ML driver 201 to train a machine learning model, as indicated by block 302. In some embodiments, a change in the telemetry information (compared to a previous state or value) is an event that causes ML driver 201 to start training the ML model. After training the ML model, the system exits standby mode (e.g., exits modern standby mode). At block 303, the ML driver also reads the TSC register(s) to perform training of the ML model. The output of the trained model (e.g., after the weights have been calibrated) is the HWM that is provided to the power management agent 101a, as indicated by block 304. Blocks 301, 302, or 303 are part of the training phase.

[0037] At block 305, the power management agent 101a compares the current dirty line (cache line) count with the HWM. If the dirty line (DL) count is greater than the HWM, the power management agent 101a causes the SoC 101 or computing system to enter a first power state, which is a power state with a lesser depth compared to the second power state. In response to such a determination, the power management agent causes the SoC 101 to enter the first power state (e.g., a shallower power state such as S0i3), as indicated by block 306. When the SoC 101 or computing system exits the first power state, as indicated by block 307, the ML driver 201 reads the TSC register(s) and updates the TIS register, as indicated by block 308. The process then returns to retraining the model, as indicated by block 302.

[0038] If the dirty line (DL) count is less than the HWM, the power management agent 101a causes the SoC 101 or computing system to enter a second power state that is a deeper power state compared to the first power state. In response to such a determination, the power management agent 101a causes the SoC 101 or computing system to enter a second power state (e.g., S0i4), which is a deeper power state compared to the first power state, as indicated by block 309. When the SoC 101 or computing system exits the second power state, as indicated by block 310, the ML driver 201 reads the TSC register(s) and updates the TIS register, as indicated by block 311. The process then returns to retraining the model, as indicated by block 302.

[0039] FIG. 4 illustrates a method 400 for intelligently predicting idle time by using inference, according to some embodiments. Method 400 is similar to method 300, but for inference by block 401 instead of training weights. In this case, blocks 302 and 303 for training are eliminated. In the inference phase, the trained weights are used by ML driver 202 together with new or updated telemetry information to generate the HWM. This process is faster than the method of FIG. 3 because no retraining of the model is performed, which is a computationally intensive task.

[0040] Elements of the embodiments (e.g., flowcharts 300, 400, and schemes described with reference to Figures 1-4) may also be provided as a machine-readable medium (e.g., memory) that stores computer-executable instructions (e.g., instructions for performing other processes described herein). In some embodiments, a computing platform has a memory, a processor, a machine-readable storage medium (also referred to as a tangible machine-readable medium), a communication interface (e.g., a wireless or wired interface), and a network bus coupling them.

[0041] In some embodiments, the processor is a digital signal processor (DSP), an application specific integrated circuit (ASIC), a general purpose central processing unit (CPU), or low power logic implementing a simple finite state machine to perform the methods and / or various embodiments of flowcharts 200-400.

[0042] In some embodiments, the various logic blocks of the system are coupled together via a network bus. Any suitable protocol may be used to implement the network bus. In some embodiments, a machine-readable storage medium includes instructions (also referred to as program software code / instructions) for intelligent prediction of processor idle time as described with reference to the various embodiments and flowcharts.

[0043] The program software code / instructions executed to implement embodiments of the disclosed subject matter associated with flowcharts 200-400 (and / or various embodiments) may be implemented as part of an operating system, or as a specific application, component, program, object, module, routine, or other sequence of instructions, or as an arrangement of multiple instruction sequences referred to as "program software code / instructions," "operating system program software code / instructions," "application program software code / instructions," or simply "software," or as firmware embedded in a processor. In some embodiments, the program software code / instructions associated with flowcharts 200-400 (and / or various embodiments) are executed by a computer system.

[0044] In some embodiments, program software codes / instructions associated with flowcharts 200-400 (and / or various embodiments) are stored on a computer-executable storage medium and executed by a processor, where a computer-executable storage medium is a tangible, machine-readable medium that can be used to store program software codes / instructions and data that, when executed by a computing device, cause one or more processors to perform a method(s) that may be recited in one or more of the appended claims directed to the disclosed subject matter.

[0045] A tangible machine-readable medium may include storage of executable software program code / instructions and data in various tangible locations, including, for example, ROM, volatile RAM, non-volatile memory, and / or cache and / or other tangible memories as referenced in this application. Portions of the program software code / instructions and / or data may be stored in any of these storage and memory devices. The program software code / instructions may also be retrieved from other storage, including, for example, via a centralized server or peer-to-peer network, including the Internet. Different portions of the software program code / instructions and data may be retrieved at different times in different communication sessions or in the same communication session.

[0046] The software program code / instructions (as associated with flowcharts 200-400 and other embodiments) and data may be obtained in their entirety prior to execution of the respective software program or application by a computing device. Alternatively, portions of the software program code / instructions and data may be obtained dynamically, e.g., just-in-time, when needed for execution. Alternatively, any combination of these techniques for obtaining the software program code / instructions and data may be performed, e.g., for different applications, components, programs, objects, modules, routines, or other instruction sequences, or an organization of multiple instruction sequences, as examples. Thus, it is not necessary that the data and instructions be present in their entirety on the tangible machine-readable medium at any particular time.

[0047] Examples of tangible computer readable media include, but are not limited to, recordable and non-recordable type media, such as, for example, volatile and non-volatile memory devices, read only memory (ROM), random access memory (RAM), flash memory devices, magnetic random access memory, ferroelectric memory, floppy and other removable disks, magnetic storage media, optical storage media (e.g., compact disk read only memory (CD ROM), digital versatile disk (DVD), etc.), among others. The software program code / instructions may be temporarily stored on a digital tangible communication link while embodied in electrical, optical, acoustic, or other form of propagated signal, such as, for example, carrier wave, infrared signal, digital signal, etc., over such tangible communication link.

[0048] Generally, a tangible machine-readable medium includes any tangible mechanism that provides information in a form accessible (i.e., stores and / or transmits in digital form, e.g., data packets) by a machine (e.g., a computing device), which may be included in a communications device, computing device, network device, personal digital assistant, manufacturing tool, mobile communications device, whether capable of downloading and executing applications and auxiliary applications from a communications network, such as an iPhone, Galaxy, Blackberry, Droid, or the like, or other device that includes a computing device. In one embodiment, the processor-based system is in the form of or is included within a PDA, mobile phone, notebook computer, tablet, game console, set-top box, embedded system, TV, personal desktop computer, or the like. Alternatively, traditional communications applications and auxiliary application(s) may be used in some embodiments of the disclosed subject matter.

[0049] FIG. 5 illustrates a smart device or computer system or SoC (system on chip) having apparatus and / or software for intelligently predicting idle time to reduce entry energy costs associated with deep sleep states, according to various embodiments. It is noted that elements of FIG. 5 having the same reference numbers (or names) as elements of other figures may operate or function in a similar manner as described, but are not limited to such. Although various embodiments are shown as being performed by power management unit 101a, any of the blocks described herein that may control the power state of a computer system may have apparatus and / or software for intelligently predicting idle time to reduce entry energy costs associated with deep sleep states. For example, PCU 2410a, PCU 2410b, and / or PMIC 2412 may perform the functions of power agent 101a.

[0050] In some embodiments, device 2400 represents any suitable computing device, such as a computing tablet, a mobile phone or smartphone, a laptop, a desktop, an Internet of Things (IOT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, or the like. It is understood that certain components are shown diagrammatically, and that not all components of such a device are shown in device 2400.

[0051] In one example, device 2400 includes a system on chip (SoC) 2401. An example boundary of SoC 2401 is illustrated in FIG. 5 using a dotted line, and some example components are illustrated as being included within SoC 2401, although SoC 2401 may include any suitable components of device 2400.

[0052] In some embodiments, device 2400 includes a processor 2404. Processor 2404 may include one or more physical devices, such as, for example, a microprocessor, an application processor, a microcontroller, a programmable logic device, a processing core, or other processing means. The processing operations performed by processor 2404 include the execution of an operating platform or operating system on which applications and / or device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting computing device 2400 to other devices, and / or the like. The processing operations may also include operations related to audio I / O and / or display I / O.

[0053] In some embodiments, the processor 2404 includes multiple processing cores (also referred to as cores) 2408a, 2408b, 2408c. Although only three cores 2408a, 2408b, 2408c are shown in FIG. 5, the processor 2404 may include any other suitable number of processing cores, such as tens or hundreds of processing cores. The processor cores 2408a, 2408b, 2408c may be implemented on a single integrated circuit (IC) chip. Additionally, the chip may include one or more shared and / or private caches, buses or interconnects, graphics controllers and / or memory controllers, or other components.

[0054] In some embodiments, the processor 2404 includes a cache 2406. In one example, sections of the cache 2406 may be dedicated to individual cores 2408 (e.g., a first section of the cache 2406 is dedicated to core 2408a, a second section of the cache 2406 is dedicated to core 2408b, etc.). In one example, one or more sections of the cache 2406 may be shared between two or more of the cores 2408. The cache 2406 may be divided into different hierarchies, such as a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, etc.

[0055] In some embodiments, processor core 2404 may include a fetch unit that fetches instructions (including instructions with conditional branches) for execution by core 2404. Instructions may be fetched from any storage device, such as memory 2430. Processor core 2404 may also include a decode unit that decodes the fetched instructions. For example, the decode unit may decode the fetched instructions into multiple micro-operations. Processor core 2404 may include a schedule unit that performs various operations associated with storing the decoded instructions. For example, the schedule unit may hold data from the decode unit until the instruction is ready to be dispatched (e.g., until all source values ​​of the decoded instruction are available). In one embodiment, the schedule unit may schedule and / or issue (or dispatch) the decoded instructions to an execution unit for execution.

[0056] The execution units may execute the dispatched instructions after they have been decoded (e.g., by a decode unit) and dispatched (e.g., by a schedule unit). In one embodiment, the execution units may include two or more execution units (e.g., an imaging computation unit, a graphics computation unit, a general-purpose computation unit, etc.). The execution units may also perform various arithmetic operations such as, for example, addition, subtraction, multiplication, and / or division, and may include one or more arithmetic logic units (ALUs). In one embodiment, a coprocessor (not shown) may perform various arithmetic operations in conjunction with the execution units.

[0057] The execution units may also execute instructions out of order. Thus, the processor core 2404 may be an out-of-order processor core in one embodiment. The processor core 2404 may also include a retirement unit. The retirement unit may retire executed instructions after they are committed. In one embodiment, retirement of executed instructions may result in the processor state being committed from execution of the instructions, physical registers used by the instructions being deallocated, etc. The processor core 2404 may also include a bus unit that allows communication between components of the processor core 2404 and other components via one or more buses. The processor core 2404 may also include one or more registers that store data accessed by various components of the core 2404 (e.g., values ​​related to assigned application priorities and / or subsystem state (mode) associations, etc.).

[0058] In some embodiments, device 2400 includes connectivity circuitry 2431. For example, connectivity circuitry 2431 may include hardware devices (e.g., wireless and / or wired connectors and communications hardware) and / or software components (e.g., drivers, protocol stacks) that, for example, enable device 2400 to communicate with external devices. Device 2400 may be isolated from external devices, such as, for example, other computing devices, wireless access points, or base stations.

[0059] In one example, the connection circuitry 2431 may include multiple different types of connections. In generalization, the connection circuitry 2431 may include cellular connection circuitry, wireless connection circuitry, etc. The cellular connection circuitry of the connection circuitry 2431 generally refers to a cellular network connection provided by a wireless carrier, such as that provided via a global system for mobile communications (GSM) or a variation or derivative thereof, a code division multiple access (CDMA) or a variation or derivative thereof, a time division multiplexing (TDM) or a variation or derivative thereof, a 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications Systems (UMTS) system or a variation or derivative thereof, a 3GPP Long Term Evolution (LTE) system or a variation or derivative thereof, a 3GPP LTE-Advanced (LTE-A) system or a variation or derivative thereof, a fifth generation (5G) wireless system or a variation or derivative thereof, a 5G mobile network system or a variation or derivative thereof, a 5G New Radio (NR) system or a variation or derivative thereof, or other cellular service standard. The wireless connection circuitry (or wireless interface) of the connection circuitry 2431 refers to non-cellular wireless connections and can include personal area networks (e.g., Bluetooth, near field, etc.), local area networks (e.g., Wi-Fi, etc.), and / or wide area networks (e.g., WiMax, etc.), and / or other wireless communications. In one example, the connection circuitry 2431 can include a network interface, such as a wired or wireless interface, such that a system embodiment can be incorporated into a wireless device, such as a mobile phone or personal digital assistant.

[0060] In some embodiments, device 2400 includes a control hub 2432, which represents hardware devices and / or software components involved in interacting with one or more I / O devices. For example, processor 2404 may communicate with one or more of a display 2422, one or more peripheral devices 2424, a storage device 2428, one or more other external devices 2429, etc. via control hub 2432. Control hub 2432 may be a chipset, a platform control hub (PCH), and / or the like.

[0061] For example, control hub 2432 illustrates one or more connection points for additional devices to connect to device 2400, e.g., through which a user may interact with the system. For example, devices that may be attached to device 2400 (e.g., device 2429) include microphone devices, speakers or stereo systems, audio devices, video systems or other display devices, keyboard or keypad devices, or other I / O devices used in a particular application, such as, for example, card readers or other devices.

[0062] As described above, the control hub 2432 can interact with audio devices, the display 2422, and the like. For example, input via a microphone or other audio device can provide input or commands for one or more applications or functions of the device 2400. Additionally, audio output can be provided instead of or in addition to a display output. In another example, if the display 2422 includes a touch screen, the display 2422 also functions as an input device that can be at least partially managed by the control hub 2432. There can also be additional buttons or switches on the computing device 2400 to provide I / O functions that are managed by the control hub 2432. In one embodiment, the control hub 2432 manages devices such as an accelerometer, a camera, a light sensor or other environmental sensors, or other hardware that can be included in the device 2400. The input can be part of a direct user interaction as well as provide environmental input to the system to affect its operation (e.g., filtering noise, adjusting the display for brightness detection, applying a flash for the camera, or other mechanisms).

[0063] In some embodiments, the control hub 2432 may couple to various devices using any suitable communications protocol, such as, for example, Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), Thunderbolt, High-Definition Multimedia Interface (HDMI), Firewire, etc.

[0064] In some embodiments, the display 2422 represents hardware (e.g., display device) and software (e.g., driver) components that provide visual and / or tactile displays for a user to interact with the device 2400. The display 2422 may include a display interface, a display screen, and / or a hardware device used to provide a display to a user. In some embodiments, the display 2422 includes a touch screen (or touch pad) device that provides both output and input to a user. In one example, the display 2422 may communicate directly with the processor 2404. The display 2422 may be one or more of an internal display, such as in a mobile electronics device or a laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display 2422 may be a head mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) or augmented reality (AR) applications.

[0065] In some embodiments, although not shown, in addition to (or instead of) the processor 2404, the device 2400 may include a graphics processing unit (GPU) including one or more graphics processing cores that may control one or more aspects of displaying content on the display 2422.

[0066] The control hub 2432 (or platform controller hub) may include hardware interfaces and connectors, and software components (eg, drivers, protocol stacks) for making peripheral connections to the peripheral devices 2424, for example.

[0067] It is understood that device 2400 may be a peripheral to other computing devices or may have peripheral devices connected to it. Device 2400 may have a "docking" connector for connecting to other computing devices, such as for purposes of managing (e.g., downloading and / or uploading, modifying, synchronizing) content on device 2400. In addition, a docking connector may enable device 2400 to connect to certain peripherals that allow computing device 2400 to control content output to, for example, an audiovisual system or other system.

[0068] In addition to dedicated docking connectors or other dedicated connection hardware, device 2400 can make peripheral connections via common or standards-based connectors. Common types can include Universal Serial Bus (USB) connectors (which can include any of a number of different hardware interfaces), Mini Display Port (MDP), High-Definition Multimedia Interface (HDMI), Firewire, or other types.

[0069] In some embodiments, the connection circuitry 2431 may be coupled to a control hub 2432, for example, in addition to or instead of being directly coupled to the processor 2404. In some embodiments, the display 2422 may be coupled to the control hub 2432, for example, in addition to or instead of being directly coupled to the processor 2404.

[0070] In some embodiments, the apparatus 2400 includes a memory 2430 coupled to the processor 2404 via a memory interface 2434. The memory 2430 includes a memory device for storing information within the apparatus 2400.

[0071] In some embodiments, the memory 2430 includes devices for maintaining stable clock generation, as described with reference to various embodiments. The memory may include non-volatile (whose state does not change when power to the memory device is interrupted) and / or volatile (whose state is indeterminate when power to the memory device is interrupted) memory devices. The memory device 2430 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with suitable performance to function as a process memory. In one embodiment, the memory 2430 may operate as a system memory of the device 2400 for storing data and instructions used when the one or more processors 2404 execute applications or processes. The memory 2430 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of the device 2400.

[0072] Elements of various embodiments and examples may also be provided as a machine-readable medium (e.g., memory 2430) that stores computer-executable instructions (e.g., instructions for performing any other process described herein). The machine-readable medium (e.g., memory 2430) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAM, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, the disclosed embodiments may be downloaded as a computer program (e.g., BIOS) that may be transferred by data signals from a remote computer (e.g., server) to a requesting computer (e.g., client) over a communications link (e.g., modem or network connection).

[0073] In some embodiments, device 2400 includes temperature measurement circuitry 2440, for example, to measure the temperature of various components of device 2400. In one example, temperature measurement circuitry 2440 may be built into, coupled to, or attached to the various components whose temperatures are to be measured and monitored. For example, temperature measurement circuitry 2440 may measure the temperature of (or temperatures within) one or more of cores 2408a, 2408b, 2408c, voltage regulator 2414, memory 2430, SOC 2401's motherboard, and / or any suitable component of device 2400.

[0074] In some embodiments, the device 2400 includes a power measurement circuit 2442, for example, to measure power consumed by one or more components of the device 2400. In one example, in addition to or instead of measuring power, the power measurement circuit 2442 may measure voltage and / or current. In one example, the power measurement circuit 2442 may be built into, coupled to, or attached to various components whose power, voltage, and / or current should be measured and monitored. For example, the power measurement circuit 2442 may measure power, current, and / or voltage supplied by one or more voltage regulators 2414, power supplied to the SOC 2401, power supplied to the device 2400, power consumed by the processor 2404 (or other components) of the device 2400, etc.

[0075] In some embodiments, the device 2400 includes one or more voltage regulator circuits, generally referred to as a voltage regulator (VR) 2414. The VR 2414 generates a signal at an appropriate voltage level that may be provided to operate any appropriate component of the device 2400. By way of example only, the VR 2414 is shown providing a signal to the processor 2404 of the device 2400. In some embodiments, the VR 2414 receives one or more Voltage Identification (VID) signals and generates a voltage signal at an appropriate level based on the VID signals. Various types of VRs may be utilized for the VR 2414. For example, the VR 2414 may include a "buck" VR, a "boost" VR, a combination of buck and boost VRs, a low dropout (LDO) regulator, a switching DC-DC regulator, etc. Buck VRs are typically used in power delivery applications that require an input voltage to be converted to an output voltage with a ratio less than one. Boost VRs are typically used in power delivery applications that require an input voltage to be converted to an output voltage with a ratio greater than one. In some embodiments, each processor core has its own VR, which is controlled by the PCU 2410a / b and / or the PMIC 2412. In some embodiments, to provide efficient control for power management, each core has a network of distributed LDOs. The LDOs can be digital LDOs, analog LDOs, or a combination of digital and analog LDOs.

[0076] In some embodiments, the apparatus 2400 includes one or more clock generator circuits, generally referred to as a clock generator 2416. The clock generator 2416 generates a clock signal at an appropriate frequency level that may be provided to any appropriate component of the apparatus 2400. By way of example only, the clock generator 2416 is shown providing a clock signal to the processor 2404 of the apparatus 2400. In some embodiments, the clock generator 2416 receives one or more Frequency Identification (FID) signals and generates a clock signal at an appropriate frequency based on the FID signals.

[0077] In some embodiments, the device 2400 includes a battery 2418 that powers various components of the device 2400. By way of example only, the battery 2418 is shown powering the processor 2404. Although not shown, the device 2400 may include charging circuitry for, for example, recharging the battery based on alternating current (AC) power received from an AC adapter.

[0078] In some embodiments, the device 2400 includes a power control unit (PCU) 2410 (also referred to as a power management unit (PMU), power controller, etc.). In one example, some sections of the PCU 2410 may be implemented by one or more processing cores 2408, and these sections of the PCU 2410 are symbolically illustrated with a dotted box and labeled PCU 2410a. In one example, some other sections of the PCU 2410 may be implemented outside of the processing cores 2408, and these sections of the PCU 2410 are symbolically illustrated with a dotted box and labeled PCU 2410b. The PCU 2410 may implement various power management operations for the device 2400. The PCU 2410 may include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks) to implement various power management operations for the device 2400.

[0079] In some embodiments, the device 2400 includes a power management integrated circuit (PMIC) 2412, for example, to implement various power management operations for the device 2400. In some embodiments, the PMIC 2412 is a Reconfigurable Power Management IC (RPMIC) and / or IMVP (Intel® Mobile Voltage Positioning). In one example, the PMIC is in an IC chip separate from the processor 2404. It may implement various power management operations for the device 2400. The PMIC 2412 may include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks) to implement various power management operations for the device 2400.

[0080] In one example, the device 2400 includes one or both of a PCU 2410 or a PMIC 2412. In one example, either the PCU 2410 or the PMIC 2412 may not be present in the device 2400, and therefore these components are illustrated using dashed lines.

[0081] Various power management operations of device 2400 may be performed by PCU 2410, by PMIC 2412, or by a combination of PCU 2410 and PMIC 2412. For example, PCU 2410 and / or PMIC 2412 may select a power state (e.g., a P-state) for various components of device 2400. For example, PCU 2410 and / or PMIC 2412 may select a power state (e.g., in accordance with the Advanced Configuration and Power Interface (ACPI) specification) for various components of device 2400. By way of example only, PCU 2410 and / or PMIC 2412 may transition various components of device 2400 into a sleep state, an active state, an appropriate C-state (e.g., a C0 state or other appropriate C-state in accordance with the ACPI specification), etc. In one example, the PCU 2410 and / or the PMIC 2412 may control the voltage output by the VR 2414 and / or the frequency of the clock signal output by the clock generator, for example, by outputting a VID signal and / or an FID signal, respectively. In one example, the PCU 2410 and / or the PMIC 2412 may control functions related to battery power usage, charging of the battery 2418, and power saving operations.

[0082] The clock generator 2416 may include a phase-locked loop (PLL), a frequency-locked loop (FLL), or any suitable clock source. In some embodiments, each core of the processor 2404 has its own clock source. Thus, each core may operate at a frequency independent of the operating frequencies of the other cores. In some embodiments, the PCU 2410 and / or the PMIC 2412 perform adaptive or dynamic frequency scaling or adjustment. For example, the clock frequency of a processor core may be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, the PCU 2410 and / or the PMIC 2412 determine the operating conditions of each core of the processor, and when the PCU 2410 and / or the PMIC 2412 determines that a core is operating below a target performance level, the PCU 2410 and / or the PMIC 2412 opportunistically adjusts the frequency and / or power supply voltage of that core without the core's clock source (e.g., its PLL) losing lock. For example, if a core is drawing less current from the power supply rails than the total current allocated to that core or processor 2404, the PCU 2410 and / or PMIC 2412 may temporarily increase the power draw for that core or processor 2404 (e.g., by increasing the clock frequency and / or power supply voltage level) so that the core or processor 2404 can achieve a higher performance level. In this manner, the voltage and / or frequency can be temporarily increased for the processor 2404 without compromising product reliability.

[0083] In one example, the PCU 2410 and / or the PMIC 2412 may perform power management operations based at least in part on receiving measurements from, for example, the power measurement circuit 2442, the temperature measurement circuit 2440, the charge level of the battery 2418, and / or other suitable information that may be used for power management. To this end, the PMIC 2412 is communicatively coupled to one or more sensors to sense / detect various values / variations in one or more factors that have an impact on the power / thermal behavior of the system / platform. Examples of the one or more factors include current, voltage droop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be located in physical proximity (and / or in thermal contact / coupled) with one or more components or logic / IP blocks of the computing system. Further, in at least one embodiment, coupling (one or more) sensors directly to the PCU2410 and / or PMIC2412 may enable the PCU2410 and / or PMIC2412 to manage processor core energy based at least in part on (one or more) values ​​detected by one or more of those sensors.

[0084] An example of the software stack of the device 2400 is also illustrated (although not all elements of the software stack are shown). By way of example only, the processor 2404 may execute application programs 2450, an operating system 2452, one or more power management (PM) application programs (e.g., generally referred to as PM applications 2458), and / or the like. The PM applications 2458 may also be executed by the PCU 2410 and / or the PMIC 2412. The OS 2452 may also include one or more PM applications 2456a, 2456b, 2456c. The OS 2452 may also include various drivers 2454a, 2454b, 2454c, etc., some of which may be specific to power management purposes. In some embodiments, the device 2400 may further include a basic input / output system (BIOS) 2420. The BIOS 2420 may communicate with the OS 2452 (eg, via one or more drivers 2454), communicate with the processor 2404, and so on.

[0085] For example, one or more of PM applications 2458, 2456, drivers 2454, BIOS 2420, etc. may be used to implement power management tasks, such as, for example, to control the voltage and / or frequency of various components of device 2400, to control the wake-up states, sleep states, and / or other suitable power states of various components of device 2400, to control battery power usage, charging of battery 2418, functions related to power saving operations, etc.

[0086] References in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or feature described in connection with those embodiments is included in at least some of the embodiments, but not necessarily all of the embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" do not necessarily all refer to the same embodiments. When the specification states that a component, feature, structure, or feature "may," "can," or "may" be included, that particular component, feature, structure, or feature need not be included. When the specification or claims refer to an element with "a" or "an," it does not mean that there is only one of that element. When the specification or claims refer to an element with "an additional," it does not exclude there being more than one of that additional element.

[0087] Also, particular features, structures, functions, or characteristics may be combined in a suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment, where the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0088] While the disclosure has been described with respect to specific embodiments thereof, numerous modifications, variations, and variations of these embodiments will become apparent to those skilled in the art in light of the foregoing description, and the disclosed embodiments are intended to encompass all such modifications, variations, and variations that fall within the broad scope of the appended claims.

[0089] In addition, for ease of illustration and explanation, and so as not to obscure the disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the figures presented. Also, configurations may be shown in block diagram form, in order to avoid obscuring the disclosure, and in light of the fact that details regarding the implementation of such block diagram configurations are highly dependent on the platform in which the disclosure will be implemented (i.e., such details should be well within the scope of the involvement of those skilled in the art). Where specific details (e.g., circuits) are described to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure may be practiced without those specific details or with variations thereon. This description is therefore to be regarded as illustrative and not limiting.

[0090] The various embodiments described herein are given by way of example, the features of which may be combined with one another as appropriate. These examples include:

[0091] Example 1: An apparatus, comprising: a power management unit that compares a high water mark (HWM) with a current number of dirty cache lines; and machine learning logic that generates the HWM according to telemetry information and / or the current number of dirty cache lines, wherein if the current number of dirty cache lines is greater than the HWM, the power management unit causes the apparatus to enter a first power state; and if the current number of dirty cache lines is less than the HWM, the power management unit causes the apparatus to enter a second power state. Device.

[0092] Example 2: The apparatus of example 1, wherein the machine learning logic reads a timestamp counter to train a machine learning model.

[0093] Example 3: The device of example 1, wherein the machine learning logic trains the machine learning model by reading a time in state register, the time in state register indicating the time the device is in a power state.

[0094] Example 4: The apparatus of example 1, wherein the machine learning logic infers the HWM via trained weights and the telemetry information.

[0095] Example 5: The apparatus of example 1, wherein the first power state is less deep than the second power state.

[0096] Example 6: The apparatus of example 1, wherein the first power state is an S0i3 state and the second power state is an S0i4 state.

[0097] Example 7: The apparatus of example 1, wherein the machine learning logic comprises a multiplier.

[0098] Example 8: The device of example 1, wherein the telemetry information includes one or more of the following: foreground application at time of power state entry and / or exit; user calendar information indicating free, busy, and / or out of office hours; battery information; time of day; and / or day of week.

[0099] Example 9: The apparatus of example 1, wherein the machine learning logic is controlled or implemented by a software driver.

[0100] Example 10: The apparatus of example 9, wherein the software driver is communicatively coupled to an operating system.

[0101] Example 11: The apparatus of example 1, wherein the HWM is a threshold number of dirty cache lines that enables the power management unit to determine whether to enter the first power state or the second power state.

[0102] Example 12: A machine-readable storage medium having machine-readable instructions stored thereon that, when executed, cause one or more processors to perform a method having: reading telemetry information; and applying machine learning to generate a high water mark (HWM) according to the telemetry information and / or a current number of dirty cache lines, the HWM being a threshold number of dirty cache lines that enables a power management unit to determine whether to enter a first power state or a second power state.

[0103] Example 13: The machine-readable storage medium of Example 12, wherein the telemetry information includes one or more of the following: foreground application at time of power state entry and / or exit, user calendar information indicating free, busy, and / or out of office hours, battery information, time of day, and / or day of the week.

[0104] Example 14: The machine-readable storage medium of Example 12, wherein the computing system is to enter a first power state if the current number of dirty cache lines is greater than the HWM and is to enter a second power state if the current number of dirty cache lines is less than the HWM.

[0105] Example 15: The machine-readable storage medium of Example 12, wherein applying the machine learning comprises reading the timestamp counter to train a machine learning model.

[0106] Example 16: The machine-readable storage medium of Example 12, wherein applying machine learning includes reading a time-in-state register to train a machine learning model, the time-in-state register indicating the time the computing system is in a power state.

[0107] Example 17: The machine-readable storage medium of Example 12, wherein applying machine learning comprises inferring the HWM via trained weights and the telemetry information.

[0108] Example 18: The machine-readable storage medium of example 12, wherein the first power state has a lesser depth than the second power state.

[0109] Example 19: The machine-readable storage medium of Example 12, wherein the first power state is an S0i3 state and the second power state is an S0i4 state.

[0110] Example 20: A system comprising: a memory; a processor coupled to the memory, the processor having a power management unit that compares a high water mark (HWM) with a current number of dirty cache lines; a driver having machine learning logic that generates the HWM according to telemetry information and / or the current number of dirty cache lines, wherein if the current number of dirty cache lines associated with the memory is greater than the HWM, the power management unit will cause the processor to enter a first power state, and if the current number of dirty cache lines associated with the memory is less than the HWM, the power management unit will cause the processor to enter a second power state; and a wireless interface that enables the processor to communicate with other devices.

[0111] Example 21: The system of Example 20, wherein the telemetry information includes one or more of the following: foreground application at time of power state entry and / or exit, user calendar information indicating free, busy, and / or out of office hours, battery information, time of day, and / or day of week.

[0112] Example 22: The system of example 20, comprising an operating system coupled to the driver.

[0113] An Abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. 1. An apparatus comprising: a power management unit that compares a high water mark (HWM) with a current number of dirty cache lines; machine learning logic that generates the HWM according to telemetry information and / or the current number of dirty cache lines; if the current number of dirty cache lines is greater than the HWM, the power management unit causes the device to enter a first power state, and if the current number of dirty cache lines is less than the HWM, the power management unit causes the device to enter a second power state; the machine learning logic trains a machine learning model by reading a time in state register, the time in state register indicating the time the device has been in a power state; Device.

2. 10. The apparatus of claim 1, wherein the machine learning logic further reads a timestamp counter to train the machine learning model.

3. The apparatus of claim 1 , wherein the machine learning logic infers the HWM via trained weights and the telemetry information.

4. The apparatus of claim 1 , wherein the first power state is of a lesser depth than the second power state.

5. 2. The apparatus of claim 1, wherein the first power state is an S0i3 state and the second power state is an S0i4 state.

6. The apparatus of claim 1 , wherein the machine learning logic comprises a multiplier.

7. The telemetry information is the foreground application at the time of power state entry and / or exit; User calendar information indicating free, busy, and / or out of office hours; Battery information, Time, and / or day of week, The apparatus of claim 1 , comprising one or more of:

8. 8. The apparatus of claim 1, wherein the machine learning logic is controlled or implemented by a software driver.

9. The apparatus of claim 8 , wherein the software driver is communicatively coupled to an operating system.

10. 8. The apparatus of claim 1, wherein the HWM is a threshold number of dirty cache lines that enables the power management unit to determine whether to enter the first power state or the second power state.

11. Reading telemetry information; applying machine learning to generate a high water mark (HWM) according to the telemetry information and / or a current number of dirty cache lines, the HWM being a threshold number of dirty cache lines that enables a power management unit to decide whether to enter a first power state or a second power state; having Applying the machine learning includes training the machine learning model by reading a time in state register, the time in state register indicating a time the computing system is in a power state. method.

12. The telemetry information is the foreground application at the time of power state entry and / or exit; User calendar information indicating free, busy, and / or out of office hours; Battery information, Time, and / or day of week, The method of claim 11 , comprising one or more of:

13. 12. The method of claim 11, wherein the computing system will enter a first power state if the current number of dirty cache lines is greater than the HWM and will enter a second power state if the current number of dirty cache lines is less than the HWM.

14. The method of claim 11 , wherein applying machine learning comprises further reading a timestamp counter to train the machine learning model.

15. The method of claim 11 , wherein applying machine learning comprises inferring the HWM via trained weights and the telemetry information.

16. The method of claim 11 , wherein the first power state is of a lesser depth than the second power state.

17. 17. The method of claim 11, wherein the first power state is an S0i3 state and the second power state is an S0i4 state.

18. 18. A machine-readable storage medium having stored thereon machine-readable instructions which, when executed, cause one or more processors to perform a method according to any one of claims 11 to 17.

19. Memory, A processor coupled to the memory, the processor comprising the device according to any one of claims 1 to 10; a wireless interface that enables the processor to communicate with other devices; A system having

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