Time synchronization device

Abstract

To solve a problem in which quality of network paths from a plurality of master devices to a time synchronizer is not considered.SOLUTION: A time synchronizer that synchronizes time by transmitting / receiving PTP (Precision Time Protocol) packets through a plurality of redundant network paths with a plurality of master devices having reference times includes detection means and selection means. The detection means detects quality of each of the plurality of network paths. The selection means selects one master device to synchronize time from among the plurality of master devices on the basis of the quality of each of the detected network paths.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a time synchronization device, a time synchronization method, and a program for performing time synchronization based on PTP (Precision Time Protocol). [Background technology]

[0002] Systems using IP (Internet Protocol) are being actively constructed in various industrial fields, and in recent years, systems using PTP, a more accurate time synchronization protocol than NTP (Network Time Protocol), have begun to be constructed. Because PTP has higher synchronization accuracy than NTP, it can also be applied to the highly accurate synchronization processing required in social infrastructure and specialized industries, which could not be achieved with NTP in the past.

[0003] As a time synchronization device that performs time synchronization based on PTP, there is a time synchronization device that synchronizes time by transmitting and receiving PTP packets through multiple redundant network paths with multiple master devices having a reference time (see, for example, Patent Document 1). This type of time synchronization device selects the most appropriate time information from multiple pieces of time information received from the multiple master devices and synchronizes its own time. BMCA (Best Master Clock Algorithm) has been disclosed as an algorithm for selecting the most appropriate time information from multiple pieces of time information.

[0004] On the other hand, Patent Document 2 describes a technology in which network quality is monitored on a node-by-node basis, and the network flow is changed by centralized monitoring at a central station based on the results. However, Patent Document 2 does not describe time synchronization based on PTP. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2021-164121 A [Patent Document 2] JP 2011-82858 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, BMCA judges the relative merits of multiple time information from multiple master devices based on several predefined parameters, and does not take into account the quality of the network paths from each master device to the time synchronization device.

[0007] An object of the present invention is to provide a time synchronization device that solves the above-mentioned problems. [Means for solving the problem]

[0008] A time synchronization device according to one aspect of the present invention includes: A time synchronization device that synchronizes time by transmitting and receiving PTP (Precision Time Protocol) packets through multiple redundant network paths between multiple master devices having a reference time, A detection means for detecting the quality of each of the plurality of network paths; a selection means for selecting one master device to synchronize time from among the plurality of master devices based on the quality of each of the detected network paths; The device is configured to include:

[0009] In addition, a time synchronization method according to another aspect of the present invention includes: A time synchronization method in a time synchronization device that synchronizes time by transmitting and receiving PTP (Precision Time Protocol) packets through multiple redundant network paths between multiple master devices having reference times, comprising: Detecting a quality of each of the plurality of network paths; selecting one master device to synchronize time from among the plurality of master devices based on the quality of each of the detected network paths; It is structured as follows.

[0010] In addition, a program according to another aspect of the present invention includes: A computer that transmits and receives Precision Time Protocol (PTP) packets through multiple redundant network paths between multiple master devices having a reference time and synchronizes the time, detecting a quality of each of the plurality of network paths; A process of selecting one master device to synchronize time from among the plurality of master devices based on the quality of each of the detected network paths; The present invention is configured to cause the Effect of the Invention

[0011] By having the above-mentioned configuration, the present invention can select one master device for time synchronization in consideration of the quality of network paths from a plurality of master devices to a time synchronization device. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration according to a first embodiment of the present invention. [Diagram 2] 1 is a diagram showing an example of the configuration of a video IP distribution system to which the present invention is applied. [Diagram 3] FIG. 1 is a diagram illustrating a configuration of a conventional IP gateway (Receiver). [Figure 4] FIG. 2 is a diagram showing an example of a PTP state machine for time control in the first embodiment of the present invention. [Diagram 5] FIG. 11 is a block diagram of a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Next, an embodiment of the present invention will be described in detail with reference to the drawings. [First embodiment] First, in order to facilitate understanding of the first embodiment of the present invention, problems assumed by the first embodiment of the present invention will be described in detail. There are two problems assumed by the first embodiment of the present invention.

[0014] First, we will explain the first issue. In recent years, the shift to IP has accelerated in video distribution systems for broadcasters, and in particular, video IP distribution systems that comply with the SMPTE ST2110 standard use time synchronization using PTP signals. In this method, time information is superimposed on the IP stream itself, and the time information is used to establish video synchronization. Also, PTP signals are transmitted in packets, but they often have a redundant configuration. As shown in Figure 2, one example of the configuration of this video IP distribution system is composed of PTP grandmaster #1 1, PTP grandmaster #2 2, network switch #1 3, network switch #2 4, IP gateway (Sender) 5, and IP gateway (Receiver) 6.

[0015] In this configuration example, the PTP clock distributed from the PTP grandmaster and network switch selects the clock source to obtain the best clock information in accordance with the BMCA rules standardized in SMPTE ST2059-1 / 2. This clock selection function is provided inside the IP gateway (Receiver) 6.

[0016] Fig. 3 shows the configuration of a conventional IP gateway (Receiver) 6. Referring to Fig. 3, the IP gateway (Receiver) 6 is composed of a packet filter #1 7, a packet filter #2 8, a PTP processing unit 10, and a depacketizing unit 20. The PTP processing unit 10 is composed of a PTP slave circuit #1 11, a PTP slave circuit #2 12, a PTP path switching circuit 13, a PTP time generating unit 14, and a BMCA circuit 15. The PTP processing unit 10 selects a clock source for obtaining the best clock information, and the clock source generates time information in the PTP time generating unit 14 and transmits a video output timing signal A to the depacketizing unit 20.

[0017] The depacketizer 20 receives the video signal packets extracted by the packet filter #1 7 and the packet filter #2 8, and passes through the Hitless circuit #1 21, the Hitless circuit #2 22, the Hitless switching circuit 23, and the depacketizer circuit 24 to extract a baseband video signal from the video signal packets, and the output buffer 25 outputs a video output signal B in accordance with the video output timing signal A. The purpose of this video output timing signal A is to output a video at a video timing that matches the phase based on the time information generated from the PTP signal, for example, a specified time.

[0018] In the configuration example of FIG. 3, in the PTP slave circuit #1 11 and the PTP slave circuit #2 12, the delay time due to the path #1 of PTP grandmaster #1 1 - network switch #1 3 - packet filter #1 7, or the delay time due to the path #2 of PTP grandmaster #2 2 - network switch #2 4 - packet filter #2 8, is corrected by PTP time correction based on the delay time calculation method defined in SMPTE ST2059-1 / 2, and further, the PTP path switching circuit 13 selects a clock source according to the BMCA method, but the clock source that reflects the amount of fluctuation occurring in the network of path #1 or path #2 is not selected.

[0019] On the other hand, the Hitless circuit #1 21 and the Hitless circuit #2 22 in the depacketizing unit 20 are provided to recover network disturbances such as packet loss, duplication, and order changes that occur on route #1 or route #2 using the Hitless switching circuit 23, and the amount of fluctuation that occurs in the network of route #1 or route #2 is absorbed within the buffer of the Hitless circuit #1 21 or the Hitless circuit #2 22.

[0020] In such a configuration example, for example, even if the network fluctuation on the path #1 side is larger than that on the path #2, if the clock source determined by the BMCA circuit 15 is the PTP grandmaster #1 1, the PTP path switching circuit 13 selects the path #1, and does not necessarily select the path with the smallest network fluctuation. On the other hand, if the amount of network fluctuation on the path #1 exceeds the amount of buffer memory of the Hitless circuit #1 21, video failure will occur, and in order to prevent this, the Hitless switching circuit 23 selects the Hitless circuit #2 22, which results in delay fluctuations in the output buffer 25, and video delays will occur because the video is forced to stay in the buffer until the delay time specified by the PTP time generation unit 14, and in the worst case, this may result in video failure.

[0021] The above is the first problem to be solved by the first embodiment of the present invention. Next, a second problem to be solved by the first embodiment of the present invention will be described.

[0022] In a video distribution system for broadcasting companies, even in the case of IP, synchronization of the video signals used within the broadcasting station is essential. Loss or disturbance of the synchronization signal immediately leads to video breakdown (instantaneous interruption, phase shift during image synthesis due to phase mismatch with other video signals, etc.). For this reason, as shown in Fig. 1, the PTP time generation unit 14 is equipped with a time control circuit 31 and an internal clock 32, and performs an operation to synchronize the time of the internal clock 32 with the PTP time based on the PTP time information signal E input to the PTP time generation unit 14. This configuration corresponds to a so-called PLL circuit.

[0023] The operation of the time control circuit 31 starts in a so-called unlocked state, in which the time of the PTP time information signal E and the internal clock 32 do not match when the PTP time information signal E is not input (initial state), and when the PTP time information signal E is input and a PLL operation is performed, the time of the PTP time information signal E and the internal clock 32 match, in a so-called locked state. After this locked state, if the PTP time information signal E is cut off or the operation becomes unstable, the internal clock 32 continues the clock operation with its own clock accuracy, in a so-called HoldOver operation, and performs a PLL operation to maintain the accuracy of the internal clock. By this HoldOver operation, even if the PTP time information signal E breaks down, the video output timing signal A output from the PTP time generation unit 14 is maintained, and the video output signal B continues to be output stably. However, a slight clock frequency deviation may occur between the PTP time information signal E and the internal clock 32 in the HoldOver state, and this frequency deviation will accumulate as a time difference after a long time. Therefore, the time when the interruption or unstable operation of the PTP time information signal E is resolved may be off, and when the HoldOver state returns to the Lock state, i.e., when switching back to normal operation, a time jump (phase shift) occurs, resulting in discontinuity of the video output timing signal A, which may ultimately result in a momentary interruption or phase shift of the video output signal B. The switching back to normal operation is automatically performed as a general PLL operation, and if the above-mentioned event occurs in the video signal during broadcast at that time, it may lead to a serious situation that could be called a broadcast accident.

[0024] The above is the second problem that the first embodiment of the present invention is intended to solve.

[0025] Next, the configuration and operation of the first embodiment of the present invention will be described in detail. The IP gateway (Receiver) 6 in this embodiment is one form of the time synchronization device of the present invention. The components of the IP gateway (Receiver) 6, that is, the packet filter #1 7, the packet filter #2 8, the PTP processing unit 10, and the depacketizing unit 20, may be realized by hardware or by executing a computer program in the IP gateway (Receiver) 6.

[0026] Fig. 1 is a diagram showing a configuration example of the first embodiment of the present invention. Referring to Fig. 1, in order to solve the first problem, the present embodiment includes a retention amount monitor circuit #1 26, a retention amount monitor circuit #2 27, and a fluctuation detection and judgment circuit 28 in the depacketizer unit 20 of the IP gateway (Receiver) 6, and a switching judgment circuit 16 in the PTP processing unit 10 of the IP gateway (Receiver) 6. The switching judgment circuit 16 is configured to select a clock source to be synchronized from the PTP grandmaster #1 1 and the PTP grandmaster #2 2 based on the clock source selection signal D output from the BMCA circuit 15 and the fluctuation detection and judgment result signal C output from the fluctuation detection and judgment circuit 28. This point will be described in detail below.

[0027] As shown in FIG. 1, two video IP streams output from an IP gateway (Sender) 5 are input to a Hitless circuit #1 21 and a Hitless circuit #2 22 via a route #1 and a route #2, respectively, and further via a packet filter #1 7 and a packet filter #2 8. As described above, this Hitless circuit is provided to recover network disturbances such as packet loss, duplication, and order change that occurred on route #1 or route #2 using a Hitless switching circuit 23, and the buffer size is determined based on the amount of network delay, etc. The retention amount monitor circuit #1 26 and the retention amount monitor circuit #2 27 observe the amount of network fluctuation occurring on route #1 or route #2 equivalently by observing the retention amount in this buffer. The fluctuation detection and judgment circuit 28 selects the route with the smaller amount of fluctuation based on the observed amount of network fluctuation occurring on route #1 and route #2. Then, the fluctuation detection determination circuit 28 outputs to the switching determination circuit 16 a fluctuation detection determination result signal C that specifies the selected path.

[0028] The following provides a more detailed explanation of the buffer accumulation monitor circuit #1 26, the buffer accumulation monitor circuit #2 27, and the fluctuation detection and determination circuit 28. The buffer accumulation monitor circuit #1 26 and the buffer accumulation monitor circuit #2 27 calculate the buffer accumulation amounts of the Hitless circuit #1 21 and the Hitless circuit #2 22, respectively, by the following formulas. Buffer backlog = maximum buffer capacity prepared in advance - current buffer capacity (1) The fluctuation detection and judgment circuit 28 determines the amount of network fluctuation occurring on paths #1 and #2 by calculating the degree of change over time in the amount of data stored in each buffer, selects the path with the lesser amount of network fluctuation, and outputs a detection and judgment result signal C.

[0029] The switching decision circuit 16 decides which of the paths #1 and #2 to select, that is, which of the PTP grandmaster #1 1 and the PTP grandmaster #2 to select, based on the fluctuation detection decision result signal C output from the fluctuation detection decision circuit 28 and the clock source selection signal D output from the BMCA circuit 15. Then, the PTP path switching circuit 13 selects a path according to the decision of the switching decision circuit 16. As a result, when the path #1 is selected, the PTP grandmaster #1 1 is selected, and when the path #2 is selected, the PTP grandmaster #2 2 is selected.

[0030] The decision logic of the switching decision circuit 16 will be described. When the BMCA circuit 15 can receive both the path #1 and the path #2, the switching decision circuit 16 selects the fluctuation detection decision result signal C, which is the output of the fluctuation detection decision circuit 28. That is, the switching decision circuit 16 selects the path with the smaller amount of network fluctuation from the path #1 and the path #2. Also, when the BMCA circuit 15 can receive only one of the path #1 and the path #2, the switching decision circuit 16 selects the path that can be received. That is, the switching decision circuit 16 selects the clock source selection signal D.

[0031] As described above, according to this embodiment, even if the clock source determined by the BMCA circuit 15 is the PTP grandmaster #11, if the network fluctuation on the path #1 side is larger than that on the path #2, the PTP path switching circuit 13 operates to select the path #1, making it possible to select a path with a smaller amount of network fluctuation. This makes it possible to select a path with a smaller amount of network fluctuation selected by the Hitless switching circuit 23, preventing the occurrence of video delays caused by being forced to stay in the buffer until the delay time specified by the PTP time generation unit 14, and ultimately preventing video breakdown due to a mismatch between the amount of path fluctuation and the clock source.

[0032] On the other hand, in order to solve the second problem, the present embodiment is configured to include a time control circuit 31, an internal clock 32, and an automatic / manual switching setting circuit 33 in the PTP time generating unit 14 as shown in Fig. 1. This point will be described in detail below.

[0033] In this embodiment, as shown in Fig. 1, an automatic / manual switching setting circuit 33 is provided, which makes it possible to select whether the action of switching back to normal operation is automatic or manual. Here, the operation of the time control circuit 31 controlled by the automatic / manual switching setting circuit 33 will be described with reference to Fig. 4.

[0034] The PTP state machine 40 represents the control within the time control circuit 31, and has the role of receiving the PTP time information signal E, performing PLL operation, and then generating the video output timing signal A. When the PTP time information signal E is not input (initial state), the PTP state machine 40 starts from an Unlock state 42. When the PLL operation is performed, the time of the PTP time information signal E and the internal clock 32 match, which is called a Lock state 43. After this Lock state, if the PTP time information signal E is cut off or the operation becomes unstable, the internal clock 32 continues the clock operation with its own clock accuracy, which is called a HoldOver state 44, and performs a PLL operation to maintain the accuracy of the internal clock. By this HoldOver operation, even if the PTP time information signal E is broken, the video output timing signal A output from the PTP time generation unit 14 is maintained, and the video output signal B continues to be output stably.

[0035] However, a slight deviation in clock frequency may occur between the PTP time information signal E and the internal clock 32 in the HoldOver state, and this frequency deviation will accumulate as a time difference after a long time. Therefore, the time when the interruption or unstable operation of the PTP time information signal E is resolved may be different. Therefore, in this embodiment, the point of returning from the HoldOver state 44 to the Lock state 43, that is, switching back to normal operation, is configured to be performed via the automatic / manual switching unit 45 (automatic / manual switching setting circuit 33).

[0036] In other words, when the automatic / manual switching setting circuit 33 is set to "automatic," it acts to return to the Lock state 43 as a normal operation, but when the automatic / manual switching setting circuit 33 is set to "manual," it continues to maintain the HoldOver state 44 without switching back to the Lock state 43, and only when the automatic / manual switching setting circuit 33 is released, i.e., set to "automatic," does it transition to the Lock state 43.

[0037] In this way, according to this embodiment, by providing the PTP state machine 40 with an automatic / manual switching unit 45 (automatic / manual switching setting circuit 33), in the video signal line that affects the video signal being broadcast, it is possible to manually time the return from the HoldOver state 44, thereby preventing video breakdown during broadcast, and ultimately making it possible to avoid serious situations that could be called broadcast accidents.

[0038] [Second embodiment] Fig. 5 is a block diagram of a second embodiment of the present invention. In this embodiment, an overview of the present invention will be described. Referring to Fig. 5, a time synchronization device 100 transmits and receives PTP (Precision Time Protocol) packets to and from a plurality of master devices 200 having a reference time through a plurality of redundant network paths 300 to synchronize the time. The time synchronization device 100 includes a detection means 110 and a selection means 120.

[0039] The detection means 110 is configured to detect the quality of each of the multiple network paths 300. The detection means 110 detects, for example, the amount of network fluctuation as the quality of each of the multiple network paths 300. The detection means 110 is configured to include, for example, a buffer provided corresponding to each of the multiple network paths 300 for absorbing network fluctuation of packets received from the corresponding network path, and a fluctuation detection and determination means for detecting the amount of network fluctuation from a temporal change in the retention amount, which is a value obtained by subtracting the amount of packets currently stored from the maximum capacity of the buffer. For example, the time synchronization device 100 is an IP gateway device that operates as a receiver on an IP network. When the time synchronization device 100 is an IP gateway device, the detection means 110 may be configured to be provided in its depacketizing section.

[0040] The selection means 120 is configured to select one master device to synchronize time from among the multiple master devices 200 based on the quality of each network path 300 detected by the detection means 110. For example, when the selection means 120 is able to receive PTP signals from multiple master devices 200, the selection means 120 selects a master device 200 with a smaller amount of detected network fluctuation from among the multiple master devices 200 from which the selection means 120 is able to receive PTP signals.

[0041] In addition, the time synchronization device 100 may be further configured to include an internal clock (not shown), a PTP time generation means (not shown) for matching the internal clock time to the PTP time from the master device 200 selected by the selection means 120, and an automatic / manual switching setting means (not shown) for setting whether the timing for returning the internal clock, which has transitioned from a Lock state in which the internal clock time matches the PTP time to a HoldOver state, to the Lock state again is to be automatic or manual.

[0042] The time synchronization device 100 configured as above functions as follows: The detection means 110 detects the quality of each of the multiple network paths 300. Next, the selection means 120 selects one master device from the multiple master devices 200 with which to synchronize time, based on the quality of each of the network paths 300 detected by the detection means 110.

[0043] According to the time synchronization device 100 configured and operating as described above, it is possible to select one master device for synchronizing time by taking into consideration the quality of the network paths from the multiple master devices to the time synchronization device. This is because the detection means 110 includes a detection means 110 that detects the quality of each of the multiple network paths 300, and a selection means 120 that selects one master device for synchronizing time from among the multiple master devices 200 based on the quality of each of the detected network paths 300.

[0044] [Other embodiments] In the first embodiment, when the BMCA circuit 15 can receive both the path #1 and the path #2, the switching determination circuit 16 selects the path with the smaller amount of network fluctuation from the path #1 and the path #2, and when the BMCA circuit 15 can receive only one of the path #1 and the path #2, the switching determination circuit 16 selects the path that can be received. However, in the present invention, the method of selecting one of the multiple redundant paths (multiple PTP grandmasters) based on the amount of network fluctuation is not limited to the above. For example, in the case of an asymmetric redundant configuration such as when a large delay difference can occur in the path #1 or the path #2, or when the accuracy or reliability of the PTP grandmaster device or the network switch is different between #1 and #2, the logic of the switching determination circuit 16 may be devised to give priority to the fluctuation detection determination result signal C and the clock source selection signal D.

[0045] For example, consider the following asymmetric redundant configuration. 1. When a large delay difference may occur on route #1 and route #2. 2. The accuracy or reliability of the PTP grandmaster device or network switch is different between route #1 and route #2. In such a case, the switching determination circuit 16 assigns the following priorities to the fluctuation detection determination result signal C and the clock source selection signal D. The priorities are assigned as follows. Fluctuation detection result signal: Priority is given to 1. "When a large delay difference may occur on route #1 or route #2." The standard for "delay difference" is Class A to D according to ST2022-7. Class A: Low skew: 10MS Class B: Medium Skew: 50MS Class C: High skew: 150MS Class D: Ultra-low skew: 150US If the routes are of the same class, no priority is given. If the routes are of different classes, the route with the lower skew is given a higher priority. Clock source selection signal: Priority is given to 2. "When the accuracy or reliability of the PTP grandmaster device or network switch differs between #1 and #2." The announcement messages sent by the BMCA are used as the criteria for "PTP Grandmaster equipment," "network switch," and "accuracy and reliability." This makes it possible to determine the clock quality, stability, and priority of the Grandmaster notified, and sets the priority of the superior clock source selection signal high. When assigning priorities, if conflicting conditions occur simultaneously, which should take precedence? The possible conditions for an asymmetric redundant configuration are the same as above, namely the following two: 1. When a large delay difference may occur on route #1 and route #2. 2. The accuracy or reliability of the PTP grandmaster device or network switch is different between #1 and #2. Consider the case where priorities are assigned in 1 and 2 above, and the results are as follows: Case 1: When both 1. and 2. are judged to have high priority on route #1. Case 2: When both 1. and 2. are judged to be low priority on route #1. Case 3: When 1. is determined to be a high priority and 2. is determined to be a low priority for route #1. Case 4: When 1. is determined to be a low priority and 2. is determined to be a high priority for route #1. Behavior for each case 1. In case 1, route #1 is set as high priority and operated. 2. In case 2, route #2 is set as high priority and operated. 3. In case 3, route #2 is set as high priority and operated. 4. In case 4, route #1 is set as high priority and operated. The reasons for the above behavior are as follows: Regarding behavior 1, since both conditions are judged to be of high priority, it can be set to high priority. Regarding behavior 2, since both conditions are judged to be low priority, it can be set to low priority. Regarding behavior 3, since condition 2 is judged to be low priority, it is set to low priority. This is because the amount of network delay is included in the criteria for condition 2. The announce message used as the criteria for condition 2 is composed of various elements including the amount of network delay. In BMCA, the most suitable GM is set as the primary based on this announce message, which is also an advantageous selection. Regarding behavior 4, condition 2 is judged to have high priority, so it can be set as high priority. This is because condition 2 contains elements of condition 1, just like behavior 3. However, in cases where the network delay is extremely large (for example, more than xx msec), it is possible that behaviors 3 and 4 may be reversed. In such cases, route A will be set as high priority and operated as an exception even in case 3. Regarding such conditions, it will be determined at the time of designing the applicable system whether or not to set this exception.

[0046] Furthermore, although the first embodiment shows an example of a video IP distribution system, even if a system intended only for PTP time synchronization, such as a PTP clock function installed in a general-purpose server, is not equipped with an IP gateway function, it is easy to infer that PTP receiving circuit switching can be realized by detecting PTP packet fluctuations by providing the PTP processing unit 10 with a packet buffer, retention amount monitor circuits 26, 27 equivalent to the Hitless circuits 21, 22 installed in the depacketizing unit 20, and a fluctuation detection judgment circuit 28.

[0047] In addition, the first embodiment is characterized in that it is possible to realize PTP receiving circuit switching by detecting PTP packet fluctuations by providing the congestion amount monitor circuit #1 26, the congestion amount monitor circuit #2 27, and the fluctuation detection and judgment circuit 28. However, even if disturbances other than fluctuations occur in the network, such as packet loss, duplication, and order change, it is possible to select a route with less disturbance by observing these conditions with the congestion amount monitor circuit and providing a detection and judgment circuit.

[0048] In addition, in the first embodiment, an automatic / manual switching unit 45 is provided for control of returning from the HoldOver state 44, allowing selection of automatic / manual switching. However, for the manual mode, it is easy to infer that an operation such as setting a time to switch back in advance, for example, to 26:00-28:00, when broadcasting is suspended, can be performed.

[0049] The present invention also includes an embodiment that solves the first problem but does not solve the second problem, that is, an embodiment that has a configuration in which the automatic / manual switching setting circuit 33 is removed from the configuration of Fig. 1. Alternatively, the present invention also includes an embodiment that solves the second problem but does not solve the first problem, that is, an embodiment that has a configuration in which the retention amount monitor circuits 26 and 27, the fluctuation detection determination circuit 28, and the switching determination circuit 16 are removed from the configuration of Fig. 1.

[0050] Although the present invention has been described with reference to the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. [Industrial Applicability]

[0051] In the field of IP transmission of video signals, this applies particularly to systems that use PTP as a synchronization method, or to devices or circuits equipped with such functions. [Explanation of symbols]

[0052] 1 PTP Grandmaster #1 2 PTP Grandmaster #2 3 Network Switch #1 4 Network Switch #2 5 IP Gateway (Sender) 6 IP Gateway (Receiver) 7 Packet Filter #1 8 Packet Filter #2 10 PTP processing section 11 PTP slave circuit #1 12 PTP slave circuit #2 13 PTP route switching circuit 14 PTP time generator 15 BMCA circuit 16 Switching judgment circuit 20 Depacketizing Department 21 Hitless Circuit #1 22 Hitless Circuit #2 23 Hitless switching circuit 24 Depacketizing circuit 25 Output Buffer 26 Accumulation volume monitor circuit #1 27 Accumulation volume monitor circuit #2 28 Fluctuation detection and judgment circuit 31 Time control circuit 32 Internal Clock 33 Automatic / Manual Switching Setting Circuit 40 PTP State Machine 42 Unlocked 43 Lock state 44 HoldOver state 45 Auto / Manual Switching Unit 100 Time synchronizer 110 Detection means 120 Selection Method 200 Master Device A Video output timing signal B Video output signal C Fluctuation detection result signal D Clock source selection signal E PTP time information signal

Claims

1. A time synchronization device that transmits and receives Precision Time Protocol (PTP) packets between a plurality of master devices having a reference time through a plurality of redundant network paths to synchronize time, A detection means for detecting the quality of each of the plurality of network paths; a selection means for selecting one master device to synchronize time from among the plurality of master devices based on the quality of each of the detected network paths; an internal clock, a PTP time generating means for matching the time of said internal clock with a PTP time from a master device selected by said selecting means, and an automatic / manual switching setting means for setting whether the timing for returning said internal clock to a Lock state again after said internal clock has transitioned from a Lock state in which the time of said internal clock matches the PTP time to a HoldOver state is to be automatic or manual; A time synchronization device comprising:

2. The detection means detects a network fluctuation amount as a quality of each of the plurality of network paths. The time synchronization device according to claim 1 .

3. The detection means includes a buffer provided corresponding to each of the plurality of network paths for absorbing network fluctuations of packets received from the corresponding network path, and a fluctuation detection and determination means for detecting the amount of network fluctuations from a time change in a value obtained by subtracting the amount of packets currently stored from the maximum capacity of the buffer. The time synchronization device according to claim 2 .

4. The time synchronization device is an IP gateway device that operates as a receiver on an IP network, and the detection means is provided in a depacketizing unit of the IP gateway device. The time synchronization device according to claim 3 .

5. When the selection means is able to receive PTP signals from the plurality of master devices, the selection means selects a master device having a smaller amount of detected network fluctuation from among the plurality of master devices able to receive the PTP signals. The time synchronization device according to claim 4.

6. A time synchronization method for a time synchronization device that synchronizes time by transmitting and receiving a Precision Time Protocol (PTP) packet through a plurality of redundant network paths between a plurality of master devices having a reference time, comprising: Detecting a quality of each of the plurality of network paths; selecting one master device to synchronize time from among the plurality of master devices based on the quality of each of the detected network paths; Synchronizing the time of the internal clock with the PTP time from the selected master device; a timing for returning the internal clock, which has transitioned from a Lock state in which the time of the internal clock coincides with the PTP time to a HoldOver state, to the Lock state again is set to be automatic or manual; Time synchronization method.

7. A computer that transmits and receives Precision Time Protocol (PTP) packets to and from a plurality of master devices having a reference time through a plurality of redundant network paths to synchronize time, detecting a quality of each of the plurality of network paths; A process of selecting one master device to synchronize time from among the plurality of master devices based on the quality of each of the detected network paths; A process of synchronizing the time of an internal clock with the PTP time from the selected master device; A process of setting whether the timing for returning the internal clock, which has transitioned from a Lock state in which the time of the internal clock coincides with the PTP time to a HoldOver state, to the Lock state again is to be performed automatically or manually; A program to carry out the above.

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