Power device with current sense

Abstract

To provide a current sensing circuit which maintains high linearity, accuracy, and sensitivity, and is highly resistant to dynamic Ron changes.SOLUTION: An electronic device comprises: a power device circuit 10 comprising a power transistor Q1 and a sensing transistor Q2 comprising a resistive sensing load R_S and a drain connected to the resistive sensing load; a feedback circuit 40; and a switching circuit 30 for connecting the power device circuit to the feedback circuit. A first input of an operational amplifier and the resistive sensing load are selectively connected to the power transistor through the switching circuit. A second input of the operational amplifier 401 and a transconductor 402 are selectively connected to the sensing transistor through the switching circuit. During an ON state of the power transistor, the output current of the transconductor is proportional to the potential difference between the main drain and the drain of the sensing transistor, resulting in a voltage across the resistive sensing load of substantially zero.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to power semiconductor devices and current sensing in power semiconductor devices, particularly but not exclusively to the use of heterostructure AlGaN / GaN high electron mobility transistors. [Background technology]

[0002] Gallium nitride (GaN) is a wide bandgap material suitable for power and RF semiconductor devices.

[0003] GaN technology allows the realization of transistors with high electron mobility and high saturation velocity, which are of great importance in the fields of power and RF electronics. GaN material offers additional advantages in power devices: the wide band gap of this material (Eg=3.39eV) results in a high critical electric field (Ec=3.3MV / cm), which leads to the design of devices with shorter drift regions and, consequently, lower on-resistance, when compared to silicon-based devices of the same breakdown voltage.

[0004] The use of an aluminum gallium nitride (AlGaN) / GaN heterostructure allows the formation of a two-dimensional electron gas (2DEG) at the heterointerface, and carriers have a very high mobility (μ=2000 cm 2 In addition, the piezoelectric polarization charges present in the AlGaN / GaN heterostructure can create a high electron density (e.g., 1e 13 cm -2 ). These properties allow the development of high electron mobility transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters. Much research is focused on the development of power devices using AlGaN / GaN heterostructures. There are several technologies enabling normally-on (Schottky gate based technologies) and normally-off (insulated gate and p-GaN gate technologies) HEMT devices.

[0005] In power electronics, protection and sensing circuits (such as current sensing, overvoltage protection, temperature sensing, etc.) often need to be integrated into the main power switch, which is in enhancement mode. Among them, current sensing is one of the important circuits that should be implemented in power devices.

[0006] Some current sensing devices include a sensing resistor to aid in detecting and / or measuring the current. The current sensing signal (V CS ) is generally proportional to the current through the sensing resistor. Ideally, the current through the sensing resistor is a constant percentage of the current through the main power device over the entire intended current range and over the entire desired operating temperature range (e.g., -55°C to 150°C).

[0007] However, existing current sensing devices have a trade-off between the sensitivity of the device on the one hand and the linearity of the current sensing / accuracy over changing conditions on the other hand. This is because a high Vcs signal increases the sensitivity of the device, while a low Vcs signal improves the linearity of the current sensing signal and its accuracy over temperature and manufacturing process variations. From the perspective of linearity and accuracy, the Vcs signal is ideally close to zero volts, ensuring that the current through the sensing HEMT is a constant percentage of the current through the main power device over the entire range of currents.

[0008] The signal Vcs can be affected by temperature for several reasons: for example, the resistance values ​​of some components used in the current sensing device, such as transistors and resistors, can change with temperature, and also the exact current sharing ratio between, for example, the main HEMT transistor and the current sensing HEMT transistor can change with temperature.

[0009] Furthermore, unlike silicon-based power devices and other semiconductor-based power devices, GaN HEMTs suffer from a condition known as dynamic on-state resistance (Ron). This condition can be described as the variation of on-state resistance when a high-voltage stress is applied to the main device in advance. Although dynamic on-state resistance is important from the perspective of device power loss during long-term operation, it also has a secondary effect on current sensing operation. For example, when a high-voltage stress is applied, only the main HEMT and current sensing transistor of a GaN device are affected by dynamic Ron, while the sensing load resistor Rcs is almost unaffected. This further deteriorates the linearity of current sensing over the entire current range and the accuracy of current sensing over temperature.

[0010] Therefore, applicants have recognized a need for a current sensing device that provides an improved tradeoff between sensitivity and measurement accuracy under a variety of conditions.

[0011] US6433386 (B1) describes a sense field effect transistor (FET) capable of achieving many usable sense current ratios after fabrication and a method for fabricating the same. The sense FET includes a main cell array of metal-oxide-semiconductor field effect transistor (MOSFET) cells connected in parallel and a main pad connected to the source of the main cell.

[0012] US10818786(B1) describes a III-nitride semiconductor-based heterojunction power device comprising a first heterojunction transistor formed on a substrate and a second heterojunction transistor formed on the substrate, where the second heterojunction transistor is used for sensing and protection functions of the first power heterojunction transistor.

[0013] US2022 / 0208761(A1) describes a nitride semiconductor-based heterojunction power device including a first heterojunction transistor formed on a substrate and a second heterojunction transistor formed on the substrate, the second heterojunction transistor being used for sensing and protection functions of the first power heterojunction transistor. The device also includes a monolithically integrated current sensing transistor having a substantially identical structure to the first heterojunction transistor, the current sensing transistor being scaled to a smaller area or a shorter gate width compared to the first heterojunction transistor.

[0014] US11081578(B1) describes a depletion mode III-nitride semiconductor based heterojunction device, which includes a substrate, a III-nitride semiconductor region formed on the substrate, and at least two highly doped semiconductor regions spaced apart from each other.

[0015] US11217687(B1) and US11404565(B1) describe the integration of an auxiliary gate terminal and pull-down network to achieve normally-off (E-Mode) GaN transistors with threshold voltages higher than 2V, low gate leakage currents, and improved switching performance.

[0016] US6304108B1 describes a reference corrected ratiometric current sensing circuit for sensing a current through a load and a power control pass device including a sense device, a sense resistor and a variable reference current source for providing a varying reference current. Summary of the Invention

[0017] The present disclosure relates generally to semiconductor structures and devices formed with wide bandgap semiconductors, and more specifically, to GaN and AlxGaN. 1-x The heterojunction power devices are high voltage HEMTs.

[0018] According to a first aspect of the present disclosure, there is provided an electronic device including a power device circuit including: (i) a main power transistor including a main drain terminal, a main source terminal, and a main gate terminal; (ii) a resistive sensing load; and (iii) a sensing transistor including a source connected to the main source terminal, a gate connected to the main gate terminal, and a drain connected to a first terminal of the resistive sensing load. The electronic device further includes a feedback circuit including at least one operational amplifier and at least one transconductor, and a switching circuit including at least one switch for connecting and disconnecting the power device circuit to the feedback circuit. A first input of the at least one operational amplifier and a second terminal of the resistive sensing load are selectively connected to the main drain terminal via the switching circuit. A second input of the at least one operational amplifier and at least one output of the at least one transconductor are selectively connected to a drain of the sensing transistor via the switching circuit. The main power transistor has a first area or gate perimeter, and the sensing transistor has a second area or gate perimeter smaller than the first area or gate perimeter. During the on-state of the main power transistor, the output current of the transconductor of the feedback circuit is proportional to the potential difference between the main drain terminal and the drain of the sensing transistor, resulting in a substantially zero voltage across the resistive sensing load.

[0019] Optionally, during an off state of the main power transistor, the switching circuit is configured to decouple the feedback circuit from the power device circuit, such that the drain-source voltage of the sensing transistor rises until said voltage is substantially the same as the drain-source voltage of the main power transistor.

[0020] Optionally, the output current of the feedback circuit is directly proportional to the current through the main power transistor.

[0021] Optionally, the operational amplifier is configured to amplify the potential difference between the main drain terminal and the drain of the sensing transistor, the output of the operational amplifier being connected to the input of the transconductor, and the output current of the transconductor being proportional to the output of the operational amplifier.

[0022] Optionally, the feedback circuit is configured to provide an output current of the transconductor to a drain terminal of the sensing transistor, forming a feedback loop configured to maintain a potential difference between the main drain terminal and the drain of the sensing transistor at a constant value.

[0023] Optionally, the op-amp is configured to operate in a low power mode with a conditioned gate drive signal in which the gate drive signal is inverted, time shifted or level shifted.

[0024] Optionally, at least one transconductor is a p-channel transistor.

[0025] Optionally, the switching circuitry is configured to (i) connect the feedback circuit to the power device circuit at a predetermined time after the power device circuit is turned on, and (ii) disconnect the feedback circuit from the power device circuit at a predetermined time before the power device circuit is turned off.

[0026] Optionally, the switching circuit includes first, second and third switches configured to respectively connect and disconnect the main drain terminal to a first input of an operational amplifier of the feedback circuit, the drain of the sensing transistor to a second input of the operational amplifier and the output of the transconductor to the drain of the sensing transistor.

[0027] Optionally, the first, second and third switches include enhancement mode HEMTs.

[0028] Optionally, the first, second and third switches comprise T-type switches having two enhancement mode transistors connected in series, and a gate terminal of each of the first, second and third switches is connected to a switch enable signal and to a high impedance component having a first end connected between the respective two enhancement mode transistors and a second end connected to ground.

[0029] Optionally, the feedback circuit Skandak The current mirror circuit is configured to generate an output current identical to the output current of the inverter.

[0030] Optionally, the electronic device is configured to convert an output current of the current mirror circuit into an output voltage signal using a resistor.

[0031] Optionally, the electronic device includes a digital programmable decoder configured to adjust the gain of the current mirror circuit in response to one or more digital inputs to the digital programmable decoder.

[0032] Optionally, the electronic device comprises a wide bandgap semiconductor die and a silicon semiconductor die, the power device circuitry and the switching circuitry being provided on the wide bandgap semiconductor die and the feedback circuitry being provided on the silicon semiconductor die.

[0033] Optionally, the wide bandgap semiconductor die and the silicon semiconductor die are integrated into a single system-in-package.

[0034] Optionally, the silicon semiconductor die includes at least one of a gate drive circuit, an overcurrent protection circuit, an overtemperature detection and protection circuit, an undervoltage detection or lockout circuit, a voltage regulator, a bandgap reference circuit, a level shifter, an ESD protection circuit, a start-up circuit, a logic circuit, a memory storage device, and / or a slew rate control circuit.

[0035] Optionally, the wide bandgap semiconductor die is a gallium nitride (GaN) die.

[0036] Optionally, the electronic device includes a wide bandgap semiconductor die and a silicon semiconductor die, the power device circuitry being provided on the wide bandgap semiconductor die and the switching circuitry and the feedback circuitry being provided on the silicon semiconductor die.

[0037] Optionally, the main power transistor comprises an active heterojunction transistor including a Miller clamp transistor, the Miller clamp transistor being monolithically integrated with a drive circuit for the active heterojunction transistor.

[0038] In general terms, the electronic device of the present disclosure uses a feedback circuit to ensure that the sensing transistor is always driven at the same voltage level as the main power transistor, such that any inferences made using the sensing transistor about the current through the main power transistor are more accurate because the output of the feedback circuit ensures that the sensing transistor (over which such inferences are made) is exposed to substantially the same operating conditions (voltage, temperature, etc.) as the main power transistor.

[0039] More generally, the sensing transistor has a similar architecture as the main power transistor, meaning that the sensing transistor and the main power transistor have substantially the same structure (i.e., are constructed from the same materials and layers as each other) and operation. However, the sensing transistor used to make inferences about the current flowing through the main power transistor is scaled to a different area or gate perimeter than the main power transistor by a given scale factor X. The scale factor X is assumed to be greater than 1, meaning that the sensing transistor is smaller than the main power transistor by that factor. For example, a scale factor of 2 means that the area or gate perimeter of the main heterojunction is twice the size of the sensing transistor. Conversely, a scale factor less than 1 means that the sensing transistor is larger than the main power transistor.

[0040] The sensitivity S of the current sensing arrangement can be defined as the ratio of the output (voltage) signal Vcs to the current Imain flowing through the main power device.

[0041]

number

[0042] For a current sensing device, "ideal" linearity means that the current sensing sensitivity is linear over the entire current range, i.e., the derivative of the sensitivity with respect to current (dS / dImain) is constant or nearly constant over the entire current range of the device. Signal linearity can therefore be defined as a measure of how nearly constant this derivative is over the entire current range.

[0043] With ideal linearity, Vcs would increase linearly with the current through the main power device 19, so that the signal Vcs would be an accurate measurement of the current through the main power device 19 (shown in FIG. 2) over the entire current range. In reality, the signal Vcs is not perfectly linear for many reasons, some of which are discussed below. However, the closer the linearity is to a constant value, the more accurate the current sensing solution will be with respect to the current.

[0044] One of the factors that affect the linearity of the current sensing signal Vcs is temperature. The accuracy of the signal Vcs with respect to temperature is determined by how close the derivative of the sensitivity with respect to temperature (dS / dT) is to zero; i.e., an "ideal" accuracy with respect to temperature means that this derivative is zero over the entire temperature range, and there is no variation in the linearity of the signal Vcs with respect to temperature (at least over the expected or desired operating temperature range).

[0045] A further factor affecting the linearity of the current sensing signal Vcs is the (manufacturing) process variation. In this context, process variation refers to a general parameter that describes the variation in the structure of the current sensing device, such as differences between metal layers, 2DEG charge, doping profile, trap distribution in different semiconductor layers or at interfaces, gate leakage between devices on the same chip, on the same wafer, between wafers or between batches. The accuracy of the signal Vcs with respect to process variation is determined by how close the derivative (dS / dPV) of the sensitivity with respect to process variation is to zero, i.e., an "ideal" accuracy with respect to process variation means that this derivative is zero over the entire range of statistical process variation and there is no variation in the linearity of the signal Vcs with respect to process variation.

[0046] Hence, better dynamic Rds onA more temperature-independent current sensing method with robustness is needed. Ideally, it can be concluded that to improve the accuracy of a current sensing solution, the voltage signal developed across the sensing load should be very small compared to the voltage drop between the source and drain terminals (or the sensing load resistance should be small compared to the resistance of the sense HEMT transistor).

[0047] In general terms, it is an objective of the present disclosure to provide a current sensing circuit that can maintain high linearity, accuracy, and sensitivity over a desired current and temperature range, and provide high tolerance to dynamic Ron changes. The present disclosure provides a solution by using a feedback circuit, as described below.

[0048] As outlined above, maintaining approximately the same drain-to-source bias of the main power transistor and the sensing transistor during both on-state and off-state operation helps improve the performance of the current sensing circuit.

[0049] Thus, as described above, in one embodiment, the feedback circuit is configured to maintain the drain potential of the sensing transistor at approximately the same potential as the drain potential of the main power transistor. As described above, the drain terminal of the main power transistor may be connected as a first input to the feedback circuit, and the drain terminal of the sensing transistor may be connected as a second input to the feedback circuit. In one example, the feedback circuit may be comprised of an operational amplifier (op-amp) receiving a voltage signal input of the feedback circuit. In operation, the op-amp may be configured such that an increase in the voltage input of the op-amp (i.e. the voltage difference between the drain potential of the main transistor and the drain potential of the sensing transistor) leads to an increase in the output of the op-amp. The output of the op-amp may be connected, as an example, to a transconductor comprised of at least one transistor. Thus, the output of the op-amp is connected to the gate of at least one transistor of the transconductor that controls the output of the feedback circuit. The output of the feedback circuit may be (indirectly) connected to the sensing terminal of the sensing transistor, as described in the first aspect of the invention, to form a feedback loop configured to maintain the drain potentials of the main power transistor and the sensing transistor at approximately the same potential. This is possible when the output current of the feedback circuit settles to an equilibrium output current of IDS / X, where IDS is the drain-source current through the main power transistor in on-state operation and X is a scale factor defined herein.

[0050] The feedback circuit output current IDS / X may be mirrored and provided as a current sense output signal of the power device. The current signal may be converted to a voltage signal using a resistor. In some examples, the current mirror gain may be adjustable using a digital decoder.

[0051] In the off-state operating mode, it may be desirable to decouple the drain terminal of the main power transistor and the sensing transistor as inputs of the feedback circuit. Similarly, the output of the feedback circuit may be decoupled from the drain terminal of the sensing transistor. This may be necessary to protect the op-amp since in the off-state operating mode the drain terminals of the main power transistor and the sensing transistor may reach high voltages (such as 50V or more). This is the function of the switching circuit described in the first aspect of the invention. The described switch must be conductive in the on-state operating mode of the power transistor and cut off in the off-state operating mode of the power transistor. Thus, the signal controlling the switch may be substantially similar to the signal driving the power transistor. Nevertheless, since it is important that the feedback circuit is always disconnected when a high voltage is present at the drain of the power transistor, the edges of the signal controlling the switch may be shifted in time compared to the edges of the signal controlling the power transistor. In another example, the signal controlling the switch may be level shifted compared to the gate drive signal of the power transistor.

[0052] In the off-state operating mode, the feedback circuit is disconnected from the drains of the power and sensing transistors, so the sensing load brings the drains of the power and sensing transistors to nearly the same potential. In this state, the off-state leakage current is small, so the voltage drop across the sensing load is negligible. By keeping the drain-source voltages between the main and sensing transistors nearly the same during the off-state, the dynamic Rds seen by the main and sensing transistors is minimized. on The increase in should be roughly the same.

[0053] In some examples, the power consumption of an op-amp or feedback circuit may depend on a gate signal for a main power transistor. A conditional version of the gate signal (e.g., inverted, time-shifted, level-shifted, etc.) may be used to enable or disable a low-power mode of the op-amp or feedback circuit.

[0054] The described design considerations are intended to improve the linearity and accuracy of the current sensing signal over temperature and manufacturing process variations while providing sensing immunity to dynamic Ron changes.

[0055] The power device circuits in the above aspects of the disclosure may be designed on wide band gap semiconductor materials. An example material may be gallium nitride (GaN), particularly devices based on AlGaN / GaN heterojunction structures. Other examples of wide band gap semiconductor materials include, but are not limited to, silicon carbide, gallium arsenide, indium phosphide, diamond, etc. Other circuits described in the first aspect of the invention may also be designed in wide band gap materials, or in different materials, such that the overall circuit is implemented on two chips made of different semiconductor materials.

[0056] The electronic devices described in the above aspects of the disclosure may be implemented on two different semiconductor materials, but may also be on the same chip. As an example, in GaN-on-Si technology, part of the circuitry is implemented on GaN (e.g. high voltage components) and part of the circuitry is implemented on silicon.

[0057] In some instances, the feedback circuitry may be implemented on a co-packaged silicon chip rather than monolithically on the same GaN chip as the main and sensing transistors. Implementing the feedback circuitry in silicon offers several advantages, including reduced power consumption, increased speed, etc., due to the availability of mature p-channel devices in silicon, which are in a fairly early stage of development in GaN technology.

[0058] Silicon chips can be included in the same package as the GaN chips, which allows for additional functionality to be implemented in a more mature technology. Examples of blocks designed on silicon to complement the operation of GaN power transistors include gate drives, bandgap references, overcurrent protection (OCP), temperature sensing and overtemperature protection (OTP), voltage regulators, slew rate control, UVLO, level shifters, ESD protection, logic circuits, start-up circuits, etc.

[0059] There may still be advantages to keeping certain additional components / circuits / circuit blocks in GaN, e.g. high voltage transistors in addition to the main power transistor, parasitic critical components / circuits in the connections to the main power transistor (e.g. Miller clamp) and / or components where matching over process / temperature is critical.

[0060] In some embodiments, the switches that connect / disconnect the feedback circuits are designed with GaN, and in other embodiments, with silicon. Designing these switches with GaN may be preferable since they are required to block high voltages, making them a similar technology to power transistors. [Brief description of the drawings]

[0061] The present disclosure will be more fully understood from the accompanying drawings, which should not be taken to limit the disclosure to the particular embodiments illustrated, but are provided solely to aid in explanation and understanding.

[0062] [Figure 1] FIG. 1 illustrates a schematic of an example of a sense field effect transistor (FET). [Diagram 2] FIG. 2 is a schematic diagram of an example current sensing circuit with an external amplifier. [Diagram 3]FIG. 3 illustrates generally an example of a block diagram of a current sensing circuit according to one embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic diagram of an example current sensing circuit according to one embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram illustrating an example of a pulse sequence according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic diagram of a second example current sensing circuit with an external current output according to an aspect of the present disclosure. [Figure 7] FIG. 7 is a schematic diagram of a third example current sensing circuit having an external current output according to an embodiment of the present disclosure. [Figure 8] FIG. 8 illustrates a schematic diagram of a fourth exemplary current sensing circuit according to an embodiment of the present disclosure. [Figure 9] FIG. 9 illustrates a schematic diagram of an exemplary switch according to an embodiment of the present disclosure. [Figure 10] FIG. 10 illustrates a schematic diagram of a second exemplary switch according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a schematic diagram of a fifth exemplary current sensing circuit according to an embodiment of the present disclosure. [Figure 12] FIG. 12 illustrates a block diagram of an electronic device according to an embodiment of the present disclosure. [Figure 13] FIG. 13 illustrates an example Miller clamp circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0063] FIG. 1 shows an example of a sense FET. The sense FET includes a main FET Qm and a sub-FET Qs. The main FET and the sub-FET are connected in parallel, but have two sources. The main source Sm of the main FET is grounded, and the sense source SS of the sub-FET is connected to an external sense resistor Rs (ext) It is connected to the sense resistor Rs to detect the voltage drop Vs. (ext)are connected externally via pins. The main FET and sub FET are made from many cells of the same structure, and therefore have the same current-voltage characteristics. However, the main FET may have many times (for example, hundreds or thousands) more cells than the sub FET. As a result, because the on-resistance of a MOSFET is inversely proportional to the number of cells in the FET, the sub FET will pass a current Is that is a certain percentage of the current Im passed by the main FET, and the on-resistance of the sub FET will be much higher than the on-resistance of the main FET.

[0064] FIG. 2 shows an example of a monolithically integrated GaN chip 200 consisting of a main power device or first power transistor 19 and a current sensing transistor 16. In this example, the current sensing transistor 16 has the same structure as the main power device 19, but the surface area or number of fingers compared to the main power device is reduced by a known ratio, for example, the current sensing transistor 16 is 100 times or 1000 times smaller than the main power device 19. The main power device 16 is a main high voltage HEMT, and the current sensing transistor is a high voltage sense HEMT. The source of the current sensing transistor 16 is connected to a load or a current sensing resistor 15. The resistor 15 may be monolithically integrated with the main power device 19 and the current sensing transistor 16, or may be external. In this arrangement, the sensing signal VCs is proportional to the current flowing through the sensing resistor 15. Under ideal conditions, the current through the sensing resistor 15 will be a constant percentage of the current through the main power device 19 over the entire current range and over the desired temperature range (eg, −55° C. to 150° C.).

[0065] In the GaN chip 200, Vcs can be adjusted by increasing or decreasing the resistance Rcs of the sensing resistor 15. During linear on-state operation, the main HEMT device 19 and the HEMT sense transistor 16 can be modeled as resistors controlled by the gate potential (with resistances Ron-main and Ron-sense, respectively). When Vcs is low (which generally improves the linearity of the current sensing solution), the ratio of Rcs to Ron-sense is ideally small (e.g., less than 0.1). Because of this model, i.e.

number

[0066] where Vds is the voltage drop across the drain-source terminals of the current sense transistor 16. As a result, RCS being small compared to Ron-sense helps to mitigate the effect of the dynamic Ron of the current sense transistor 16 and improve the current sensing accuracy of the device.

[0067] One solution to the trade-off between sensitivity and linearity of the signal Vcs is to keep Vcs relatively low (e.g., over temperature and process variations) to improve the linearity and accuracy of the current sensing, and provide an external amplifier 50 connected to the Vcs node to improve the sensitivity of the current sensing device, as shown in FIG. 2. In this case, the current sensing sensitivity is given by the ratio of the output signal Vo (equal to the product of Vcs and the amplification factor of the amplifier 50) to the current Imain flowing through the main power device 19. However, providing the external amplifier 50 increases the bill of materials (BOM) and manufacturing costs. In addition, parasitic components (e.g., parasitic inductance, parasitic capacitance, parasitic resistance) resulting from the extra connection between the GaN chip 200 and the external chip of the amplifier 50 may affect the current sensing reading, especially at high operating frequencies. Attempting to monolithically integrate the amplifier 50 with the power switching device 19 of the GaN chip 200 is significantly complicated by the fact that the potential of the current sensing node Vcs is very low (in most cases below the threshold voltage of an enhancement mode transistor) and the sensing load 15 is attached to ground level.

[0068] On the other hand, as mentioned above, it is often advantageous to limit the maximum voltage across the sensing load. If this sensing voltage is too high (e.g., greater than 0.3V), the current through the current sensing transistor will not be proportional to the current through the main transistor, and the linearity of the sensing signal Vcs may be compromised. Moreover, as already mentioned, the linearity and accuracy may be further compromised over the entire temperature range and in the presence of other factors such as dynamic on-state resistance (specific to GaN HEMTs) and manufacturing tolerances. Therefore, it can be seen from the above discussion that it may be advantageous to limit the maximum voltage drop across the sensing load to as small as possible, for example, less than 0.3V, less than 0.2V, or even less than 0.1V. When the sensing load and the sensing transistor are arranged in series (see Figures 1 and 2), the sum of the voltages across the sensing load and the sensing transistor (i.e., between the drain and source terminals of the sensing transistor) is equal or approximately equal to the voltage drop between the drain and source terminals of the main transistor. During normal on-state operation, the voltage drop across the source-drain terminals of the main transistor is often less than 2 V, and the voltage drop across the sensing load is advantageously on the order of 0.2 V or less, so the sensing load resistor may be selected to be less than 1 / 10 of the on-state resistance of the sensing load transistor. Typical values ​​for these resistors may be in the ohm range (e.g., 1-5 ohms), although it will be appreciated that all of the above values ​​may vary significantly depending on the particular rating and application in which the device is used.

[0069] As a result, broadly speaking, in the current sensing devices described in this disclosure, it is advantageous, but not essential, that the voltage signal developed across the sensing load is small compared to the voltage drop across the source-drain terminals of the sensing transistor (and / or it is desirable for the sensing load resistance to be small compared to the resistance of the sensing transistor) in order to improve the accuracy of the current sensing solution. This equally applies when the sensing load is located between the main power transistor and the drain terminal of the sensing transistor, as shown in FIG.

[0070] 3 is a schematic diagram of a current sense architecture according to the present disclosure illustrating at a high level the advantages provided by the feedback circuit. The architecture comprises a power device circuit 10, a switching circuit 30 and a feedback circuit 40. The power device circuit 10 comprises a power transistor Q1, a sensing transistor Q2 and a resistive sensing load R_S. The switching circuit 30 connects and disconnects the power device circuit 10 to the feedback circuit 40 based on a Switch_Enable signal. The feedback circuit 40 includes an operational amplifier AMP1 (401) and a transconductor 402.

[0071] 4, the feedback circuit 40 includes an operational amplifier AMP1 and an additional p-channel transistor Q3 as a transconductor. The switching circuit 30 consists of three switches 1, 2, 3. During steady-state operation of the power transistor, it is ensured that the sensing transistor always "follows" the power transistor in terms of terminal voltage, and that the voltage drop across the resistive sensing load is approximately zero.

[0072] In active current sensing mode, when the gate signal is HIGH, switches 1, 2, and 3 are closed and feedback circuit 40 is connected. To ensure that feedback circuit 40 is protected, the signal to close switches 1, 2, and 3 may be delayed compared to the gate signal going HIGH. This is to ensure that there is enough time for the drain-source potential across the main power transistor to drop during turn-on before feedback circuit 40 is connected. An exemplary pulse sequence is shown in FIG.

[0073] During on-state operation, the VDS of the power transistor is also established across the sensing transistor due to the action of the feedback circuit. Since VDS is ideally equal to VDSS, the current through the resistor (R_S) is ideally zero.

[0074] In this way, a current signal that is a known ratio of the current through the main power transistor is present in the circuit at the output of the feedback circuit. The sensing transistor has a similar architecture to the main power transistor, but has a significantly lower area, i.e., gate perimeter, due to the design ratio m=X, which determines the ratio between the measured current of the sensing transistor and the actual current of the power transistor.

[0075] When the gate signal is LOW and the main power transistor operates in the off-state operating mode, switches 1, 2, and 3 are opened and the feedback circuit is disconnected. This prevents high voltage from occurring at the input of the feedback circuit when turned on or in the off state. In order to disconnect the feedback circuit before the drain terminal potential of the main power transistor rises, the signal changeover switches 1, 2, and 3 can be made to lead the gate signal for a short time, as shown in Figure 5.

[0076] Power transistor V DSis established across the sensing transistor through resistor R_S. Since the leakage current through the sensing transistor in the off state is very small (e.g., less than 1 μA), the voltage drop across R_S is negligible. Therefore, the dynamic Ron change is reproduced in both the sense HEMT and the power HEMT.

[0077] The example of FIG. 3 shows how the current IDS / X is obtained in the circuit. In an additional example shown in FIG. 6, the sense current IDS / X can be mirrored using transistors Q4 and / or Q5. In the case of a current mirror using transistor Q5, the sense current can be provided as an external current output. In the case of a current mirror using transistor Q4, the output current can be converted to a current sense voltage signal using an external resistor. The external resistor can be selected according to the specifications of the controller used in the electronic device.

[0078] In another example, further flexibility can be provided by using a digital decoder 501 that allows the gain of the current mirror to be adjusted by adjusting the size of transistors Q4 and / or Q5. This is shown in Figure 7. The digital decoder inputs may be provided as external terminals g0, g1 so that the gain of the current mirror can be adjusted with an off-chip signal.

[0079] As outlined herein, when the gate signal is low, the feedback circuit 40, and therefore the op-amp AMP1, is disconnected. During this period, the op-amp is not functional, so it is beneficial to limit the power consumption of the op-amp. This can be achieved by providing a Low_Power_Enable signal to the op-amp during the period when the gate signal is low. The Low_Power_Enable signal can therefore be an inverted gate drive signal, as shown in FIG. 8.

[0080] Figure 9 shows examples of switches 30a, 30b, and 30c. The switches may be simple enhancement mode transistors similar to the main power transistors (although the size may differ by design). For example, in the case of switch 30a, the drain terminal of the switch is connected to the drain terminal of the main power transistor.

[0081] 10 is a schematic diagram of SWITCH1, which connects Vds to the IN- input of the operational amplifier AMP1 according to the present disclosure. The other switches SWITCH2 and SWITCH3 have a similar structure. These switches avoid high voltages being applied to the operational amplifier when the power device circuit is turned off, and also allow feedback from the transconductor to be provided to the drain terminal of the sensing transistor.

[0082] FIG. 11 shows another embodiment of the present disclosure in which the current sense architecture includes a power device circuit 10 consisting of a power transistor Q1 and a sensing transistor Q2 implemented on a wide bandgap semiconductor chip 60, and a feedback circuit 40 implemented on a silicon chip 20a. Implementing the power device circuit on a wide bandgap semiconductor chip allows for effective high voltage operation. The switching circuit 30 is also preferably implemented on the wide bandgap semiconductor chip 60 since a switch is required to block high voltages and therefore can be of similar technology to the power transistors. Implementing the op-amp on a silicon chip is beneficial because the switch allows selective application of signals to the inputs of the op-amp, protecting it from high voltages.

[0083] In this embodiment, the wide bandgap semiconductor chip 60 may be made of gallium nitride (GaN). Other examples of wide bandgap semiconductor chips include, but are not limited to, silicon carbide, gallium arsenide, indium phosphide, or diamond. Implementing the feedback circuit 40 on a silicon chip, rather than monolithically integrating the feedback circuit on a GaN chip, can provide advantages in terms of speed, power dissipation, design flexibility, yield, etc., due to the maturity of silicon technology compared to GaN technology, especially with respect to the availability of p-channel devices.

[0084] In another embodiment, the electronic device comprises a system in package consisting of a GaN semiconductor die 60 and a silicon semiconductor die 20, as shown in FIG. 12. The GaN semiconductor die 60 includes power and sense transistors, and the silicon semiconductor die includes control and protection circuitry. The control and protection circuitry may include, but is not limited to, gate drives, overcurrent protection, overtemperature detection and protection, operational amplifiers, voltage regulators, bandgap references, slew rate control, UVLO, level shifters, ESD protection, logic circuits, start-up circuits, and / or other control and protection circuitry. A Miller clamp 104 may also be included in the GaN semiconductor die 60.

[0085] FIG. 13 shows an example of the Miller clamp 104 shown in FIG. 12. The Miller clamp may be driven by a driving circuit (e.g., an inverter) located on the same GaN die or may be driven by a driving circuit located on the silicon die. In another example, the Miller clamp is configured as a distributed Miller clamp, i.e., a network of sub-transistors connected to a distributed network of main power sub-transistors. This allows the Miller clamp sub-transistors and their associated main power sub-transistors to be closer together, reducing the parasitic components of the connection between them. This can suppress oscillations and / or capacitive coupling effects in the device during operation.

[0086] It should be noted that the above illustrated embodiments are only some examples, and the present disclosure may be practiced in other embodiments, such as monolithically integrating all circuitry within a GaN semiconductor package, combining GaN and silicon semiconductor devices within a single package, or integrating one or more other types of semiconductor devices, such as silicon carbide, gallium arsenide, indium phosphide, or diamond, within a single package.

[0087] Those skilled in the art will appreciate that in the foregoing description and in the appended claims, positional terms such as "top," "upper," "over," "under," "side," and the like are made with reference to conceptual illustrations of the device, such as those showing standard cross-sectional perspectives and those shown in the accompanying drawings. These terms are used for ease of reference and are not intended to be limiting in nature. Thus, these terms should be understood to refer to the device when oriented as shown in the accompanying drawings.

[0088] Although the present disclosure has been described in terms of preferred embodiments as above, it should be understood that these embodiments are merely illustrative and the claims are not limited to these embodiments. Those skilled in the art will be able to make modifications and substitutions in light of the present disclosure, which are intended to be included in the scope of the appended claims. Each feature disclosed or illustrated in this specification can be incorporated into the present disclosure, either alone or in appropriate combination with other features disclosed or illustrated in this specification.

[0089] Many other effective alternatives will occur to those skilled in the art, and it will be understood that the present disclosure is not limited to the described embodiments, but encompasses all modifications that fall within the scope of the disclosure and the appended claims.

Claims

1. 1. A power device circuit, comprising: a main power transistor including a main drain terminal, a main source terminal, and a main gate terminal; a resistive sensing load; a sensing transistor having a source connected to the main source terminal, a gate connected to the main gate terminal, and a drain connected to a first terminal of the resistive sensing load; a power device circuit including: a feedback circuit including at least one operational amplifier and at least one transconductor; a switching circuit including at least one switch for connecting and disconnecting the power device circuit to the feedback circuit; Including, a first input of the at least one operational amplifier and a second terminal of the resistive sensing load are selectively connected to the main drain terminal via the switching circuit; a second input of the at least one operational amplifier and at least one output of the at least one transconductor are selectively connected to a drain of the sensing transistor via the switching circuit; the main power transistor has a first area or gate perimeter; the sensing transistor has a second area or gate perimeter that is smaller than the first area or gate perimeter; As a result, during the on-state of the main power transistor, the output current of the transconductor of the feedback circuit is proportional to the potential difference between the main drain terminal and the drain of the sensing transistor, resulting in a voltage developed across the resistive sensing load that is substantially zero.

2. 2. The electronic device of claim 1, wherein during an off-state of the main power transistor, the switching circuit is configured to decouple the feedback circuit from the power device circuit, such that the drain-source voltage of the sensing transistor rises until the voltage is substantially the same as the drain-source voltage of the main power transistor.

3. 2. The electronic device of claim 1, wherein the output current of the feedback circuit is directly proportional to the current through the main power transistor.

4. the operational amplifier is configured to amplify a potential difference between the main drain terminal and a drain of the sensing transistor; the output of the operational amplifier is connected to the input of the transconductor; The output current of the transconductor is proportional to the output of the operational amplifier. The electronic device of claim 1 .

5. 5. The electronic device of claim 4, wherein the feedback circuit is configured to generate a feedback loop configured to supply an output current of the transconductor to a drain terminal of the sensing transistor and to maintain a potential difference between the main drain terminal and the drain of the sensing transistor at a constant value.

6. 10. The electronic device of claim 1, wherein the operational amplifier is configured to operate in a low power mode by a conditional gate drive signal, the gate drive signal being inverted, time shifted or level shifted.

7. 10. The electronic device of claim 1, wherein at least one transconductor is a p-channel transistor.

8. 2. The electronic device of claim 1, wherein the switching circuitry is configured to: (i) connect the feedback circuitry to the power device circuitry for a predetermined time after the power device circuitry is turned on; and (ii) disconnect the feedback circuitry from the power device circuitry for a predetermined time before the power device circuitry is turned off.

9. The switching circuit includes: a first input of the operational amplifier of the feedback circuit from the main drain terminal; a drain of the sensing transistor to a second input of the operational amplifier; The output of the transconductor is connected to the drain of the sensing transistor.

10. The electronic device of claim 1, further comprising first, second and third switches configured to respectively connect and disconnect

10. The electronic device of claim 9 , wherein the first, second and third switches comprise enhancement mode HEMTs.

11. 10. The electronic device of claim 9, wherein the first, second and third switches comprise T-type switches having two enhancement mode transistors connected in series, and a gate terminal of each of the first, second and third switches is connected to a switch enable signal and to a high impedance component having a first end connected between each of the two enhancement mode transistors and a second end connected to ground.

12. The electronic device of claim 1 , wherein the feedback circuit includes a current mirror circuit configured to generate an output current identical to an output current of the transconductor.

13. The electronic device of claim 12 , wherein the electronic device is configured to convert an output current of the current mirror circuit into an output voltage signal using a resistor.

14. 13. The electronic device of claim 12, further comprising a digital programmable decoder configured to adjust a gain of the current mirror circuit in response to one or more digital inputs to the digital programmable decoder.

15. 2. The electronic device of claim 1, comprising a wide bandgap semiconductor die and a silicon semiconductor die, the power device circuitry and the switching circuitry being provided on the wide bandgap semiconductor die, and the feedback circuitry being provided on the silicon semiconductor die.

16. The electronic device of claim 15 , wherein the wide bandgap semiconductor die and the silicon semiconductor die are integrated into a single system-in-package.

17. the silicon semiconductor die Gate drive circuit, overcurrent protection circuit, Overheat detection and protection circuit, Low voltage detection circuit or lockout circuit, Voltage regulators, A bandgap reference circuit, Level shifters, ESD protection circuits, startup circuits, logic circuits, memory storage, Slew Rate Control Circuit The electronic device of claim 15 , comprising at least one of:

18. The electronic device of claim 15 , wherein the wide bandgap semiconductor die is a gallium nitride (GaN) die.

19. 2. The electronic device of claim 1, comprising a wide bandgap semiconductor die and a silicon semiconductor die, the power device circuitry being provided on the wide bandgap semiconductor die, and the switching circuitry and the feedback circuitry being provided on the silicon semiconductor die.

20. 2. The electronic device of claim 1, wherein the main power transistor comprises an active heterojunction transistor including a Miller clamp transistor, the Miller clamp transistor being monolithically integrated with a drive circuit for the active heterojunction transistor.

Images