Capacitor-based synaptic network structure with metal shielding between outputs

Abstract

The neural network device includes a first plurality of synaptic network capacitors, where the synaptic network capacitors of the first plurality of synaptic network capacitors share a first output terminal. The neural network device further includes a second plurality of synaptic network capacitors, where the synaptic network capacitors of the second plurality of synaptic network capacitors share a second output terminal. The neural network device further includes a metal shield disposed between the first output terminal and the second output terminal. The neural network device can be used as part of an artificial intelligence system.

Description

[Background technology]

[0001] A deep neural network (DNN) is an example of an artificial neural network (ANN) that is a structure consisting of many layers (e.g., an input layer, multiple hidden or intermediate layers, and an output layer) that contain network nodes (representing "neurons") that are operatively connected by connectors that are weighted based on the relative importance of the connections (representing "synapses") in different configurations. DNNs have many hidden or intermediate layers (e.g., on the order of tens, hundreds, or even thousands, hence the term "deep") and are designed to mimic the decision-making functions of a biological human (or animal) brain.

[0002] As such, DNNs have been implemented in many technology fields, including but not limited to artificial intelligence systems that include machine learning or deep learning algorithms implemented in one or more neuromorphic or neural network devices. Examples of applications of neural network-based artificial intelligence systems include, but are not limited to, image or object recognition, in which a type of DNN called a convolutional neural network (CNN) is used (e.g., CNNs perform mathematical convolution operations to generate one or more image classifications).

[0003] The underlying computing hardware used to implement a DNN (CNN or any other form of ANN) can include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), or an application-specific integrated circuit (ASIC) based on standard complementary metal-oxide semiconductor (CMOS) logic. Resistor-based (e.g., memristor) networks have been commonly used to implement the synapses of a DNN. Summary of the Invention

[0004] An embodiment of the present invention provides a capacitor-based synapse network structure with metal shielding between the outputs. In one exemplary embodiment, the neural network device includes a first plurality of synaptic network capacitors, the first plurality of synaptic network capacitors sharing a first output terminal. The neural network device further includes a second plurality of synaptic network capacitors, the second plurality of synaptic network capacitors sharing a second output terminal. The neural network device further includes a metal shield disposed between the first output terminal and the second output terminal.

[0005] Further exemplary embodiments are provided in the form of a method for manufacturing a neural network device having a capacitor-based synapse network with metal-shielded outputs, and an artificial intelligence system with a neural network device having a capacitor-based synapse network with metal-shielded outputs, respectively.

[0006] These and other features and advantages of the embodiments described herein will become more apparent from the accompanying drawings and the following detailed description. [Brief description of the drawings]

[0007] [Figure 1] 1 illustrates a block diagram of a neural network computing environment in which one or more exemplary embodiments may be implemented. [Diagram 2] 1 illustrates a circuit diagram of a neural network device in which one or more exemplary embodiments may be implemented. [Diagram 3] Figure 1 shows a schematic diagram of a single-output capacitor-based structure used to implement a positive synapse network. [Figure 4]Figure 1 shows a schematic diagram of a single-output capacitor-based structure used to implement a negative synapse network. [Diagram 5] Shows a schematic diagram of the coupling capacitance problem in multiple-output capacitor-based structures used to implement synaptic networks. [Figure 6] 1 illustrates an isometric view of a multiple-output capacitor-based structure with metal shielding between the outputs and used to implement a synaptic network in accordance with an illustrative embodiment. [Figure 7] 1 shows a circuit diagram of a multiple-output capacitor-based structure having metal shielding between the outputs and used to implement a synaptic network in accordance with an illustrative embodiment. [Figure 8A] 1 illustrates a flow diagram of a method for fabricating a multiple-output capacitor-based structure having metal shielding between the outputs and used to implement a synaptic network according to an illustrative embodiment. [Figure 8B] 1 illustrates another flow diagram of a method for fabricating a multiple-output capacitor-based structure having metal shielding between the outputs and used to implement a synaptic network in accordance with an illustrative embodiment. [Figure 8C] FIG. 1 illustrates a block diagram of an artificial intelligence system having one or more neural network devices with a capacitor-based synaptic network with metal-shielded outputs, according to an exemplary embodiment. [Figure 9] 1 illustrates a diagram of an exemplary processor system, according to an exemplary embodiment. [Figure 10] 1 illustrates a diagram of a cloud computing environment in accordance with an illustrative embodiment. [Figure 11] 1 is an illustration of an abstraction model layers diagram in accordance with an illustrative embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] As previously discussed in the background section, the basic computing hardware used to implement a DNN (CNN or any ANN) can include, but is not limited to, a CPU, a GPU, an ASIC, etc. For example, resistive random access memory (ReRAM) or phase change memory (PCM) devices (called cross-point structures) have been used to perform the computations associated with DNNs, where resistance / conductance is used to represent synapses. ReRAM is a type of non-volatile RAM that uses the change in electrical resistance across a dielectric solid material called a memristor to store data. PCM is a type of non-volatile RAM that uses the electrical resistance contrast between a highly conductive crystalline phase and a less conductive amorphous phase of a phase change material to store data.

[0009] In addition to the above resistor-based approach to implementing synapses in DNNs, it is understood that capacitors can be used to represent synapses. Capacitor-based synaptic networks provide similar neuronal connectivity functions as resistor-based synaptic networks, but do not consume static power. However, one drawback of neural networks with capacitor-based synapses is that output nodes may interact with each other through unwanted coupling capacitances.

[0010] Before further describing the drawbacks associated with existing capacitor-based synaptic networks and how exemplary embodiments overcome these and other drawbacks, an example of an artificial intelligence system having a set of neural network devices in which exemplary embodiments can be implemented will be described.

[0011] 1 illustrates a neural network environment 100 that includes a neural network device 102 in which one or more exemplary embodiments may be implemented. As shown, the neural network device 102 includes a neural network 104 that receives one or more input signals and generates one or more output signals.

[0012] By way of example only, in an image or object recognition application, the input signal(s) may include an image, and the neural network device implements a CNN that generates one or more image classifications, etc., as output signal(s). A CNN uses convolutional layers of neurons connected via synapses, and features are extracted from the image and processed through the network. The final layer of the CNN provides a calculated classification that is associated with the input image, resulting in a neural network trained with weights and feature detectors. The trained neural network is then used for real-time image recognition based on a target image.

[0013] Thus, in FIG. 1, the neural network device 102 is configured to train a neural network 104 and then use the trained neural network 104 for image or object recognition. As just a simple example, the CNN can be trained using images of automobiles, and then the trained CNN can be applied to the images to determine whether any subsequent images contain automobiles. Image recognition using a neural network device such as that shown in FIG. 1 can be used in a variety of applications, including, but not limited to, engineering, security, and medicine, to name a few. Multiple neural network devices 102 can be used together to form an artificial intelligence system. Furthermore, in some embodiments, a single neural network device 102 can include multiple neural networks 104. Furthermore, in some embodiments with multiple neural network devices 102, one or more neural network devices 102 can have a single neural network 104, while one or more other neural network devices 102 can have multiple neural networks 104.

[0014] 2 illustrates a circuit diagram of a neural network device 200 in which one or more exemplary embodiments may be implemented. It should be appreciated that the neural network device 200 is an exemplary implementation of the neural network device 102 having the neural network 104 of FIG. 1. It should be appreciated that portions of the neural network device 102 and the neural network 104 that are relevant to the detailed description of the exemplary embodiments are illustrated in FIG. 2. Thus, the neural network device and the neural network may have one or more other components and elements not explicitly illustrated in FIG. 2.

[0015] As shown, the neural network device 200 includes a plurality of word lines 210 (WL1, WL2, WL3, WL4, ..., WLN) and a plurality of bit lines 220 (BL1, BL2, BL3, ..., BLP). The plurality of word lines 210 and the plurality of bit lines 220 are not directly connected, but have synaptic elements connected between them at their respective cross points (i.e., the word lines and bit lines are adjacent to each other but are not physically connected). The synaptic elements are represented in FIG. 2 as synaptic elements 231, 232, 234, ..., 23Q. Each bit line 220 further includes an integrator 240 and a threshold detector 242 connected as shown. The plurality of synaptic elements 231, 232, 234, ..., 23Q, the integrator 240, and the threshold detector 242 collectively comprise a neural network portion 230 (e.g., a portion of the neural network 104 of the neural network device 102). Each of the neural network portions 230 is configured to change its capacitance in response to one or more input signals. Furthermore, each individual synaptic element 231, 232, 234, ..., 23Q is addressable via its corresponding word line, while the plurality of synaptic devices forming each neural network portion 230 is addressable via its corresponding bit line. In an exemplary embodiment, the neural network portion 230 is implemented using semiconductor fabrication techniques to create one or more semiconductor devices. Although memory device type terminology such as "word lines" and "bit lines" are illustratively used herein, these control signal lines are more commonly used to access individual synaptic elements, respectively, and are not necessarily to be considered word lines and bit lines in all neuromorphic embodiments.

[0016] 3 illustrates a circuit diagram of a single-output capacitor-based structure 300 that may be used to implement a positive synapse network. More specifically, the single-output capacitor-based structure 300 is an example of multiple synaptic elements 231, 232, 233, 234, ..., 23Q in the neural network portion 230 of FIG. 2. As illustrated, the single-output capacitor-based structure 300 includes multiple capacitors C1, C2, C3, ..., C4, C5, C6, ..., C7, ..., C8, ..., C9, ..., C10, ..., C11, ..., C12, ..., C13, ..., C14, ..., C15, ..., C16, ..., C17, ..., C18, ..., C19, ..., C20, ..., C21, ..., C22, ..., C23, ..., C24, ..., C25, ..., C26, ..., C27, ..., C28, ..., C39, ..., C31, ..., C32, ..., C33, ..., C34, ..., C35, ..., C36, ..., C37, ..., C38, ..., C39 ... n , each of which is a capacitor C1, C2, C3, ..., C n Input voltage sources V1, V2, V3, …, V n , V1, V2, V3, ..., V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, ..., V14, V15, ..., V16, ... n corresponds to the word (access) lines WL1, WL2, WL3, ..., WLN in FIG. 2, and the output V O Note that each of the capacitors C1, C2, C3, ..., C n The capacitance of each input voltage V1, V2, V3, …, V n It should be appreciated that for simplicity, the integrator 240 and the threshold detector 242 are not shown in FIG. 3. However, the integrator 240 is configured to be adjustable to one of a number of levels based on each of the capacitors C1, C2, C3, ..., C n It should be appreciated that the integrated circuit 240 receives signals indicative of the capacitance level of the total capacitance C and generates an integrated signal therefrom. The integrated signal is then compared to a given threshold in the threshold detector 242. More specifically, the total capacitance C tot is determined by the following formula:

number

number

[0017] It is clear that V0 is a linear combination of all the input voltages. i The synaptic value for C i / C tot V0 is compared to a given threshold and a decision is generated by the neural network portion 230 based on the result of the comparison.

[0018] 4 illustrates a circuit diagram of a single-output capacitor-based structure 400 that may be used to implement a negative synapse network. More specifically, the single-output capacitor-based structure 400 is another example of the multiple synaptic elements 231, 232, 233, 234, ..., 23Q in the neural network portion 230 of FIG. 2. As illustrated, the single-output capacitor-based structure 400 includes multiple capacitors C 11 , C 12 , C 21 , C 22 , … , C n1 , C n2 each of the capacitors having a respective C 11 , C 12 , C 21 , C 22 , … , C n1 , C n2 Input voltage sources V1, -V1, V2, -V2, …, V n , -V n and a second terminal coupled to a single common output V0. 11 , C 12 , C 21 , C 22 , … , C n1 , C n2 The capacitance of each input voltage V1, -V1, V2, -V2, …, V n , -V n It should be appreciated that for ease of illustration, the integrator 240 and the threshold detector 242 are not shown in FIG. 4. However, the integrator 240 is configured to be adjustable to one of a number of levels based on each capacitor C 11 , C 12, C 21 , C 22 , … , C n1 , C n2 It should be appreciated that the integrated circuit 240 receives signals indicative of the capacitance level of the capacitance sensor 10 and generates an integrated signal therefrom. The integrated signal is compared to a given threshold in the threshold detector 242. More specifically, similar to equations (1) and (2) above, it is defined as follows:

number

number

[0019] C i1 <C i2 If so, the synapse is considered negative. Again, V0 is compared to a given threshold and a decision is generated by the neural network portion 230 based on the result of the comparison.

[0020] FIG. 5 shows a circuit diagram of the coupling capacitance problem in a multiple-output capacitor-based structure 500 used to implement synaptic networks. As shown, the multiple-output capacitor-based structure 500 includes a first plurality of capacitors C 11 , C 21 , C 31 , … , C n1 and a second plurality of capacitors C 12 , C 22 , C 32 , … , C n2 The first plurality of capacitors C 11 , C 21 , C 31 , … , C n1 Each capacitor in n and a single common output V ol and a second terminal coupled to the second plurality of capacitors C 12 , C 22 , C 32, … , C n2 Each capacitor is connected to the input voltage sources V1, V2, V3, ..., V n and a single common output V o2 5 and a second terminal coupled to the output V. Each of the two sets of capacitors in FIG. 5 is the same as the capacitors shown in FIG. 3, but each set can be configured alternately in the same manner as the capacitors shown in FIG. 4. The important point is that due to parasitic capacitive coupling effects caused by electric fields, one signal in close proximity to another signal will cause interference in the form of noise to the other signal. Thus, as shown in FIG. 5, the output V 01 is the output V 02 The parasitic capacitive coupling effect between the two outputs can interfere with the coupling capacitance C x It is expressed as: C x Due to the existence of V 01 and V 02 The output V 01 and V 02 This unwanted coupling capacitance between poses a problem for neural networks in that it can cause errors in the integration (integrator 240) and threshold detection (threshold detector 242) stages and therefore can lead to incorrect decisions in the overall artificial intelligence algorithm.

[0021] The illustrative embodiments overcome the above and other drawbacks associated with capacitor-based synapse networks by providing a structure having metal shielding between outputs.

[0022] FIG. 6 illustrates an isometric view of a multiple-output capacitor-based structure 600 having metal shielding between outputs and used to implement a synapse network, according to an exemplary embodiment. More specifically, as illustrated, the multiple-output capacitor-based structure 600 includes three sets of capacitors 602-1, 602-2, and 602-3, where each set itself includes three capacitors, each capacitor shown as 610. Each capacitor 610 (represented by the capacitor in the upper right corner of the figure for simplicity) includes a first terminal 612 and a second terminal 614, with a dielectric material 616 disposed between the two terminals 612 and 614. The first terminal 612 of each capacitor 610 is operably coupled to an input voltage of V1, V2, or V3, respectively. The second terminal 614 of each capacitor 610 is coupled to an output voltage, in this case V1, V2, or V3. o3 (i.e., as shown, the capacitors in the same plurality of capacitors are operatively coupled to the same output V o1 , V o2 Or V o3 operably coupled to the dielectric material 616. The dielectric material 616 is a high-κ material, such as, but not limited to, hafnium dioxide (HfO2), zirconium dioxide, and the like, as well as combinations thereof.

[0023] Additionally, each of the plurality of capacitors 602 has a metal shield 620 associated therewith. In an exemplary embodiment, the metal shield 620 is constructed of a material such as, but not limited to, titanium nitride (TiN), tungsten (W), copper (Cu), and the like, as well as combinations thereof. In an exemplary embodiment, the size of the metal shield 620 may range from a few nanometers to hundreds of nanometers, depending on the dimensions of the capacitor. As shown, the metal shield 620 is disposed between each of the plurality of capacitors 602 shown. The metal shield 620 thus disposed prevents interference from adjacent outputs for a given output, e.g., V o1 and V o2 are capacitively isolated from each other, and at the same time, V o2 and V o3are capacitively decoupled from each other. In the exemplary embodiment shown in FIG. 6, the metal shield 620 is grounded. However, the metal shield 620 may be connected to ground, as will be further explained below in the context of FIG. tot Add.

[0024] 7 shows a circuit diagram of a multiple-output capacitor-based structure 700 used to implement a synapse network with a metal shield between the outputs, according to an exemplary embodiment. The multiple-output capacitor-based structure 700 is similar to the multiple-output capacitor-based structure 500 of FIG. 5, but with a metal shield 620 disposed between the multiple capacitors 702-1 and 702-2, as shown in FIG. 6, such that the output V o1 is a separate shielding capacity C x1 At the same time, the output Vo2 has a separate shielding capacitance C x2 It is understood that it is envisaged that the

[0025] Thus, as an example for the plurality of capacitors 702-1, C tot is defined as follows:

number

number

[0026] C for the plurality of capacitors 702-2 tot and V o2 vary in the same way as shown in equations (5) and (6), respectively, while C x1 Instead of C x2 With the addition of.

[0027] 8 illustrates a flow diagram of a method 800 for fabricating a multiple-output capacitor-based structure having metal shielding between the outputs and used to implement a synaptic network, according to an exemplary embodiment. It should be appreciated that method 800 may be performed as part of a semiconductor fabrication process for fabricating neural network devices, such as 102 in FIG. 1, for example. However, in alternative embodiments, method 800 may be performed by other fabrication techniques configured to perform the steps of the method.

[0028] Step 802 forms at least two sets of a plurality of capacitors, where the same set of a plurality of capacitors has separate inputs but shares a common output (see, for example, FIG. 6 or FIG. 7). Semiconductor fabrication of the at least two sets of a plurality of capacitors can be done in a variety of ways. By way of example only, the capacitor fabrication techniques described in U.S. Patent No. 10,505,108, issued December 10, 2019, entitled "Memcapacitors, Neuro Devices, and Neural Network Devices," can be adapted to fabricate the at least two sets of a plurality of capacitors in step 802.

[0029] Step 804 forms a metal shield between each pair of outputs in at least two sets of a plurality of capacitors as described herein.

[0030] In at least one semiconductor fabrication-based embodiment, in conjunction with the multiple-output capacitor-based structure 600 (of FIG. 6), FIG. 8B illustrates a method 810 implemented for forming a metal shield between the outputs of each pair of the multiple capacitors 602.

[0031] First, in step 811, the output terminal metal line (V o1 , V o2 Or V o3) is formed. Next, in step 812, a high-κ dielectric material 616 is formed and patterned. In step 813, a first interlayer dielectric (ILD) layer is formed and a chemical mechanical planarization (CMP) operation is applied. Next, in step 814, trenches are formed in the first ILD layer and metal is deposited to form shielding metal lines. In step 815, a second ILD layer is formed and CMP is applied. In step 816, a via structure is etched down to the high-κ dielectric material 616 and then the via structure is metallized. In step 817, the input metal lines (V1, V2 or V3) of the capacitor are formed. It should be appreciated that the fabrication process in FIG. 8B is merely an example and alternative embodiments contemplate additional or alternative fabrication steps and techniques, with different sequences of steps, to form a multiple output capacitor-based structure with metal shielding between the outputs.

[0032] 8C illustrates a block diagram of an artificial intelligence system 820 having one or more neural network devices with a capacitor-based synaptic network with metal-shielded outputs, according to one exemplary embodiment. In one or more exemplary embodiments, the capacitor-based synaptic network with metal-shielded outputs can be fabricated according to method 800 in FIG. 8A or method 810 in FIG. 8B, or both.

[0033] As shown, the artificial intelligence system 820 includes one or more neural network devices 822 having capacitor-based synaptic networks with metal-shielded outputs 824. In one exemplary embodiment, the artificial intelligence system 820's one or more neural network devices 822 having capacitor-based synaptic networks with metal-shielded outputs 824 are implemented by one or more application-specific integrated circuits (ASICs). An ASIC is a customized integrated circuit (IC) chip or device that includes logic (e.g., circuits, processors, memory, etc.) programmed with executable program code (e.g., instruction code, computer program code, etc.) or configured for another specific application. In this exemplary case, the specific application is the implementation and execution of an artificial intelligence system (e.g., machine learning algorithms), and more specifically, the implementation of a synaptic network used as part of a neural network. An ASIC is also referred to as a system-on-chip (SoC).

[0034] Furthermore, it should be appreciated that the artificial intelligence system 820 and its elements may be implemented in alternative circuit / processor-based technologies, such as technologies including one or more multi-core central processing units (CPUs), one or more graphics processing units (GPUs), and one or more field programmable gate arrays (FPGAs).

[0035] The techniques illustrated in Figures 1-8C may further include providing a system including separate software modules as described herein, each of the separate software modules embodied on a tangible computer-readable recordable storage medium. All of the modules (or any subset thereof) may reside on the same medium, or each may reside, for example, on different media. The modules may include any or all of the components shown in the figures or described herein, or both. In one embodiment of the invention, the modules may be executed, for example, on a hardware processor. And, the method steps may be performed using the separate software modules of the system as described above executing on the hardware processor. Additionally, the computer program product may include a tangible computer-readable recordable storage medium having code adapted to be executed to perform at least one method step as described herein, including providing a system having separate software modules.

[0036] 1-8C may be implemented via a computer program product that may include computer usable program code stored on a computer readable storage medium of a data processing system, the computer usable program code being downloaded over a network from a remote data processing system. Additionally, in one embodiment of the present invention, the computer program product may include computer usable program code stored on a computer readable storage medium of a server data processing system, the computer usable program code being downloaded over a network to the remote data processing system for use in the computer readable storage medium by the remote system.

[0037] An embodiment of the present invention or elements thereof may be implemented in the form of an apparatus including a memory and at least one processor coupled to the memory and configured to perform the exemplary method steps.

[0038] Further, embodiments of the present invention may employ software executing on a computer or workstation. With reference to FIG. 9, such an implementation could employ, for example, a processor 902, memory 904, and an input / output interface formed, for example, by a display 906 and a keyboard 908. The term "processor" as used herein is intended to include any processing device, such as, for example, a multi-core CPU, a GPU, one including an FPGA, or other forms of processing circuitry such as one or more ASICs, or combinations thereof. Furthermore, the term "processor" may refer to more than one individual processor. The term "memory" is intended to include memory associated with a processor (e.g., CPU, GPU, FPGA, ASIC, etc.), such as, for example, RAM (random access memory), ROM (read only memory), fixed memory devices (e.g., hard disks), removable memory devices (e.g., diskettes), flash memory, etc. Additionally, the term "input / output interface" as used herein is intended to include, for example, mechanisms for inputting data into a processing unit (e.g., a mouse) and mechanisms for providing results related to the processing unit (e.g., a printer). The processor 902, memory 904, and input / output interfaces such as a display 906 and keyboard 908 may be interconnected, for example, via a bus 910 as part of a data processing unit 912. Suitable interconnections, for example via the bus 910, may be provided to a network interface 914, such as a network card, which may be provided for interfacing with a computer network, and to a media interface 916, such as a diskette or CD-ROM drive, which may be provided for interfacing with media 918.

[0039] Thus, computer software including instructions or code for carrying out the methods of the embodiments of the present invention described herein can be stored in an associated memory device (e.g., ROM, fixed memory or removable memory) and, when ready for use, partially or fully loaded (e.g., into RAM) and executed by the CPU. Such software can include, but is not limited to, firmware, resident software, microcode, etc.

[0040] A data processing system suitable for storing and / or executing program code includes at least one processor 902 coupled directly or indirectly to memory elements 904 through a system bus 910. The memory elements can include local memory used during the actual execution of the program code, bulk storage, and cache memory that provides temporary storage of at least some of the program code to reduce the number of times the code needs to be retrieved from bulk storage during execution.

[0041] Input / output or I / O devices (including but not limited to keyboard 908, display 906, pointing device, etc.) can be coupled to the system either directly (e.g., via bus 910) or through intervening I / O controllers (omitted for clarity).

[0042] Network adapters, such as network interface 914, may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems and Ethernet cards are some types of network adapters currently available.

[0043] As used herein, including in the claims, a "server" includes a physical data processing system that executes a server program (e.g., system 912 shown in FIG. 9). It should be understood that such a physical server may or may not include a display and keyboard.

[0044] The present invention may be embodied as a system, method, or computer program product, or combination thereof, at any possible level of technical detail. The computer program product may include a computer readable storage medium or media having computer readable program instructions for causing a processor to perform aspects of the present invention.

[0045] A computer readable storage medium may be any tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disks (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves having instructions recorded thereon, and any suitable combination of the above. As used herein, a computer-readable storage medium is not to be construed as a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses through a fiber optic cable), or an electrical signal sent through a wire.

[0046] The computer readable program instructions described herein may be downloaded from a computer readable storage medium to each computing / processing device or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and transfers the computer readable program instructions for storage in a computer readable storage medium in the respective computing / processing device.

[0047] The computer readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk, C++, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on a remote computer or server. In the last scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions to individualize the electronic circuitry by utilizing state information of the computer readable program instructions to perform aspects of the invention.

[0048] Aspects of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0049] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, whereby the instructions executed by the processor of the computer or other programmable data processing apparatus create means for performing the functions / operations specified in one or more blocks of the flowcharts or block diagrams, or both. These computer program instructions, which may direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, may also be stored in a computer readable medium, whereby the instructions stored in the computer readable medium may include an article of manufacture including instructions implementing aspects of the functions / operations specified in one or more blocks of the flowcharts or block diagrams, or both.

[0050] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, such that the instructions executing on the computer or other programmable apparatus provide a process for performing the functions / operations specified in one or more blocks of the flowcharts or block diagrams or both.

[0051] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts may represent a module, segment, or portion of code, including one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions shown in the blocks may occur in a different order than that shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or these blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that executes the specified functions or operations, or executes a combination of dedicated hardware and computer instructions.

[0052] It should be noted that any of the method steps described herein may include the additional step of providing a system including separate software modules embodied on a computer readable storage medium, where the modules may include any or all of the components detailed herein. The method steps may then be performed using separate software modules or sub-modules or both of such a system executing on the hardware processor 902. Additionally, a computer program product may include a computer readable storage medium having code adapted to be executed to perform at least one method step described herein, including providing a system having separate software modules.

[0053] In any case, it will be understood that the components illustrated herein can be implemented in various forms of hardware, software, or combinations thereof, such as, for example, application specific integrated circuits (ASICs), functional circuits, appropriately programmed digital computers with associated memories, etc. Given the teachings of the invention provided herein, one of ordinary skill in the relevant art will be able to contemplate other implementations of the components of the invention.

[0054] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings described herein is not limited to a cloud computing environment. Rather, embodiments of the invention may be practiced in conjunction with any other type of computing environment now known or later developed.

[0055] Cloud computing is a model of service delivery for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal administrative effort or interaction with the service provider. The cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0056] Its features are as follows.

[0057] On-Demand Self-Service: Cloud consumers can automatically and unilaterally provision computing capacity, such as server time and network storage, as they need it, without the need for human interaction with the provider of the service.

[0058] Pervasive Network Access: Functionality is available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin- or thick-client platforms (e.g., cell phones, laptops, and PDAs).

[0059] Resource Pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically allocated and reallocated on demand. Consumers are location independent in that they generally have no control or knowledge of the exact location of the resources provided to them, although they may be able to specify a location at a higher level of abstraction (e.g., country, state, or data center).

[0060] Rapid Elasticity: Capabilities can be rapidly provisioned and rapidly scaled out, and rapidly released and rapidly scaled in, rapidly and elastically, sometimes automatically. To the consumer, the capabilities available for provisioning often appear unlimited, and can be purchased in any quantity at any time.

[0061] Metered Services: Cloud systems automatically control and optimize resource usage by using metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services being used.

[0062] The service model is as follows:

[0063] Software as a Service (SaaS): The functionality provided to the consumer is the use of the provider's applications running on a cloud infrastructure. These applications are accessible from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or individual application capabilities, with the expected exception of limited user-specific application configuration settings.

[0064] Platform as a Service (PaaS): The functionality offered to the consumer is the deployment onto a cloud infrastructure of applications the consumer creates or acquires, written using programming languages ​​and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does control the deployed applications and, in some cases, the configuration of the environment that hosts the applications.

[0065] Infrastructure as a Service (IaaS): The functionality provided to a consumer is to provision processing, storage, network, and other basic computing resources onto which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating systems, storage, deployed applications, and possibly limited control over the selection of network components (e.g., host firewalls).

[0066] The deployment model is as follows:

[0067] Private Cloud: Cloud infrastructure is operated exclusively for an organization. It can be managed by that organization or a third party and can exist on-premise or off-premise.

[0068] Community Cloud: Cloud infrastructure is shared by several organizations to support a specific community with common concerns (e.g., mission, security requirements, policies, and compliance considerations). It can be managed by those organizations or by a third party and can reside on-premise or off-premise.

[0069] Public Cloud: The cloud infrastructure is available to the general public or large industry groups and is owned by organizations that sell cloud services.

[0070] Hybrid Cloud: The cloud infrastructure is a blend of two or more clouds (private, community, or public) that remain unique entities but are tied together by standardized or proprietary technologies (e.g., cloud bursting for load balancing between clouds) that enable data and application portability.

[0071] Cloud computing environments are service-oriented and focus on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0072] 10, an exemplary cloud computing environment 1050 is shown. As shown, the cloud computing environment 1050 includes one or more cloud computing nodes 1010 with which a local computing device used by a cloud consumer, such as, for example, a personal digital assistant (PDA) or cellular phone 1054A, a desktop computer 1054B, a laptop computer 1054C, or an automobile computer system 1054N, or a combination thereof, can communicate. The nodes 1010 can communicate with each other. The nodes 1010 can be physically or virtually grouped in one or more networks, such as a private cloud, a community cloud, a public cloud, or a hybrid cloud, or a combination thereof, as described above (not shown). This enables the cloud computing environment 1050 to provide Infrastructure as a Service, Platform as a Service, or Software as a Service, or a combination thereof, without the cloud consumer having to maintain resources on a local computing device. It will be understood that the types of computing devices 1054A-N shown in FIG. 10 are intended to be merely exemplary, and that the computing node 10 and cloud computing environment 1050 are capable of communicating with any type of computerized device (e.g., using a web browser) via any type of network or network-addressable connection or both.

[0073] Referring now to Figure 11, a set of functional abstraction layers provided by cloud computing environment 1050 (Figure 10) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 11 are intended to be merely illustrative, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0074] Hardware and software layer 1160 includes hardware and software components. Example hardware components include mainframe 1161, RISC (Reduced Instruction Set Computer) architecture based servers 1162, servers 1163, blade servers 1164, storage devices 1165, and networks and networking components 1166. In some embodiments, software components include network application server software 1167 and database software 1168.

[0075] Virtualization layer 1170 provides an abstraction layer that may provide the following examples of virtual entities: virtual servers 1171, virtual storage 1172, virtual networks including virtual private networks 1173, virtual applications and operating systems 1174, and virtual clients 1175. In one example, management layer 1180 may provide the functionality described below: Resource provisioning 1181 provides dynamic procurement of computing and other resources utilized to perform tasks within the cloud computing environment. Metering and pricing 1182 provides cost tracking as resources are utilized within the cloud computing environment and billing or charging for the consumption of these resources.

[0076] In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User Portal 1183 provides access to the cloud computing environment for consumers and system administrators. Service Level Management 1184 provides allocation and management of cloud computing resources so that required service levels are met. Service Level Agreement (SLA) Planning and Fulfillment 1185 provides pre-allocation and procurement of cloud computing resources for forecasted future needs according to SLAs.

[0077] Workloads tier 1190 provides examples of functionality that can utilize a cloud computing environment. Examples of workloads and functionality that can be provided from this tier include mapping and navigation 1191, software development and lifecycle management 1192, virtual classroom instructional delivery 1193, data analytics processing 1194, transaction processing 1195, and artificial intelligence algorithm processing 1196, in accordance with one or more embodiments of the present invention.

[0078] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, it will be understood that the terms "comprise" and / or "comprising" as used herein specify the presence of stated features, integers, steps, operations, elements or components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups, or combinations thereof.

[0079] At least one embodiment of the present invention may provide beneficial effects such as, for example, a framework (e.g., a set of one or more framework configurations) that replaces complex manual (e.g., bespoke) development of model recovery logic. As illustratively described herein, the framework is instantiated, consisting of a set of fault detection components and associated model recovery pipelines. Once instantiated, the framework is plugged into a given lifecycle with logs as input, and sends new model artifacts for a new model version to the existing lifecycle pipeline. In one or more exemplary embodiments, the framework is a framework and platform for end-to-end development and lifecycle management of AI applications.

[0080] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but they are not intended to be exhaustive or to be limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification have been selected to best explain the principles, practicality, or technical improvements over the art found in the marketplace of the embodiments, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. a first plurality of synaptic network capacitors, the first plurality of synaptic network capacitors sharing a first output terminal; a second plurality of synaptic network capacitors, the second plurality of synaptic network capacitors sharing a second output terminal; a metal shield disposed between the first output terminal and the second output terminal; A neural network device comprising:

2. The neural network device of claim 1 , wherein the metal shield disposed between the first output terminal and the second output terminal is connected to a ground terminal.

3. 2. The neural network device of claim 1, wherein the metal shield is disposed between the first output terminal and the second output terminal such that the metal shield capacitively decouples the first output terminal from the second output terminal.

4. 2. The neural network device of claim 1, wherein each of the synaptic network capacitors in the first plurality of synaptic network capacitors has an input terminal that is independent from the input terminals of each of the other synaptic network capacitors of the first plurality of synaptic network capacitors.

5. 5. The neural network device of claim 4, wherein each of the synaptic network capacitors in the second plurality of synaptic network capacitors has an input terminal that is independent from the input terminals of each of the other synaptic network capacitors of the second plurality of synaptic network capacitors.

6. 6. The neural network device of claim 5, wherein the input terminal of each synaptic network capacitor is addressable via a given word line of the neural network device, and each of the first and second pluralities of synaptic network capacitors is further addressable via a given bit line of the neural network device.

7. The neural network device of claim 1 , wherein the neural network device is part of an artificial intelligence system.

8. forming a first plurality of synaptic network capacitors, the synaptic network capacitors sharing a first output terminal; forming a second plurality of synaptic network capacitors, the synaptic network capacitors sharing a second output terminal; forming a metallic shield between the first output terminal and the second output terminal; The method includes:

9. 9. The method of claim 8, further comprising connecting the metal shield formed between the first output terminal and the second output terminal to a ground terminal.

10. 9. The method of claim 8, wherein the metal shield formed between the first output terminal and the second output terminal capacitively decouples the first output terminal from the second output terminal.

11. 9. The method of claim 8, wherein each of the synaptic network capacitors in the first plurality of synaptic network capacitors comprises an input terminal that is independent from the input terminals of each of the other synaptic network capacitors of the first plurality of synaptic network capacitors.

12. 12. The method of claim 11, wherein each of the synaptic network capacitors in the second plurality of synaptic network capacitors comprises an input terminal that is independent from the input terminals of each of the other synaptic network capacitors of the second plurality of synaptic network capacitors.

13. 13. The method of claim 12, further comprising addressing the input terminal of each synaptic network capacitor via a given word line of a neural network device, and further addressing each of the first and second pluralities of synaptic network capacitors via a given bit line of the neural network device.

14. The method of claim 13 , wherein the neural network device is part of an artificial intelligence system.

15. at least one processing device including a neural network structure having a plurality of layers of neuron nodes operatively coupled by synaptic elements; The synapse element is composed of at least two sets of a plurality of synapse elements, The at least two sets of a plurality of synaptic elements include: a first plurality of synapse elements, the first plurality of synapse elements sharing a first output terminal; a second plurality of synapse elements, the second plurality of synapse elements sharing a second output terminal; a metal shield disposed between the first output terminal and the second output terminal; Equipped with Artificial intelligence system.

16. 16. The artificial intelligence system of claim 15, wherein the metal shield disposed between the first output terminal and the second output terminal is connected to a ground terminal.

17. 16. The artificial intelligence system of claim 15, wherein the metal shield is disposed between the first output terminal and the second output terminal so as to isolate the first output terminal from the second output terminal.

18. 16. The artificial intelligence system of claim 15, wherein each of the synapse elements in the first plurality of synapse elements has an input terminal that is independent of the input terminals of each of the other synapse elements of the first plurality of synapse elements.

19. 20. The artificial intelligence system of claim 18, wherein each of the synapse elements in the second plurality of synapse elements has an input terminal that is independent of the input terminals of each of the other synapse elements of the second plurality of synapse elements.

20. 20. The artificial intelligence system of claim 19, wherein the input terminal of each synapse element is addressable via a given word line of the at least one processing device, and each of the first and second pluralities of synapse elements is further addressable via a given bit line of the at least one processing device.

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