LIQUID EJECTION APPARATUS AND LIQUID EJECTION HEAD

Abstract

To provide a liquid discharge device capable of coping with a request from a user who gives priority to printing speed over image quality.SOLUTION: A liquid discharge device comprises: a first shift register consisting of a first region capable of holding data of a first data size, a second region capable of holding data of a second data size, and a third region capable of holding data of a third data size, which are continuous; a plurality of discharge parts capable of discharging droplets based on head control data; and first wiring for transmitting the head control data to the first shift register. The liquid discharge device can operate in a first printing mode of performing printing using a first gradation number and a second printing mode of performing printing using a second gradation number lower than the first gradation number based on the head control data. In the first printing mode, a data size of the head control data is the sum of the first data size, the second data size and the third data size, whereas in the second printing mode, a data size of the head control data is the sum of the first data size and the second data size.SELECTED DRAWING: Figure 16

Description

[Technical field]

[0001] The present invention relates to a liquid ejection device. [Background technology]

[0002] For printing with inkjet printers and the like, a so-called piezoelectric printing device is known in which a drive element including a piezoelectric element provided in a liquid ejection head is driven by a drive signal, and liquid such as ink filled in a cavity is ejected from a nozzle by driving the drive element, thereby forming characters or images on a medium.

[0003] There is known a printing device that controls a piezoelectric element by outputting information that defines the amount of liquid ejected from the liquid ejection head from a liquid ejection head control circuit that controls the driving of the liquid ejection head, thereby forming characters and images on a medium. For example, Patent Document 1 discloses a control circuit for an inkjet printer that can control the liquid ejection head based on print data SI and pattern data SP. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2010-155470 A Summary of the Invention [Problem to be solved by the invention]

[0005] The control circuit of the liquid ejection device described in Patent Document 1 prints ink ejected from the nozzles in four gradations: large dots, medium dots, small dots, and no ejection. Because so-called multi-gradation printing is performed, the characters and images printed on the medium are of high image quality. However, there is an issue that the high image quality results in long printing times, making it difficult to meet the needs of users who prioritize printing speed over image quality. [Means for solving the problem]

[0006] a first shift register including a first area capable of holding data of a first data size, a second area capable of holding data of a second data size, and a third area capable of holding data of a third data size, all of which are arranged in succession; a plurality of ejection units capable of ejecting droplets based on the head control data held in the first shift register; a first wiring for transmitting the head control data to the first shift register; a first print mode in which the droplets are ejected from the plurality of ejection sections based on the head control data to perform printing with a first number of gradations; a second print mode in which the droplets are ejected from the plurality of ejection sections based on the head control data, and printing is performed with a second number of gradations that is lower than the first number of gradations, In the first printing mode, a data size of the head control data is a sum of the first data size, the second data size, and the third data size, In the second printing mode, The data size of the head control data is the sum of the first data size and the second data size. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a liquid ejection device. [Diagram 2] FIG. 2 is a diagram illustrating a functional configuration of the liquid ejection device. [Diagram 3] FIG. 2 is a diagram for explaining a schematic configuration of a discharge unit. [Figure 4] FIG. 4 is a diagram showing a configuration of a drive signal selection circuit. [Diagram 5] FIG. 4 is a diagram showing an electrical configuration of a selection control circuit. [Figure 6] 3A to 3C are diagrams for explaining a latch signal, a change signal, a clock signal, a head control signal, and a drive signal. [Figure 7] 5 is a diagram showing an example of a data configuration of a head control signal. FIG. [Figure 8] FIG. 13 is a diagram showing the decoded contents of a decoder. [Figure 9] FIG. 4 is a diagram showing the configuration of a selection circuit corresponding to one of the ejection parts. [Figure 10] 13 is a diagram showing an example of a head control signal DI output by a control mechanism during an ejection control period. FIG. [Figure 11] 13 is a diagram showing the decoded contents in a decoder of the selection control circuit during the discharge control period. FIG. [Figure 12] 12 is a diagram for explaining the operation of a selection circuit when a selection signal S shown in FIG. 11 is supplied. FIG. [Figure 13] 5A to 5C are diagrams for explaining a latch signal, a change signal, a clock signal, a head control signal, and a drive signal in a binary mode. [Figure 14] 13 is a diagram showing an example of a head control signal DI output by a control mechanism during an ejection control period in a binary mode. FIG. [Figure 15] 13 is a diagram showing the decoded contents in a decoder of a selection control circuit during a discharge control period in a binary mode. FIG. [Figure 16] 16 is a diagram for explaining the operation of a selection circuit when a selection signal S shown in FIG. 15 is supplied. FIG. [Figure 17] FIG. 11 is a diagram showing a configuration of a drive signal selection circuit in a second embodiment. [Figure 18] FIG. 11 is a diagram showing the configuration of a selection circuit corresponding to one of the ejection parts in the second embodiment. [Figure 19] 13A to 13C are diagrams for explaining a latch signal, a change signal, a clock signal, a head control signal, and a drive signal in a multi-tone mode in the second embodiment. [Figure 20] 13 is a diagram showing an example of a head control signal DI output by a control mechanism during an ejection control period in a multi-tone mode in the second embodiment. FIG. [Figure 21] FIG. 13 is a diagram showing the decoded contents in a decoder included in a selection control circuit during an ejection control period in a multi-tone mode in the second embodiment. [Figure 22]FIG. 13 is a diagram showing the decoded contents in a decoder included in a selection control circuit during an ejection control period in a multi-tone mode in the second embodiment. [Diagram 23] 23 is a diagram for explaining the operation of the selection circuit when selection signals Sa and Sb shown in FIGS. 21 and 22 are supplied. FIG. [Figure 24] 13A to 13C are diagrams for explaining a latch signal, a change signal, a clock signal, a head control signal, and a drive signal in the binary mode of the second embodiment. [Diagram 25] 13 is a diagram showing an example of a head control signal DI output by a control mechanism during an ejection control period in a binary mode in the second embodiment. FIG. [Figure 26] FIG. 13 is a diagram showing the decoded contents in a decoder of a selection control circuit during a discharge control period in a binary mode in the second embodiment. [Figure 27] FIG. 13 is a diagram showing the decoded contents in a decoder of a selection control circuit during a discharge control period in a binary mode in the second embodiment. [Figure 28] 28 is a diagram for explaining the operation of the selection circuit when selection signals Sa and Sb shown in FIGS. 26 and 27 are supplied. FIG. [Figure 29] FIG. 13 is a diagram showing an electrical configuration of a selection control circuit in a third embodiment. [Diagram 30] FIG. 13 is a diagram showing an example of a data configuration of a head control signal in the third embodiment. [Diagram 31] FIG. 13 is a diagram showing the decoded contents of a decoder in the third embodiment. [Diagram 32] 13A to 13C are diagrams for explaining a latch signal, a change signal, a clock signal, a head control signal, and a drive signal in a multi-tone mode in the third embodiment. [Diagram 33] 13A and 13B are diagrams showing an example of head control signals DIa and DIb output by a control mechanism during an ejection control period in a multi-tone mode in a third embodiment. [Diagram 34] FIG. 13 is a diagram showing the decoded contents in a decoder of the selection control circuit 210 during a discharge control period in a multi-tone mode in the third embodiment. [Diagram 35] 35 is a diagram for explaining the operation of the selection circuit when the selection signal S shown in FIG. 34 is supplied. FIG. [Diagram 36] 13A to 13C are diagrams for explaining a latch signal, a change signal, a clock signal, a head control signal, and a drive signal in the binary mode of the third embodiment. [Figure 37] 13A to 13C are diagrams showing an example of head control signals DIa, DIb output by a control mechanism during an ejection control period in a binary mode according to a third embodiment. [Figure 38] FIG. 13 is a diagram showing the decoded contents in a decoder of the selection control circuit 210 during a discharge control period in the binary mode in the third embodiment. [Figure 39] 39 is a diagram for explaining the operation of the selection circuit when the selection signal S shown in FIG. 38 is supplied. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings are used for the convenience of explanation. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. Overview of the liquid ejection device FIG. 1 is a diagram showing a schematic configuration of a liquid ejection device 1. The liquid ejection device 1 in this embodiment is an inkjet printer of a serial printing type in which a carriage 20 mounted with a liquid ejection head 21 that ejects ink as an example of liquid moves back and forth to eject ink onto a medium P being transported, thereby forming an image on the medium P. In the following description, the direction in which the carriage 20 moves is the X direction, the direction in which the medium P is transported is the Y direction, and the direction in which the ink is ejected is the Z direction. Note that the X direction, the Y direction, and the Z direction are described as directions perpendicular to each other, but the various components constituting the liquid ejection device 1 are not limited to being arranged perpendicular to each other. In addition, any printing target such as printing paper, a resin film, or a fabric can be used as the medium P. Note that the liquid ejection device 1 may be an inkjet printer of a so-called line printing type in which the liquid ejection heads 21 are arranged in a row so as to form a nozzle row greater than the width of the medium, and a desired image is formed on the medium by ejecting ink from the liquid ejection heads 21 onto the medium being transported.

[0010] As shown in FIG. 1, the liquid ejection device 1 includes an ink container 2, a control mechanism 10, a carriage 20, a moving mechanism 30, and a transport mechanism 40.

[0011] The ink container 2 stores multiple types of ink to be ejected onto the medium P. Colors of ink stored in the ink container 2 include black, cyan, magenta, yellow, red, gray, etc. As the ink container 2 in which such ink is stored, an ink cartridge, a bag-shaped ink pack formed of a flexible film, an ink tank that can be refilled with ink, etc. can be used.

[0012] The control mechanism 10 includes a processing circuit such as a CPU (Central Processing Unit) or an FPGA (Field Programmable Gate Array) and a storage circuit such as a semiconductor memory, and controls each element of the liquid ejection device 1 including the liquid ejection head 21.

[0013] A liquid ejection head 21 is mounted on the carriage 20. The carriage 20 is fixed to an endless belt 32 included in a moving mechanism 30. The ink container 2 may be mounted on the carriage 20.

[0014] A control signal Ctrl-H for controlling the liquid ejection head 21, which is output by the control mechanism 10, and one or more drive signals COM for driving the liquid ejection head 21 are input to the liquid ejection head 21. The liquid ejection head 21 ejects ink supplied from the ink container 2, based on the input control signal Ctrl-H and drive signal COM.

[0015] The movement mechanism 30 includes a carriage motor 31 and an endless belt 32. The carriage motor 31 operates based on a control signal Ctrl-C input from the control mechanism 10. The endless belt 32 rotates in accordance with the operation of the carriage motor 31. As a result, the carriage 20 fixed to the endless belt 32 reciprocates in the X direction.

[0016] The transport mechanism 40 includes a transport motor 41 and a transport roller 42. The transport motor 41 operates based on a control signal Ctrl-T input from the control mechanism 10. The transport roller 42 rotates in accordance with the operation of the transport motor 41. The medium P is transported in the Y direction in accordance with the rotation of the transport roller 42.

[0017] As described above, the liquid ejection device 1 ejects ink along the Z direction from the liquid ejection head 21 mounted on the carriage 20 in conjunction with the transport of the medium P by the transport mechanism 40 and the reciprocating movement of the carriage 20 by the moving mechanism 30, causing the ink to land at any position on the surface of the medium P, thereby forming a desired image on the medium P.

[0018] 2. Functional configuration of the liquid ejection device Next, a description will be given of the functional configuration of the liquid ejection device 1. Fig. 2 is a diagram showing the functional configuration of the liquid ejection device 1. As shown in Fig. 2, the liquid ejection device 1 includes a control mechanism 10, a liquid ejection head 21, a carriage motor 31, a transport motor 41, and a linear encoder 90.

[0019] The control mechanism 10 includes a drive circuit 50 and a control circuit 100. The control circuit 100 includes a processor such as a microcontroller, for example. The control circuit 100 generates various data for controlling the liquid ejection device 1 and signals based on the data based on various signals such as image data input from a host computer or the like connected to an external device so as to be able to communicate with the outside, and outputs the generated data to a corresponding component.

[0020] A specific example of the operation of the control circuit 100 will be described. The control circuit 100 grasps the scanning position of the liquid ejection head 21 mounted on the carriage 20 based on a detection signal input from the linear encoder 90. Then, the control circuit 100 generates and outputs various signals according to the scanning position of the liquid ejection head 21. In detail, the control circuit 100 generates a control signal Ctrl-C for controlling the reciprocating movement of the liquid ejection head 21 and outputs it to the carriage motor 31. The control circuit 100 also generates a control signal Ctrl-T for controlling the transportation of the medium P and outputs it to the transport motor 41. Note that the control signal Ctrl-C may be converted via a driver circuit (not shown) and then input to the carriage motor 31, and similarly, the control signal Ctrl-T may be converted via a driver circuit (not shown) and then input to the transport motor 41.

[0021] The control circuit 100 also controls the liquid ejection head 21 based on various signals such as image data input from a host computer and the scanning position of the liquid ejection head 21. As the control signal Ctrl-H, a head control signal DI, a change signal CH, a latch signal LAT, and a clock signal SCK are generated and output to the liquid ejection head 21 .

[0022] In addition, the control circuit 100 outputs a basic drive signal d, which is a digital signal, to the drive circuit 50.

[0023] The drive circuit 50 includes a drive signal output circuit 51 and a reference voltage signal output circuit 52. The basic drive signal d is input to the drive signal output circuit 51. The drive signal output circuit 51 converts each of the basic drive signals d into digital / analog signals, and then generates and outputs the drive signal COM as a drive signal by amplifying the converted analog signal by class D. That is, the basic drive signal d is a digital signal that defines the waveform of the drive signal COM. The drive signal output circuit 51 then generates and outputs the drive signal COM by amplifying the waveform defined by the basic drive signal d by class D. That is, the drive signal output circuit 51 includes a class D amplifier circuit. Note that the basic drive signal d may be any signal that can define the waveform of the drive signal COM, and may be, for example, an analog signal. In addition, the drive signal output circuit 51 may be configured to include, for example, a class A amplifier circuit, a class B amplifier circuit, or a class AB amplifier circuit, as long as it can amplify the waveform defined by the basic drive signal d.

[0024] The reference voltage signal output circuit 52 outputs a reference voltage signal VBS indicating a reference potential of the drive signal COM. The reference voltage signal VBS may be, for example, a signal having a ground potential with a voltage value of 0 V, or may be a DC voltage signal having a voltage value of 5.5 V, 6 V, or the like.

[0025] The drive signal COM and the reference voltage signal VBS output by the drive circuit 50 are output to the liquid ejection head 21.

[0026] The liquid ejection head 21 includes a drive signal selection circuit 200, a memory circuit 250, and ejection units 600[1] to 600[n]. For example, n is a value such as 400, 800, or 1600. Note that the ejection units 600[1] to 600[n] all have the same configuration, and may be simply referred to as the ejection unit 600 when there is no need to distinguish between them.

[0027] The drive signal selection circuit 200 is configured as, for example, an integrated circuit device. A clock signal SCK, a latch signal LAT, a change signal CH, a head control signal DI, and a drive signal COM are input to each of the drive signal selection circuits 200. The drive signal selection circuit 200 generates VOUT[1] to VOUT[n] by selecting or not selecting the drive signal COM based on the clock signal SCK, the latch signal LAT, the change signal CH, and the input head control signal DI, and outputs them to the corresponding ejection units 600[1] to 600[n]. When there is no need to distinguish between VOUT[1] to VOUT[n], they may be simply referred to as VOUT.

[0028] The ejection section 600 has a piezoelectric element 60 to which VOUT is supplied. Fig. 3 is a diagram for explaining a schematic configuration of the ejection section 600. As shown in Fig. 3, the ejection section 600 includes a piezoelectric element 60, a vibration plate 621, a cavity 631, and a nozzle 651. The cavity 631 is filled with ink supplied from a reservoir 641. In addition, ink is introduced into the reservoir 641 from the ink container 2 via a supply port 661.

[0029] The vibration plate 621 is displaced by being driven by a piezoelectric element 60 provided on the upper surface in FIG. 3. The internal volume of the cavity 631 filled with ink expands and contracts in accordance with the displacement of the vibration plate 621. In other words, the vibration plate 621 functions as a diaphragm that changes the internal volume of the cavity 631. The nozzle 651 is an opening provided in the nozzle plate 632, and communicates with the cavity 631. The internal volume of the cavity 631 expands and contracts in accordance with the displacement of the vibration plate 621. As the internal volume changes, an amount of ink corresponding to the change in the internal volume is introduced into the cavity 631 and ejected from the nozzle 651 .

[0030] The piezoelectric element 60 has a structure in which a piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. When VOUT is supplied to the electrode 611 of the piezoelectric element 60 and a reference voltage signal VBS is supplied to the electrode 612, the central portions of the electrodes 611 and 612 of the piezoelectric body 601 are displaced in the vertical direction together with the diaphragm 621 in accordance with the potential difference between the voltages supplied by the electrodes 611 and 612. That is, when VOUT based on the drive signal COM is supplied, the piezoelectric element 60 is driven.

[0031] In the ejection section 600 configured as above, when the piezoelectric element 60 bends upward, the vibration plate 621 is displaced upward, and the internal volume of the cavity 631 is expanded. As a result, the ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 bends downward, the vibration plate 621 is displaced downward, and the internal volume of the cavity 631 is reduced. Then, an amount of ink according to the degree of reduction in the internal volume of the cavity 631 is ejected from the nozzle 651 communicating with the cavity 631. Note that the structure of the piezoelectric element 60 is not limited to that shown in FIG. 3, and any structure may be used as long as ink can be ejected from the nozzle 651 in response to the driving of the piezoelectric element 60.

[0032] As described above, the liquid ejection device 1 in this embodiment includes a liquid ejection head 21 having a piezoelectric element 60 that ejects ink from a nozzle 651 by being driven by VOUT generated based on a drive signal COM, a drive signal selection circuit 200 that switches whether or not the drive signal COM is supplied to the piezoelectric element 60, and a control mechanism 10 having a drive signal output circuit 51 that outputs the drive signal COM, and a control circuit 100 that outputs a clock signal SCK, a latch signal LAT, a change signal CH, and a head control signal DI to control the drive signal selection circuit 200. The liquid ejection head 21 is controlled by the control mechanism 10, whereby ink lands at a desired position on the medium P, thereby forming a desired image on the medium P.

[0033] Here, the piezoelectric element 60 is an example of a drive element, the drive signal selection circuit 200 is an example of a switching circuit, and the control mechanism 10 that controls the liquid ejection head 21 is an example of a liquid ejection head control circuit. Also, the control circuit 100 that outputs the clock signal SCK, the latch signal LAT, the change signal CH, and the head control signal DI that control the drive signal selection circuit 200 is an example of a switching control circuit. And the drive signal COM output by the drive signal output circuit 51 is an example of a drive signal in this embodiment. Note that, although this embodiment will be described with reference to a case where the liquid ejection device 1 includes one liquid ejection head 21, the liquid ejection device 1 may include a plurality of liquid ejection heads 21.

[0034] 3. Drive signal selection circuit configuration Next, we will explain the configuration of the drive signal selection circuit 200. Fig. 4 is a diagram showing the configuration of the drive signal selection circuit 200. As shown in Fig. 4, the drive signal selection circuit 200 has a selection control circuit 210 and selection circuits 230[1] to 230[n].

[0035] A clock signal SCK, a latch signal LAT, a change signal CH, and a head control signal DI are input to the selection control circuit 210. Then, based on the clock signal SCK, the latch signal LAT, the change signal CH, and the head control signal DI, the selection control circuit 210 outputs selection signals S[1] to S[n] for switching whether or not each of the selection circuits 230[1] to 230[n] described below outputs the drive signal COM as VOUT.

[0036] The selection circuits 230[1] to 230[n] correspond to the ejection units 600[1] to 600[n]. The selection circuits 230[1] to 230[n] switch whether or not to output the drive signals COM as VOUT[1] to VOUT[n] based on the selection signals S[1] to S[n] output by the selection control circuit 210.

[0037] Specifically, the selection circuit 230[1] receives the selection signal S[1] output by the selection control circuit 210 and the drive signal COM. The selection circuit 230[1] generates VOUT[1] by selecting or not selecting the drive signal COM based on the selection signal S[1], and outputs VOUT[1] to the discharge unit 600[1]. The selection circuit 230[n] receives the selection signal S[n] output by the selection control circuit 210 and the drive signal COM. The selection circuit 230[n] generates VOUT[n] by selecting or not selecting the drive signal COM based on the selection signal S[n], and outputs VOUT[n] to the discharge unit 600[n].

[0038] That is, the selection signal S[i] output by the selection control circuit 210 and the drive signal COM are input to the selection circuit 230[i] (i is any of 1 to n). The selection circuit 230[i] then generates VOUT[i] by selecting or not selecting the drive signal COM based on the selection signal S[i], and outputs it to the discharge section 600[i].

[0039] Next, a specific example of the configuration of the selection control circuit 210 will be described. Note that the selection control circuit 210 will be described assuming that it receives a clock signal SCK, a latch signal LAT, a change signal CH, and a head control signal DI, and outputs selection signals S[1] to S[n].

[0040] 5 is a diagram showing an electrical configuration of the selection control circuit 210. As shown in FIG. 5, the selection control circuit 210 has a control logic circuit 260 and n selection signal output units 270 provided corresponding to the n discharge units 600. That is, the selection control circuit 210 has n selection signal output units 270, the same number as the total number of discharge units 600 that output VOUT. The selection control circuit 210 generates selection signals S[1] to S[n] corresponding to each of the discharge units 600[1] to 600[n] based on the head control signal DI propagated in synchronization with the clock signal SCK at a timing defined by the input latch signal LAT and the change signal CH, and outputs the selection signals S[1] to S[n] to the corresponding selection circuits 230[1] to 230[n].

[0041] Here, in describing the electrical configuration of the selection control circuit 210, we will first describe the latch signal LAT, change signal CH, clock signal SCK, head control signal DI, and drive signal COM that are input to the selection control circuit 210. Fig. 6 is a diagram for explaining the latch signal LAT, change signal CH, clock signal SCK, head control signal DI, and drive signal COM.

[0042] The latch signal LAT is a pulse signal output by the control circuit 100 based on a signal indicating the scanning position of the carriage 20 carrying the liquid ejection head 21, output by the linear encoder 90. Between pulses of this latch signal LAT, the liquid ejection head 21 ejects droplets to form dots on the medium. That is, the liquid ejection head 21 ejects ink to form dots on the medium P. This allows the liquid ejection head 21 to eject a predetermined amount of ink at a desired position on the medium P along the main scanning direction, and therefore allows dots of a desired size to be formed at a desired position on the medium P. The period from the rising edge of this latch signal LAT to the rising edge of the next latch signal corresponds to a printing cycle, which corresponds to a dot formation cycle T for forming dots on the medium P. That is, the latch signal LAT is a signal indicating the scanning position of the liquid ejection head 21 relative to the medium P, and is also a signal that specifies the dot formation cycle T for forming dots on the medium P according to the scanning position of the liquid ejection head 21.

[0043] The change signal CH is a pulse signal that specifies the switching timing at which the drive signal selection circuit 200 switches whether or not to supply the drive signal COM as VOUT to the discharge unit 600. The control circuit 100 outputs a change signal CH so as to divide the dot formation period T into a plurality of periods. In this embodiment, the change signal CH is described as a pulse signal that is output three times in the dot formation period T. That is, in this embodiment, the change signal CH defines the dot formation period T into four periods: period T1, period T2, period T3, and period T4.

[0044] Then, the drive signal selection circuit 200 switches whether or not to supply the drive signal COM as VOUT to the discharge section 600 in period T1, and switches whether or not to supply the drive signal COM as VOUT to the discharge section 600 in period T2. Similarly, the drive signal selection circuit 200 switches whether or not to supply the drive signal COM as VOUT to the discharge section 600 in period T3, and switches whether or not to supply the drive signal COM as VOUT to the discharge section 600 in period T4. As a result, on the medium P, the ink discharged in period T1, the ink discharged in period T2, the ink discharged in period T3, and the ink discharged in period T4 are combined to form one dot in the dot formation cycle T.

[0045] As described above, the drive signal selection circuit 200 uses the change signal CH to define the dot formation cycle T as the period T1, period T2, period T3, and period T4, and switches whether or not to supply the drive signal COM as VOUT to the ejection section 600 during each of the periods T1, T2, T3, and T4. This enables the liquid ejection head 21 to form dots of various sizes on the medium P. This allows multi-tone dots to be formed on the medium P, and a high-definition image to be formed on the medium P. That is, the change signal CH defines the switching timing of the drive signal selection circuit 200. Such a printing method is sometimes called a multi-tone mode or multi-value control.

[0046] In this embodiment, the change signal CH is described as defining the dot formation period T as four periods T1, T2, T3, and T4, however, the defined number of dot formation periods T may be changed depending on the material of the medium being used, the physical properties of the ink, and even the requirements of the user.

[0047] For example, one change signal CH may be used to define the dot formation period T as two, or four change signals CH may be used to define the dot formation period T as five.

[0048] The head control signal DI is a signal synchronized with the clock signal SCK, and includes, in series, an ejection control signal SI that individually defines the amount of ink ejected onto the medium P by the nozzles 651 of each of the n ejection units 600, and a setting information signal SP for defining the relationship between the logical level of the selection signal S output during each of the periods T1, T2, T3, and T4 defined by the change signal CH and the ejection control signal SI. This head control signal DI is supplied to the selection control circuit 210 during the dot formation period T before the latch signal LAT rises in synchronization with the clock signal SCK, and is held in a register of the selection control circuit 210 in a state corresponding to the n ejection units 600. The head control signals DI held in the register are latched all at once at the rise of the latch signal LAT, thereby defining the logical level of the selection signal S during the dot formation period T defined to include the latch signal LAT.

[0049] The drive signal COM includes at least one drive waveform, which will be described here as a drive waveform. It includes a waveform in which a drive waveform dp1 arranged in a period T1 from when the latch signal LAT rises until the first change signal CH rises, a drive waveform dp2 arranged in a period T2 from when the first change signal CH rises until the second change signal CH rises, a drive waveform dp3 arranged in a period T3 from when the second change signal CH rises until the third change signal CH rises, and a drive waveform dp4 arranged in a period T4 from when the third change signal CH rises until the latch signal LAT rises. The drive waveforms dp1 to dp4 are an example of an ejection pulse.

[0050] The drive waveform dp3 is a waveform for ejecting a small amount of ink from the nozzle 651, and the drive waveform dp2 is a waveform for ejecting a medium amount of ink, which is more than a small amount, from the nozzle 651. The drive waveform dp1 is a waveform for ejecting a large amount of ink, which is more than a medium amount, from the nozzle 651. Moreover, dp4 is a waveform that does not eject ink from the nozzle 651, and is a waveform that slightly vibrates the ink near the opening of the nozzle 651 to prevent an increase in ink viscosity.

[0051] Here, as shown in FIG. 6, the voltage at the start timing and end timing of each of the drive waveforms dp1, dp2, dp3, and dp4 is the same as the voltage Vc. That is, each of the drive waveforms dp1, dp2, dp3, and dp4 starts and ends at the voltage Vc. In FIG. 6, the drive waveforms dp1, dp2, dp3, and dp4 are illustrated as different waveforms, but the same waveform may be included in multiple waveforms. That is, the waveform of the drive signal COM is not limited to the waveform shown in FIG. 6, and various waveforms may be combined depending on the moving speed of the carriage 20 on which the liquid ejection head 21 is mounted, the properties of the ink supplied to the liquid ejection head 21, the material of the medium P, and the like.

[0052] Here, the details of the head control signal DI, which includes the ejection control signal SI and the setting information signal SP, will be described with reference to Fig. 7. Fig. 7 is a diagram showing an example of the data configuration of the head control signal DI. As shown in Fig. 7, the head control signal DI includes the ejection control signal SI and the setting information signal SP, and the ejection control signal SI includes upper ejection data SIH and lower ejection data SIL.

[0053] Specifically, the ejection control signal SI is an n-bit serial signal that includes two bits of data, upper ejection data SIH and lower ejection data SIL, for controlling the driving of the piezoelectric element 60 included in the ejection section 600, corresponding to each of the n ejection sections 600.

[0054] In detail, the ejection control signal SI includes n-bit upper-order ejection data SIH in serial order, in the form of upper-order ejection data SIH corresponding to ejection section 600[n], upper-order ejection data SIH corresponding to ejection section 600[n-1], ..., upper-order ejection data SIH corresponding to ejection section 600[1], and after the upper-order ejection data SIH, includes n-bit lower-order ejection data SIL in serial order, in the form of lower-order ejection data SIL corresponding to ejection section 600[n], lower-order ejection data SIL corresponding to ejection section 600[n-1], ..., lower-order ejection data SIL corresponding to ejection section 600[1].

[0055] In the following description, the upper-order ejection data SIH corresponding to the ejection section 600[i] may be referred to as the upper-order ejection data SIHi, and the lower-order ejection data SIL corresponding to the ejection section 600[i] may be referred to as the lower-order ejection data SILi.

[0056] Then, the ejection unit 600[i] ejects an amount of ink defined by two bits, the upper ejection data SIHi and the lower ejection data SILi. That is, the ejection control signal SI controls the driving of the piezoelectric element 60 included in the ejection unit 600, thereby defining the amount of ink ejected from the nozzle 651. That is, the ejection control signal SI is a signal for controlling the gradation of dots formed on the medium P by ejecting ink from the nozzle 651. Here, in the following description, the upper ejection data SIH and the lower ejection data SIL corresponding to the ejection unit 600 may be referred to as ejection data [SIH, SIL], and the upper ejection data SIHi and the lower ejection data SILi corresponding to the ejection unit 600[i] may be referred to as ejection data [SIHi, SILi].

[0057] The setting information signal SP is used to set the rules for selecting the drive waveform to be applied to the piezoelectric element 60. Specifically, the setting information signal SP includes four types of setting information PA00 to PA03 indicating the drive pattern of the piezoelectric element 60 determined by a combination with the ejection data [SIH, SIL] included in the ejection control signal SI during a period T1 defined by the change signal CH, four types of setting information PA10 to PA13 indicating the drive pattern of the piezoelectric element 60 determined by a combination with the ejection data [SIH, SIL] included in the ejection control signal SI during a period T2, four types of setting information PA20 to PA23 indicating the drive pattern of the piezoelectric element 60 determined by a combination with the ejection data [SIH, SIL] included in the ejection control signal SI during a period T3, and four types of setting information PA30 to PA33 indicating the drive pattern of the piezoelectric element 60 determined by a combination with the ejection data [SIH, SIL] included in the ejection control signal SI during a period T4.

[0058] Specifically, the setting information PA is a 16-bit signal that is serially included in the order of PA33, PA32, PA31, PA30, PA23, PA22, PA21, PA20, PA13, PA12, PA11, PA10, PA03, PA02, PA01, and PA00. That is, the setting information signal SP is the state of the drive signal selection circuit 200 in the periods T1, T2, T3, and T4 that are defined by the change signal CH, and specifically, defines the relationship between the logic level of the selection signal S that defines the state of the selection circuits 230[1] to 230[n] described later and the ejection data [SIH, SIL] included in the ejection control signal SI.

[0059] In this embodiment, the setting information signal SP is described as being a 16-bit signal, but it may be a signal of more than 16 bits or a signal of less than 16 bits depending on the number of periods defined by the change signal CH, etc.

[0060] As described above, the control circuit 100 outputs to the selection control circuit 210 a latch signal LAT that determines the dot formation period T, a change signal CH that determines the switching timing at which the drive signal selection circuit 200 switches whether or not to supply the drive signal COM as VOUT to the ejection section 600, an ejection control signal SI that individually determines the amount of ink ejected by the n nozzles 651 onto the medium P, a setting information signal SP that determines the relationship between the logical level of the selection signal S that determines the state of the selection circuits 230[1] to 230[n] during each of periods T1, T2, T3, and T4 and the ejection control signal SI, and a clock signal SCK that propagates the head control signal DI that includes the ejection control signal SI and the setting information signal SP in serial.

[0061] Returning to FIG. 5, the control logic circuit 260 includes a SP register group 261 and a selection control signal generating unit 262. The SP register group 261 includes a plurality of serially connected registers, and constitutes a so-called shift register that sequentially propagates the head control signal DI, which is input in synchronization with the clock signal SCK, to the registers in the subsequent stages. When the supply of the clock signal SCK is stopped, the SP register group 261 holds the setting information PA33 to PA00 contained in the setting information signal SP among the head control signal DI. The selection control signal generating unit 262 latches the setting information PA33 to PA00 held in the SP register group 261 at the rising edge of the latch signal LAT, and translates the latched setting information PA33 to PA00 to generate selection signals Q1, Q2, Q3, and Q4, and outputs them to the decoders 226 of the n selection signal output units 270.

[0062] Here, the selection signal Q1 specifies the logic level of the selection signal S output from the selection control circuit 210 including the setting information PA00, PA01, PA02, and PA03 during the period T1, the selection signal Q2 specifies the logic level of the selection signal S output from the selection control circuit 210 including the setting information PA10, PA11, PA12, and PA13 during the period T2, the selection signal Q3 specifies the logic level of the selection signal S output from the selection control circuit 210 including the setting information PA20, PA21, PA22, and PA23 during the period T3, and the selection signal Q4 specifies the logic level of the selection signal S output from the selection control circuit 210 including the setting information PA30, PA31, PA32, and PA33 during the period T4. This signal defines the logic level of the selection signal S output from 10.

[0063] In the following description, the selection signal Q1 including setting information PA00, PA01, PA02, PA03 may be referred to as selection signal Q1[PA00, PA01, PA02, PA03], the selection signal Q2 including setting information PA10, PA11, PA12, PA13 may be referred to as selection signal Q2[PA10,11,PA12,PA13], the selection signal Q3 including setting information PA20, PA21, PA22, PA23 may be referred to as selection signal Q3[PA20,PA21,PA22,PA23], and the selection signal Q4 including setting information PA30, PA31, PA32, PA33 may be referred to as selection signal Q4[PA30,PA31,PA32,PA33].

[0064] Each of the n selection signal output units 270 includes a first register 222 a , a second register 222 b , a first latch circuit 224 a , a second latch circuit 224 b , and a decoder 226 .

[0065] The second register 222b included in each of the n selection signal output units 270 is serially connected to the rear stage of the SP register group 261 including a plurality of registers, and the first register 222a included in each of the n selection signal output units 270 is serially connected to the rear stage of the n serially connected second registers 222b. Specifically, the second register 222b included in the selection signal output unit 270 corresponding to the discharge unit 600[1] is connected to the rear stage of the SP register group 261.

[0066] In addition, the second register 222b included in the selection signal output unit 270 corresponding to the discharge unit 600[1] is connected in series to the rear of the second register 222b included in the selection signal output unit 270 corresponding to the discharge unit 600[2], the second register 222b included in the selection signal output unit 270 corresponding to the discharge unit 600[3], ..., the second register 222b included in the selection signal output unit 270 corresponding to the discharge unit 600[n], in that order.

[0067] The first register 222a included in the selection signal output unit 270 corresponding to the discharge unit 600[1] is connected to the rear stage of the second register 222b included in the selection signal output unit 270 corresponding to the discharge unit 600[n]. The first register 222a included in the selection signal output unit 270 corresponding to the discharge unit 600[2], the first register 222a included in the selection signal output unit 270 corresponding to the discharge unit 600[3], ..., the first register 222a included in the selection signal output unit 270 corresponding to the discharge unit 600[n] are connected in series to the rear stage of the first register 222a included in the selection signal output unit 270 corresponding to the discharge unit 600[1] in this order.

[0068] That is, the SP register group 261, the n second registers 222b included in each of the n selection signal output units 270, and the n first registers 222a included in each of the n selection signal output units 270 configure a shift register. The head control signal DI input to the SP register group 261 is propagated to the subsequent stages in the order of the n second registers 222b included in each of the n selection signal output units 270 and the n first registers 222a included in each of the n selection signal output units 270 in synchronization with the clock signal SCK. Thereafter, the supply of the clock signal SCK is stopped, so that the second register 222b included in the selection signal output unit 270 corresponding to the ejection unit 600[i] holds the lower ejection data SILi corresponding to the ejection unit 600[i], and the first register 222a included in the selection signal output unit 270 corresponding to the ejection unit 600[i] holds the upper ejection data SIHi corresponding to the ejection unit 600[i].

[0069] Here, the data size that can be held in the SP register group 261 is an example of a first data size, and the data size that can be held in the second register 222b is an example of a second data size. The data size that can be held in the first register 222a is the third data size. The register formed by consecutively connecting the SP register group 261, the second register 222b, and the first register 222a is an example of a first shift register.

[0070] The upper ejection data SIH held in the first register 222a of each of the n selection signal output units 270 is latched by the corresponding first latch circuit 224a at the rising edge of the latch signal LAT, and the lower ejection data SIL held in the second register 222b of each of the n selection signal output units 270 is latched by the corresponding second latch circuit 224b at the rising edge of the latch signal LAT. The first latch circuit 224a outputs the latched upper ejection data SIH to the decoder 226 as latch data LTa, and the second latch circuit 224b outputs the latched lower ejection data SIL to the decoder 226 as latch data LTb.

[0071] Here, the head control signal DI is an example of head control data. Also, the wiring A that transmits the head control signal DI to the SP register group 261, the second register 222b, and the first register 222a is an example of a first wiring. Also, the SP register group 261 is an example of a first region, the second register 222b is an example of a second region, and the first register 222a is an example of a third region.

[0072] Here, the head control signal DI held in the SP register group 261 is an example of first head control data, the head control signal DI held in the second register 222b is an example of second head control data, and the head control signal DI held in the first register 222a is an example of third head control data.

[0073] In the following description, the latch data LTa output by the first latch circuit 224a of the selection signal output unit 270 corresponding to the discharge unit 600[i] may be referred to as latch data LTai, and the latch data LTb output by the second latch circuit 224b of the selection signal output unit 270 corresponding to the discharge unit 600[i] may be referred to as latch data LTbi. Also, the latch data LTa, LTb may be referred to as latch data [LTa, LTb], and the latch data [LTa, LTb] corresponding to the discharge unit 600[i] may be referred to as latch data [LTai, LTbi].

[0074] The decoder 226 receives the selection signals Q1 [PA00, PA01, PA02, PA03], Q2 [PA10, PA11, PA12, PA13], Q3 [PA20, PA21, PA22, PA23], and Q4 [PA30, PA31, PA32, PA33] output by the selection control signal generating unit 262, and the latch data [LTa, LTb] corresponding to the ejection data [SIH, SIL]. The decoder 226 generates a selection signal S based on the selection signals Q1, Q2 and the latch data [LTa, LTb], and outputs it to the corresponding selection circuit 230.

[0075] Fig. 8 is a diagram showing the decoded contents of the decoder 226. As shown in Fig. 8, the decoder 226 outputs the logic level defined by the selection signal Q1 [PA00, PA01, PA02, PA03] as the selection signal S in a period T1, outputs the logic level defined by the selection signal Q2 [PA10, PA11, PA12, PA13] as the selection signal S in a period T2, outputs the logic level defined by the selection signal Q3 [PA20, PA21, PA22, PA23] as the selection signal S in a period T3, and outputs the logic level defined by the selection signal Q4 [PA30, PA31, PA32, PA33] as the selection signal S in a period T4.

[0076] That is, the change signal CH that defines the periods T1, T2, T3, and T4 is The timing of switching is specified as to whether the selection circuit 200 switches whether to supply the drive signal COM to the piezoelectric element 60 based on the selection signal Q1 [PA00, PA01, PA02, PA03], whether to switch whether to supply the drive signal COM to the piezoelectric element 60 based on the selection signal Q2 [PA10, PA11, PA12, PA13], whether to switch whether to supply the drive signal COM to the piezoelectric element 60 based on the selection signal Q3 [PA20, PA21, PA22, PA23], or whether to switch whether to supply the drive signal COM to the piezoelectric element 60 based on the selection signal Q4 [PA30, PA31, PA32, PA33].

[0077] Specifically, when ejection data [SIH, SIL] = [0, 0] is input during dot formation period T, the decoder 226 outputs the logical level of setting information PA00 as selection signal S during period T1, outputs the logical level of setting information PA10 as selection signal S during period T2, outputs the logical level of setting information PA20 as selection signal S during period T3, and outputs the logical level of setting information PA30 as selection signal S during period T4, in accordance with the contents specified by selection signals Q1, Q2, Q3, and Q4.

[0078] In addition, when ejection data [SIH, SIL] = [0, 1] is input during the dot formation period T, the decoder 226 outputs the logical level of setting information PA01 as selection signal S during period T1, outputs the logical level of setting information PA11 as selection signal S during period T2, outputs the logical level of setting information PA21 as selection signal S during period T3, and outputs the logical level of setting information PA31 as selection signal S during period T4, in accordance with the contents specified by selection signals Q1, Q2, Q3, and Q4.

[0079] In addition, when ejection data [SIH, SIL] = [1, 0] is input during the dot formation period T, the decoder 226 outputs the logical level of setting information PA02 as selection signal S during period T1, outputs the logical level of setting information PA12 as selection signal S during period T2, outputs the logical level of setting information PA22 as selection signal S during period T3, and outputs the logical level of setting information PA32 as selection signal S during period T4, in accordance with the contents specified by selection signals Q1, Q2, Q3, and Q4.

[0080] Furthermore, when ejection data [SIH, SIL] = [1, 1] is input during the dot formation period T, the decoder 226 outputs the logical level of setting information PA03 as selection signal S during period T1, outputs the logical level of setting information PA13 as selection signal S during period T2, outputs the logical level of setting information PA23 as selection signal S during period T3, and outputs the logical level of setting information PA33 as selection signal S during period T4, in accordance with the contents specified by selection signals Q1, Q2, Q3, and Q4.

[0081] As described above, the selection control circuit 210 outputs selection signals S[1] to S[n] that control the states of the selection circuits 230[1] to 230[n] corresponding to the ejection sections 600[1] to 600[n], respectively, based on the clock signal SCK, the latch signal LAT, the change signal CH, and the head control signal DI.

[0082] Next, the configuration of the selection circuits 230[1] to 230[n] will be described. Here, the selection circuits 230[1] to 230[n] all have the same configuration. Therefore, when there is no need to distinguish between the selection circuits 230[1] to 230[n], they may be simply referred to as selection circuits 230. The following description will be given on the assumption that the selection signal S of the selection signals S[1] to S[n] is input to the selection circuit 230.

[0083] 9 is a diagram showing the configuration of the selection circuit 230 corresponding to one of the discharge units 600. As shown in FIG. 9, the selection circuit 230 includes an inverter 232 which is a NOT circuit, and a transfer The selection circuit 230 has a gate 234. Here, the selection circuit 230 is an example of a switch circuit. Also, the wiring that transmits the drive signal COM is an example of a second wiring.

[0084] The selection signal S output by the selection control circuit 210 is input to a positive control terminal of the transfer gate 234 that is not marked with a circle, and is also logically inverted by the inverter 232 and input to a negative control terminal of the transfer gate 234 that is marked with a circle. A drive signal COM is also supplied to the input terminal of the transfer gate 234. Specifically, the transfer gate 234 provides conduction between the input terminal and the output terminal when the input selection signal S is at an H level, and provides non-conduction between the input terminal and the output terminal when the input selection signal S is at an L level.

[0085] When the input selection signal S is at an H level, the transfer gate 234 outputs VOUT from the output terminal of the transfer gate 234. That is, when the input selection signal S is at an H level, the transfer gate 234 is ON, and when the input selection signal S is at an L level, the transfer gate 234 is OFF.

[0086] In the liquid ejection device 1 of this embodiment, the control mechanism 10 has an ejection control period in which it controls the liquid ejection head 21 to eject ink from the nozzles 651, and a non-ejection control period in which it controls the liquid ejection head 21 so that ink is not ejected from the nozzles 651. The control mechanism 10 outputs a head control signal DI containing different data during the ejection control period and the non-ejection control period, thereby reducing the risk of malfunction of the liquid ejection device 1 even when the control of the drive signal selection circuit 200 of the liquid ejection head 21 is executed using common signals: the clock signal SCK, the latch signal LAT, the change signal CH, and the head control signal DI.

[0087] As described above, the drive signal selection circuit 200 in this embodiment selects or deselects the drive signal COM based on the input clock signal SCK, latch signal LAT, change signal CH, and head control signal DI, thereby generating VOUT[1] to VOUT[n] and outputting them to the corresponding ejection sections 600[1] to 600[n], thereby performing printing.

[0088] That is, the control mechanism 10 controls the drive signal selection circuit 200 using the clock signal SCK, the latch signal LAT, the change signal CH, and the head control signal DI to supply VOUT[1] to VOUT[n] based on the drive signal COM to each of the ejection sections 600[1] to 600[n], thereby causing the corresponding ejection sections 600[1] to 600[n] to eject ink.

[0089] 4. Multi-tone mode Next, an operation will be described in which the control mechanism 10 controls the liquid ejection head 21 during the ejection control period to perform printing in the multi-tone mode. Note that the multi-tone mode is an example of the first printing mode.

[0090] 10 is a diagram showing an example of a head control signal DI output by the control mechanism 10 during the ejection control period. Here, the ejection control signal SI included in each head control signal DI is a signal that specifies the amount of ink ejected for each of the n nozzles 651, and the logical level changes appropriately during the ejection control period. In other words, the ejection data [SIH, SIL] included in the ejection control signal SI is either 0 or 1 depending on the amount of ink ejected from the corresponding nozzle 651 in the dot formation cycle T. In the following explanation, it is assumed that "1" means an H level signal and "0" means an L level signal.

[0091] As shown in FIG. 10, during the discharge control period, the control mechanism 10 generates a setting information signal SP. The head control signal DI including the setting information PA33 to PA00 is output to the selection control circuit 210.

[0092] Specifically, setting information in which the setting information PA33, PA32, PA32, and PA31 are "0", "0", "0", and "1", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA23, PA22, PA21, and PA20 are "1", "1", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA13, PA12, PA11, and PA10 are "1", "0", "1", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA03, PA02, PA01, and PA00 are "1", "1", "0", and "0", respectively, is output to the selection control circuit 210.

[0093] Therefore, the selection control signal generating unit 262 included in the control logic circuit 260 of the selection control circuit 210 generates the selection signals Q1 to Q4 based on the setting information PA, and outputs them to the decoder 226. Specifically, the selection control circuit 210 generates the selection signal Q1 [PA00, PA01, PA02, PA03] = [0, 0, 1, 1], the selection signal Q2 [PA10, PA11, PA12, PA13] = [0, 1, 0, 1], the selection signal Q3 [PA20, PA21, PA22, PA23] = [0, 0, 1, 1], and the selection signal Q4 [PA30, PA31, PA32, PA33] = [1, 0, 0, 0], and outputs them to the decoder 226.

[0094] Fig. 11 is a diagram showing the decoded contents in the decoder 226 of the selection control circuit 210 during the discharge control period. As shown in Fig. 11, the decoder 226 outputs a selection signal S corresponding to the discharge data [SIH, SIL].

[0095] Specifically, when the discharge data [SIH, SIL] = [0, 0] is input, the decoder 226 outputs a selection signal S of L level in period T1, L level in period T2, L level in period T3, and H level in period T4. Also, when the discharge data [SIH, SIL] = [0, 1] is input, the decoder 226 outputs a selection signal S of L level in period T1, H level in period T2, L level in period T3, and L level in period T4.

[0096] Furthermore, when the discharge data [SIH, SIL] = [1, 0] is input, the decoder 226 outputs a selection signal S of H level in period T1, L level in period T2, H level in period T3, and L level in period T4. Furthermore, when the discharge data [SIH, SIL] = [1, 1] is input, the decoder 226 outputs a selection signal S of H level in period T1, H level in period T2, H level in period T3, and L level in period T4.

[0097] Fig. 12 is a diagram for explaining the operation of the selection circuit 230 when the selection signal S shown in Fig. 11 is supplied. The transfer gate 234 is turned ON or OFF according to the selection signal S supplied in accordance with the ejection data [SIH, SIL].

[0098] Specifically, when the ejection data [SIH, SIL]=[0,0], the transfer gate 234 is OFF in the period T1, OFF in the period T2, OFF in the period T3, and ON in the period T4. Also, when the ejection data [SIH, SIL]=[0,1], the transfer gate 234 is OFF in the period T1, ON in the period T2, OFF in the period T3, and OFF in the period T4.

[0099] Also, when the discharge data [SIH, SIL] = [1, 0], transfer gate 23 4 is ON during period T1, OFF during period T2, ON during period T3, and OFF during period T4. In addition, when the ejection data [SIH, SIL]=[1, 1], the transfer gate 234 is ON during period T1, ON during period T2, ON during period T3, and OFF during period T4.

[0100] Next, the dots formed on the medium P for each ejection data [SIH, SIL] will be described. When the ejection data [SIH, SIL]=[0,0], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during periods T1, T2, and T3, and a drive waveform dp4 is supplied as VOUT during period T4. In this case, only the vicinity of the nozzle 651 vibrates slightly, and ink is not ejected from the nozzle 651. Therefore, no dots are formed on the medium P.

[0101] When the ejection data [SIH, SIL] = [0, 1], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during periods T1, T3, and T4, and a drive waveform dp2 is supplied as VOUT during period T2. In this case, a medium amount of ink is ejected once from the nozzle 651 and lands on the medium P. Therefore, a small dot is formed on the medium P.

[0102] When the ejection data [SIH, SIL] = [1, 0], a constant waveform at voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during periods T2 and T4, a drive waveform dp1 is supplied as VOUT during period T1, and a drive waveform dp3 is supplied as VOUT during period T3. In this case, a large amount of ink and a small amount of ink are ejected from the nozzle 651 and land on the medium P. Thereafter, the large amount of ink and the small amount of ink that have landed on the medium P combine to form a medium dot on the medium P.

[0103] When the ejection data [SIH,SIL]=[1,1], a constant waveform at voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T4, drive waveform dp1 is supplied as VOUT during period T1, drive waveform dp2 is supplied as VOUT during period T2, and drive waveform dp3 is supplied as VOUT during period T3. In this case, a large amount of ink, a medium amount of ink, and a small amount of ink are ejected from the nozzle 651 and land on the medium P. After that, the large amount of ink, the medium amount of ink, and the small amount of ink that have landed on the medium P combine to form a large dot on the medium P.

[0104] As described above, during the ejection control period, the control mechanism 10 outputs a head control signal DI as shown in FIG. 10 to the liquid ejection head 21, and the liquid ejection head 21 forms four types of dots, large dots, medium dots, small dots, and non-printing dots, on the medium P based on the ejection control signal SI and the setting information signal SP.

[0105] In the multi-tone mode of this embodiment, the drive signal selection circuit 200 defines the dot formation cycle T into four periods T1 to T4 by the change signal CH, and switches whether or not to supply the drive signal COM as VOUT to the ejection section 600 in each period. This enables the liquid ejection head 21 to form four types of dots, including non-recording, on the medium P. This enables the liquid ejection device 1 to print in four gradations, and form a high-definition image on the medium P. Note that the number of gradations, four, in the multi-tone mode of this embodiment is an example of the first number of gradations.

[0106] In the multi-tone mode of the present embodiment, an example has been given in which four types of dots, large dots, medium dots, small dots, and non-recording, are formed on the medium P, but for example, three types of dots, large dots, medium dots, and non-recording, may be formed on the medium P. In this case, the liquid ejection device 1 is capable of printing in three gradations. Generally, when printing in the multi-tone mode, the number of gradations is three or more. can be.

[0107] 5. Binary Mode 13 is a diagram showing an example of the latch signal LAT, change signal CH, clock signal SCK, head control signal DI, and drive signal COM input to the selection control circuit 210 in the binary mode. Here, an example is shown in which the drive signal COM is composed of two types of drive waveforms, and a single change signal CH defines the dot formation cycle T to two periods T1 and T2. Note that the binary mode is an example of the second print mode.

[0108] The driving waveform dp10 is a waveform for ejecting a medium amount of ink from the nozzle 651, and the driving waveform dp11 is a waveform for preventing ink from being ejected from the nozzle 651, and for preventing an increase in ink viscosity by slightly vibrating the ink near the opening of the nozzle 651. These two types of driving waveforms dp10 and dp11 are switched as VOUT to control whether or not to eject ink from the nozzle 651. That is, the binary mode controls two states, a state in which ink is ejected from the nozzle 651 and a state in which ink is not ejected, so that the number of gradations is two. The number of gradations in the binary mode in this embodiment, 2, is an example of the second number of gradations.

[0109] 14 is a diagram showing an example of a head control signal DI output by the control mechanism 10 during the ejection control period in the binary mode. Here, the ejection control signal SI included in each head control signal DI is a signal that specifies the amount of ink ejected for each of the n nozzles 651, and the logical level changes appropriately during the ejection control period. In other words, the ejection data [SIH, SIL] included in the ejection control signal SI is either 0 or 1 depending on the amount of ink ejected from the corresponding nozzle 651 in the dot formation cycle T. In the following explanation, it is assumed that "1" means an H level signal and "0" means an L level signal.

[0110] 14, during the discharge control period, the control mechanism 10 outputs the head control signal DI, which includes the setting information PA33-PA00 constituting the setting information signal SP, to the selection control circuit 210. In this case, the setting information signal SP is 16 bits. Here, the setting information signal SP, which includes the setting information PA33-PA00, is an example of a setting information signal group.

[0111] Specifically, setting information in which the setting information PA33, PA32, PA32, and PA31 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA23, PA22, PA21, and PA20 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA13, PA12, PA11, and PA10 are "0", "1", "0", and "1", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA03, PA02, PA01, and PA00 are "1", "0", "1", and "0", respectively, is output to the selection control circuit 210.

[0112] Therefore, the selection control signal generating unit 262 included in the control logic circuit 260 of the selection control circuit 210 generates the selection signals Q1 to Q4 based on the setting information PA, and outputs them to the decoder 226. Specifically, the selection control circuit 210 generates the selection signal Q1 [PA00, PA01, PA02, PA03] = [0, 1, 0, 1], the selection signal Q2 [PA10, PA11, PA12, PA13] = [1, 0, 1, 0], the selection signal Q3 [PA20, PA21, PA22, PA23] = [0, 0, 0, 0], and the selection signal Q4 [PA30, PA31, PA32, PA33] = [0, 0, 0, 0], and outputs them to the decoder 226.

[0113] Here, the setting information signal SP is set so that the bit data of the setting information PA00-PA03 and the setting information PA10-PA13 are inverted, and therefore the bit data of the selection signal Q1 and the selection signal Q2 are inverted. Here, the setting information PA00-PA03 is an example of a first setting information signal, and the setting information PA10-PA13 is an example of a second setting information signal.

[0114] Fig. 15 is a diagram showing the decoded contents in the decoder 226 of the selection control circuit 210 during the discharge control period. As shown in Fig. 15, the decoder 226 outputs a selection signal S corresponding to the discharge data [SIH, SIL].

[0115] Specifically, when the discharge data [SIH, SIL]=[0,0] is input, the decoder 226 outputs a selection signal S of L level in period T1 and of H level in period T2, and when the discharge data [SIH, SIL]=[0,1] is input, the decoder 226 outputs a selection signal S of H level in period T1 and of L level in period T2.

[0116] Furthermore, when the discharge data [SIH, SIL]=[1, 0] is input, the decoder 226 outputs a selection signal S of L level in period T1 and H level in period T2. When the discharge data [SIH, SIL]=[1, 1] is input, the decoder 226 outputs a selection signal S of H level in period T1 and L level in period T2.

[0117] Fig. 16 is a diagram for explaining the operation of the selection circuit 230 when the selection signal S shown in Fig. 15 is supplied. The transfer gate 234 is turned ON or OFF according to the selection signal S supplied in accordance with the ejection data [SIH, SIL].

[0118] Specifically, when [SIH, SIL]=[0, 0], the transfer gate 234 is turned OFF in period T1 and turned ON in period T2. When the ejection data [SIH, SIL]=[0, 1], the transfer gate 234 is turned ON in period T1 and turned OFF in period T2.

[0119] In addition, when the ejection data [SIH, SIL]=[1, 0], the transfer gate 234 is turned OFF in the period T1 and turned ON in the period T2. In addition, when the ejection data [SIH, SIL]=[1, 1], the transfer gate 234 is turned ON in the period T1 and turned OFF in the period T2.

[0120] Next, the dots formed on the medium P for each ejection data [SIH, SIL] will be described. When the ejection data [SIH, SIL]=[0,0], a constant waveform at voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T1, and a drive waveform dp11 is supplied as VOUT during period T2. In this case, only the vicinity of the nozzle 651 vibrates slightly, and ink is not ejected from the nozzle 651. Therefore, no dots are formed on the medium P.

[0121] When the ejection data [SIH, SIL] = [0, 1], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T2, and a drive waveform dp10 is supplied as VOUT during period T1. In this case, a medium amount of ink is ejected once from the nozzle 651 and lands on the medium P. Therefore, a dot is formed on the medium P.

[0122] When the ejection data [SIH, SIL] = [1, 0], a constant waveform of voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T1, and a drive waveform dp11 is supplied as VOUT during period T2. In this case, only the vicinity of the nozzle 651 vibrates slightly, and ink is not ejected from the nozzle 651. Therefore, dots are formed on the medium P. I can't.

[0123] When the ejection data [SIH, SIL] = [1, 1], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T2, and a drive waveform dp10 is supplied as VOUT during period T1. In this case, a medium amount of ink is ejected once from the nozzle 651 and lands on the medium P. Therefore, a dot is formed on the medium P.

[0124] As described above, in the binary mode, the setting information signal SP is set so that the bit data of the selection signals Q1 and Q2 are inverted, and therefore printing in the binary mode can be performed according to the value of the ejection data [SIL] regardless of the value of the ejection data [SIH]. Specifically, when [SIL]=[0], ink is not ejected from the nozzle 651, so no dots are formed on the medium P, and when the ejection data [SIL]=[1], ink is ejected from the nozzle 651, and dots are formed on the medium P. The ejection data [SIL] is an example of a first ejection control signal.

[0125] That is, in the binary mode, the head control signal DI does not need to include the ejection data [SIH]. Because the data size of the head control signal DI can be reduced, the dot formation period T per printing cycle can be shortened compared to the multi-tone mode.

[0126] The data size of the ejection data [SIH] increases in proportion to the number of nozzles 651, so the data size of the ejection data [SIH] that can be omitted increases as the number of nozzles 651 increases. In other words, the effect of shortening the printing cycle increases as the number of nozzles 651 increases.

[0127] For example, when the number of nozzles 651 is 400, the data size of the ejection data [SIH] is 400 bits, and when the number of nozzles 651 is 800, the data size of the ejection data [SIH] is 800 bits. Therefore, when the number of nozzles 651 is 800, the data size of the omittable ejection data [SIH] is 400 bits more than when the number of nozzles 651 is 400.

[0128] In this embodiment, since the multi-tone mode and the binary mode can be executed with the same hardware configuration, the user can arbitrarily switch between the modes, expanding the range of use.

[0129] In this embodiment, in both the multi-tone mode and the binary mode, the selection signals Q1 to Q4 are generated based on a 16-bit setting information signal SP. In the binary mode, the selection signals Q1 and Q2 may be generated based on an 8-bit setting information signal SP. This reduces the data size of the head control signal DI, allowing the printing cycle to be shortened.

[0130] Furthermore, in the binary mode of this embodiment, the ejection of ink from the nozzle 651 is controlled using two drive waveforms, dp10 and dp11, but the same effect as that obtained in the binary mode of this embodiment can be obtained using only dp10. That is, by turning off the transfer gate 234, control may be performed so that the nozzle 651 is not vibrated slightly and dots are not formed on the medium P. When there is one drive waveform, the dot formation period T does not need to be determined by the change signal CH, and therefore the printing period can be further shortened.

[0131] 6. Second embodiment A liquid ejection device 1 in the second embodiment will be described. In describing the liquid ejection device 1 in the second embodiment, the same configuration as that of the liquid ejection device 1 in the first embodiment will be described. In the above, the same reference numerals are used and the description thereof will be omitted or simplified.

[0132] 17 is a diagram showing the configuration of a drive signal selection circuit 200 in the second embodiment. The drive signal selection circuit 200 in the second embodiment includes a selection control circuit 210 and selection circuits 230[1] to 230[n]. The selection control circuit 210 outputs a selection signal Sa for switching whether or not to output the drive signal COMA as VOUT, and a selection signal Sb for switching whether or not to output the drive signal COMB as VOUT, to the selection circuits 230[1] to 230[n].

[0133] In the second embodiment, the clock signal SCK, the latch signal LAT, the change signals CHA and CHB, the head control signal DI, and the drive signals COMA and COMB are input to the drive signal selection circuit 200. The drive signal selection circuit 200 generates VOUT[1] to VOUT[n] by selecting or not selecting the drive signals COMA and COMB based on the clock signal SCK, the latch signal LAT, the change signals CHA and CHB, and the input head control signal DI, and outputs them to the corresponding ejection sections 600[1] to 600[n]. The piezoelectric element 60 is driven by the supply of VOUT based on the drive signals COMA and COMB.

[0134] A clock signal SCK, a latch signal LAT, change signals CHA, CHB, and a head control signal DI are input to the selection control circuit 210. Then, based on the clock signal SCK, the latch signal LAT, the change signals CHA, CHB, and the head control signal DI, the selection control circuit 210 outputs selection signals Sa[1] to Sa[n], Sb[1] to Sb[n] for switching whether or not each of the selection circuits 230[1] to 230[n] outputs as VOUT based on the drive signals COMA, COMB.

[0135] The wiring A that transmits the head control signal DI to the selection control circuit 210 is an example of a first wiring. More specifically, the wiring A transmits the head control signal DI to the SP register group 261, the second register 222b, and the first register 222a.

[0136] Next, the configuration of the selection circuits 230[1] to 230[n] will be described. The selection circuits 230[1] to 230[n] all have the same configuration. The selection circuit 230 receives a selection signal Sa among the selection signals Sa[1] to Sa[n] and a selection signal Sb among the selection signals Sb[1] to Sb[n].

[0137] Fig. 18 is a diagram showing the configuration of a selection circuit 230 corresponding to one of the discharge sections 600. As shown in Fig. 18, the selection circuit 230 has inverters 232a and 232b, which are NOT circuits, and transfer gates 234a and 234b.

[0138] The selection signal Sa output by the selection control circuit 210 is input to a positive control terminal of the transfer gate 234a that is not marked with a circle, and is also logically inverted by the inverter 232a and input to a negative control terminal of the transfer gate 234a that is marked with a circle. A drive signal COMA is supplied to the input terminal of the transfer gate 234a. Specifically, the transfer gate 234a makes the input terminal and output terminal conductive when the input selection signal Sa is at H level, and makes the input terminal and output terminal non-conductive when the input selection signal Sa is at L level.

[0139] Similarly, the selection signal Sb output by the selection control circuit 210 is input to a positive control terminal of the transfer gate 234b that is not marked with a circle, and is also logically inverted by the inverter 232b and input to a negative control terminal of the transfer gate 234b that is marked with a circle. Specifically, the transfer gate 234b provides electrical continuity between the input terminal and the output terminal when the input selection signal Sb is at H level, and provides no electrical continuity between the input terminal and the output terminal when the input selection signal Sb is at L level.

[0140] The output terminal of the transfer gate 234a and the output terminal of the transfer gate 234b are connected in common, VOUT is output from the common connection point, and ink is ejected from the corresponding ejection section 600. The selection circuit 230 is an example of a switch circuit. The wiring that transmits the drive signals COMA and COMB is an example of a second wiring.

[0141] 7. Multi-tone mode in the second embodiment Next, an operation will be described in which the control mechanism 10 controls the liquid ejection head 21 during the ejection control period to perform printing in the multi-tone mode. Note that the multi-tone mode is an example of the first printing mode.

[0142] Fig. 19 is a diagram for explaining the latch signal LAT, the change signal CH, the clock signal SCK, the head control signal DI, and the drive signal COM. Fig. 19 is a diagram showing an example of the latch signal LAT, the change signals CHA and CHB, the clock signal SCK, the head control signal DI, and the drive signals COMA and COMB input to the selection control circuit 210.

[0143] A clock signal SCK, a latch signal LAT, a change signal CHA, a head control signal DI, and drive signals COMA and COMB are input to the selection control circuit 210. In the second embodiment, the change signals CHA and CHB are explained as pulse signals that are output once in a dot formation cycle T. That is, in the second embodiment, the change signal CHA defines the dot formation cycle T as periods Ta1 and Ta2, and the change signal CHB defines the dot formation cycle T as periods Tb1 and Tb2.

[0144] Then, the selection circuit 230 switches whether to supply the drive signal COMA as VOUT to the discharge section 600 during the periods Ta1 and Ta2 based on the selection signal Sa. Similarly, the selection circuit 230 switches whether to supply the drive signal COMB as VOUT to the discharge section 600 during the periods Tb1 and Tb2 based on the selection signal Sb.

[0145] The drive signal COMA includes drive waveforms Adp1 and Adp2, and the drive signal COMB includes drive waveforms Bdp1 and Bdp2. The drive waveform Adp1 is a waveform for ejecting a large amount of ink from the nozzle 651, and the drive waveform Adp2 is a waveform for ejecting a medium amount of ink from the nozzle 651. The drive waveform Bdp2 is a waveform for ejecting a small amount of ink from the nozzle 651, and Bdp1 is a waveform that does not eject ink from the nozzle 651 and is a waveform that slightly vibrates the ink near the opening of the nozzle 651 to prevent an increase in ink viscosity.

[0146] 20 is a diagram showing an example of a head control signal DI output by the control mechanism 10 during the ejection control period. Here, the ejection control signal SI included in the head control signal DI is a signal that specifies the amount of ink ejected for each of the n nozzles 651, and the logical level changes appropriately during the ejection control period. In other words, the ejection data [SIH, SIL] included in the ejection control signal SI is either 0 or 1 depending on the amount of ink ejected from the corresponding nozzle 651 in the dot formation cycle T.

[0147] 20, during the discharge control period, the control mechanism 10 outputs the head control signal DI, which includes the setting information PA33 to PA00 and PB33 to PB00 constituting the setting information signal SP, to the selection control circuit 210. In this case, the setting information signal SP is 32 bits. The setting information PA33 to PA00 is setting information for setting a rule for selecting, from the drive signal COMA, the drive waveform Adp1 or Adp2 to be applied to the piezoelectric element 60, and the setting information PB33 to PB00 is setting information for setting a rule for selecting, from the drive signal COMB, the drive waveform Bdp1 or Bdp2 to be applied to the piezoelectric element 60. Here, the setting information PA33 to PA00 and the setting information signal SP including the setting information PB33 to PB00 are an example of a setting information signal group.

[0148] Specifically, setting information in which the setting information PA33, PA32, PA32, and PA31 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA23, PA22, PA21, and PA20 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA13, PA12, PA11, and PA10 are "1", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA03, PA02, PA01, and PA00 are "1", "1", "0", and "0", respectively, is output to the selection control circuit 210.

[0149] Therefore, the selection control signal generating unit 262 included in the control logic circuit 260 of the selection control circuit 210 generates the selection signals Qa1 to Qa4 based on the setting information PA, and outputs them to the decoder 226. Specifically, the selection control circuit 210 generates the selection signal Qa1 [PA00, PA01, PA02, PA03] = [0, 0, 1, 1], the selection signal Qa2 [PA10, PA11, PA12, PA13] = [0, 0, 0, 1], the selection signal Qa3 [PA20, PA21, PA22, PA23] = [0, 0, 0, 0], and the selection signal Qa4 [PA30, PA31, PA32, PA33] = [0, 0, 0, 0], and outputs them to the decoder 226.

[0150] Similarly, setting information in which setting information PB33, PB32, PB32, and PB31 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which setting information PB23, PB22, PB21, and PB20 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which setting information PB13, PB12, PB11, and PB10 are "0", "1", "1", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which setting information PB03, PB02, PB01, and PB00 are "0", "0", "0", and "1", respectively, is output to the selection control circuit 210.

[0151] Therefore, the selection control signal generating unit 262 included in the control logic circuit 260 of the selection control circuit 210 generates selection signals Qb1 to Qb4 based on the setting information PB, and outputs them to the decoder 226. Specifically, the selection control circuit 210 generates a selection signal Qb1 [PB00, PB01, PB02, PB03] = [1, 0, 0, 0], a selection signal Qb2 [PB10, PB11, PB12, PB13] = [0, 1, 1, 0], a selection signal Qb3 [PB20, PB21, PB22, PB23] = [0, 0, 0, 0], and a selection signal Qb4 [PB30, PB31, PB32, PB33] = [0, 0, 0, 0], and outputs them to the decoder 226.

[0152] Fig. 21 is a diagram showing the decoded contents in the decoder 226 of the selection control circuit 210 during the discharge control period. As shown in Fig. 21, the decoder 226 outputs a selection signal Sa corresponding to the discharge data [SIH, SIL].

[0153] Specifically, when the discharge data [SIH, SIL]=[0, 0] is input, the decoder 226 outputs a selection signal Sa of L level in the period Ta1 and of L level in the period Ta2. Also, when the discharge data [SIH, SIL]=[0, 1] is input, the decoder 226 outputs a selection signal Sa of L level in the period Ta1 and of L level in the period Ta2. Output Sa.

[0154] Furthermore, when the discharge data [SIH, SIL] = [1, 0] is input, the decoder 226 outputs a selection signal Sa of H level in period Ta1 and of L level in period Ta2. Furthermore, when the discharge data [SIH, SIL] = [1, 1] is input, the decoder 226 outputs a selection signal Sa of H level in period Ta1 and of H level in period Ta2. Note that in the multi-tone mode of the second embodiment, the dot formation cycle T is regulated to two periods Ta1 and Ta2 by the change signal CHA, so that the selection signals Qa1 and Qa2 are selected and Qa3 and Qa4 are not selected.

[0155] Fig. 22 is a diagram showing the decoded contents in the decoder 226 of the selection control circuit 210 during the discharge control period. As shown in Fig. 22, the decoder 226 outputs a selection signal Sb corresponding to the discharge data [SIH, SIL].

[0156] Specifically, when the discharge data [SIH, SIL]=[0,0] is input, the decoder 226 outputs a selection signal Sb of H level in period Tb1 and of L level in period Tb2. When the discharge data [SIH, SIL]=[0,1] is input, the decoder 226 outputs a selection signal Sb of L level in period Tb1 and of H level in period Ta2.

[0157] Furthermore, when the decoder 226 receives ejection data [SIH, SIL]=[1,0], it outputs a selection signal Sb of L level in period Tb1 and H level in period Tb. Furthermore, when the decoder 226 receives ejection data [SIH, SIL]=[1,1], it outputs a selection signal Sb of L level in period Tb1 and L level in period Tb2. Note that in the multi-tone mode of the second embodiment, the dot formation cycle T is regulated to two periods Tb1 and Tb2 by the change signal CHB, so that the selection signals Qb1 and Qb2 are selected and Qb3 and Qb4 are not selected.

[0158] Fig. 23 is a diagram for explaining the operation of the selection circuit 230 when the selection signals Sa and Sb shown in Fig. 21 and 22 are supplied. The transfer gates 234a and 234b are turned ON or OFF according to the selection signal S supplied in accordance with the ejection data [SIH, SIL].

[0159] Specifically, when the ejection data [SIH, SIL] = [0, 0], the transfer gate 234a is OFF in the period Ta1 and is OFF in the period Ta2. The transfer gate 234b is ON in the period Tb1 and is OFF in the period Tb2. When the ejection data [SIH, SIL] = [0, 1], the transfer gate 234a is OFF in the period Ta1 and is OFF in the period Ta2. The transfer gate 234b is OFF in the period Tb1 and is ON in the period Tb2.

[0160] Moreover, when the ejection data [SIH, SIL] = [1, 0], the transfer gate 234a is ON during the period Ta1 and OFF during the period Ta2. The transfer gate 234b is OFF during the period Tb1 and ON during the period Tb2. Moreover, when the ejection data [SIH, SIL] = [1, 1], the transfer gate 234a is ON during the period Ta1 and ON during the period Ta2. The transfer gate 234b is OFF during the period Tb1 and OFF during the period Tb2.

[0161] Next, the dots formed on the medium P for each ejection data [SIH, SIL] will be described. When the ejection data [SIH, SIL]=[0,0], the corresponding piezoelectric element 60 is supplied with a constant waveform at voltage Vc as VOUT during period Tb2, and is supplied with a drive waveform Bdp1 as VOUT during period Tb1. In this case, the vicinity of the nozzle 651 is subjected to micro vibrations. However, no ink is ejected from the nozzle 651. Therefore, no dots are formed on the medium P.

[0162] When the ejection data [SIH, SIL] = [0, 1], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period Tb1, and a drive waveform Bdp2 is supplied as VOUT during period Tb2. In this case, a small amount of ink is ejected once from the nozzle 651 and lands on the medium P. Therefore, a small dot is formed on the medium P.

[0163] When the ejection data [SIH, SIL] = [1, 0], the driving waveform Adp1 is supplied as VOUT to the corresponding piezoelectric element 60 during the period Ta1, and the driving waveform Bdp2 is supplied as VOUT during the period Tb2. In this case, a large amount of ink and a small amount of ink are ejected from the nozzle 651 and land on the medium P. Thereafter, the large amount of ink and the small amount of ink that have landed on the medium P combine to form a medium dot on the medium P.

[0164] When the ejection data [SIH, SIL] = [1, 1], the driving waveform Adp1 is supplied as VOUT to the corresponding piezoelectric element 60 during the period Ta1, and the driving waveform Adp2 is supplied as VOUT during the period Ta2. In this case, a large amount of ink, a medium amount of ink, and a small amount of ink are ejected from the nozzle 651 and land on the medium P. Thereafter, the large amount of ink, the medium amount of ink, and the small amount of ink that have landed on the medium P combine to form a large dot on the medium P.

[0165] As described above, during the ejection control period, the control mechanism 10 outputs a head control signal DI to the liquid ejection head 21, and the liquid ejection head 21 forms four types of dots, large dots, medium dots, small dots, and non-printing dots, on the medium P based on the ejection control signal SI and the setting information signal SP.

[0166] In the multi-tone mode of the second embodiment, the drive signal selection circuit 200 specifies the dot formation cycle T as periods Ta1, Ta2, Tb1, and Tb2 by the change signals CHA and CHB, and switches whether or not to supply the drive signal COMA or the drive signal COMB as VOUT to the ejection section 600 in each period. This enables the liquid ejection head 21 to form four types of dots, including non-recording, on the medium P. This enables the liquid ejection device 1 to print in four gradations, and to form a high-definition image on the medium P. Note that the number of gradations, four, in the multi-gradation mode of the second embodiment is an example of the first number of gradations.

[0167] 8. Binary mode in the second embodiment Next, an operation will be described in which the control mechanism 10 controls the liquid ejection head 21 during the ejection control period to perform printing in the binary mode. Note that the binary mode is an example of the second print mode.

[0168] 24 is a diagram for explaining the latch signal LAT, the change signal CH, the clock signal SCK, the head control signal DI, and the drive signal COM. It is a diagram showing an example of the latch signal LAT, the change signals CHA and CHB, the clock signal SCK, the head control signal DI, and the drive signals COMA and COMB input to the selection control circuit 210.

[0169] The selection control circuit 210 receives the clock signal SCK, the latch signal LAT, the change signals CHA and CHB, the head control signal DI, and the drive signals COMA and COMB. In the binary mode of the second embodiment, the change signals CHA and CHB are at the L level, so the dot formation cycle T is not regulated. The selection circuit 230 outputs the drive signals COMA and COMB to the VO for each dot formation cycle T, i.e., for each printing cycle, based on the selection signals Sa and Sb. It switches whether or not to supply the UT to the discharge part 600.

[0170] The drive signal COMA includes a drive waveform Adp10, and the drive signal COMB includes a drive waveform Bdp10. The drive waveform Adp10 is a waveform for ejecting a medium amount of ink from the nozzle 651, and the drive waveform Bdp10 is a waveform for preventing ink from being ejected from the nozzle 651, and for preventing an increase in ink viscosity by slightly vibrating the ink near the opening of the nozzle 651. That is, the binary mode controls two states, a state in which ink is ejected from the nozzle 651 and a state in which ink is not ejected, and therefore the number of gradations of the formed dots is two. Note that the number of gradations in the binary mode in the second embodiment, two, is an example of the second number of gradations.

[0171] 25 is a diagram showing an example of a head control signal DI output by the control mechanism 10 during a discharge control period in the binary mode. Here, the discharge control signal SI included in the head control signal DI is a signal that specifies the amount of ink discharged for each of the n nozzles 651, and the discharge data [SIH, SIL] included in the discharge control signal SI is either 0 or 1 depending on the amount of ink discharged from the corresponding nozzle 651 in the dot formation cycle T.

[0172] As shown in FIG. 25, during the discharge control period, the control mechanism 10 outputs the head control signal DI, which includes the setting information PA33-PA00 and PB33-PB00 constituting the setting information signal SP, to the selection control circuit 210. In this case, the setting information signal SP is 32 bits. The setting information PA33-PA00 is setting information for setting a rule for selecting the drive waveform Adp10 to be applied to the piezoelectric element 60 from the drive signal COMA, and the setting information PB33-PB00 is setting information for setting a rule for selecting the drive waveform Bdp10 to be applied to the piezoelectric element 60 from the drive signal COMB. Here, the setting information signal SP, which includes the setting information PA33-PA00 and the setting information PB33-PB00, is an example of a setting information signal group.

[0173] Specifically, setting information in which the setting information PA33, PA32, PA32, and PA31 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA23, PA22, PA21, and PA20 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA13, PA12, PA11, and PA10 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which the setting information PA03, PA02, PA01, and PA00 are "0", "1", "0", and "1", respectively, is output to the selection control circuit 210.

[0174] Therefore, the selection control signal generating unit 262 included in the control logic circuit 260 of the selection control circuit 210 generates the selection signals Qa1 to Qa4 based on the setting information PA, and outputs them to the decoder 226. Specifically, the selection control circuit 210 generates the selection signal Qa1 [PA00, PA01, PA02, PA03] = [1, 0, 1, 0], the selection signal Qa2 [PA10, PA11, PA12, PA13] = [0, 0, 0, 0], the selection signal Qa3 [PA20, PA21, PA22, PA23] = [0, 0, 0, 0], and the selection signal Qa4 [PA30, PA31, PA32, PA33] = [0, 0, 0, 0], and outputs them to the decoder 226.

[0175] Similarly, setting information in which setting information PB33, PB32, PB32, and PB31 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which setting information PB23, PB22, PB21, and PB20 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, setting information in which setting information PB13, PB12, PB11, and PB10 are "0", "0", "0", and "0", respectively, is output to the selection control circuit 210. Thereafter, The setting information, which are “1”, “0”, “1”, and “0”, respectively, are output to the selection control circuit 210.

[0176] Therefore, the selection control signal generating unit 262 included in the control logic circuit 260 of the selection control circuit 210 generates selection signals Qb1 to Qb4 based on the setting information PB, and outputs them to the decoder 226. Specifically, the selection control circuit 210 generates a selection signal Qb1 [PB00, PB01, PB02, PB03] = [0, 1, 0, 1], a selection signal Qb2 [PB10, PB11, PB12, PB13] = [0, 0, 0, 0], a selection signal Qb3 [PB20, PB21, PB22, PB23] = [0, 0, 0, 0], and a selection signal Qb4 [PB30, PB31, PB32, PB33] = [0, 0, 0, 0], and outputs them to the decoder 226.

[0177] Here, the setting information signal SP is set so that the bit data of the setting information PA00-PA03 and the setting information PB00-PB03 are inverted, and therefore the bit data of the selection signal Qb1 and the selection signal Qa2 are inverted. Note that the setting information PA00-PA03 is an example of a first setting information signal, and the setting information PB00-PB03 is an example of a second setting information signal.

[0178] Fig. 26 is a diagram showing the decoded contents in the decoder 226 of the selection control circuit 210 during the discharge control period. As shown in Fig. 26, the decoder 226 outputs a selection signal Sa corresponding to the discharge data [SIH, SIL]. Note that in the binary mode of the second embodiment, the dot formation period T is not regulated by the change signal CHA, so the selection signal Qa1 is selected.

[0179] Specifically, during the dot formation period T, the decoder 226 of the selection control circuit 210 outputs an H level when ejection data [SIH,SIL]=[0,0] is input, outputs an L level when ejection data [SIH,SIL]=[0,1] is input, outputs an H level when ejection data [SIH,SIL]=[1,0] is input, and outputs an L level when ejection data [SIH,SIL]=[1,1] is input.

[0180] Fig. 27 is a diagram showing the decoded contents in the decoder 226 of the selection control circuit 210 during the discharge control period. As shown in Fig. 27, the decoder 226 outputs a selection signal Sb corresponding to the discharge data [SIH, SIL]. Note that in the binary mode of the second embodiment, the dot formation period T is not regulated by the change signal CHB, so the selection signal Qb1 is selected.

[0181] Specifically, during the dot formation period T, the decoder 226 of the selection control circuit 210 outputs an L level when ejection data [SIH,SIL]=[0,0] is input, outputs an H level when ejection data [SIH,SIL]=[0,1] is input, outputs an L level when ejection data [SIH,SIL]=[1,0] is input, and outputs an H level when ejection data [SIH,SIL]=[1,1] is input.

[0182] Fig. 28 is a diagram for explaining the operation of the selection circuit 230 when the selection signals Sa and Sb shown in Fig. 26 and 27 are supplied. The transfer gates 234a and 234b are turned ON or OFF according to the selection signals Sa and Sb supplied according to the ejection data [SIH, SIL].

[0183] Specifically, when [SIH, SIL]=[0, 0], the transfer gate 234a is ON and the transfer gate 234b is OFF. In this case, the drive waveform Adp10 is supplied to VOUT, and the vicinity of the nozzle 651 only vibrates slightly, and ink is not ejected from the nozzle 651. Therefore, no dots are formed on the medium P.

[0184] Furthermore, when the ejection data [SIH, SIL] = [0, 1], the transfer gate 234a is turned OFF and the transfer gate 234b is turned ON. In this case, the drive waveform Bdp10 is supplied to VOUT, and a medium amount of ink is ejected once from the nozzle 651 and lands on the medium P. Therefore, a dot is formed on the medium P.

[0185] Furthermore, when [SIH, SIL]=[1, 0], the transfer gate 234a is ON and the transfer gate 234b is OFF. In this case, the drive waveform Adp10 is supplied to VOUT, and only the vicinity of the nozzle 651 vibrates slightly, and no ink is ejected from the nozzle 651. Therefore, no dots are formed on the medium P.

[0186] Furthermore, when the ejection data [SIH, SIL]=[1,1], the transfer gate 234a is turned OFF and the transfer gate 234b is turned ON. In this case, the drive waveform Bdp10 is supplied to VOUT, and a medium amount of ink is ejected once from the nozzle 651 and lands on the medium P. Therefore, a dot is formed on the medium P.

[0187] As described above, in the binary mode of the second embodiment, the setting information signal SP is set so that the bit data of the selection signal Qa1 and the selection signal Qb1 are inverted, and therefore printing in the binary mode can be performed according to the value of the ejection data [SIL] regardless of the value of the ejection data [SIH]. Specifically, when [SIL]=[0], ink is not ejected from the nozzle 651, so no dots are formed on the medium P, and when the ejection data [SIL]=[1], ink is ejected from the nozzle 651, and dots are formed on the medium P. The ejection data [SIL] is an example of a first ejection control signal.

[0188] That is, in the binary mode of the second embodiment, the head control signal DI does not need to include the ejection data [SIH]. Because the data size of the head control signal DI can be reduced, the dot formation period T, which corresponds to the printing period, can be shortened compared to the case of the multi-tone mode.

[0189] The data size of the ejection data [SIH] increases in proportion to the number of nozzles 651, so the data size of the ejection data [SIH] that can be omitted increases as the number of nozzles 651 increases. In other words, the effect of shortening the printing cycle increases as the number of nozzles 651 increases.

[0190] For example, when the number of nozzles 651 is 400, the data size of the ejection data [SIH] is 400 bits, and when the number of nozzles 651 is 800, the data size of the ejection data [SIH] is 800 bits. Therefore, when the number of nozzles 651 is 800, the data size of the omittable ejection data [SIH] is 400 bits more than when the number of nozzles 651 is 400.

[0191] In the second embodiment, the multi-tone mode and the binary mode can be executed with the same hardware configuration, so that the user can arbitrarily switch between the modes, expanding the range of use.

[0192] In the second embodiment, in both the multi-tone mode and the binary mode, the selection signals Qa1 to Qa4 and the selection signals Qb1 to Qb4 are generated based on a 32-bit setting information signal SP. In the binary mode, the selection signals Qa1, Qa2 and the selection signals Qb1, Qb2 may be generated based on a 16-bit setting information signal SP. The data size of the head control signal DI is reduced, and the printing cycle can be shortened.

[0193] In addition, in the binary mode of the second embodiment, the ejection of ink from the nozzle 651 is controlled using four drive waveforms Adp1, Adp2, Bdp1, and Bdp2. However, for example, the same effect as that obtained in the binary mode of the present embodiment can be obtained by using only Adp1. That is, instead of slightly vibrating the nozzle 651, the transfer gate 234 may be turned OFF so that dots are not formed on the medium P. When there is only one drive waveform, the dot formation period T does not need to be determined by the change signal CH, and therefore the printing period can be further shortened.

[0194] 9. Third embodiment A liquid ejection device 1 in the third embodiment will be described. In describing the liquid ejection device 1 in the third embodiment, the same components as those in the liquid ejection device 1 in the first embodiment will be denoted by the same reference numerals, and the description thereof will be omitted or simplified.

[0195] 29 is a diagram showing the configuration of the selection control circuit 210 in the third embodiment. Head control signals DIa and DIb are input to the selection control circuit 210 in the third embodiment.

[0196] Here, the details of the head control signals DIa, DIb including the ejection control signal SI and the setting information signal SP will be described with reference to Fig. 30. Fig. 30 is a diagram showing an example of the data configuration of the head control signals DIa, DIb. As shown in Fig. 30, the head control signal DIa includes an ejection control signal SI and a setting information signal SP, and the ejection control signal SI includes middle ejection data SIM and lower ejection data SIL. The head control signal DIb includes an ejection control signal SI and a setting information signal SP, and the ejection control signal SI includes dummy data D1 to Dn and upper ejection data SIH.

[0197] Specifically, the ejection control signal SI is a signal that includes three bits of data, namely, upper ejection data SIH, middle ejection data SIM, and lower ejection data SIL, for controlling the driving of the piezoelectric element 60 included in the ejection section 600, corresponding to each of the n ejection sections 600.

[0198] In detail, the ejection control signal SI included in the head control signal DIa includes n-bit medium-level ejection data SIM serially in the order of medium-level ejection data SIM corresponding to ejection section 600[n], medium-level ejection data SIM corresponding to ejection section 600[n-1], ..., medium-level ejection data SIM corresponding to ejection section 600[1], and after the medium-level ejection data SIM, includes n-bit lower-level ejection data SIL serially in the order of lower-level ejection data SIL corresponding to ejection section 600[n], lower-level ejection data SIL corresponding to ejection section 600[n-1], ..., lower-level ejection data SIL corresponding to ejection section 600[1].

[0199] On the other hand, the ejection control signal SI included in the head control signal DIb includes n-bit dummy data D1 to Dn, followed by n-bit upper ejection data SIH, which are serially arranged in the order of the upper ejection data SIH corresponding to the ejection unit 600[n], the upper ejection data SIH corresponding to the ejection unit 600[n-1], ..., the upper ejection data SIH corresponding to the ejection unit 600[1]. Note that since the dummy data D1 to Dn are held in the dummy register 222d and are invalid, the logical level of the dummy data D1 to Dn may be either H level or L level.

[0200] Fig. 31 is a diagram showing the decoded contents of the decoder 226. As shown in Fig. 31, the decoder 226 outputs a logic level defined by the selection signal Q1 [PA00, PA01, PA02, PA03, PA04, PA05, PA06, PA07] as the selection signal S during a period T1, outputs a logic level defined by the selection signal Q2 [PA10, PA11, PA12, PA13, PA14, PA15, PA16, PA17] as the selection signal S during a period T2, outputs a logic level defined by the selection signal Q3 [PA20, PA21, PA22, PA23, PA24, PA25, PA26, PA27] as the selection signal S during a period T3, and outputs a logic level defined by the selection signal Q4 [PA30, PA31, PA32, PA33, PA34, PA35, PA36, PA37] as the selection signal S during a period T4.

[0201] Returning to Fig. 29, the control logic circuit 260 includes a first SP register group 261a, a second SP register group 261b, and a selection control signal generator 262. The first SP register group 261a includes a plurality of registers connected in series, and constitutes a so-called shift register that propagates the head control signal DIa, which is input in synchronization with the clock signal SCK, to the registers in the subsequent stages in sequence. When the supply of the clock signal SCK is stopped, the first SP register group 261a holds the setting information PA00 to PA17 included in the setting information signal SP, among the head control signal DIa.

[0202] The second SP register group 261b includes a plurality of serially connected registers, and constitutes a so-called shift register that propagates the head control signal DIb, which is input in synchronization with the clock signal SCK, to the registers in the subsequent stages in sequence. When the supply of the clock signal SCK stops, the second SP register group 261b holds the setting information PB00 to PB17 included in the setting information signal SP, among the head control signals DIb.

[0203] The selection control signal generation unit 262 latches the setting information PA00 to PA17 held in the first SP register group 261a and the setting information PB00 to PB17 held in the second SP register group 261b at the rising edge of the latch signal LAT, and generates selection signals Q1 to Q4 that specify the logical level of the selection signal S output from the selection control circuit 210.

[0204] Specifically, a selection signal Q1 is generated by translating the latched setting information PA00 to PA07, a selection signal Q2 is generated by translating the latched setting information PA10 to PA17, a selection signal Q3 is generated by translating the latched setting information PB00 to PB07, and a selection signal Q4 is generated by translating the latched setting information PB10 to PB17, and these are output to the decoders 226 possessed by each of the n selection signal output units 270.

[0205] The selection control circuit 210 includes a first register 222a, a second register 222b, a third register 222c, and a dummy register 222d.

[0206] The second register 222b included in each of the n selection signal output units 270 is connected in series to the rear stage of the first SP register group 261a including a plurality of registers, and the first register 222a included in each of the n selection signal output units 270 is connected in series to the rear stage of the n serially connected second registers 222b. The third register 222c included in each of the n selection signal output units 270 is connected in series to the rear stage of the second SP register group 261b including a plurality of registers, and the dummy register 222d is connected to the rear stage of the n serially connected third registers.

[0207] Here, the data size that can be held in the first SP register group 261a is an example of a first data size, the data size that can be held in the second register 222b is a second data size, and the data size that can be held in the first register 222a is a third data size. Also, the data size that can be held in the second SP register group 261b is an example of a fourth data size, the data size that can be held in the third register 222c is a fifth data size, and the data size that can be held in the dummy register 222d is a sixth data size.

[0208] The second register 222b and the first register 222a form a shift register. The head control signal DIa input to the first SP register group 261a is propagated to the second register 222b and then the first register 222a in synchronization with the clock signal SCK. After that, the supply of the clock signal SCK is stopped, so that the second register 222b holds the low-level ejection data SIL and the first register 222a holds the medium-level ejection data SIM.

[0209] The third register 222c and the dummy register 222d form a shift register. The head control signal DIb input to the second SP register group 261b is propagated to the subsequent stages in the order of the third register 222c and the dummy register 222d in synchronization with the clock signal SCK. After that, the supply of the clock signal SCK is stopped, so that the third register 222c holds the high-order ejection data SIH, and the dummy register 222d holds the dummy data D1 to Dn included in the ejection control signal SI.

[0210] The head control signal DIa is an example of head control data. The wiring A that transmits the head control signal DIa to the first SP register group 261a, the second register 222b, and the first register 222a is an example of the first wiring. The first SP register group 261a is an example of the first region, the second register 222b is an example of the second region, and the first register 222a is an example of the third region. The head control signal DI held in the first SP register group 261a is an example of the first head control data, the head control signal DI held in the second register 222b is an example of the second head control data, and the head control signal DI held in the first register 222a is an example of the third head control data. The register in which the first SP register group 261a, the second register 222b, and the first register 222a are successively arranged is an example of the first shift register.

[0211] The head control signal DIb is an example of head control data. The wiring B that transmits the head control signal DIb to the second SP register group 261b, the third register 222c, and the dummy register 222d is an example of a third wiring. The second SP register group 261b is an example of a fourth region, the third register 222c is an example of a fifth region, and the dummy register 222d is an example of a sixth region. The head control signal DI held in the second SP register group 261b is an example of fourth head control data, the head control signal DI held in the third register 222c is an example of fifth head control data, and the head control signal DI held in the dummy register 222d is an example of sixth head control data. The register in which the second SP register group 261b, the second register 222b, and the first register 222a are successively arranged is an example of a second shift register.

[0212] The middle ejection data SIM held in the first register 222a is latched by the corresponding first latch circuit 224a at the rising edge of the latch signal LAT, the lower ejection data SIL held in the second register 222b is latched by the corresponding second latch circuit 224b at the rising edge of the latch signal LAT, and the upper ejection data SIH held in the third register 222c is latched by the corresponding third latch circuit 224c at the rising edge of the latch signal LAT. The dummy data D1 to Dn included in the ejection control signal SI held in the dummy register 222d becomes invalid data.

[0213] The first latch circuit 224a outputs the latched middle-level ejection data SIM as latched data LTb to the decoder 226. The second latch circuit 224b outputs the latched lower-level ejection data SIL as latched data LTc to the decoder 226. The third latch circuit 224c outputs the latched upper-level ejection data SIH to the decoder 226 as latched data LTa.

[0214] 10. Multi-tone mode in the third embodiment FIG. 32 is a diagram showing an example of the latch signal LAT, change signal CH, clock signal SCK, head control signals DIa, DIb, and drive signal COM input to the selection control circuit 210 in the multi-tone mode of the third embodiment. Here, an example is shown in which the drive signal COM includes four types of drive waveforms, and the dot formation cycle T is defined into four periods T1 to T4 by three change signals CH. Note that the multi-tone mode is one of the first printing modes. Here is an example.

[0215] The drive waveform dp3 is a waveform for ejecting a small amount of ink from the nozzle 651, and the drive waveform dp2 is a waveform for ejecting a medium amount of ink, which is more than a small amount, from the nozzle 651. The drive waveform dp1 is a waveform for ejecting a large amount of ink, which is more than a medium amount, from the nozzle 651. Moreover, dp4 is a waveform that does not eject ink from the nozzle 651, and is a waveform that slightly vibrates the ink near the opening of the nozzle 651 to prevent an increase in ink viscosity.

[0216] 33 is a diagram showing an example of head control signals DIa, DIb output by the control mechanism 10 during the ejection control period in the multi-tone mode of the third embodiment. Here, the ejection control signals SI included in the head control signals DIa, DIb are signals that define the amount of ink ejected for each of the n nozzles 651, and the logical level changes appropriately during the ejection control period. That is, the ejection data [SIH, SIM, SIL] included in the ejection control signals SI are either 0 or 1 depending on the amount of ink ejected from the corresponding nozzles 651 in the dot formation cycle T. Also, the dummy data D1 to Dn of the ejection control signals SI can be either 0 or 1, since they are held in the dummy register 222d and become invalid data.

[0217] 33, during the discharge control period, the control mechanism 10 outputs a head control signal DIa including setting information PA37-PA20 constituting the setting information signal SP to the selection control circuit 210, and outputs a head control signal DIb including setting information PA17-PA00 to the selection control circuit 210. In this case, the setting information signal SP is 32 bits. Here, the setting information signal SP including the setting information PA37-PA20 and the setting information PA17-PA00 is an example of a setting information signal group.

[0218] Fig. 34 is a diagram showing the decoded contents in the decoder 226 of the selection control circuit 210 during the discharge control period. As shown in Fig. 34, the decoder 226 outputs a selection signal S corresponding to the discharge data [SIH, SIM, SIL].

[0219] Specifically, setting information in which the setting information PA37, PA36, PA35, PA34, PA33, PA32, PA31, and PA30 held in the first SP register group 261a are each "0", "0", "0", "0", "0", "0", "0", and "1" is output to the selection control circuit 210, and setting information in which the setting information PA27, PA26, PA25, PA24, PA23, PA22, PA21, and PA20 are each "1", "0", "1", "0", "1", "0", "1", and "0" is output to the selection control circuit 210.

[0220] Thereafter, setting information in which the setting information PA17, PA16, PA15, PA14, PA13, PA12, PA11, and PA10 held in the second SP register group 261b are each "1", "1", "0", "0", "1", "1", "0", and "0" is output to the selection control circuit 210, and setting information in which the setting information PA07, PA06, PA05, PA04, PA03, PA02, PA01, and PA00 are each "1", "1", "1", "1", "0", "0", "0", and "0" is output to the selection control circuit 210.

[0221] Therefore, the selection control circuit 210 includes a selection control signal generator 262 that generates selection signals Q1 to Q4 based on the setting information PA, and outputs the selection signals Q1 to Q4 to the decoder 226. Specifically, the selection control circuit 210 generates selection signals Q1 [PA00, PA01, PA02, PA03, PA04, PA05, PA06, PA07] = [0,0,0,0,1,1,1,1], selection signal Q2 [PA10, PA11, PA12, PA13, PA14, PA15, PA16, PA17] = [0,0,1,1,0,0,1,1], and selection signal Q3 [PA20, PA21, PA22, PA23, PA24, PA25, PA It generates selection signal Q3[PA30, PA31, PA32, PA33, PA34, PA35, PA36, PA37] = [1, 0, 0, 0, 0, 0, 0, 0] and outputs them to decoder 226.

[0222] During the dot formation period T, when the ejection data [SIH, SIM, SIL] = [0, 0, 0] is input, the decoder 226 of the selection control circuit 210 outputs a selection signal S of L level in period T1, L level in period T2, L level in period T3, and H level in period T4, and when the ejection data [SIH, SIM, SIL] = [0, 0, 1] is input, the decoder 226 outputs a selection signal S of L level in period T1, L level in period T2, H level in period T3, and L level in period T4. In addition, when the ejection data [SIH, SIM, SIL] = [0, 1, 0] is input, the decoder 226 outputs a selection signal S of L level in period T1, H level in period T2, L level in period T3, and L level in period T4. When the ejection data [SIH, SIM, SIL] = [0, 1, 1] is input, the decoder 226 outputs a selection signal S of L level in period T1, H level in period T2, H level in period T3, and L level in period T4.

[0223] In addition, when the discharge data [SIH, SIM, SIL]=[1, 0, 0] is input, the decoder 226 of the selection control circuit 210 outputs a selection signal S of H level in period T1, L level in period T2, L level in period T3, and L level in period T4, and when the discharge data [SIH, SIM, SIL]=[1, 0, 1] is input, the decoder 226 outputs a selection signal S of H level in period T1, L level in period T2, H level in period T3, and L level in period T4. In addition, when the ejection data [SIH, SIM, SIL] = [1, 1, 0] is input, the decoder 226 outputs a selection signal S of H level in period T1, H level in period T2, L level in period T3, and L level in period T4. When the ejection data [SIH, SIM, SIL] = [1, 1, 1] is input, the decoder 226 outputs a selection signal S of H level in period T1, H level in period T2, H level in period T3, and L level in period T4.

[0224] Fig. 35 is a diagram for explaining the operation of the selection circuit 230 when the selection signal S shown in Fig. 34 is supplied. The transfer gate 234 is turned ON or OFF according to the selection signal S supplied according to the ejection data [SIH, SIM, SIL].

[0225] Specifically, when [SIH, SIM, SIL]=[0, 0, 0], the transfer gate 234 is OFF in period T1, OFF in period T2, OFF in period T3, and ON in period T4. Also, when the ejection data [SIH, SIL]=[0, 0, 1], the transfer gate 234 is OFF in period T1, OFF in period T2, ON in period T3, and OFF in period T4.

[0226] In addition, when the ejection data [SIH, SIM, SIL] = [0, 1, 0], the transfer gate 234 is OFF in the period T1, ON in the period T2, OFF in the period T3, and OF in the period T4. In addition, when the ejection data [SIH, SIM, SIL] = [0, 1, 1], the transfer gate 234 is OFF in the period T1, ON in the period T2, ON in the period T3, and OFF in the period T4.

[0227] In addition, when [SIH, SIM, SIL]=[1, 0, 0], the transfer gate 234 is ON in the period T1, OFF in the period T2, OFF in the period T3, and OFF in the period T4. In addition, when the ejection data [SIH, SIL]=[1, 0, 1], the transfer gate 234 is ON in the period T1. , it is turned OFF in period T2, turned ON in period T3, and turned OFF in period T4.

[0228] In addition, when the ejection data [SIH, SIM, SIL] = [1, 1, 0], the transfer gate 234 is ON in the period T1, ON in the period T2, OFF in the period T3, and OFF in the period T4. In addition, when the ejection data [SIH, SIM, SIL] = [1, 1, 1], the transfer gate 234 is ON in the period T1, ON in the period T2, ON in the period T3, and OFF in the period T4.

[0229] Here, to illustrate the gradations in the multi-gradation mode of the third embodiment, the amounts of ink ejected from the nozzle 651 by the drive waveforms dp1 to dp4 are assumed to be as follows: The amount of ink ejected from the nozzle 651 by the drive waveform dp1 is assumed to be "4", the amount of ink ejected from the nozzle 651 by the drive waveform dp2 is assumed to be "2", the amount of ink ejected from the nozzle 651 by the drive waveform dp3 is assumed to be "1", and the amount of ink ejected from the nozzle 651 by the drive waveform dp4 is assumed to be "0".

[0230] The dots formed on the medium P for each ejection data [SIH, SIM, SIL] will be described. When the ejection data [SIH, SIM, SIL] = [0, 0, 0], a constant waveform at voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 except for period T4, and a drive waveform dp4 is supplied as VOUT during period T4. In this case, only the vicinity of the nozzle 651 vibrates slightly, and no dots are formed. Therefore, the amount of ink ejected from the nozzle 651 is "0".

[0231] When the ejection data [SIH, SIM, SIL] = [0, 0, 1], a constant waveform of voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 except for the period T3. In the period T3, the drive waveform dp3 is supplied as VOUT to form a dot. Therefore, the amount of ink ejected from the nozzle 651 is "1".

[0232] When the ejection data [SIH, SIM, SIL] = [0, 1, 0], a constant waveform of voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 except for the period T2. In the period T2, the drive waveform dp2 is supplied as VOUT to form a dot. Therefore, the amount of ink ejected from the nozzle 651 is "2".

[0233] When the ejection data [SIH, SIM, SIL] = [0, 1, 1], a constant waveform of voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 except for periods T2 and T3. In period T2, drive waveform dp2 is supplied as VOUT, and in period T3, drive waveform dp3 is supplied as VOUT, forming a dot. Therefore, the amount of ink ejected from nozzle 651 is "3".

[0234] When the ejection data [SIH, SIM, SIL] = [1, 0, 0], a constant waveform of voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 except for the period T1. In the period T1, the drive waveform dp1 is supplied as VOUT to form a dot. Therefore, the amount of ink ejected from the nozzle 651 is "4".

[0235] When the ejection data [SIH, SIM, SIL] = [1, 0, 1], a constant waveform of voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 except for periods T1 and T3. In period T1, drive waveform dp1 is supplied as VOUT, and in period T3, drive waveform dp3 is supplied as VOUT, forming a dot. Therefore, the amount of ink ejected from nozzle 651 is "5".

[0236] When the ejection data [SIH, SIM, SIL] = [1, 1, 0], a constant waveform of voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 except for periods T1 and T2. In period T1, drive waveform dp1 is supplied as VOUT, and in period T2, drive waveform dp2 is supplied as VOUT, forming a dot. Therefore, the amount of ink ejected from nozzle 651 is "6".

[0237] When the ejection data [SIH, SIM, SIL] = [1, 1, 1], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T4. During period T1, drive waveform dp1 is supplied as VOUT, during period T2, drive waveform dp2 is supplied as VOUT, and during period T3, drive waveform dp3 is supplied as VOUT, forming a dot. Therefore, the amount of ink ejected from nozzle 651 is "7".

[0238] As described above, during the ejection control period, the control mechanism 10 outputs the head control signals DIa and DIb to the liquid ejection head 21, which enables the liquid ejection head 21 to form eight types of dots, including non-recording, on the medium P based on the ejection control signal SI and the setting information signal SP. This enables the liquid ejection device 1 to print in eight gradations, and form a high-definition image on the medium P. Note that the number of gradations, eight, in the multi-gradation mode of the third embodiment is an example of the first number of gradations.

[0239] 11. Binary mode in the third embodiment Fig. 36 is a diagram showing an example of the latch signal LAT, change signal CH, clock signal SCK, head control signals DIa, DIb, and drive signal COM input to the selection control circuit 210 in the binary mode of the third embodiment. Here, an example is shown in which the drive signal COM is composed of two types of drive waveforms, and a single change signal CH defines the dot formation cycle T to two periods T1 and T2. Note that other items are the same as in Fig. 6, so explanations will be omitted. Note that the binary mode is an example of the second print mode.

[0240] The driving waveform dp30 is a waveform for ejecting a medium amount of ink from the nozzle 651, and the driving waveform dp31 is a waveform for preventing ink from being ejected from the nozzle 651, and for preventing an increase in ink viscosity by slightly vibrating the ink near the opening of the nozzle 651. These two types of driving waveforms dp30 and dp31 are switched as VOUT to be supplied to the ejection section 600 to control whether or not ink is ejected from the nozzle 651. That is, the binary mode controls two states, a state in which ink is ejected from the nozzle 651 and a state in which ink is not ejected, so that the number of gradations of the formed dots is two. The number of gradations in the binary mode in the third embodiment, 2, is an example of the second number of gradations.

[0241] 37 is a diagram showing an example of head control signals DIa, DIb output by the control mechanism 10 during the ejection control period in the binary mode of the third embodiment. Here, the ejection control signals SI included in the head control signals DIa, DIb are signals that define the amount of ink ejected for each of the n nozzles 651, and the logical level changes appropriately during the ejection control period. That is, the ejection data [SIH, SIM, SIL] included in the ejection control signals SI are either 0 or 1 depending on the amount of ink ejected from the corresponding nozzles 651 in the dot formation cycle T. Also, the dummy data D1 to Dn of the ejection control signals SI can be either 0 or 1, since they are held in the dummy register 222d and become invalid data.

[0242] As shown in Fig. 37, during the discharge control period, the control mechanism 10 outputs a head control signal DIa including setting information PA37 to PA20 constituting the setting information signal SP to the selection control circuit 210, and outputs a head control signal DIb including setting information PA17 to PA00 to the selection control circuit 210. In this case, the setting information signal SP is 32 bits. Here, the setting information PA3 The setting information signal SP including the setting information PA17 to PA00 and the setting information PA7 to PA20 is an example of a setting information signal group.

[0243] Fig. 38 is a diagram showing the decoded contents in the decoder 226 of the selection control circuit 210 during the discharge control period. As shown in Fig. 34, the decoder 226 outputs a selection signal S corresponding to the discharge data [SIH, SIM, SIL].

[0244] Specifically, setting information in which the setting information PA37, PA36, PA35, PA34, PA33, PA32, PA31, and PA30 held in the first SP register group 261a are each "0", "0", "0", "0", "0", "0", "0", is output to the selection control circuit 210, and setting information in which the setting information PA27, PA26, PA25, PA24, PA23, PA22, PA21, and PA20 are each "0", "0", "0", "0", "0", "0", "0", "0", is output to the selection control circuit 210.

[0245] Thereafter, setting information in which the setting information PA17, PA16, PA15, PA14, PA13, PA12, PA11, and PA10 held in the second SP register group 261b are each "0", "1", "0", "1", "0", "1", "0", and "1" is output to the selection control circuit 210, and setting information in which the setting information PA07, PA06, PA05, PA04, PA03, PA02, PA01, and PA00 are each "1", "0", "1", "0", "1", "0", "1", and "0" is output to the selection control circuit 210.

[0246] Therefore, the selection control signal generating unit 262 included in the control logic circuit 260 of the selection control circuit 210 generates the selection signals Q1 to Q4 based on the setting information PA, and outputs them to the decoder 226. Specifically, the selection control circuit 210 generates the selection signal Q1 [PA00, PA01, PA02, PA03, PA04, PA05, PA06, PA07] = [0,1,0,1,0,1,0,1], the selection signal Q2 [PA10, PA11, PA12, PA13, PA14, PA15, PA16, PA17] = [1,0,1,0,1,0,1,0], and the selection signal Q3 [PA40, PA41, PA42, PA43, PA44, PA45, PA46, PA47] = [1,0,1,0,1,0,1,0,0]. The decoder 226 generates a selection signal Q3[PA20, PA21, PA22, PA23, PA24, PA25, PA26, PA27]=[0,0,0,0,0,0,0,0,0] and a selection signal Q4[PA30, PA31, PA32, PA33, PA34, PA35, PA36, PA37]=[0,0,0,0,0,0,0,0,0] and outputs them to the decoder 226.

[0247] Here, the setting information signal SP is set so that the bit data of the setting information PA00-PA07 and the setting information PA10-PA17 are inverted, and therefore the bit data of the selection signal Q1 and the selection signal Q2 are inverted. Here, the setting information PA00-PA07 is an example of a first setting information signal, and the setting information PA10-PA17 is an example of a second setting information signal.

[0248] During the dot formation cycle T, the decoder 226 of the selection control circuit 210 outputs a selection signal S of L level in period T1 and H level in period T2 when ejection data [SIH, SIM, SIL] = [0, 0, 0] is input, and outputs a selection signal S of H level in period T1 and L level in period T2 when ejection data [SIH, SIM, SIL] = [0, 0, 1] is input. Also, when ejection data [SIH, SIM, SIL] = [0, 1, 0] is input, the decoder 226 outputs a selection signal of L level in period T1 and H level in period T2, and when ejection data [SIH, SIM, SIL] = [0, 1, 1] is input, the decoder 226 outputs a selection signal of H level in period T1 and L level in period T2.

[0249] When the discharge data [SIH, SIM, SIL] = [1, 0, 0] is input, the selection signal is output at L level in period T1 and at H level in period T2. When the discharge data [SIH, SIM, SIL] = [1, 0, 1] is input, the selection signal is output at H level in period T1 and at H level in period T2. When the ejection data [SIH, SIM, SIL] = [1, 1, 0] is input, the selection signal is output at L level in the period T1 and at H level in the period T2, and when the ejection data [SIH, SIM, SIL] = [1, 1, 1] is input, the selection signal is output at H level in the period T1 and at L level in the period T2.

[0250] Fig. 39 is a diagram for explaining the operation of the selection circuit 230 when the selection signal S shown in Fig. 38 is supplied. The transfer gate 234 is turned ON or OFF according to the selection signal S supplied according to the ejection data [SIH, SIM, SIL].

[0251] Specifically, when [SIH, SIM, SIL]=[0, 0, 0], the transfer gate 234 is turned OFF in period T1 and turned ON in period T2. When the ejection data [SIH, SIL]=[0, 0, 1], the transfer gate 234 is turned ON in period T1 and turned OFF in period T2.

[0252] In addition, when the ejection data [SIH, SIM, SIL] = [0, 1, 0], the transfer gate 234 is turned OFF in the period T1 and turned ON in the period T2. In addition, when the ejection data [SIH, SIM, SIL] = [0, 1, 1], the transfer gate 234 is turned ON in the period T1 and turned OFF in the period T2.

[0253] In addition, when [SIH, SIM, SIL]=[1, 0, 0], the transfer gate 234 is turned OFF in the period T1 and turned ON in the period T2. In addition, when the ejection data [SIH, SIL]=[1, 0, 1], the transfer gate 234 is turned ON in the period T1 and turned OFF in the period T2.

[0254] In addition, when the ejection data [SIH, SIM, SIL] = [1, 1, 0], the transfer gate 234 is turned OFF in the period T1 and turned ON in the period T2. In addition, when the ejection data [SIH, SIM, SIL] = [1, 1, 1], the transfer gate 234 is turned ON in the period T1 and turned OFF in the period T2.

[0255] Next, the dots formed on the medium P for each ejection data [SIH, SIM, SIL] will be described. When the ejection data [SIH, SIM, SIL]=[0,0,0], a constant waveform at voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T1, and a drive waveform dp31 is supplied as VOUT during period T2. In this case, only the vicinity of the nozzle 651 vibrates slightly, and ink is not ejected from the nozzle 651. Therefore, no dots are formed on the medium P.

[0256] When the ejection data [SIH, SIM, SIL] = [0, 0, 1], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T2, and a drive waveform dp30 is supplied as VOUT during period T1. In this case, a medium amount of ink is ejected once from the nozzle 651 and lands on the medium P. Therefore, a dot is formed on the medium P.

[0257] When the ejection data [SIH, SIM, SIL] = [0, 1, 0], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T1, and the drive waveform dp31 is supplied as VOUT during period T2. In this case, only the vicinity of the nozzle 651 vibrates slightly, and ink is not ejected from the nozzle 651. Therefore, no dots are formed on the medium P.

[0258] When the discharge data [SIH, SIM, SIL] = [0, 1, 1], the corresponding piezoelectric element 6 At time T0, a constant waveform with voltage Vc is supplied as VOUT during period T2, and a driving waveform dp30 is supplied as VOUT during period T1. In this case, a medium amount of ink is ejected once from nozzle 651 and lands on medium P. Therefore, a dot is formed on medium P.

[0259] When the ejection data [SIH, SIM, SIL] = [1, 0, 0], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T1, and the drive waveform dp31 is supplied as VOUT during period T2. In this case, only the vicinity of the nozzle 651 vibrates slightly, and ink is not ejected from the nozzle 651. Therefore, no dots are formed on the medium P.

[0260] When the ejection data [SIH, SIM, SIL] = [1, 0, 1], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T2, and a drive waveform dp30 is supplied as VOUT during period T1. In this case, a medium amount of ink is ejected once from the nozzle 651 and lands on the medium P. Therefore, a dot is formed on the medium P.

[0261] When the ejection data [SIH, SIM, SIL] = [1, 1, 0], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T1, and a drive waveform dp31 is supplied as VOUT during period T2. In this case, only the vicinity of the nozzle 651 vibrates slightly, and ink is not ejected from the nozzle 651. Therefore, no dots are formed on the medium P.

[0262] When the ejection data [SIH, SIM, SIL] = [1, 1, 1], a constant waveform with voltage Vc is supplied as VOUT to the corresponding piezoelectric element 60 during period T2, and a drive waveform dp30 is supplied as VOUT during period T1. In this case, a medium amount of ink is ejected once from the nozzle 651 and lands on the medium P. Therefore, a dot is formed on the medium P.

[0263] As described above, in the binary mode of the third embodiment, the setting information signal SP is set so that the bit data of the selection signal Q1 and the selection signal Q2 are inverted, and therefore printing in the binary mode can be performed according to the value of the ejection data [SIL] regardless of the values ​​of the ejection data [SIH] and the ejection data [SIM]. Specifically, when [SIL]=[0], ink is not ejected from the nozzle 651, so that no dots are formed on the medium P, and when the ejection data [SIL]=[1], ink is ejected from the nozzle 651, and dots are formed on the medium P. The ejection data [SIL] is an example of a first ejection control signal, and the ejection data [SIH] is an example of a second ejection control signal.

[0264] That is, in the binary mode of the third embodiment, the head control signals DIa and DIb do not need to include the ejection data [SIH] and the ejection data [SIM]. Since the data size of the head control signals DIa and DIb can be reduced, the dot formation period T, which corresponds to the printing period, can be shortened compared to the case of the multi-tone mode.

[0265] In the binary mode of the third embodiment, the ejection data [SIH] and the ejection data [SIM] are not included in the head control signals DIa and DIb, so that the ejection control signal SI can be made smaller than in the binary mode of the first embodiment, and therefore the printing cycle can be made shorter.

[0266] In addition, in the third embodiment, the multi-tone mode and the binary mode can be executed with the same hardware configuration, so that the user can arbitrarily switch between the modes, thereby expanding the range of use of the liquid ejection device 1. do.

[0267] In the third embodiment, in both the multi-tone mode and the binary mode, the selection signals Q1 to Q4 are generated based on a 32-bit setting information signal SP. In the binary mode of the third embodiment, the selection signals Q1 and Q2 may be generated based on a 16-bit setting information signal SP. The data size of the head control signals DIa and DIb is reduced, and the printing cycle can be shortened.

[0268] Furthermore, in the binary mode of the third embodiment, the ejection of ink from the nozzle 651 is controlled using two drive waveforms, dp30 and dp31, but the same effect as that obtained in the binary mode of this embodiment can be obtained using only dp30. That is, instead of micro-vibrating the nozzle 651, it is also possible to control so that dots are not formed on the medium P by turning off the transfer gate 234. Furthermore, when there is one drive waveform, it is not necessary to define the dot formation period T by the change signal CH, and therefore the printing period can be further shortened.

[0269] 12.Effects As described above, the liquid ejection device 1 in this embodiment can print in multi-tone mode and binary mode with the same hardware configuration. This allows the user to freely switch between multi-tone mode and binary mode, expanding the range of use.

[0270] In the binary mode of the first embodiment, the setting information PA included in the setting information signal SP is set so that the bit data of the selection signal Q1 and the selection signal Q2 are inverted. Therefore, printing in the binary mode can be performed according to the value of the ejection data [SIL] regardless of the value of the ejection data [SIH]. Specifically, when [SIL]=[0], ink is not ejected from the nozzle 651, so no dots are formed on the medium P, and when the ejection data [SIL]=[1], ink is ejected from the nozzle 651, and two-tone printing is performed.

[0271] That is, in the binary mode of the first embodiment, the head control signal DI does not need to include all or part of the ejection data [SIH]. This makes it possible to reduce the data size of the head control signal DI, and therefore makes it possible to shorten the dot formation period T, which corresponds to the printing period, compared to the case of the multi-tone mode.

[0272] In the binary mode of the second embodiment, the setting information PA and PB included in the setting information signal SP are set so that the bit data of the selection signals Qa1 and Qb1 are inverted, and therefore printing in the binary mode can be performed according to the value of the ejection data [SIL] regardless of the value of the ejection data [SIH]. Specifically, when [SIL]=[0], ink is not ejected from the nozzle 651, so no dots are formed on the medium P, and when the ejection data [SIL]=[1], ink is ejected from the nozzle 651, and two-level printing is performed.

[0273] That is, in the binary mode of the second embodiment, the head control signal DI does not need to include all or part of the ejection data [SIH]. This allows the data size of the head control signal DI to be reduced, and therefore the printing cycle becomes shorter than in the multi-tone mode.

[0274] In the binary mode of the third embodiment, the setting information PA included in the setting information signal SP is set so that the bit data of the selection signals Q1 and Q2 are inverted, so printing in the binary mode can be performed according to the value of the ejection data [SIL] regardless of the values ​​of the ejection data [SIH] and the ejection data [SIM]. Specifically, when [SIL]=[0], ink is not ejected from the nozzle 651, so no dots are formed on the medium P, and the ejection data [ SIL=[1], ink is ejected from nozzle 651, and two-tone printing is performed.

[0275] That is, in the binary mode of the third embodiment, the head control signals DIa and DIb do not need to include all or part of the ejection data [SIH] and the ejection data [SIM]. This allows the data size of the head control signals DIa and DIb to be reduced, and therefore the printing cycle is shorter than in the multi-tone mode.

[0276] The data size of the ejection data [SIH, SIM] increases in proportion to the number of nozzles 651, so the data size of the ejection data [SIH, SIM] that can be omitted increases as the number of nozzles 651 increases. In other words, the effect of shortening the printing cycle increases as the number of nozzles 651 increases.

[0277] For example, when the number of nozzles 651 is 400, the data size of the ejection data [SIH, SIM] is 800 bits, and when the number of nozzles 651 is 800, the data size of the ejection data [SIH, SIM] is 1600 bits. Therefore, when the number of nozzles 651 is 800, the data size of the omissible ejection data [SIH, SIM] is 800 bits more than when the number of nozzles 651 is 400.

[0278] In the third embodiment, the multi-tone mode and the binary mode can be executed using the same hardware configuration, so that the user can arbitrarily switch between the modes, expanding the range of use.

[0279] In the third embodiment, in both the multi-tone mode and the binary mode, the selection signals Q1 to Q4 are generated based on a 32-bit setting information signal SP. In the binary mode, the selection signals Q1 and Q2 may be generated based on a 16-bit setting information signal SP. This reduces the data size of the head control signal DI, allowing the printing cycle to be shortened.

[0280] In addition, in the binary mode of this embodiment, the ejection of ink from the nozzle 651 is controlled using two drive waveforms, dp30 and dp31, but the same effect as that obtained in the binary mode of this embodiment can be obtained using only dp30. That is, by turning off the transfer gate 234, control may be performed so that the nozzle 651 is not vibrated slightly and dots are not formed on the medium P. When there is one drive waveform, the dot formation period T does not need to be determined by the change signal CH, and therefore the printing period can be further shortened.

[0281] Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments, and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiments can be appropriately combined.

[0282] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods and results, or configurations with the same purpose and effect). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0283] The following can be derived from the above-described embodiment and modified examples.

[0284] One aspect of the liquid ejection device is a first shift register including a first area capable of holding data of a first data size, a second area capable of holding data of a second data size, and a third area capable of holding data of a third data size, all of which are arranged in succession; a plurality of ejection units capable of ejecting droplets based on the head control data held in the first shift register; a first wiring for transmitting the head control data to the first shift register; a first print mode in which the droplets are ejected from the plurality of ejection sections based on the head control data to perform printing with a first number of gradations; a second print mode in which the droplets are ejected from the plurality of ejection sections based on the head control data, and printing is performed with a second number of gradations that is lower than the first number of gradations, In the first printing mode, a data size of the head control data is a sum of the first data size, the second data size, and the third data size, In the second printing mode, The data size of the head control data is the sum of the first data size and the second data size.

[0285] According to this liquid ejection device, printing can be performed at a second number of gradations that is lower than the first number of gradations, depending on the data size of the head control data. In the first printing mode, the data size of the head control data is set to be the sum of the first data size, the second data size, and the third data size, and in the second printing mode, the data size of the head control data is set to be the sum of the first data size and the second data size, so that the data size of the head control data in the second printing mode is smaller than the data size of the head control data in the first printing mode. Therefore, in the second printing mode, the time required for the head control data to be transmitted to the first shift register is shorter than in the first printing mode. This makes it possible to make the printing time in the second printing mode shorter than the printing time in the first printing mode.

[0286] In one aspect of the liquid ejection device, a second wiring for transmitting a drive signal including a drive waveform; In the first printing mode, performing printing by supplying the drive waveforms to the plurality of ejection sections in accordance with the first head control data stored in the first area, the second head control data stored in the second area, and the third head control data stored in the third area; In the second printing mode, A liquid ejection device characterized in that printing is performed by supplying the ejection pulse to the multiple ejection sections in accordance with the first head control data and the second head control data, regardless of the third head control data.

[0287] According to this liquid ejection device, In the first printing mode, printing is performed based on the first head control data, the second head control data, and the third head control data, but in the second printing mode, unlike the first printing mode, printing is performed without relying on the third head control data, thereby making it possible to shorten the printing time.

[0288] In one aspect of the liquid ejection device, A printing cycle in the second printing mode may be shorter than a printing cycle in the first printing mode.

[0289] According to this liquid ejection device, the printing cycle in the second printing mode is shorter than the printing cycle in the first printing mode, so high speed printing is possible in the second printing mode.

[0290] In one aspect of the liquid ejection device, the first printing mode is a multi-tone mode, The second print mode may be a binary mode.

[0291] According to this liquid ejection device, the first print mode may be a multi-tone mode with three or more gradations, and the second print mode may be a binary mode with two gradations. By selecting the multi-tone mode when priority is given to image quality, and selecting the binary mode when priority is given to printing speed, the user can arbitrarily switch between modes, expanding the range of use.

[0292] In one aspect of the liquid ejection device, a second shift register including a fourth area capable of holding data of a fourth data size and a fifth area capable of holding data of a fifth data size, the second shift register being arranged in succession; The recording medium may include a third wiring that transmits the fourth head control data held in the fourth area and the fifth head control data held in the fifth area.

[0293] According to this liquid ejection device, the number of gradations of the dots formed is controlled by the first head control data, the second head control data, and the third head control data transmitted by the first wiring, and the fourth head control data and fifth head control data transmitted by the third wiring, making it possible to print at a higher number of gradations in the first printing mode.

[0294] In one aspect of the liquid ejection device, In the second print mode, printing is performed based on the first head control data and the second head control data transmitted through the first wiring; In the first printing mode, the printing may be based on the first head control data transmitted through the first wiring, the second head control data, the third head control data, the fourth head control data transmitted through the third wiring, and fifth head control data.

[0295] According to this liquid ejection device, in the first print mode, the number of gradations is controlled by the first head control data, the second head control data, the third head control data, the fourth head control data, and the fifth head control data, so that the number of gradations in the first print mode can be increased. Also, in the second print mode, the third head control data, the fourth head control data, and the fifth head control data are not required in the first print mode. Therefore, the second print mode can have a shorter printing time than the first print mode.

[0296] In one aspect of the liquid ejection device, The plurality of discharge parts may include 800 or more discharge parts.

[0297] According to this liquid ejection device, the ejection control signals control the gradations of 800 or more dots formed by ejecting droplets from 800 or more ejectors, and so the data size becomes very large. Since the difference in printing time between the first and second printing modes is proportional to the data size of the head control signals, the greater the number of ejectors, the greater the effect of shortening the printing time in the second mode. [Explanation of symbols]

[0298] 1...liquid ejection device, 2...ink container, 10...control mechanism, 20...carriage, 21...liquid ejection head, 30...movement mechanism, 31...carriage motor, 32...endless belt, 40...transport mechanism, 41...transport motor, 42...transport roller, 50...drive circuit, 51...drive signal output circuit, 52...reference voltage signal output circuit, 60...piezoelectric element, 90...linear encoder, 1 00... control circuit, 200... drive signal selection circuit, 210... selection control circuit, 222a... first register, 222b... second register, 222c... third register, 222d... dummy register, 224a... first latch circuit, 224b... second latch circuit, 224c... third latch circuit, 226... decoder, 230... selection circuit, 232... inverter, 232a... inverter, 232b... inverter, 234... transfer gate, 234a... Sphergate, 234b...transfer gate, 260...control logic circuit, 261...SP register group, 261a...first SP register group, 261b...second SP register group, 262...selection control signal generation unit, 270...selection signal output unit, 600...ejection unit, 601...piezoelectric body, 611...electrode, 612...electrode, 621...vibration plate, 631...cavity, 632...nozzle plate, 641...reservoir, 651...nozzle, 661...supply port, P...medium

Claims

1. a first shift register including a first region capable of holding data of a first data size, a second region capable of holding data of a second data size, and a third region capable of holding data of a third data size, which are successively arranged; a plurality of ejection units capable of ejecting droplets based on head control data held in the first shift register; a first wiring for transmitting the head control data to the first shift register; a second wiring for transmitting a drive signal including a drive waveform; a first print mode in which the droplets are ejected from the plurality of ejection sections based on the head control data to perform printing with a first number of gradations; a second print mode in which the droplets are ejected from the plurality of ejection sections based on the head control data, and printing is performed with a second number of gradations that is lower than the first number of gradations, In the first printing mode, a data size of the head control data is a sum of the first data size, the second data size, and the third data size, performing printing by supplying the drive waveforms to the plurality of ejection sections in accordance with the first head control data stored in the first area, the second head control data stored in the second area, and the third head control data stored in the third area; In the second printing mode, a data size of the head control data is a sum of the first data size and the second data size, In response to the first head control data and the second head control data, the drive waveform is supplied to the plurality of ejection sections, regardless of the third head control data, to perform printing. A liquid ejection device comprising:

2. The liquid ejection apparatus according to claim 1 , wherein a printing cycle in the second printing mode is shorter than a printing cycle in the first printing mode.

3. the first printing mode is a multi-tone mode, 3. The liquid ejection apparatus according to claim 1, wherein the second printing mode is a binary mode.

4. a second shift register including a fourth area capable of holding data of a fourth data size and a fifth area capable of holding data of a fifth data size, the second shift register being configured to be continuous with the fourth area; 4. A liquid ejection device according to claim 1, further comprising a third wiring that transmits fourth head control data held in the fourth region and fifth head control data held in the fifth region.

5. In the second print mode, printing is performed based on the first head control data and the second head control data transmitted through the first wiring; A liquid ejection device as described in claim 4, characterized in that in the first printing mode, printing is performed based on the first head control data transmitted through the first wiring, the second head control data, the third head control data, the fourth head control data transmitted through the third wiring, and the fifth head control data.

6. 6. The liquid ejection device according to claim 1, wherein the plurality of ejection units includes 800 or more ejection units.

7. A first shift register including a first region capable of holding data of a first data size, a second region capable of holding data of a second data size, and a third region capable of holding data of a third data size, all of which are connected in series; a plurality of ejection units capable of ejecting droplets based on head control data held in the first shift register; a first wiring for transmitting the head control data to the first shift register; a second wiring for transmitting a drive signal including a drive waveform; a first print mode in which the droplets are ejected from the plurality of ejection sections based on the head control data to perform printing with a first number of gradations; a second print mode in which the liquid droplets are ejected from the plurality of ejection sections based on the head control data, and printing is performed with a second number of gradations that is lower than the first number of gradations, In the first printing mode, a data size of the head control data is a sum of the first data size, the second data size, and the third data size, performing printing by supplying the drive waveforms to the plurality of ejection sections in accordance with the first head control data stored in the first area, the second head control data stored in the second area, and the third head control data stored in the third area; In the second printing mode, a data size of the head control data is a sum of the first data size and the second data size, In response to the first head control data and the second head control data, the drive waveform is supplied to the plurality of ejection sections, regardless of the third head control data, to perform printing. A liquid ejection head comprising:

8. The liquid ejection head of claim 7, wherein the printing period in the second printing mode is shorter than the printing period in the first printing mode.

9. The first printing mode is a multi-tone mode, 9. The liquid ejection head according to claim 7, wherein the second printing mode is a binary mode.

10. A second shift register including a fourth region capable of holding data of a fourth data size and a fifth region capable of holding data of a fifth data size, the second shift register being configured to be continuous with each other; 10. A liquid ejection head according to claim 7, further comprising a third wiring that transmits fourth head control data held in the fourth region and fifth head control data held in the fifth region.

11. In the second print mode, printing is performed based on the first head control data transmitted through the first wiring and the second head control data; A liquid ejection head as described in claim 10, characterized in that in the first printing mode, printing is performed based on the first head control data transmitted through the first wiring, the second head control data, the third head control data, the fourth head control data transmitted through the third wiring, and the fifth head control data.

12. A liquid ejection head described in any one of claims 7 to 11, characterized in that the multiple ejection parts have 800 or more ejection parts.

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