ARCHITECTURE-BASED POWER MANAGEMENT FOR MEMORY DEVICES - Patent application

Abstract

To provide a method for supporting a low power mode that has lower power consumption than an idle mode.SOLUTION: A method includes operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] [Cross Reference] This patent application claims priority to PCT Application No. PCT / US2020 / 045412, entitled "ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE," filed on August 7, 2020, by Laurent et al., which claims priority to U.S. patent application Ser. No. 16 / 551,597, entitled "ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE," filed on August 26, 2019, which is assigned to the assignee of the present invention and each of which is expressly incorporated by reference in its entirety herein.

[0002] The following relates generally to systems that include at least one memory device, and more particularly to architecture-based power management for memory devices. [Background technology]

[0003] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, often indicated by a logical 1 or a logical 0. In other devices, more than two states may be stored. To access the stored information, a component of the device can read or sense at least one state stored in the memory device. To store information, a component of the device can write or program a state into the memory device.

[0004] There are various types of memory devices, including magnetic hard disks, random access memories (RAMs), read only memories (ROMs), dynamic RAMs (DRAMs), synchronous dynamic RAMs (SDRAMs), ferroelectric RAMs (FeRAMs), magnetic RAMs (MRAMs), resistive RAMs (RRAMs), flash memories, phase change memories (PCMs), and others. Memory devices may be volatile or non-volatile. Non-volatile memories, such as FeRAMs, can maintain their stored logic states for extended periods of time, even in the absence of an external power source. Volatile memory devices, such as DRAMs, can lose their stored states when disconnected from an external power source. FeRAMs may be capable of achieving densities similar to volatile memories, but have a non-volatile nature due to the use of ferroelectric capacitors as storage devices.

[0005] Improving memory devices may generally include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or improving manufacturing processes, among other metrics. Solutions for improving power consumption in memory devices may be desirable. Summary of the Invention

[0006] A method according to one aspect of the present invention comprises the steps of: operating a first memory bank in a memory device in a first mode and operating a second memory bank in the memory device in a second mode; receiving a power down command at the memory device and switching the second memory bank from the second mode to a low power mode based at least in part on receiving the power down command; receiving a power up command at the memory device and switching the second memory bank from the low power mode to the second mode based at least in part on receiving the power up command; Includes. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 illustrates an example of a system that supports architecture-based power management for memory devices, according to an embodiment disclosed herein. [Diagram 2] FIG. 2 illustrates an example of a memory die that supports architecture-based power management for memory devices according to embodiments disclosed herein. [Diagram 3]FIG. 2 illustrates an example of a memory die system that supports architecture-based power management for memory devices according to embodiments disclosed herein. [Figure 4] FIG. 2 illustrates an example of a state diagram that supports architecture-based power management for a memory device, according to an embodiment disclosed herein. [Diagram 5] FIG. 2 illustrates an example of a state diagram that supports architecture-based power management for a memory device, according to an embodiment disclosed herein. [Figure 6] FIG. 2 illustrates an example of a state diagram that supports architecture-based power management for a memory device, according to an embodiment disclosed herein. [Figure 7] FIG. 1 is a block diagram of a memory device that supports architecture-based power management for memory devices in accordance with aspects of the present disclosure. [Figure 8] 1 is a flowchart illustrating one or more methods for supporting architecture-based power management for a memory device according to embodiments disclosed herein. [Figure 9] 1 is a flowchart illustrating one or more methods for supporting architecture-based power management for a memory device according to embodiments disclosed herein. [Figure 10] 1 is a flowchart illustrating one or more methods for supporting architecture-based power management for a memory device according to embodiments disclosed herein. [Figure 11] 1 is a flowchart illustrating one or more methods for supporting architecture-based power management for a memory device according to embodiments disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Some memory devices may support one or more low power modes (alternatively, states) in which the memory device may disable or modify the operation of one or more components (which may be collectively referred to as circuitry) to reduce power consumption by the memory device. For example, the memory device may support an idle mode as well as a low power mode having a lower power consumption than the idle mode, and transitioning to the low power mode may include deactivating some amount of circuitry. In the low power mode, the memory device may not be able to perform access operations (e.g., read operations, write operations, etc.) on memory cells of the memory device, or may be able to transition directly to an active mode in which such operations may be performed (e.g., when in a lower power mode, the memory device may have to transition first to an idle mode and then to an active mode). In some cases, the memory device may support different low power modes associated with different reduced levels of current consumption (e.g., associated with different amounts of deactivated circuitry).

[0009] For some memory devices, the low power modes may be operated and thus controlled at the memory die level, meaning that each sub-block (e.g., bank, bank group, etc.) in the memory die can enter or exit the same low power mode together. Thus, such memory devices may not support, for example, operating some sub-blocks of the memory die in a low power mode (e.g., with some or all of the sub-blocks' circuitry deactivated) while operating one or more other sub-blocks of the memory die in an idle or active mode to support access operations in the one or more other sub-blocks. Similarly, such memory devices may not support operating some sub-blocks of the memory die in a first low power mode while operating one or more other sub-blocks of the memory die in a second low power mode, as another example, which may have greater power savings (e.g., greater amount of deactivated circuitry) but may have a longer startup time. As a result, a memory die may only be switched into a low power mode if the n expected time until the next access operation for the memory die is long enough to correspond to the die-level power-up time and / or to counter the power consumption associated with transitioning the die into or out of the low power mode. Thus, the memory die may achieve less power savings than desired (e.g., the memory die may operate in a low power mode relatively infrequently due to the latency required to power up the device or the entire die).

[0010] However, as described herein, a memory device may achieve greater power savings (e.g., lower overall or average current consumption) by operating different portions of the memory device or a die therein (e.g., different portions of a single memory array) in different power modes. In some cases, a memory device may operate different portions of the device in different low power modes based on the architecture of the memory device, and different portions of the memory device may be assigned to different hierarchical levels based on the memory device architecture. For example, circuitry at the die hierarchy level may be shared by (common to) all memory sub-blocks (e.g., banks or groups of banks (sometimes referred to as bank groups)) within a memory die. As another example, circuitry at the bank hierarchy level may be specific (dedicated) to one memory bank within a memory die and independent (not shared by) any other banks within the memory die. And, as another example, circuitry at the group hierarchy level may be shared (e.g., accessible by, used by, coupled to, or combinable with) multiple memory banks (sometimes referred to as bank groups), but may not necessarily be shared by all memory banks in a memory die - i.e., circuitry at the group hierarchy level may be shared by all banks in a bank group, but may be independent of (not shared by) any other banks in the memory die. A memory die may include any number of memory banks and bank groups.

[0011] Thus, a memory device architecture may be divided into different levels of hierarchy based on functional dependencies or shared circuits between aspects of the memory device. If entities at one hierarchical level share some circuits or have some other functional dependency, the shared circuits or functional dependency may be assigned to another, higher hierarchical level. Thus, although some embodiments are described herein in terms of hierarchical levels including bank level, group level, and die level, it should be understood that any number of hierarchical levels may be defined (e.g., based on entities that have some circuits or other components in common), including at a sub-bank level, at a supra-die level, or at any intermediate level. Although some embodiments are described herein based on FeRAM devices and architectures or DRAM devices and architectures, it should also be understood that the teachings herein may be applied to any type of memory device and associated architecture.

[0012] Different entities (e.g., different dies, different bank groups, different banks) at the same hierarchical level of a memory device may be switched into and out of low power modes independent of one other. Thus, one entity at a hierarchical level may be in one low power mode and another entity at the same hierarchical level may be in another low power mode or some other operating mode (e.g., idle or active). Additionally or alternatively, different entities at the same hierarchical level but within the same hierarchical group (e.g., banks in the same bank group, bank groups in the same die) may be switched into and out of low power modes together. These and other changes in operating mode may be accomplished, for example, through power mode commands that are specific to a hierarchical level and a hierarchical group within that hierarchical level (e.g., bank-specific, bank-group-specific, die-specific). As described herein, one or more registers may be used to store state information or other information supporting operating the memory device in accordance with such power mode commands.

[0013] In some cases, the memory device may automatically power down some or all circuitry at a higher hierarchical level when all entities at a lower hierarchical level are operating in a low power mode. For example, if all banks in a bank group are switched to a low power mode via a bank-specific power down command, the memory device may automatically deactivate some or all group-level circuitry for the bank group. In some cases, the memory device may also support switching aspects of the memory device from one low power mode to another low power mode, or from having only lower hierarchical level entities in a low power mode to also having at least one higher level entity in a low power mode (which may be considered a higher level low power mode) without going through an intermediate (e.g., idle) state.

[0014] By operating different aspects of a memory device independently of one another as described herein, enhanced power savings may be achieved, among other benefits that may be appreciated by those skilled in the art. For example, greater flexibility may be provided to more frequently place aspects of a memory device into the deepest low power mode possible based on usage patterns for the different aspects of the memory device, so that the different aspects of the memory device may be in a low power mode (or a deeper low power mode) more often. As an example, data associated with (e.g., accessed by) the same application may be stored in the same bank or bank group such that when the application is active or expected to be active within some threshold amount of time, other banks or bank groups may be in a low power mode (or a deeper low power mode) and the associated bank or bank group may be in an idle mode (or a less deep low power mode).

[0015] These and other features of the present disclosure are first described in the context of memory systems and memory dies with reference to Figures 1-2. Features of the present disclosure are then described in the context of example memory die architectures and associated state diagrams with reference to Figures 3-6. These and other features of the present disclosure are further illustrated by and described in the context of apparatus diagrams and flow charts relating to architecture-based power management for memory devices with reference to Figures 7-11.

[0016] 1 illustrates an embodiment of a system 100 utilizing one or more memory devices according to embodiments disclosed herein. System 100 may include an external memory controller 105, a memory device 110, and multiple channels 115 coupling external memory controller 105 with memory device 110. Although system 100 may include one or more memory devices, for ease of explanation, the one or more memory devices may be described as a single memory device 110.

[0017] System 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, or the like. Memory device 110 may be a component of a system configured to store data for one or more other components of system 100. In some examples, system 100 is capable of machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0018] At least a portion of system 100 may be an embodiment of a host device. Such a host device may be an embodiment of a device that uses memory to execute processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, or any other fixed or portable electronic device. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that performs the functions of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or a host device. In some examples, system 100 is a graphics card.

[0019] In some cases, memory device 110 may be an independent device or component configured to communicate with other components of system 100 and provide physical memory addresses / space potentially used or referenced by system 100. In some embodiments, memory device 110 may be configurable to work with at least one or more different types of system 100. Signaling between components of system 100 and memory device 110 may be operable to support modulation schemes for modulating signals, different pin designs for communicating signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0020] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave type device to the system 100 (e.g., execute in response to commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity for data storage. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0021] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may be in electronic communication with each other using a bus 140.

[0022] Processor 120 may be configured to control at least portions of system 100. Processor 120 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, a discrete hardware component, or a combination of these types of components. In such cases, processor 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), or a system-on-a-chip (SoC) implementation, among other implementations.

[0023] BIOS component 125 may be a software component including a BIOS operated as firmware to initialize and run various hardware components of system 100. BIOS component 125 may also manage data flow between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0024] Peripheral component 130 may be any input or output device, or interface for such a device, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a peripheral component interconnect (PCI) or a dedicated graphics port. Peripheral component 130 may be other components that are understood to be peripherals by those skilled in the art.

[0025] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input devices 145, or output devices 150. I / O controller 135 may manage peripheral devices not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0026] Inputs 145 may represent devices or signals external to system 100 that provide information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, inputs 145 may be peripherals that interface with system 100 through one or more peripheral components 130 and may be managed by I / O controller 135.

[0027] Output 150 may represent a device or signal external to system 100 configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 and may be managed by I / O controller 135.

[0028] Memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 may be a collection (e.g., a grid) of memory cells, each configured to store at least one bit of digital data. Features of memory array 170 and / or memory cells are described in more detail with reference to FIG. 2.

[0029] The memory device 110 may be an embodiment of a two-dimensional (2D) array of memory cells or an embodiment of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any amount of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N are stacked on top of each other or next to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a deck, level, layer, or die. A 3D memory device may include any amount of stacked memory dies 160-N (e.g., two high, three high, four high, five high, six high, seven high, eight high). This may increase the amount of memory cells that can be positioned on a substrate compared to a single 2D memory device, which may decrease production costs or increase performance of the memory array, or both. In some 3D memory devices, different decks may share at least one common access line, such that some decks may share at least one of the word lines, digit lines, and / or plate lines.

[0030] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to execute commands and may be configured to receive, send, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with the external memory controller 105, one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 can store certain data on behalf of a component of the system 100 (e.g., the processor 120) or a read command indicating that the memory device 110 can provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110, as described herein in connection with the local memory controller 165 of the memory die 160. Examples of components included within the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, etc.

[0031] The local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. The local memory controller 165 may also be configured to communicate with (e.g., receive and send data and / or commands to) the device memory controller 155. The local memory controller 165 may support the device memory controller 155 to control the operation of the memory device 110 described herein. In some cases, the memory device 110 may not include the device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0032] The external memory controller 105 may be configured to enable communication of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110 such that the components of the system 100 may not need to know the details of the operation of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 that the external memory controller 105 satisfies. The external memory controller 105 may convert or translate communications between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0033] In some cases, the external memory controller 105 or other components of the system 100, or its functions described herein, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is shown to be external to the memory device 110, in some cases, the external memory controller 105, or its functions described herein, may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Similarly, in some cases, one or more functions attributed in this specification to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (either separate from processor 120 or included in processor 120).

[0034] Components of the system 100 may exchange information with the memory device 110 using multiple channels 115. In some embodiments, the channels 115 may enable communication between the external memory controller 105 and the memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with the components of the system 100. For example, the channel 115 may include a first terminal including one or more pins or pads at the external memory controller 105 and one or more pins or pads at the memory device 110. The pins may be examples of conductive input or output points of the devices of the system 100, and the pins may be configured to function as part of the channel. In some cases, the pins or pads of the terminals may be part of the signal paths of the channel 115. Additional signal paths may be coupled to the terminals of the channel to route signals within the components of the system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to the memory device 110 or its components, such as internal to memory device 110 or memory die 160) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0035] Channel 115 (and associated signal paths and terminals) may be dedicated to communicating a particular type of information. In some cases, channel 115 may be an aggregated channel and thus include multiple individual channels. For example, data channel 190 may be ×4 (e.g., including four signal paths), ×8 (e.g., including eight signal paths), ×16 (including sixteen signal paths), etc. Signals communicated on the channel may use a double data rate (DDR) timing scheme. For example, some symbols of the signal may be registered on the rising edge of a clock signal and other symbols of the signal may be registered on the falling edge of the clock signal. Signals communicated on the channel may use single data rate (SDR) signaling. For example, one symbol of the signal may be registered every clock cycle.

[0036] In some cases, the channel 115 may include one or more command and address (CA) channels 186. The CA channel 186 may be configured to communicate commands between the external memory controller 105 and the memory device 110, including control information associated with the command (e.g., address information). For example, the CA channel 186 may include a read command with an address of the desired data. In some cases, the CA channel 186 may be registered on a rising clock signal edge and / or a falling clock signal edge. In some cases, the CA channel 186 may include any amount of signal paths (e.g., eight or nine signal paths) for decoding the address and command data.

[0037] In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The CK channels 188 may be configured to communicate one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to oscillate between a high state and a low state to coordinate the actions of the external memory controller 105 and the memory device 110. In some cases, the clock signals may be differential outputs (e.g., a CK_t signal and a CK_c signal) and the signal paths of the CK channels 188 may be configured accordingly. In some cases, the clock signals may be single-ended. The CK channels 188 may include any amount of signal paths. In some cases, the clock signals CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and address operations or other system-wide operations to the memory device 110. Thus, the clock signal CK may be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0038] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channel 190 may be configured to communicate data and / or control information between external memory controller 105 and memory device 110. For example, data channel 190 may communicate information to be written to memory device 110 (e.g., bidirectionally) or information to be read from memory device 110.

[0039] In some cases, the channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any amount of signal paths.

[0040] Channel 115 may couple external memory controller 105 with memory device 110 using a variety of different architectures. Examples of the various architectures may include a bus, a point-to-point connection, a crossbar, a high density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may include at least in part a high density interposer such as a silicon interposer or a glass interposer.

[0041] Signals communicated on the channel 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to 2. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0042] Aspects of memory device 110 may be assigned or considered to be at different hierarchical levels (e.g., die level, group level, bank level, etc.). Based on one or more commands, memory device 110 may switch different aspects of memory device 110 into or out of a low power mode, either collectively or independently of one another. For example, memory device 110 may receive a command to switch a memory bank into a low power mode, and the memory device may deactivate circuitry dedicated to that memory bank. As another example, memory device 110 may receive a command to switch a bank group from a first mode (e.g., an idle mode) to a low power mode, and memory device 110 may deactivate group level circuitry dedicated to the bank group (shared by all memory banks in the bank group) as well as bank level circuitry dedicated to individual memory banks in the bank group. As yet another example, memory device 110 may receive a command to switch memory die 160 from a first mode (e.g., an idle mode) to a low power mode, and memory device 110 may deactivate the group level circuitry for each bank group and the bank level circuitry for each memory bank in memory die 160, as well as the die level circuitry shared by all memory banks (and thus by all bank groups) within that memory die 160. Thus, for a power down command for an indicated entity at an indicated hierarchical level (which may alternatively be referred to as an enter command for the low power mode), memory device 110 may deactivate the circuitry at the indicated hierarchical level for the indicated entity (e.g., may deactivate the group level circuitry for the indicated bank group) and may also deactivate circuitry at any lower hierarchical levels for entities within the indicated entity (e.g., may deactivate the bank level circuitry for the banks in the indicated bank group).

[0043] Similarly, for some power-up commands for an indicated entity at an indicated hierarchical level (which may alternatively be referred to as an exit command for a low power mode), memory device 110 may activate circuitry at the indicated hierarchical level for the indicated entity (e.g., it may activate group-level circuitry for the indicated bank group) and may also activate circuitry at any lower hierarchical levels for entities within the indicated entity (e.g., it may activate bank-level circuitry for the banks within the indicated bank group).

[0044] Additionally or alternatively, the memory device may receive a cancel command (which may alternatively be referred to as a remove command) for a previous power down command for the indicated entity at the indicated hierarchical level, in which case the memory device 110 may restore the indicated entity, along with any lower hierarchical levels for entities within the indicated entity, to their respective operating modes at the time the previous power down command was received.

[0045] In some cases, the memory device 110 may track whether a lower-level entity (e.g., a bank or bank group) is operating in one or more low-power modes and may automatically deactivate circuitry at a higher hierarchical level (e.g., group-level circuitry or die-level circuitry) if all of the lower-level entities within the higher-level entity are individually operating in a low-power mode. For example, the memory device 110 may determine that all memory banks of a first bank group are operating in a low-power mode, and the memory device 110 may deactivate the group-level circuitry for the first bank group. As another example, the memory device 110 may determine that all of the memory banks (or bank groups) of the first memory die 160 are operating in a low-power mode, and the memory device 110 may deactivate the group-level circuitry (if not already deactivated) along with the die-level circuitry for the first memory die 160. In some cases, the memory device 110 may further track whether an entity has been placed into a low power mode by an automatic transition or a command transition, and in response to a cancel command for a previous power off command, the memory device 110 may reverse (rewind, undo, cancel) the command transition only - i.e., if an entity within range of the cancel command is in a low power mode as a result of an automatic transition, the memory device 110 may ignore the cancel command for that entity.

[0046] FIG. 2 illustrates an example of a memory die 200 according to an embodiment disclosed herein. The memory die 200 may be an example of the memory die 160 described with reference to FIG. 1. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logical states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cells 205 may be configured to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, or a logical 11).

[0047] The memory cells 205 may store a state (e.g., a polarization state or a dielectric charge) that represents digital data. In a FeRAM architecture, the memory cells 205 may include a capacitor that includes a ferroelectric material for storing a charge and / or a polarization that represents a programmable state. In a DRAM architecture, the memory cells 205 may include a capacitor that includes a dielectric material for storing a charge that represents a programmable state.

[0048] Operations such as read and write may be performed on memory cells 205 by activating or selecting access lines such as word line 210, digit line 215, and / or plate line 220. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, digit lines, plate lines, or the like, may be interchangeable without loss of understanding or operation. Activating or selecting a word line 210, digit line 215, or plate line 220 may include applying a voltage to the respective line.

[0049] The memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a checkerboard pattern. Memory cells 205 may be positioned at intersections of the word lines 210, digit lines 215, and / or plate lines 220. A single memory cell 205 may be accessed at an intersection by biasing the word lines 210, digit lines 215, and plate lines 220 (e.g., applying a voltage to the word lines 210, digit lines 215, or plate lines 220).

[0050] Accessing the memory cells 205 may be controlled via a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from a local memory controller 265 and activate a word line 210 based on the received row address. The column decoder 230 receives a column address from the local memory controller 265 and activates a digit line 215 based on the received column address. The plate driver 235 may receive a plate address from the local memory controller 265 and activates a plate line 220 based on the received plate address. For example, the memory die 200 may include a number of word lines 210 labeled WL_1 to WL_M, a number of digit lines 215 labeled DL_1 to DL_N, and a number of plate lines labeled PL_1 to PL_P, where M, N, and P depend on the size of the memory array. Thus, by activating word lines 210, digit lines 215, and plate lines 220, e.g., WL_1, DL_3, and PL_1, memory cells 205 can be accessed at their intersections. In either a two-dimensional or three-dimensional configuration, the intersections of word lines 210 and digit lines 215 may be referred to as addresses of memory cells 205. In some cases, the intersections of word lines 210, digit lines 215, and plate lines 220 may be referred to as addresses of memory cells 205.

[0051] The memory cell 205 may include a logical storage component, such as a capacitor 240, and a switching component 245. The capacitor 240 may be an implementation of a ferroelectric capacitor. A first node of the capacitor 240 may be coupled to the switching component 245, and a second node of the capacitor 240 may be coupled to the plate line 220. The switching component 245 may be an implementation of a transistor or any other type of switch device that selectively establishes or de-establishes electronic communication between two components.

[0052] Selecting or deselecting the memory cell 205 may be accomplished by activating or deactivating the switching component 245. The capacitor 240 may be in electronic communication with the digit line 215 using the switching component 245. For example, the capacitor 240 may be isolated from the digit line 215 when the switching component 245 is deactivated, and the capacitor 240 may be coupled to the digit line 215 when the switching component 245 is activated. In some cases, the switching component 245 includes a transistor, the operation of which is controlled by applying a voltage to the transistor gate, and the voltage difference between the transistor gate and the transistor source is greater or less than the threshold voltage of the transistor. In some cases, the switching component 245 may be a p-type transistor or an n-type transistor. The word line 210 may be in electronic communication with the gate of the switching component 245 and may activate / deactivate the switching component 245 based on the voltage applied to the word line 210.

[0053] The word line 210 may be a conductive line in electronic communication with the memory cell 205 that is used to perform access operations on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with a gate of a switching component 245 of the memory cell 205 and may be configured to control the switching component 245 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205 and the memory cell 205 may not include a switching component.

[0054] The digitline 215 may be a conductive line that connects the memory cell 205 with the sensing component 250. In some architectures, the memory cell 205 may be selectively coupled to the digitline 215 during a portion of an access operation. For example, the wordline 210 and the switching component 245 of the memory cell 205 may be configured to selectively couple and / or isolate the capacitor 240 of the memory cell 205 with the digitline 215. In some architectures, the memory cell 205 may be in electronic communication with the digitline 215 (e.g., all the time).

[0055] The plate line 220 may be a conductive line in electronic communication with the memory cell 205 that is used to perform an access operation on the memory cell 205. The plate line 220 may be in electronic communication with a node (e.g., at the bottom of the cell) of the capacitor 240. The plate line 220 may be configured to cooperate with the digit line 215 to bias the capacitor 240 during an access operation of the memory cell 205.

[0056] The sensing component 250 may be configured to determine a state (e.g., polarization state or charge) stored on the capacitor 240 of the memory cell 205 and determine a logic state of the memory cell 205 based on the detected state. The charge stored by the memory cell 205 may be extremely small in some cases. Therefore, the sensing component 250 may include one or more sense amplifiers to amplify the signal output of the memory cell 205. The sense amplifiers may detect minute changes in the charge of the digit line 215 during a read operation and may generate a signal corresponding to either a logic 0 or a logic 1 based on the detected charge. During a read operation, the capacitor 240 of the memory cell 205 may output a signal (e.g., discharge a charge) to its corresponding digit line 215. The signal may change the voltage of the digit line 215. The sensing component 250 may be configured to compare the signal received from the memory cell 205 on the digit line 215 to a reference signal 255 (e.g., a reference voltage). The sense component 250 can determine the stored state of the memory cell 205 based on this comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 255, the sense component 250 can determine that the stored state of the memory cell 205 is logic 1, and if the digit line 215 has a lower voltage than the reference signal 255, the sense component 250 can determine that the stored state of the memory cell 205 is logic 0. The sense component 250 can include various transistors or amplifiers to detect and amplify the difference in the signals. The detected logic state of the memory cell 205 can be provided as an output of the sense component 250 (e.g., to the input / output 260), which can indicate the detected logic state to another component of the memory device 110 including the memory die 200, such as the device memory controller 155 (e.g., directly or using a local memory controller 265).In some cases, the sensing component 250 can be in electronic communication with the row decoder 225, the column decoder 230, and / or the plate driver 235.

[0057] The local memory controller 265 may control operation of the memory cells 205 via various components (e.g., row decoder 225, column decoder 230, plate driver 235, and sense component 250). The local memory controller 265 may be an embodiment of the local memory controller 165 described with reference to FIG. 1. In some cases, one or more of the row decoder 225, column decoder 230, and plate driver 235, and sense component 250 may be co-located with the local memory controller 265. The local memory controller 265 may be configured to receive one or more commands and / or data from the external memory controller 105 (or the device memory controller 155 described with reference to FIG. 1), convert the commands and / or data into information usable by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. The local memory controller 265 may generate row address signals, column address signals, and / or plate line address signals to activate the target word lines 210, the target digit lines 215, and the target plate lines 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory die 200.

[0058] In some cases, the local memory controller 265 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify a target memory cell 205 for performing a write operation. The local memory controller 265 may identify a target word line 210, a target digit line 215, and / or a target plate line 220 that is in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The local memory controller 265 may apply a particular signal (e.g., voltage) to the digit line 215 and a particular signal (e.g., voltage) to the plate line 220 during a write operation to store a particular state in the capacitor 240 of the memory cell 205, the particular state indicating a desired logic state.

[0059] In some cases, the local memory controller 265 may be configured to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logical state stored in the memory cells 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 265 may identify a target memory cell 205 for performing a read operation. The local memory controller 265 may identify a target word line 210, a target digit line 215, and / or a target plate line 220 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The target memory cell 205 may transfer a signal to the sensing component 250 in response to biasing the access line. The sensing component 250 may amplify the signal. The local memory controller 265 may activate (e.g., latch) the sensing component 250, thereby comparing the signal received from the memory cell 205 to a reference signal 255. Based on the comparison, the sensing component 250 may determine the logic state stored on the memory cell 205. The local memory controller 265 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller) as part of a read operation.

[0060] In some memory architectures, accessing a memory cell 205 may degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed on a ferroelectric memory cell may destroy the logic state stored in the ferroelectric capacitor. In another embodiment, a read operation performed in a DRAM architecture may partially or fully discharge the capacitor of the target memory cell. The local memory controller 265 may perform a rewrite or refresh operation to return the memory cell to its original logic state. The local memory controller 265 may rewrite the logic state to the target memory cell after the read operation. In some cases, the rewrite operation may be considered as part of the read operation. Additionally, activating a single access line, such as the word line 210, may disturb the states stored in several memory cells in electronic communication with that access line. Thus, a rewrite or refresh operation may be performed on one or more memory cells that may not have been accessed.

[0061] Different entities within memory die 200 may be organized according to an architecture that includes different hierarchical levels, as described herein, including with reference to Figure 3. Additionally, memory device 110 that includes memory die 200 may cause different entities to operate according to different power mode commands (e.g., power down commands, power up commands, cancel commands) and associated power mode information (e.g., state information related to operating modes or automatic transitions), as described herein.

[0062] 3 illustrates an example of a memory die architecture 300 that supports architecture-based power management for a memory device according to embodiments disclosed herein. Although only a memory die 305 is shown, it should be understood that a memory device may include any number of memory dies 305 that may operate independently or together according to any higher hierarchical level according to the teachings herein. The memory die 305 may be an example of a memory die 160, 200 described with reference to FIGS. 1 and 2.

[0063] The memory die 305 may be organized according to a hierarchical architecture that includes multiple hierarchical levels, which may be based on functional dependencies and shared circuitry of different components.

[0064] One example of a first hierarchical level may be the bank level. Each memory bank 320 may include, be coupled to, or be associated with dedicated circuitry for operating the memory bank 320 (e.g., for performing access operations to the memory bank 320), and circuitry that is not common to (shared by) any two memory banks 320 may be referred to as bank-level circuitry.

[0065] An example of a second hierarchical level may be a group level, which may be considered a hierarchical level higher than the bank level. For example, some circuits may be shared by multiple memory banks 320 (e.g., to conserve area in the memory die 305). Circuits shared by more than one memory bank 320 but not by all memory banks 320 in the memory die 305 may be referred to as group level circuits, and memory banks 320 that share the same set of group level circuits 315 may be referred to as bank groups 310. Circuits in a set of group level circuits 315 may be coupled or couplable (e.g., selectively) with all memory banks 320 in the respective bank groups 310. For example, circuits in a set of group level circuits 315-a may be coupled with each of memory banks 0-3 or may be selectively couplable with any one or more of memory banks 0-3. Examples of group level circuits may include charge pumps or error correction code (ECC) components.

[0066] An example of a third hierarchical level may be the die level, which may be considered a higher hierarchical level than the group level. For example, some circuits may be shared by all memory banks 320 (and therefore all bank groups 310) in a memory die 305. Circuits shared by all memory banks 320 in a memory die 305 may be referred to as die-level circuits. Thus, each memory die 305 may include a set of die-level circuits 307. Examples of die-level circuits may include a fuse array or a command decoder (e.g., for user commands).

[0067] Although other hierarchical levels may exist, such as levels higher than the die level (e.g., for a multi-die device), levels lower than the bank level (e.g., for portions of memory bank 320), or intermediate levels, the bank level, group level, and die level may serve as exemplary lower, intermediate, and higher hierarchical levels, and therefore the examples herein may be described in terms of the bank level, group level, and die level for illustrative clarity. In general, any circuitry shared by entities at a first hierarchical level may be considered to be at a second hierarchical level that is higher than the first hierarchical level.

[0068] When memory bank 320 is operating in an idle mode, dedicated circuitry for memory bank 320 may consume a first amount of power. For example, in the idle mode, memory bank 320 may maintain certain aspects of memory bank 320 (e.g., access line drivers, access line decoders, sensing components, etc.) in a prepared (e.g., pre-charged) state such that these components are ready to perform access operations on memory cells of memory bank 320 if an activate (ACT) command is subsequently received for memory bank 320 (in which case the memory device may switch memory bank 320 to an active mode, which may correspond to a second, larger amount of power consumption). Thus, when operating in an idle mode, dedicated bank-level circuitry for memory bank 320 may draw a first amount of current and thus consume a first amount of power.

[0069] The memory bank 320 may also support one or more bank-level low power modes that reduce current consumption in the memory bank 320. In some cases, a memory device (e.g., a memory controller such as the external memory controller 105, the device memory controller 155, or the local memory controller 165) may switch the memory bank 320 into and out of one or more bank-level low power modes independent of operating modes of other memory banks 320. A bank-level low power mode may be any operating mode in which the amount of current and therefore the power consumption by the memory bank 320 is lower than when the memory bank is in an idle mode. Switching the memory bank 320 into a bank-level low power mode may include deactivating or powering down one or more components of the dedicated circuitry for the memory bank 320. Switching the memory bank 320 from a bank-level low power mode to a target mode (e.g., an idle mode, a less deep low power mode) may include activating some or all of the bank-level circuitry for the memory bank 320 that has not yet been activated.

[0070] If multiple low power modes are supported for memory bank 320, each of the bank-level low power modes may correspond to a different amount of deactivated circuitry or to a different amount of current and power consumption for memory bank 320. For example, switching memory bank 320 to a first bank-level low power mode may include deactivating a first amount of bank-level circuitry for memory bank 320, and switching memory bank 320 to a second bank-level low power mode may include deactivating a greater amount of bank-level circuitry for memory bank 320. The second bank-level low power mode may be referred to as a deeper low power mode than the first bank-level low power mode. Any number of bank-level low power modes may be supported for memory bank 320, each corresponding to a progressively larger amount of deactivated bank-level circuitry for memory bank 320 and each corresponding to a progressively smaller amount of power consumption for memory bank 320. In some cases, each low power mode may also correspond to a progressively larger amount of time for the memory bank 320 to exit the low power mode and switch to an idle mode, which may be referred to as the start-up time or exit time.

[0071] At the group level, when at least one memory bank 320 of a bank group 310 is operating in an idle mode, an active mode, or other non-low power mode, a corresponding set of group-level circuits 315 may be activated to support operation for the memory bank 320 and therefore consume an associated amount of current and power. A bank group 310 may also support any number of group-level low power modes, but switching a bank group 310 to a group-level low power mode may include deactivating a corresponding amount (e.g., some or all) of the circuitry in the corresponding set of group-level circuits 315. Thus, when multiple group-level low power modes are supported, each may correspond to a progressively larger amount of deactivated group-level circuitry for the corresponding set of group-level circuits 315, and each may correspond to a progressively smaller amount of power consumption for the bank group 310, similar to that described with respect to multiple bank-level low power modes. In some cases, switching a bank group 310 to a group-level low power mode may include switching all memory banks 320 in the bank group 310 to a bank-level low power mode (e.g., the deepest bank-level low power mode supported by the memory banks 320)--along with deactivating some amount of group-level circuitry 315--if the corresponding memory banks 320 are not already in the bank-level low power mode. In some cases, switching a bank group 310 out of a group-level low power mode may include switching all memory banks 320 in the bank group 310 to an idle mode--along with deactivating some amount of group-level circuitry 315.

[0072] At the die level, when at least one memory bank 320 (and thus at least one bank group 310) of the memory die 305 is operating in an idle mode, an active mode, or other non-low power mode, a corresponding set of die-level circuits 307 may be activated to support operation for one or more memory banks 320 and thus consume an associated amount of current and power. However, similar to what was described with respect to the bank level and group level, the set of die-level circuits may support any number of die-level low power modes. Switching the memory die 305 to a die-level low power mode may include deactivating a corresponding amount (e.g., some or all) of circuitry in the corresponding set of die-level circuits 307. Thus, when multiple die-level low power modes are supported, each may correspond to a progressively larger amount of deactivated die-level circuitry for the memory die 305 and each may correspond to a progressively smaller amount of power consumption for the memory die 305, similar to what was described with respect to the multiple bank-level low power modes. In some cases, switching the memory die 305 to the die-level low power mode may include switching all bank groups 310 in the memory die 305 to a group-level low power mode (e.g., the deepest group-level low power mode supported by the bank groups 310)—along with deactivating some amount of die-level circuitry 307—if the bank groups 310 and memory banks 320 are not already in such a low power mode, and therefore switching all memory banks 320 in the memory die 305 to a bank-level low power mode (e.g., the deepest bank-level low power mode supported by the memory banks 320). In some cases, switching the memory die 305 out of the die-level low power mode may include switching all memory banks 320 in the memory die 305 to an idle mode—along with deactivating some amount of die-level circuitry 307—and activating all sets of group-level circuitry 315 in the memory die 305.

[0073] 4 illustrates an example of a state diagram 400 supporting architecture-based power management for a memory device according to embodiments disclosed herein. Aspects of the state diagram 400 may be implemented by the memory device 110, memory die 160, memory die 200, or memory die architecture 300 described with reference to FIGS. 1-3. The state diagram 400 illustrates an example of how portions of a memory device (e.g., a memory bank, a bank group, a memory die, etc.) may switch between different operating modes, including an idle mode 405 and one or more low power modes. In some cases, the transitions between the operating modes illustrated in the state diagram 400 may occur in response to one or more commands that may be received by the memory device.

[0074] A memory device may be configured to independently switch entities at a given hierarchical level into and out of different operational modes for the hierarchical level without necessarily affecting the operational modes of other entities at the same hierarchical level. For example, a memory device may be configured to (i) switch a memory bank 320 into and out of different operational modes without affecting the operational modes of other memory banks 320, (ii) switch a bank group 310 into and out of different operational modes without affecting the operational modes of other bank groups 310, and (iii) switch a memory die 305 into and out of different operational modes without affecting the operational modes of other memory dies 305 (in a multi-die device).

[0075] 4, the idle mode 405 may broadly represent an idle mode that is applicable to any number of hierarchical levels. When a memory bank 320 is in the idle mode 405, bank-level circuits that are inactivated in one or more bank-level low power modes 410 may be activated. When a bank group 310 is in the idle mode 405, group-level circuits that are inactivated in one or more group-level low power modes 415 may be activated. When a memory die is in the idle mode 405, die-level circuits that are inactivated in one or more die-level low power modes 420 may be activated.

[0076] The transition 425 may represent a transition for the memory bank 320 between the idle mode 405 and the bank-level low power mode 410. In some cases, the transition 425 may occur in response to power-down and power-up commands (which may alternatively be referred to as entry and exit commands) specific to the target memory bank 320. For example, a bank-level power-down command may be indicated as an EnterPowerDownYBankX command, where X may be an index, address, or other identifier of the target memory bank 320 and Y may be an index or other identifier of the target bank-level low power mode. Thus, if only one bank-level low power mode is supported, Y may be unnecessary.

[0077] In response to the EnterPowerDownYBankX command, the memory device may switch memory bank 320X to bank-level low power mode Y (e.g., by deactivating some or all of the corresponding bank-level circuitry or by reducing power consumption by memory bank 320X) without changing the operating mode of any other memory banks 320 or of any set of group-level circuits 315 or die-level circuits 307.

[0078] Similarly, a bank-level power-up command may be denoted as an ExitPowerDownBankX command. In response to an ExitPowerDownBankX command, the memory device may switch memory bank 320X to the idle mode 405 (e.g., by activating some or all of the corresponding bank-level circuitry or by increasing power consumption by memory bank 320X) without changing the operational mode of any other memory banks 320.

[0079] If the bank group 310 that includes memory bank 320X is in a group-level low power mode, the memory device may also switch the bank group 310 to the idle mode 405 (e.g., by activating a corresponding set of group-level circuits 315) in response to the ExitPowerDownBankX command, but the memory device may not change the operating mode of any other bank group 310. Similarly, if the memory die 305 that includes memory bank X is in a die-level low power mode, the memory device may also switch the memory die 305 to the idle mode 405 (e.g., by activating a corresponding set of die-level circuits 307) in response to the ExitPowerDownBankX command, but the memory device may not change the operating mode of any other memory die 305. If the bank group 310 or memory die 305 that includes memory bank 320X is already in the idle mode 405, the memory device may not change the operating mode of the bank group 310 or memory die 305 in response to the ExitPowerDownBankX command.

[0080] The example of FIG. 4 shows two bank-level low power modes 410: bank PD-1 (Y=1) and bank PD-2 (Y=2). While operating in the first bank-level low power mode 410-a, the memory bank 320 may consume less power than when operating in the idle mode 405. While operating in the second bank-level low power mode 410-b, the memory bank 320 may consume less power (e.g., more bank-level circuitry may be deactivated) than when operating in the first bank-level low power mode 410-a. Although two bank-level low power modes are shown in FIG. 4, it should be understood that any number of bank-level low power modes are possible.

[0081] The transition 430 may represent a transition for the bank group 310 between the idle mode 405 and the group-level low power mode 415. In some cases, the transition 430 may occur in response to power-down and power-up commands specific to the target bank group 310. For example, a group-level power-down command may be indicated as an EnterPowerDownYBankGroupX command, where X may be an index, address, or other identifier of the target bank group 310 and Y may be an index or other identifier of the target group-level low power mode. Thus, if only one group-level low power mode is supported, Y may be unnecessary.

[0082] In response to the EnterPowerDownYBankGroupX command, the memory device may switch the bank group 310X to group-level low power mode Y (e.g., by deactivating some or all of the set of group-level circuits 315 or by reducing power consumption by the corresponding set of group-level circuits 315) without changing the operating mode of any other bank groups 310 or of any die-level circuitry 307.

[0083] If any memory banks 320 in the bank group 310X are not already in a bank-level low power mode, the memory device may switch such memory banks 320 to a bank-level low power mode (e.g., the deepest supported bank-level low power mode) in response to the EnterPowerDownYBankGroupX command. Thus, in response to the EnterPowerDownYBankGroupX command, one or more memory banks 320 in the bank group 310X may be switched out of the idle mode 405 or out of a less deep bank-level low power mode (e.g., from bank PD-1 to bank PD-2).

[0084] Similarly, a bank-level power-up command may be denoted as an ExitPowerDownBankGroupX command. In response to an ExitPowerDownBankGroupX command, the memory device may switch the bank group 310X to the idle mode 405 (e.g., by activating some or all of the corresponding set of group-level circuits 315 or by increasing the power consumption by the corresponding set of group-level circuits 315) without changing the operating mode of any other bank groups 310. The memory device may also switch all memory banks 320 included in the bank group 310X to the idle mode 405.

[0085] If the memory die 305 that includes memory bank X is in a die-level low power mode, the memory device may also switch the memory die 305 to the idle mode 405 (e.g., by activating a corresponding set of die-level circuits 307) in response to the ExitPowerDownBankX command, but the memory device may not change the operating mode of any other memory die 305. If the memory die 305 that includes memory bank 320X is already in the idle mode 405, the memory device may not change the operating mode of the memory die 305 in response to the ExitPowerDownBankX command.

[0086] The example of Figure 4 shows one group-level low power mode 415 (bank group PD-1 (Y=1)). While operating in the group-level low power mode 415, the bank group 310 may consume less power than when operating in the idle mode 405. Although one group-level low power mode is shown in Figure 4, it should be understood that any number of group-level low power modes are possible.

[0087] The transition 435 may represent a transition for the memory die 305 between the idle mode 405 and the die-level low power mode 420. In some cases, the transition 435 may occur in response to power down and power up commands specific to the target memory die 305. For example, a die-level power down command may be indicated as an EnterPowerDownYDieX command, where X may be an index, address, or other identifier of the target memory die 305 and Y may be an index or other identifier of the target die-level low power mode. Thus, X may be unnecessary if the memory device includes only one memory die 305, and Y may be unnecessary if only one group-level low power mode is supported.

[0088] In response to the EnterPowerDownYDieX command, the memory device may switch memory die 305X to die-level low power mode Y (e.g., by deactivating some or all of the set of die-level circuits 307 or by reducing power consumption by the corresponding set of die-level circuits 307) without changing the operational mode of any other memory die 305.

[0089] If any memory banks 320 or bank groups 310 in the memory die 305X are not already in a bank-level or group-level low power mode associated with the die-level low power mode Y, the memory device may switch such memory banks 320 or bank groups 310 to the associated bank-level or group-level low power mode (e.g., the deepest supported bank-level or group-level low power mode) in response to an EnterPowerDownYDieX command. Thus, one or more memory banks 320 or bank groups 310 in the memory die 305X may be switched out of the idle mode 405 or out of a less deep bank-level or group-level low power mode in response to an EnterPowerDownYDieX command.

[0090] Similarly, a die-level power-up command may be denoted as an ExitPowerDownDieX command. In response to an ExitPowerDownDieX command, the memory device may switch the memory die 305X to the idle mode 405 (e.g., by activating some or all of the corresponding set of die-level circuits 307 or by increasing the power consumption by the corresponding set of die-level circuits 307) without changing the operational mode of any other memory die 305. The memory device may also switch all memory banks 320 (and therefore all bank groups 310) included in the memory die 305X to the idle mode 405.

[0091] The example of FIG. 4 shows two die level low power modes 420: die PD-1 (Y=1) and die PD-2 (Y=2). While operating in the first die level low power mode 420-a, the memory die 305 may consume less power than when operating in the idle mode 405. While operating in the second die level low power mode 420-b, the memory die 305 may consume less power (e.g., more die level circuitry may be deactivated) than when operating in the first die level low power mode 420-a. Although two die level low power modes are shown in FIG. 4, it should be understood that any number of die level low power modes are possible.

[0092] Thus, in general, a command to power down an entity at a lower hierarchical level may not affect other entities at that lower hierarchical level or other entities at a higher hierarchical level, and a command to power up an entity at a lower hierarchical level may likewise not affect other entities at that lower hierarchical level, but may cause an entity at a higher hierarchical level to be activated (e.g., into idle mode 405) if it is not already activated.

[0093] Also, in general, a command to power down an entity at a higher hierarchical level may not affect other entities at that higher hierarchical level, but may cause entities at a lower hierarchical level to be deactivated (e.g., put into a corresponding low power mode), and a command to power up an entity at a higher hierarchical level may not affect other entities at that higher hierarchical level, but may cause entities at the lower hierarchical level to be activated (e.g., put into idle mode 405).

[0094] In some cases, a memory device may support switching an entity at a hierarchical level directly between different low power modes for that hierarchical level (e.g., from a less deep low power mode to a deeper low power mode, or vice versa), where switching directly between modes means that the entity or any lower level entities therein do not go into idle mode 405 as part of the transition. Such a change of power mode within a level may be referred to as an intra-level power down change command.

[0095] For example, the memory device may switch the memory bank 320 from a first bank level low power mode 410-a to a second bank level low power mode 410-b (or vice versa) in response to an intra-bank-level power-down change command 440, which may include an indication of the memory bank 320 and the target bank level low power mode 410. As another example, the memory device may switch the bank group 310 from a first group level low power mode 415 to a second group level low power mode 415 (not shown in FIG. 4 ) (or vice versa) in response to an intra-group-level power-down change command, which may include an indication of the bank group 310 and the target group level low power mode 415. As yet another example, the memory device may switch the memory die 305 from a first die level low power mode 420-a to a second die level low power mode 420-b (or vice versa) in response to a die level power down change command 445, which may include an indication of the memory die 305 and the target die level low power mode 420.

[0096] When an entity at a hierarchical level is switched directly between different low power modes for that hierarchical level, other entities at the same hierarchical level as well as entities at other hierarchical levels may not be affected and may remain in their respective operating modes. For example, when a memory bank 320 is switched between different bank level low power modes 410, there may be no impact on the operating modes of other memory banks 320 or on the operating modes of bank groups 310 or memory die 305.

[0097] In some cases, a memory device may also support switching from having only lower hierarchical level entities in a corresponding low power mode to also having at least one higher level entity in a corresponding low power mode without passing through an intermediate (e.g., idle) state - which may be thought of as switching the memory device from a lower hierarchical level low power mode to a higher hierarchical level low power mode.

[0098] Transition 450 may represent a transition for the memory device directly from a lower hierarchical level low power mode to a higher hierarchical level low power mode (e.g., without entering idle mode 405 as part of the transition). Transition 450 may occur in response to a power down command associated with the higher hierarchical level. For example, as described above, in response to an EnterPowerDownYBankGroupX command, not only may the circuitry at the group level (e.g., the set of group level circuits 315 corresponding to the indicated bank group 310) be powered down (e.g., at least partially deactivated), but the memory banks 320 within the bank group 310 may also change operating modes (e.g., switch to the deepest supported bank level power mode). Similarly, and as described above, in response to the EnterPowerDownYDieX command, not only may the circuitry at the die level (e.g., the set of die level circuits 307 corresponding to the indicated memory die 305) be powered down (e.g., at least partially deactivated), but the memory banks 320 and bank groups 310 within the memory die 305 may also change operating modes (e.g., switch to the deepest supported bank-level power mode and group-level power mode).

[0099] 5 illustrates another example of a state diagram 500 supporting architecture-based power management for a memory device according to embodiments disclosed herein. State diagram 500 may correspond to state diagram 400, but transitions 430, 435, 450 are not shown, as other types of transitions may be shown without loss of visual clarity. It should be understood that some or all aspects of state diagrams 400 and 500 may be combined in any combination according to the teachings herein.

[0100] For example, state diagram 500 includes transitions 550 and 555 that may represent transitions in response to a cancel command (which may alternatively be referred to as a delete command). The cancel command may be associated with (e.g., may include an indicator indicating) a target entity (e.g., bank group 310) within the memory device. In response to the cancel command, the memory device may switch the target entity to the idle mode 405 (e.g., may activate circuitry for the target entity) and may switch any lower level entities within that entity to their respective operating modes when the most recent power down command for the target entity was received. For example, in response to a cancel command for bank group 310, the memory device may activate a set of group level circuits 315 for bank group 310 and may restore each memory bank 320 of bank group 310 to its respective operating mode when the most recent EnterPowerDownYBankGroupX command for bank group 310 was received. Thus, a power-on command for a higher hierarchical level entity may transition each lower-level entity therein to idle mode 405, while a cancel command for a higher hierarchical level entity may transition each lower-level entity therein to its respective previous operating mode (which may happen to be idle mode 405, but may also be a lower-level power-down mode).

[0101] To support the cancel command, the memory device may maintain state information (one or more state variables) that indicates the respective states of different entities at different hierarchical levels within the memory device. The memory device may maintain the state information in one or more registers (e.g., a mode register, a status register, or other registers) and may update the state information as commands are received for different entities. When the memory device receives a cancel command for a target entity, the memory device may consult the state information to determine the respective previous operating modes of any lower level entities within the target entity. Table 1 shows an example of state variables and therefore state information for different entities at different hierarchical levels within the memory device.

[0102] [Table 1]

[0103] For each hierarchical level, the memory device may use an encoding scheme to assign a unique combination of state variables to each low power mode at that hierarchical level along with an idle mode for that hierarchical level. For example, at the bank level, the memory base may assign a first logical value (00) to the idle mode 405, a second logical value (01) to the first bank level low power mode 410-a, and a third logical value (10) to the second bank level low power mode 410-b. As another example, at the group level, the memory device may assign a first logical value (0) to the idle mode 405 and a second logical value (1) to the group level low power mode 415. As yet another example, at the die level, the memory device may assign a first logical value (00) to the idle mode 405, a second logical value (01) to the first die level low power mode 420-a, and a third logical value (10) to the second die level low power mode 420-b.

[0104] In some cases, the memory device may assign a priority to each hierarchical level. For example, the memory device may prioritize state information for a higher hierarchical level over state information for a lower hierarchical level - e.g., state information for a memory die 305 may be prioritized over state information for a bank group 310 within the memory die, which may be prioritized over state information for a memory bank 320 within the bank group 310. The memory device may determine an operational mode of an entity within the memory device based on state information (state variables) for the entity along with state information for any higher level entities that include (or have priority over) the entity. Additionally, because the memory device may update (e.g., overwrite) state information for an entity in response to receiving a command associated with the entity, the memory device may prioritize commands for different hierarchical levels according to priorities assigned to state information for the different hierarchical levels.

[0105] Table 1 provides an illustrative example of how a memory device may utilize state information to manage the operating modes of different entities at different hierarchical levels. Although Table 1 shows state information for one memory die 305, for one bank group 310X within memory die 305X, and for one memory bank 320X within bank group 310X, it should be understood that a memory device may include and maintain state information for any number of memory dies 305, bank groups 310, memory banks 320, or other entities at any number of hierarchical levels.

[0106] When the state variable for the memory die 305X is (10), the memory device can determine that the memory die 305X is in the second die-level low power mode 420-b. Thus, the memory device can operate the memory die 305X in the second die-level low power mode 420-b and can operate all entities in the memory die 305X in their respective deepest supported low power modes regardless of the state variable (denoted as "-" in Table 1, which may indicate "don't care"). Thus, the memory device can operate the bank group 310X in the group-level low power mode 415 and the memory bank 320X in the second bank low power mode 410-b.

[0107] When the state variable for the memory die 305X is (01), the memory device may determine that the memory die 305X is in the first die-level low power mode 420-a. Thus, the memory device may operate the memory die 305X in the first die-level low power mode 420-a and may operate all entities in the memory die 305X in their respective deepest supported low power modes regardless of the state variable. Thus, the memory device may operate the bank group 310X in the group-level low power mode 415 and the memory bank 320X in the second bank low power mode 410-b.

[0108] In general, when an entity at a higher hierarchical level is in a low power mode, the memory device can operate any entity therein at a lower hierarchical level according to a low power mode supported by the lower level entity. In some cases (e.g., to maximize power savings), the entity therein at the lower hierarchical level can be operated according to the deepest low power mode supported by the lower level entity. In other cases (e.g., to minimize start-up time), the entity therein at the lower hierarchical level can be operated according to the power mode supported by the lower level entity having the fastest start-up time (e.g., the shallowest low power mode supported by the lower level entity). It should be understood that the low power mode that the lower level entity can enter based on the higher level entity being powered down can be any low power mode supported by the lower level entity and can further be statically or dynamically configured.

[0109] When the state variable for the memory die 305X is (00), the memory device may determine that the memory die 305X is in the idle mode 405 (e.g., all circuits in the corresponding set of die-level circuits 307 are activated). Thus, the memory device may operate the memory die 305X in the idle mode 405 and may evaluate group-level state information for the bank groups 310 within the memory die 305X. Thus, in general, when an entity at a higher hierarchical level is in the idle mode, the state information for the entity may not affect how the memory device operates lower-level entities therein.

[0110] When the state variable for the memory die 305X is (00) and the state variable for the bank group 310X is (1), the memory device can determine that the memory die 305X is in the idle mode 405 and the bank group 310X is in the group-level low power mode 415. Thus, the memory device can operate the bank group 310X in the group-level low power mode 415 and operate all entities within the bank group 310X in their respective deepest supported low power modes, regardless of the state variables. Thus, the memory device can operate the memory bank 320X in the second bank low power mode 410-b.

[0111] When the state variable for memory die 305X is (00) and the state variable for bank group 310X is (0), the memory device can determine that memory die 305X and bank group 310X are both in idle mode 405 (e.g., all circuits in the corresponding set of die level circuits 307 and the corresponding set of group level circuits 315 are activated). Thus, the memory device can operate memory bank 320X according to the state variable for memory bank 320X - in the second bank level low power mode 410-b if the state variable for memory bank 320X is (10), in the first bank level low power mode 410-a if the state variable for memory bank 320X is (01), and in idle mode 405 if the state variable for memory bank 320X is (00). Thus, in general, when all relevant entities at a higher hierarchical level are in idle mode, the memory device can operate lower level entities therein according to the operating modes indicated by the state information for the lower level entities.

[0112] When the memory device receives a power down command that places entity X in operational mode Y (e.g., an EnterPowerDownYDieX command, an EnterPowerDownYBankGroupX command, or an EnterPowerDownYBankX command), the memory device may update state information stored by entity X to reflect state variables associated with operational mode Y, and may operate the memory device and entities therein based on the corresponding state information.

[0113] In some cases, when the memory device receives a cancel command for entity X, the memory device may switch entity X to idle mode 405 (e.g., activate circuitry for entity X at the corresponding hierarchical level), consult state information regarding any lower-level entities within entity X, and operate such lower-level entities according to the respective state information. If the memory device maintains lower-level state information that is not changed in response to a power-down command for a higher-level entity, the state information regarding such lower-level entities reflects the respective operating modes of such lower-level entities at the time the most recent power-down command for entity X was received. Thus, by operating such lower-level entities according to their respective state information, the memory device operates such lower-level entities in their respective operating modes at the time the most recent power-down command for entity X was received.

[0114] 5, when a cancel command is received for a bank group 310X, the memory device may activate a corresponding set of group-level circuits 315 depending on the state information for the memory banks 320, may switch the memory banks 320 in the bank group 310X from the second bank-level low power mode 410-b to the idle mode 405 (as indicated by transition 550-c), to the first bank-level low power mode 410-a (as indicated by transition 550-b), or may maintain the memory banks 320 in the second bank-level low power mode 410-b (as indicated by transition 550-a). If different memory banks 320 in the bank group 310X have different corresponding state variables, the memory banks 320 may be switched to different bank-level operating modes in response to the cancel command.

[0115] 5, when a cancel command is received for a memory die 305X, when the memory die 305X is in either the first die-level low power mode 420-a or the second die-level low power mode 420-b, the memory device can activate a corresponding set of die-level circuits 307. Also, for any bank groups 310 in the memory die 305X whose corresponding state variable is (1), the memory device can switch the bank group 310 to the group-level low power mode 415 (e.g., any memory banks 320 therein that can maintain the corresponding set of group-level circuits 315 when deactivated can be maintained in the second bank-level low power mode 410-b) as shown by transitions 555-a and 555-b. Alternatively, for any bank group 310 in the memory die 305X whose corresponding state variable is (0), the memory device may switch the memory bank 320 in the bank group 310X from the second bank-level low power mode 410-b to the idle mode 405 (as indicated by transitions 550-d and 550-f), to the first bank-level low power mode 410-a (as indicated by transitions 550-e and 550-f), or maintain the memory bank 320 in the second bank-level low power mode 410-b (as indicated by transitions 550-c and 555-f), depending on the state information for the memory bank 320.

[0116] Thus, in response to a cancel (remove) command, the memory device may be conceptualized as removing the device from one or more higher hierarchical level low power modes such that the lower level entities along with the memory device are operated according to their respective previous operating modes. Thus, the impact of the cancel (remove) command may depend on state information regarding each lower level entity within the higher level entity targeted by the command.

[0117] 6 illustrates another example of a state diagram 600 supporting architecture-based power management for a memory device according to embodiments disclosed herein. Aspects of state diagram 600 may be implemented by memory device 110, memory die 160, memory die 200, memory die architecture 300, state diagram 400, or state diagram 500 described with reference to FIGS. 1-5. State diagram 600 illustrates an example in which a memory device automatically switches an entity at a higher hierarchical level to a low power mode (thus powering down the device deeper from the device's perspective to a lower power mode) when at least a threshold number (e.g., all) of lower level entities within the higher level entity are operating (e.g., are individually switched into) a corresponding low power mode.

[0118] For example, the memory device can determine that all memory banks 320 in a bank group 310 are individually operating in the bank-level low power mode 410, and the memory device can automatically (e.g., without receiving an additional group-level command) switch the bank group 310 to the group-level low power mode 415 (e.g., can deactivate some or all of the set of group-level circuits 315 for the bank group 310, transition any memory banks 320 in the bank group 310 that are not already in the deepest bank-level low power mode 410 to the deepest bank-level low power mode 410).

[0119] 6, the transitions indicated by "and" between the bank-level low power mode 410 and the group-level low power mode 415 are examples of automatic transitions. The "and" blocks may represent logic operations and associated circuitry (e.g., one or more AND gates, or counter and comparator circuitry) configured to initiate an automatic transition when a threshold amount (e.g., all) of the memory banks 320 in a bank group 310 are individually operating in the bank-level low power mode 410.

[0120] As another example, the memory device can determine that all bank groups 310 in the memory die 305 are individually operating in the group-level low power mode 415, and the memory device can automatically (e.g., without receiving an additional die-level command) switch the memory die 305 to the die-level low power mode 420 (e.g., transition any bank groups 310 in the memory die 305 that are not already in the deepest group-level low power mode 415 to the deepest group-level low power mode 415, which can deactivate some or all of the set of die-level circuitry 307 for the memory die 305). In FIG. 6, the transitions indicated with "and" between the group-level low power mode 415 and the die-level low power mode 420 are examples of such transitions.

[0121] 6, individual memory banks 320 can transition between an idle mode 405 and one or more supported bank-level low power modes 410 in response to a bank-level power-down and power-up (entry / exit) command 625. Similarly, individual bank groups can transition between an idle mode 405 and one or more supported group-level low power modes 415 in response to a group-level power-down and power-up (entry / exit) command 630, and individual memory dies 305 can transition between an idle mode 405 and one or more supported die-level low power modes 420 in response to a die-level power-down and power-up (entry / exit) command 635. Thus, in general, power-down and power-up commands may be received for individual entities at any hierarchical level, which can transition entities at that hierarchical level, along with associated entities at lower or higher hierarchical levels, between operating modes, e.g., as described with reference to FIG. Additionally, an automatic transition may occur with respect to a higher level entity based on all lower level entities therein being in a low power mode.

[0122] In some cases, a memory device may support higher level low power modes but need not support higher level power down and power up commands. For example, a memory device may support bank level entry / exit commands 625 but not group level entry / exit commands 630 or die level entry / exit commands 635. In such cases, the memory device may nevertheless support group level low power mode 415 and the bank group may be switched to group level low power mode 415 based on receiving a bank level power down (entry) command 625 for all memory banks 320 of the bank group 310. Similarly, a memory device may nevertheless support die level low power mode 420 and the memory die 305 may be switched to die level low power mode 420 based on receiving a bank level power down (entry) command 625 for all memory banks 320 in all bank groups 310 of the memory die 305. The higher-level entity may then be activated (switched to idle mode 405) based on receiving a power-on command for the lower-level entity therein.

[0123] Some memory devices may support automatic transitions (e.g., as described with reference to FIG. 6) in conjunction with the cancel (delete) command described herein. In such cases, the cancel command may have no effect on (e.g., may not reverse) any transitions that occur automatically. For example, if a bank group 310 is switched to the group-level low power mode 415, a subsequently received cancel command for the bank group 310 may have no effect and the bank group 310 may be maintained in the group-level low power mode 415 (each of the memory banks 320 in the bank group 310 may also be maintained in the bank-level low power mode 410).

[0124] In some cases, to support distinguishing between low power modes entered via automatic transitions and low power modes entered via commanded transitions (e.g., to support only removing commanded transitions in response to a cancel command), the memory device may maintain additional state information (e.g., additional state variables) to store an indication of the entity's current operating mode as well as whether the current operating mode was entered via a commanded transition or an automatic transition. The memory device may store the state information in one or more registers (e.g., mode registers, status registers) or other storage devices. Table 2 may represent an example of such state information.

[0125] [Table 2]

[0126] The example of Table 2 may be for a memory device that supports one bank-level low power mode 410, one group-level low power mode 415, and one die-level low power mode 420. For each entity (e.g., each memory bank 320, bank group 310, or memory die 305), the memory device may store one operating mode variable that indicates the operating mode of the entity. For example, an operating mode variable of (0) may indicate an idle mode 405 for the entity, and an operating mode variable of (1) may indicate a low power mode for the entity. If multiple low power modes are supported at the entity's hierarchical level, the memory device may store multiple operating mode variables to indicate the operating mode of the entity.

[0127] For each entity that is not at the lowest hierarchical level (e.g., each bank group 310 or each memory die 305), the memory device may also store an additional transition variable that indicates whether the value of the operational mode variable (and therefore the operational mode) for the entity was the result of a command or an automatic transition. For example, a transition variable value of (0) may indicate that the operational mode for the entity was the result of a command, and a transition variable value of (1) may indicate that the operational mode for the entity was the result of an automatic transition.

[0128] Table 2 may show state information possibilities for one memory die 305X, one bank group 310X within the memory die 305X, and one memory bank 320X within the bank group 310X, along with the resulting operating mode for each entity. In Table 2, for a column with two state variables, the right-most state variable may be an operating mode variable and the left-most state variable may be a transition variable.

[0129] A lower level entity may be operated according to its state variables when all corresponding higher level entities are in the idle mode. Thus, for example, when the state variables for memory die 305X and bank group 310X are all zero, memory bank 320X may be in the operational mode indicated by the operational mode variable for memory bank 320X.

[0130] When a higher level entity is in command low power mode (01), the state variables for the lower level entities therein may be maintained regardless of the state variables for the lower level entities, however any lower level entities therein are in the corresponding low power mode. Thus, for example, when the state variables for bank group 310X are (01), the state variables for memory bank 320X may be maintained at "-" (don't care) for purposes of determining the operating mode of memory bank 320X, but may be commanded (used to determine) the operating mode that memory bank 320X will transition to in the event of a cancel command for bank group 310X.

[0131] When a higher level entity is in a low power mode due to an automatic transition, the operating mode variable for that higher level entity may be "don't care," and the operating mode variable for any lower level entity therein is, by definition, associated with a lower power mode for the entity (e.g., if multiple low power modes are supported for the entity, the deepest supported low power mode for that entity). Thus, for example, when the state variable for memory die 305X is (1-), the state variables for bank group 310X and memory bank 320X may be (01) and (1), respectively, or (11) and (1), respectively, and a cancel command for memory die 305X does not change the operating mode of any of memory die 305X, bank group 310X, or memory bank 320X.

[0132] 7 illustrates a block diagram 700 of a memory device 705 supporting architecture-based power management for memory devices according to embodiments disclosed herein. The memory device 705 may be an embodiment of the aspects of a memory device described with reference to FIGS. 1-6. The memory device 705 may include a command manager 710, a bank mode manager 715, a bank group mode manager 720, a die mode manager 725, and a state information manager 730. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0133] In some embodiments, the bank mode manager 715 can operate a first memory bank in the memory device in a first mode and a second memory bank in the memory device in a second mode. The command manager 710 can receive a power down command for the first memory bank in the memory device while operating the first memory bank in the first mode and the second memory bank in the second mode. The bank mode manager 715 can switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode based on the command manager 710 receiving the power down command for the first memory bank, the first low power mode corresponding to less power consumption by the first memory bank than the first mode.

[0134] In some embodiments, switching the first memory bank from the first mode to the first low power mode may include deactivating circuitry dedicated to the first memory bank.

[0135] In some embodiments, the command manager 710 can receive a second power down command for the first memory bank at the memory device while operating the first memory bank in the first low power mode. The bank mode manager 715 can switch the first memory bank from the first low power mode to a second low power mode based on the command manager 710 receiving the second power down command for the first memory bank, the second low power mode corresponding to a different amount of power consumption by the first memory bank than the first low power mode.

[0136] In some embodiments, switching the first memory bank from the first low power mode to the second low power mode may include deactivating additional circuitry dedicated to the first memory bank. In some embodiments, switching the first memory bank from the first low power mode to the second low power mode may include activating a portion of the deactivated circuitry dedicated to the first memory bank.

[0137] In some embodiments, the command manager 710 can receive a power down command for the first memory bank at the memory device while operating the first memory bank in the first low power mode. The bank mode manager 715 can switch the first memory bank from the first low power mode to an idle mode based on the command manager 710 receiving the power up command for the first memory bank, the idle mode corresponding to a greater power consumption by the first memory bank than the first low power mode. The bank group mode manager 720 can activate circuitry shared by the first memory bank and at least one other memory bank of the memory device based on the command manager 710 receiving the power up command for the first memory bank.

[0138] In some embodiments, the bank group mode manager 720 can operate a first group of memory banks in the memory device in a first mode and a second group of memory banks in the memory device in a second mode, with a first set of circuits shared by the memory banks of the first group and a second set of circuits shared by the memory banks of the second group. The command manager 710 can receive a power down command for the first group of memory banks at the memory device while operating the first group of memory banks in the first mode and the second group of memory banks in the second mode. The bank group mode manager 720 can deactivate the first set of circuits based on the command manager 710 receiving the power down command for the first group of memory banks and the bank mode manager 715 can maintain the second group of memory banks in the second mode.

[0139] In some embodiments, each memory bank of the first group of memory banks supports a set of one or more low power modes, and the bank mode manager 715 can switch each memory bank of the first group to a first low power mode of the set based on the command manager 710 receiving a power down command for the first group of memory banks. In some embodiments, each low power mode of the set corresponds to a respective power consumption level, and the first low power mode corresponds to a lower power consumption level than each other low power mode of the set.

[0140] In some embodiments, switching each memory bank of the first group to the first low power mode may include deactivating a respective set of dedicated circuitry for each memory bank of the first group.

[0141] In some embodiments, the command manager 710 can receive a power-on command for the first memory bank of the first group after deactivating the first set of circuits. The bank group mode manager 720 can activate the first set of circuits based on the command manager 710 receiving the power-on command for the first memory bank. The bank mode manager 715 can switch the first memory bank to an idle mode while maintaining the second memory bank of the first group in a first low power mode based on the command manager 710 receiving the power-on command for the first memory bank.

[0142] In some embodiments, the command manager 710 can receive a power-on command for the first group of memory banks after deactivating the first set of circuits. The bank group mode manager 720 can activate the first set of circuits based on the command manager 710 receiving the power-on command for the first group of memory banks. The bank mode manager 715 can switch each memory bank of the first group to an idle mode based on the command manager 710 receiving the power-on command for the first memory group of memory banks.

[0143] In some embodiments, the die mode manager 725 can activate a third set of circuitry shared by the first group of memory banks and the second group of memory banks based on the command manager 710 receiving a power-on command for the first group of memory banks.

[0144] In some embodiments, the command manager 710 may receive a power-on command for a memory die including a first group of memory banks and a second group of memory banks after deactivating the first set of circuits. The bank group mode manager 720 may activate the first set of circuits and the second set of circuits based on the command manager 710 receiving the power-on command for the memory die. The die mode manager 725 may activate a third set of circuits shared by the first group of memory banks and the second group of memory banks based on the command manager 710 receiving the power-on command for the memory die. The bank mode manager 715 may switch each memory bank of the first group and each memory bank of the second group to an idle mode based on the command manager 710 receiving the power-on command for the memory die.

[0145] In some embodiments, the state information manager 730 can store and update state variables indicating a respective operating mode for each memory bank of the first group based on the command manager 710 receiving a power down command for the first group of memory banks. The command manager 710 can receive a cancel command for the first group of memory banks after deactivating the first set of circuits, the cancel command reversing the power down command for the first group of memory banks. The bank mode manager 715 can access the stored state variables based on the command manager 710 receiving the cancel command, and the bank mode manager 715 can switch each memory bank of the first group to a respective operating mode based on accessing the stored state variables.

[0146] In some embodiments, bank group mode manager 720 can activate a first set of circuitry based on command manager 710 receiving a cancel command. In some embodiments, die mode manager 725 can activate a third set of circuitry shared by the first group of memory banks and the second group of memory banks based on command manager 710 receiving a cancel command.

[0147] In some embodiments, the bank group mode manager 720 can operate the first group of memory banks in a respective first mode and the second group of memory banks in a respective second mode, both of which are included in a memory die. The command manager 710 can receive a power down command for the memory die while operating the first group of memory banks in the respective first mode and the second group of memory banks in the respective second mode. The bank mode manager 715 can switch each memory bank of the first group and each memory bank of the second group to a low power mode corresponding to a lower power consumption level than at least one of the respective first mode or the respective second mode based on the command manager 710 receiving the power down command for the memory die. The bank group mode manager 720 can deactivate a set of circuitry shared by the first group of memory banks and the second group of memory banks based on the command manager 710 receiving the power down command for the memory die.

[0148] In some embodiments, the command manager 710 can receive a power-on command for the first group of memory banks while a set of circuits shared by the first group of memory banks and the second group of memory banks is deactivated. The bank mode manager 715 can switch each memory bank of the first group from the low power mode to an idle mode while maintaining each memory bank of the second group in the low power mode based on receiving the power-on command for the first group of memory banks. The bank group mode manager 720 can activate a second set of circuits shared by the memory banks of the first group while maintaining a third set of circuits shared by the memory banks of the second group deactivated based on receiving the power-on command for the first group of memory banks. The die mode manager 725 can activate a set of circuits shared by the first group of memory banks and the second group of memory banks based on receiving the power-on command for the first group of memory banks.

[0149] In some embodiments, the command manager 710 can receive a power-on command for a first memory bank of the first group of memory banks while a set of circuits shared by the first group of memory banks and the second group of memory banks is deactivated. The bank mode manager 715 can switch the first memory bank from the low power mode to an idle mode while maintaining each other memory bank of the first group and each memory bank of the second group in the low power mode based on the command manager 710 receiving the power-on command for the first memory bank. The bank group mode manager 720 can activate a second set of circuits shared by the memory banks of the first group while maintaining a third set of circuits shared by the memory banks of the second group deactivated based on the command manager 710 receiving the power-on command for the first memory bank. The die mode manager 725 can activate a set of circuits shared by the first group of memory banks and the second group of memory banks based on the command manager 710 receiving the power-on command for the first memory bank.

[0150] In some embodiments, the bank group mode manager 720 can activate a set of circuitry shared by all memory banks in a group of memory banks in a memory device. The bank group mode manager 720 can determine that a quantity of the memory banks in the group are operating in a low power mode, the low power mode being associated with a lower power consumption level than a second mode supported by each memory bank in the group. The bank group mode manager 720 can deactivate the set of circuitry shared by the group of memory banks based on determining that a quantity of the memory banks in the group are operating in the low power mode.

[0151] In some embodiments, determining that a quantity of memory banks in the group are operating in a low power mode may include determining that all memory banks in the group are operating in a low power mode.

[0152] In some embodiments, the memory device includes a set of groups of memory banks, and for each of the groups of memory banks, the memory device includes a respective set of circuitry in the set that is shared by all of the memory banks in the group of memory banks. The die mode manager 725 can operate the set of circuitry shared by all of the memory banks in the set of groups of memory banks. The die mode manager 725 can determine that the respective set of circuitry is deactivated for at least a certain amount of the groups of memory banks in the set. The die mode manager 725 can deactivate the set of circuitry shared by all of the memory banks in the set of groups of memory banks based on determining that the respective set of circuitry is deactivated for at least a certain amount of the groups of memory banks in the set. In some embodiments, determining that the respective set of circuitry is deactivated for at least a certain amount of the groups of memory banks in the set can include determining that the respective set of circuitry is deactivated for all of the groups of memory banks in the set.

[0153] In some embodiments, the set of groups of memory banks includes all groups of memory banks included on a memory die in the memory device.

[0154] In some embodiments, die mode manager 725 can activate a set of circuitry shared by all memory banks within a die of a memory device. Die mode manager 725 can determine that all memory banks within the die are operating in a low power mode. Die mode manager 725 can deactivate a set of circuitry shared by all memory banks within the die based on determining that all memory banks within the die of a memory device are operating in a low power mode.

[0155] In some embodiments, operating in the low power mode includes operating in one of a set of low power modes, each corresponding to a respective power consumption level lower than a power consumption level corresponding to the second mode, In some embodiments, the second mode includes an idle mode.

[0156] In some embodiments, state information manager 730 can store an indication that the set of circuitry shared by the group of memory banks has been deactivated based on determining that a quantity of the memory banks in the group are operating in a low power mode. After command manager 710 has deactivated the set of circuitry shared by the group of memory banks, command manager 710 can receive a cancel command for the group of memory banks that reverses a previous power down command for the group of memory banks. Die mode manager 725 can access the stored indication based on receiving the cancel command, and die mode manager 725 can maintain the set of circuitry shared by the group of memory banks as deactivated based on the stored indication.

[0157] FIG. 8 illustrates a flowchart illustrating one or more methods 800 for supporting architecture-based power management for a memory device according to aspects of the disclosure. The operations of method 800 may be performed by a memory device or components thereof described herein. For example, the operations of method 800 may be performed by a memory device described with reference to FIG. 7. In some embodiments, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use application specific hardware to perform aspects of the described functions.

[0158] At 805, the memory device may operate a first memory bank in the memory device in a first mode and a second memory bank in the memory device in a second mode. The operations of 805 may be performed according to methods described herein. In some embodiments, aspects of the operations of 805 may be performed by a bank mode manager as described with reference to FIG.

[0159] At 810, while the memory device is operating the first memory bank in a first mode and the second memory bank in a second mode, a power down command for the first memory bank may be received at the memory device. The operations of 810 may be performed according to methods described herein. In some embodiments, aspects of the operations of 810 may be performed by a command manager such as described with reference to FIG.

[0160] At 815, the memory device may switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode based on receiving a power down command for the first memory bank, the first low power mode corresponding to less power consumption by the first memory bank than the first mode. The operations of 815 may be performed according to methods described herein. In some embodiments, aspects of the operations of 815 may be performed by a bank mode manager as described with reference to FIG. 7.

[0161] In some examples, an apparatus described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for operating a first memory bank in a memory device in a first mode and a second memory bank in the memory device in a second mode, receiving, at the memory device, a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode, and switching the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode based on receiving the power down command for the first memory bank, the first low power mode corresponding to less power consumption by the first memory bank than the first mode.

[0162] In some embodiments of the method 800 and apparatus described herein, switching the first memory bank from the first mode to the first low power mode may include deactivating circuitry dedicated to the first memory bank.

[0163] Some embodiments of the method 800 and apparatus described herein may further include operations, features, means, or instructions for receiving, at the memory device, a second power down command for the first memory bank while operating the first memory bank in the first low power mode, and switching the first memory bank from the first low power mode to a second low power mode based on receiving the second power down command for the first memory bank, the second power mode corresponding to a different amount of power consumption by the first memory bank than the first low power mode.

[0164] In some embodiments of the method 800 and apparatus described herein, switching the first memory bank from the first low power mode to the second low power mode may include deactivating additional circuitry dedicated to the first memory bank or may include activating a portion of the deactivated circuitry dedicated to the first memory bank.

[0165] Some embodiments of the method 800 and apparatus described herein may further include operations, features, means, or instructions for receiving, at the memory device, a power-on command for the first memory bank while operating the first memory bank in the first low power mode, and switching the first memory bank from the first low power mode to an idle mode based on receiving the power-on command for the first memory bank, the idle mode corresponding to an amount of power consumption by the first memory bank that is greater than the first low power mode.

[0166] Some embodiments of the method 800 and apparatus described herein may further include an operation, feature, means, or instruction for activating circuitry shared by the first memory bank and at least one other memory bank of the memory device based on receiving a power-on command for the first memory bank.

[0167] FIG. 9 illustrates a flowchart illustrating one or more methods 900 for supporting architecture-based power management for a memory device according to aspects of the disclosure. The operations of method 900 may be performed by a memory device or components thereof described herein. For example, the operations of method 900 may be performed by a memory device described with reference to FIG. 7. In some embodiments, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use application specific hardware to perform aspects of the described functions.

[0168] At 905, the memory device can operate a first group of memory banks in the memory device in a first mode and a second group of memory banks in the memory device in a second mode, where the first set of circuits is shared by the memory banks of the first group and the second set of circuits is shared by the memory banks of the second group. The operations of 905 can be performed according to methods described herein. In some embodiments, aspects of the operations of 905 can be performed by a bank mode manager as described with reference to FIG. 7.

[0169] At 910, while the memory device is operating the first group of memory banks in a first mode and the second group of memory banks in a second mode, the memory device may receive a power down command for the first group of memory banks. The operations of 910 may be performed according to methods described herein. In some embodiments, aspects of the operations of 910 may be performed by a command manager such as described with reference to FIG. 7.

[0170] At 915, the memory device may deactivate the first set of circuits while maintaining the second group of memory banks in the second mode based on receiving a power down command for the first group of memory banks. The operations of 915 may be performed according to methods described herein. In some examples, aspects of the operations of 915 may be performed by a bank group mode manager or a bank mode manager as described with reference to FIG.

[0171] In some examples, an apparatus described herein may perform one or more methods, such as method 900. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for operating a first group of memory banks in a memory device in a first mode and a second group of memory banks in the memory device in a second mode, where a first set of circuits is shared by the memory banks of the first group and a second set of circuits is shared by the memory banks of the second group, receiving, at the memory device while operating the first group of memory banks in the first mode and the second group of memory banks in the second mode, a power down command for the first group of memory banks, and deactivating the first set of circuits while maintaining the second group of memory banks in the second mode based on receiving the power down command for the first group of memory banks.

[0172] In some embodiments of the method 900 and apparatus described herein, each memory bank of the first group of memory banks may support a set of one or more low power modes. The method 900 and apparatus described herein may further include an operation, feature, means, or instruction for switching each memory bank of the first group to a first low power mode of the set based on receiving a power down command for the first group of memory banks.

[0173] In some embodiments of the method 900 and apparatus described herein, switching each memory bank of the first group to the first low power mode may include deactivating a respective set of dedicated circuitry for each memory bank of the first group.

[0174] In some embodiments of the method 900 and the apparatus described herein, each low power mode of the set corresponds to a respective power consumption level, and the first low power mode corresponds to a lower power consumption level than each other low power mode of the set.

[0175] Some embodiments of the method 900 and apparatus described herein may further include operations, features, means, or instructions for receiving a power-on command for a first memory bank of the first group after deactivating the first set of circuits, activating the first set of circuits based on receiving the power-on command for the first memory bank, and switching the first memory bank to an idle mode while maintaining a second memory bank of the first group in a first low power mode based on receiving the power-on command for the first memory bank.

[0176] Some embodiments of the method 900 and apparatus described herein may further include operations, features, means, or instructions for receiving a power-on command for the first group of memory banks after deactivating the first set of circuits, activating the first set of circuits based on receiving the power-on command for the first group of memory banks, and switching each memory bank of the first group to an idle mode based on receiving the power-on command for the first memory group of memory banks.

[0177] Some embodiments of the method 900 and apparatus described herein may further include an operation, feature, means, or instruction for activating a third set of circuitry that may be shared by the first group of memory banks and the second group of memory banks based on receiving a power-on command for the first group of memory banks.

[0178] Some embodiments of method 900 and apparatus described herein may further include operations, features, means, or instructions for receiving a power-on command for a memory die including a first group of memory banks and a second group of memory banks after deactivating the first set of circuits, activating the first set of circuits and the second set of circuits based on receiving the power-on command for the memory die, activating a third set of circuits that may be shared by the first group of memory banks and the second group of memory banks based on receiving the power-on command for the first group of memory banks, and switching each memory bank of the first group and each memory bank of the second group to an idle mode based on receiving the power-on command for the memory die.

[0179] Some embodiments of method 900 and apparatus described herein may further include operations, features, means, or instructions for storing and updating state variables indicative of a respective operating mode for each memory bank of the first group based on receiving a power down command for the first group of memory banks; receiving a cancel command for the first group of memory banks after deactivating the first set of circuits, the cancel command reversing the power down command for the first group of memory banks; accessing the stored state variables based on receiving the cancel command; and switching each memory bank of the first group to a respective operating mode based on accessing the stored state variables.

[0180] Some embodiments of the method 900 and apparatus described herein may further include an operation, feature, means, or instruction for activating the first set of circuits based on receiving the cancel command.

[0181] Some embodiments of the method 900 and apparatus described herein may further include an operation, feature, means, or instruction for activating a third set of circuitry that may be shared by the first group of memory banks and the second group of memory banks based on receiving the revocation command.

[0182] FIG. 10 illustrates a flowchart illustrating one or more methods 1000 of supporting architecture-based power management for a memory device according to aspects of the disclosure. The operations of method 1000 may be performed by a memory device or components thereof described herein. For example, the operations of method 1000 may be performed by a memory device described with reference to FIG. 7. In some embodiments, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use application specific hardware to perform aspects of the described functions.

[0183] At 1005, the memory device can operate a first group of memory banks in a respective first mode and a second group of memory banks in a respective second mode, both of which are included on a memory die. The operations of 1005 can be performed according to methods described herein. In some embodiments, aspects of the operations of 1005 can be performed by a bank mode manager as described with reference to FIG. 7.

[0184] At 1010, the memory device may receive a power down command for the memory die while operating a first group of memory banks in a respective first mode and a second group of memory banks in a respective second mode. The operation of 1010 may be performed according to methods described herein. In some embodiments, aspects of the operation of 1010 may be performed by a command manager such as described with reference to FIG.

[0185] At 1015, the memory device may switch each memory bank of the first group and each memory bank of the second group to a low power mode corresponding to a lower power consumption level than at least one of the respective first mode or the respective second mode based on receiving a power down command for the memory die. The operations of 1015 may be performed according to methods described herein. In some examples, aspects of the operations of 1015 may be performed by a bank mode manager as described with reference to FIG.

[0186] At 1020, the memory device may deactivate a set of circuitry shared by the first group of memory banks and the second group of memory banks based on receiving a power down command for the memory die. The operations of 1020 may be performed according to methods described herein. In some embodiments, aspects of the operations of 1020 may be performed by a die mode manager as described with reference to FIG.

[0187] In some examples, an apparatus described herein may perform one or more methods, such as method 1000. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for operating a first group of memory banks in a respective first mode and a second group of memory banks in a respective second mode, where both the first group of memory banks and the second group of memory banks are included in a memory die; receiving a power-down command for the memory die while operating the first group of memory banks in their respective first modes and the second group of memory banks in their respective second modes; switching each memory bank of the first group and each memory bank of the second group to a low power mode corresponding to a lower power consumption level than at least one of the respective first mode or the respective second mode based on receiving the power-down command for the memory die; and deactivating a set of circuitry shared by the first group of memory banks and the second group of memory banks based on receiving the power-down command for the memory die.

[0188] Some embodiments of the method 1000 and apparatus described herein may further include operations, features, means, or instructions for receiving a power-on command for the first group of memory banks while a set of circuits shared by the first group of memory banks and the second group of memory banks may be deactivated; switching each memory bank of the first group from the low power mode to an idle mode while maintaining each memory bank of the second group in the low power mode based on receiving the power-on command for the first group of memory banks; activating a second set of circuits shared by the memory banks of the first group while keeping a third set of circuits shared by the memory banks of the second group deactivated based on receiving the power-on command for the first group of memory banks; and activating the set of circuits shared by the first group of memory banks and the second group of memory banks based on receiving the power-on command for the first group of memory banks.

[0189] Some embodiments of the method 1000 and apparatus described herein may further include operations, features, means, or instructions for receiving a power-on command for a first memory bank of the first group of memory banks while a set of circuits shared by the first group of memory banks and the second group of memory banks may be deactivated; switching the first memory bank from the low power mode to an idle mode while maintaining each other memory bank of the first group and each memory bank of the second group in the low power mode based on receiving the power-on command for the first memory bank; activating a second set of circuits shared by the memory banks of the first group while maintaining a third set of circuits shared by the memory banks of the second group as deactivated based on receiving the power-on command for the first memory bank; and activating the set of circuits shared by the first group of memory banks and the second group of memory banks based on receiving the power-on command for the first memory bank.

[0190] FIG. 11 illustrates a flowchart illustrating one or more methods 1100 of supporting architecture-based power management for a memory device according to aspects of the disclosure. The operations of method 1100 may be performed by a memory device or components thereof described herein. For example, the operations of method 1100 may be performed by a memory device described with reference to FIG. 7. In some embodiments, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use application specific hardware to perform aspects of the described functions.

[0191] At 1105, the memory device may operate a set of circuitry shared by all memory banks in a group of memory banks in the memory device. The operations of 1105 may be performed according to methods described herein. In some embodiments, aspects of the operations of 1105 may be performed by a bank group mode manager as described with reference to FIG.

[0192] At 1110, the memory device may determine that a quantity of memory banks in a group are operating in a low power mode, the low power mode being associated with a lower power consumption level than a second mode supported by each memory bank in the group. The operations of 1110 may be performed according to methods described herein. In some embodiments, aspects of the operations of 1110 may be performed by a bank group mode manager as described with reference to FIG.

[0193] At 1115, the memory device may deactivate a set of circuitry shared by a group of memory banks based on determining that a quantity of the memory banks in the group are operating in a low power mode. The operations of 1115 may be performed according to methods described herein. In some embodiments, aspects of the operations of 1115 may be performed by a bank group mode manager as described with reference to FIG.

[0194] In some examples, an apparatus described herein may perform one or more methods, such as method 1100. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for operating a set of circuitry shared by all memory banks in a group of memory banks in a memory device, determining that a quantity of the memory banks in the group are operating in a low power mode, the low power mode being associated with a lower power consumption level than a second mode supported by each memory bank in the group, and deactivating the set of circuitry shared by the group of memory banks based on determining that a quantity of the memory banks in the group are operating in the low power mode.

[0195] In some embodiments of the method 1100 and apparatus described herein, determining that a certain amount of memory banks in the group are operating in the low power mode may include determining that all memory banks in the group are operating in the low power mode.

[0196] Some embodiments of the method 1100 and apparatus described herein may further include operations, features, means, or instructions for operating a set of circuitry shared by all memory banks in the set of groups of memory banks, determining that each set of circuitry is deactivated for at least a certain amount of the group of memory banks in the set, and deactivating the set of circuitry shared by all memory banks in the set of groups of memory banks based on determining that each set of circuitry is deactivated for at least that certain amount of the group of memory banks in the set.

[0197] In some embodiments of method 1100 and the apparatus described herein, determining that each set of circuits is deactivated for at least a certain amount of groups of memory banks in the set may include determining that each set of circuits is deactivated for all groups of memory banks in the set.

[0198] In some embodiments of the method 1100 and apparatus described herein, the set of groups of memory banks includes all groups of memory banks included on a memory die in the memory device.

[0199] Some embodiments of the method 1100 and apparatus described herein may further include operations, features, means, or instructions for operating a set of circuitry shared by all memory banks within a die of the memory device, determining that all memory banks within the die are operating in a low power mode, and deactivating the set of circuitry shared by all memory banks within the die based on determining that all memory banks within the die of the memory device are operating in a low power mode.

[0200] In some embodiments of method 1100 and the apparatus described herein, operating in the low power mode may include operating in any of a set of low power modes, each corresponding to a respective power consumption level that may be lower than the power consumption level corresponding to the second mode.

[0201] In some embodiments of the method 1100 and apparatus described herein, the second mode is an idle mode.

[0202] Some embodiments of the method 1100 and apparatus described herein may further include operations, features, means, or instructions for storing an indication that the set of circuitry shared by the group of memory banks has been deactivated based on determining that a certain amount of memory banks in the group are operating in a low power mode; receiving a cancel command for the group of memory banks after deactivating the set of circuitry shared by the group of memory banks, the cancel command reversing a previous power down command for the group of memory banks; accessing the stored indication based on receiving the cancel command; and maintaining the set of circuitry shared by the group of memory banks deactivated based on the stored indication.

[0203] It should be noted that the methods described herein are possible implementations, and that the acts and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, parts from two or more of the methods may be combined.

[0204] An apparatus is described. The apparatus may include a memory device, which may include a set of memory banks each supporting an idle mode, and a set of one or more low power modes corresponding to lower power consumption than the idle mode. The apparatus may further include a set of dedicated circuits, each specific to a respective memory bank of the set, a set of shared circuits, each shared by a respective group of the memory banks of the set, a controller coupled to the set of memory banks, the set of dedicated circuits, and the set of shared circuits. The controller may be configured to cause the apparatus to switch the memory banks of the set to a set first low power mode after the memory device receives a power down command specific to the memory banks. The controller may be further configured to cause the apparatus to switch all memory banks of the group of memory banks that includes the memory bank to the set first low power mode, and to deactivate the set of shared circuits of the set shared by the group of memory banks after the memory device receives a power down command specific to the group of memory banks.

[0205] In some embodiments, the controller may be further configured to cause the apparatus to switch the memory bank to an idle mode after the memory device receives a power-on command specific to the memory bank, switch all memory banks of the group of memory banks to the idle mode, and activate the set of shared circuitry after the memory device receives a power-on command specific to the group of memory banks.

[0206] In some embodiments, the controller may be further configured to cause the apparatus to activate the set of shared circuits after the memory device receives a power-on command specific to the memory bank.

[0207] Some embodiments of the apparatus may include a set of one or more registers configured to store an indication of a respective operating mode for the set of memory banks and an indication of a respective activation state for a set of the multiple sets of shared circuitry. The controller may be further configured to cause the apparatus to maintain the indication of the respective operating mode and the indication of the respective activation state in the set of one or more registers after the memory device receives a power-down command specific to the group of memory banks. The controller may be further configured to cause the apparatus to identify the respective operating modes and the respective activation states based at least in part on accessing the set of registers after the memory device receives a cancel command specific to the group of memory banks, the cancel command reversing a previous power-down command specific to the group of memory banks, and to switch all memory banks of the group of memory banks to the respective operating modes and operate the multiple sets of shared circuitry according to the respective activation states.

[0208] In some embodiments, the controller may be further configured to cause the device to monitor whether all memory banks of the group of memory banks are in a set low power mode, and to deactivate a set of shared circuitry shared by the group of memory banks based on identifying all memory banks of the group of memory banks being in the low power mode.

[0209] Some embodiments may further include a set of one or more registers configured to store a respective indication of whether the set of shared circuitry has been deactivated based on identifying all memory banks of the group of memory banks being in the low power mode, wherein the controller may be further configured to cause the apparatus to identify the respective indication based at least in part on accessing the set of registers and to maintain the set of shared circuitry deactivated based at least in part on identifying the respective indication after the memory device receives a cancel command specific to the group of memory banks, the cancel command reversing a previous power down command specific to the group of memory banks.

[0210] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Although some drawings may show a signal as a single signal, those skilled in the art will understand that a signal may represent a bus of signals, and that the bus may have various bit widths.

[0211] The terms "electronic communication," "conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with one another (or in conductive contact or connected or coupled) if there exists any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with one another (or in conductive contact or connected or coupled) can be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intermediate components, such as switches, transistors, or other components. In some cases, the flow of signals between connected components can be temporarily interrupted using one or more intermediate components, such as, for example, switches or transistors.

[0212] The term "coupled" refers to a state of moving from an open circuit relationship between components, where signals cannot currently be communicated between the components via conductive paths, to a closed circuit relationship between the components, where signals can be communicated between the components via conductive paths. When a component, such as a controller, couples other components together, it initiates changes that can allow signals to flow between the other components via conductive paths where signals previously could not flow.

[0213] The term "isolated" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch positioned between them are isolated from one another when the switch is open. When a controller isolates two components from one another, the controller affects a change that causes signals to no longer flow between the components using a conductive path that previously allowed signals to flow.

[0214] The term "layer" as used herein refers to a stratum or sheet of a geometric structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure, e.g., a thin film, in which two dimensions are greater than the third dimension. A layer may include different elements, components, and / or materials. In some cases, a layer may be composed of two or more sublayers. In some of the accompanying figures, two dimensions of a three-dimensional layer are shown for illustrative purposes.

[0215] As used herein, the term "electrode" may refer to an electrical conductor and, in some cases, may be used as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of a memory array.

[0216] Devices including memory arrays discussed herein can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or subregions of the substrate, can be controlled through doping using various species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation or any other doping means during the initial formation or growth of the substrate.

[0217] The switching components or transistors discussed herein may represent field effect transistors (FETs), which include three terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic elements via conductive materials, e.g., metals. The source and drain may be conductive and may include highly doped, e.g., degenerate semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The conductivity of the channel may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, may result in the channel being conductive. A transistor is "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor is "off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0218] The description set forth herein in conjunction with the accompanying drawings illustrates exemplary configurations and does not represent every example that may be implemented or is within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and does not mean "preferred" or "advantageous over other examples." The detailed description includes specific details for the purposes of understanding the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0219] In the accompanying drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. When only a first reference label is used in the specification, the description may apply to any one of the similar components having the same first reference label, regardless of the second reference label.

[0220] The various example blocks and modules described in connection with the disclosure herein may be implemented or executable by a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in association with a DSP core, or any other such configuration).

[0221] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. When implemented in software executed by a processor, the functions may be stored or transmitted as one or more instructions or codes on a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the accompanying claims. For example, due to the nature of software, the functions described may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The mechanisms that implement the functions may be physically located in various locations, including being distributed such that some of the functions are implemented in different physical locations. Also, as used herein, including the claims, "or" used in a list of items (e.g., a list of items prefaced with phrases such as "at least one of" or "one or more") indicates an inclusive list, such as, for example, a list of at least one of A, B, or C means A, or B, or C, or AB, or AC, or BC, or ABC (i.e., A and B and C). Also, the phrase "based on" as used herein should not be construed as expressing a closed set of conditions. For example, an example step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted the same as the phrase "based at least in part on."

[0222] Computer-readable media includes both non-transitory computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media may be any available medium accessible by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, Electrically Erasable Programmable Read-Only Memory (EEPROM), Compact Disk (CD) ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer, or a general purpose or special purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included within the definition of media. As used herein, disk and disc include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while discs reproduce data optically by means of a laser. Combinations of the above are also included within the scope of computer-readable media.

[0223] The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method by a memory device, comprising: operating a first memory bank in the memory device in a first mode and operating a second memory bank in the memory device in a second mode; receiving, at the memory device, a power down command having a first index associated with a plurality of low power modes and a second index associated with a plurality of memory banks of the memory device, the first index having a first value corresponding to a first low power mode of the plurality of low power modes and the second index having a second value corresponding to the second memory bank; switching the second memory bank from the second mode to the first low power mode of the plurality of low power modes based at least in part on the power down command having the first index and the second index; receiving, at the memory device, a power-on command having a third index associated with the plurality of memory banks, the third index having the second value corresponding to the second memory bank; switching the second memory bank from the first low power mode to the second mode of the plurality of low power modes based at least in part on the power-on command having the third index; The method includes:

2. operating a third memory bank in the memory device in the second mode; switching the third memory bank from the second mode to the first low power mode based at least in part on receiving the power down command; The method of claim 1 further comprising:

3. switching the third memory bank from the first low power mode to the second mode based at least in part on receiving the power-on command; The method of claim 2 further comprising:

4. The method of claim 1 , wherein the first low power mode is associated with less power consumption than the second mode.

5. 2. The method of claim 1, wherein the first mode is associated with greater power consumption than the first low power mode and less power consumption than the second mode.

6. 2. The method of claim 1 , wherein operating the second memory bank in the second mode comprises operating the second memory bank in an idle mode, and operating the first memory bank in the first mode comprises operating the first memory bank in an active mode.

7. 10. The method of claim 1, wherein the first memory bank and the second memory bank are in a dynamic random access memory (DRAM) device.

8. A memory device, comprising: a first memory bank and a second memory bank; one or more controllers coupled to the first memory bank and the second memory bank; The one or more controllers: operating the first memory bank in a first mode and operating the second memory bank in a second mode; receiving, at the memory device, a power down command having a first index associated with a plurality of low power modes and a second index associated with a plurality of memory banks of the memory device, the first index having a first value corresponding to a first low power mode of the plurality of low power modes and the second index having a second value corresponding to the second memory bank; switching the second memory bank from the second mode to the first low power mode of the plurality of low power modes based at least in part on the power down command having the first index and the second index; receiving, at the memory device, a power-on command having a third index associated with the plurality of memory banks, the third index having the second value corresponding to the second memory bank; switching the second memory bank from the first low power mode to the second mode based at least in part on the power-on command having the third index; The memory device is configured to cause the memory device to perform the following:

9. The one or more controllers: operating a third memory bank in the memory device in the second mode; switching the third memory bank from the second mode to the first low power mode based at least in part on receiving the power down command; The memory device of claim 8 , further configured to cause the memory device to:

10. The one or more controllers: switching the third memory bank from the first low power mode to the second mode based at least in part on receiving the power-on command; The memory device of claim 9 , further configured to cause the memory device to:

11. The memory device of claim 8 , wherein the first low power mode is associated with less power consumption than the second mode.

12. 9. The memory device of claim 8, wherein the first mode is associated with greater power consumption than the first low power mode and less power consumption than the second mode.

13. 9. The memory device of claim 8, wherein operating the second memory bank in the second mode comprises operating the second memory bank in an idle mode, and operating the first memory bank in the first mode comprises operating the first memory bank in an active mode.

14. 9. The memory device of claim 8, wherein the first memory bank and the second memory bank are in a dynamic random access memory (DRAM) device.

15. A non-transitory computer readable medium storing code including instructions that, when executed by one or more processors of an electronic device, operating a first memory bank in a memory device in a first mode and operating a second memory bank in the memory device in a second mode; receiving, at the memory device, a power down command having a first index associated with a plurality of low power modes and a second index associated with a plurality of memory banks of the memory device, the first index having a first value corresponding to a first low power mode of the plurality of low power modes and the second index having a second value corresponding to the second memory bank; switching the second memory bank from the second mode to the first low power mode of the plurality of low power modes based at least in part on the power down command having the first index and the second index; receiving, at the memory device, a power-on command having a third index associated with the plurality of memory banks, the third index having the second value corresponding to the second memory bank; switching the second memory bank from the first low power mode to the second mode of the plurality of low power modes based at least in part on the power-on command having the third index; A non-transitory computer-readable medium that causes the electronic device to perform the steps of:

16. The instructions, when executed by the one or more processors of the electronic device, operating a third memory bank in the memory device in the second mode; switching the third memory bank from the second mode to the first low power mode based at least in part on receiving the power down command; 20. The non-transitory computer-readable medium of claim 15, further causing the electronic device to:

17. The instructions, when executed by the one or more processors of the electronic device, switching the third memory bank from the first low power mode to the second mode based at least in part on receiving the power-on command; 20. The non-transitory computer-readable medium of claim 16, further causing the electronic device to:

18. 16. The non-transitory computer-readable medium of claim 15, wherein the first low power mode is associated with less power consumption than the second mode.

19. 16. The non-transitory computer-readable medium of claim 15, wherein the first mode is associated with greater power consumption than the first low power mode and less power consumption than the second mode.

20. 16. The non-transitory computer-readable medium of claim 15, wherein operating the second memory bank in the second mode comprises operating the second memory bank in an idle mode, and operating the first memory bank in the first mode comprises operating the first memory bank in an active mode.

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