Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device with excellent reliability, and a manufacturing method for a semiconductor device that can be manufactured at low cost.SOLUTION: A semiconductor device includes a substrate, an oxide semiconductor layer on the substrate, a gate insulating layer on the oxide semiconductor layer, a metal oxide layer on the gate insulating layer, and a gate electrode on the metal oxide layer. A first side surface of the metal oxide layer protrudes from a second side surface of the gate electrode in a plan view. The oxide semiconductor layer is formed on the substrate, the gate insulating film is formed on the oxide semiconductor layer, the metal oxide film is formed on the gate insulating film, a metal film is formed on the metal oxide film, resist is formed on the metal film, and the gate electrode and the metal oxide layer are formed by continuously wet-etching the metal film and the metal oxide film using the resist as a mask.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor device including an oxide semiconductor. Also, an embodiment of the present invention relates to a method for manufacturing a semiconductor device including an oxide semiconductor. [Background technology]

[0002] In recent years, development of transistors (semiconductor devices) using oxide semiconductors in the semiconductor layer instead of amorphous silicon, low-temperature polysilicon, or single crystal silicon has been progressing (for example, Patent Document 1). Semiconductor devices using oxide semiconductors can be manufactured with a simple structure and low-temperature process, similar to semiconductor devices using amorphous silicon in the semiconductor layer. It is also known that semiconductor devices using oxide semiconductors have higher mobility than semiconductor devices using amorphous silicon in the semiconductor layer. It is also known that semiconductor devices using oxide semiconductors in the semiconductor layer have a very low off-current. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication 2016-197708 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device including an oxide semiconductor, hydrogen or water penetrating into the oxide semiconductor causes a change in the properties of the oxide semiconductor. Therefore, in order to improve the reliability of the semiconductor device, it has been necessary to improve the coverage of the insulating layer covering the oxide semiconductor layer. In addition, in order to manufacture a semiconductor device including an oxide semiconductor at low cost, it has been desired to repurpose a manufacturing line for a semiconductor device including amorphous silicon. That is, even in a semiconductor device including an oxide semiconductor, it has been necessary to wet etch a metal film using a large-area substrate.

[0005] An object of an embodiment of the present invention is to provide a semiconductor device having excellent reliability. Another object of an embodiment of the present invention is to provide a method for manufacturing a semiconductor device that can be manufactured at low cost. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a substrate, an oxide semiconductor layer on the substrate, a gate insulating layer on the oxide semiconductor layer, a metal oxide layer on the gate insulating layer, and a gate electrode on the metal oxide layer, and a first side surface of the metal oxide layer protrudes from a second side surface of the gate electrode in a plan view.

[0007] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming an oxide semiconductor layer on a substrate, forming a gate insulating film on the oxide semiconductor layer, forming a metal oxide film on the gate insulating film, forming a metal film on the metal oxide film, forming a resist on the metal film, and successively wet-etching the metal film and the metal oxide film using the resist as a mask, thereby forming a gate electrode and a metal oxide layer. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic enlarged cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 3A] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3B] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3C] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3D] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3E]1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3F] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3G] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 5A] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5B] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. However, the present invention can be implemented in various forms without departing from the gist of the present invention, and should not be interpreted as being limited to the description of the embodiments exemplified below. In addition, in the drawings, the width, thickness, shape, etc. of each part may be shown in a schematic manner compared to the actual form in order to make the explanation clearer, but these schematic drawings are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements that are the same or similar to those described in the previous drawings may be given the same reference numerals, and duplicate explanations may be omitted.

[0010] In the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer.

[0011] In this specification, expressions such as "above" and "below" in describing the drawings express the relative positional relationship between a structure of interest and other structures. In this specification, the direction from a first substrate to a pixel electrode, which will be described later, is defined as "above" in a side view, and the opposite direction is defined as "below". In this specification and the claims, when expressing a mode in which another structure is disposed on a certain structure, the term "above" is used to include both a case in which another structure is disposed directly above the certain structure so as to be in contact with the certain structure, and a case in which another structure is disposed above the certain structure via another structure, unless otherwise specified.

[0012] First Embodiment [1. Configuration of Semiconductor Device 10] The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to FIGS.

[0013] Fig. 1 is a schematic cross-sectional view showing a configuration of a semiconductor device 10 according to one embodiment of the present invention. As shown in Fig. 1, the semiconductor device 10 includes a substrate 100, a light-shielding layer 110, a first insulating layer 120, an oxide semiconductor layer 130, a gate insulating layer 140, a metal oxide layer 150, a gate electrode 160, a second insulating layer 170, a source electrode 180, and a drain electrode 190.

[0014] The light-shielding layer 110 is provided on the substrate 100. The first insulating layer 120 covers the side and upper surface of the light-shielding layer 110 and is provided on the substrate 100 and the light-shielding layer 110. The oxide semiconductor layer 130 is provided on the first insulating layer 120. The oxide semiconductor layer 130 includes a channel region 131 overlapping with the gate insulating layer 140 and a high-concentration impurity region 132 not overlapping with the gate insulating layer 140. The gate insulating layer 140 is provided on the oxide semiconductor layer 130. The metal oxide layer 150 is provided on the gate insulating layer 140. The gate electrode 160 is provided on the metal oxide layer 150. The second insulating layer 170 covers the side surface of the gate insulating layer 140, the side surface of the metal oxide layer 150, and the side surface and the upper surface of the gate electrode 160, and is provided on the first insulating layer 120, the oxide semiconductor layer 130, the gate insulating layer 140, the metal oxide layer 150, and the gate electrode 160. The second insulating layer 170 is provided with an opening that exposes a part of the upper surface of the oxide semiconductor layer 130 (more specifically, the high-concentration impurity region 132). The source electrode 180 and the drain electrode 190 are provided in the opening of the second insulating layer 170 and on the second insulating layer 170. The source electrode 180 and the drain electrode 190 are in contact with the high-concentration impurity region 132 of the oxide semiconductor layer 130 through the opening of the second insulating layer 170. Therefore, the source electrode 180 and the drain electrode 190 are electrically connected to the oxide semiconductor layer 130.

[0015] The semiconductor device 10 has an oxide semiconductor layer 130 below a gate insulating layer 140, and has a gate electrode 160 above the gate insulating layer 140. In other words, the semiconductor device 10 is a so-called top-gate transistor.

[0016] The substrate 100 may be, for example, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate. The substrate 100 may also be a rigid substrate having no light-transmitting properties, such as a silicon substrate. The substrate 100 may also be a flexible substrate having light-transmitting properties, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate. In order to improve the heat resistance of the substrate 100, impurities may be introduced into the above-mentioned resin substrate. The substrate 100 may also be a substrate in which a silicon oxide film or a silicon nitride film is formed on the above-mentioned rigid substrate or flexible substrate.

[0017] The light-shielding layer 110 can reflect or absorb external light. The light-shielding layer 110 is provided with an area larger than the channel region 131 of the oxide semiconductor layer 130, and can therefore block external light incident on the channel region 131. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy or compound thereof can be used as the light-shielding layer 110. Furthermore, when electrical conductivity is not required, the light-shielding layer 110 does not necessarily need to contain a metal. For example, a black matrix made of a black resin can be used. Furthermore, the light-shielding layer 110 can have not only a single-layer structure but also a laminated structure. For example, the light-shielding layer 110 can have a laminated structure of a red color filter, a green color filter, and a blue color filter.

[0018] The first insulating layer 120 can prevent diffusion of impurities into the oxide semiconductor layer 130. That is, the first insulating layer 120 can function as a so-called undercoat layer. For example, silicon oxide or silicon nitride can be used as the first insulating layer 120. The first insulating layer 120 can have not only a single-layer structure but also a multilayer structure. Note that the first insulating layer 120 may not be provided.

[0019] The oxide semiconductor layer 130 can form a channel. For example, an oxide semiconductor such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium aluminum zinc oxide (IAZO), or zinc oxide (ZnO) can be used as the oxide semiconductor layer 130. Note that the oxide semiconductor layer 130 is preferably an oxide semiconductor containing indium.

[0020] The gate insulating layer 140 may be made of, for example, silicon oxide, silicon nitride, aluminum oxide, or aluminum nitride.

[0021] The metal oxide layer 150 can supply oxygen to the oxide semiconductor layer 130 through the gate insulating layer 140, or can prevent oxygen from being extracted from the oxide semiconductor layer 130 through the gate insulating layer 140. For example, the above-mentioned oxide semiconductors or oxide conductors such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or gallium zinc oxide (GZO) can be used as the metal oxide layer 150. Hereinafter, for convenience, the oxide semiconductor and oxide conductor constituting the metal oxide layer may be described as metal oxides.

[0022] The gate electrode 160 may be, for example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof. The gate electrode 160 may have not only a single-layer structure but also a laminated structure. The gate electrode 160 preferably contains aluminum, and preferably has, for example, a laminated structure of molybdenum / aluminum / molybdenum. That is, it is preferable that a molybdenum film is provided in contact with the metal oxide layer 150, and an aluminum film is provided on the molybdenum film.

[0023] The second insulating layer 170 can reduce external influences (e.g., moisture). The second insulating layer 170 can function as a so-called protective layer. For example, silicon oxide or silicon nitride can be used as the second insulating layer 170. The second insulating layer 170 can have not only a single-layer structure but also a multilayer structure.

[0024] Each of the source electrode 180 and the drain electrode 190 may be made of, for example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof. Each of the source electrode 180 and the drain electrode 190 may have not only a single-layer structure but also a multilayer structure. Each of the source electrode 180 and the drain electrode 190 may have a structure similar to that of the gate electrode 160.

[0025] 2 is a schematic enlarged cross-sectional view showing the configuration of a semiconductor device 10 according to one embodiment of the present invention, specifically, an enlarged view of a region A shown in FIG.

[0026] The side surface of the metal oxide layer 150 protrudes from the side surface of the gate electrode 160 in a plan view. The taper angle α (the angle between the lower surface and the side surface of the metal oxide layer 150) of the side surface of the metal oxide layer 150 is smaller than the taper angle β (the angle between the lower surface and the side surface of the gate electrode 160) of the side surface of the gate electrode 160. That is, the side surface of the metal oxide layer 150 has a gentler inclination than the side surface of the gate electrode 160. Therefore, the coverage performance of the second insulating layer 170 covering the side surface of the metal oxide layer 150 and the side surface of the gate electrode 160 is improved. As a result, moisture that penetrates into the oxide semiconductor layer 130 through the second insulating layer 170 is suppressed, and the reliability of the semiconductor device 10 can be improved.

[0027] The taper angle α is, for example, 30° or more and 70° or more. If the taper angle α is too small, the gate insulating layer 140 becomes large, making it difficult to miniaturize the semiconductor device 10. Also, if the taper angle α is too large, the coverage performance of the second insulating layer 170 decreases. Therefore, the taper angle α is preferably in the above range. The taper angle α also depends on the film thickness of the metal oxide layer 150. For example, as the film thickness of the metal oxide layer 150 increases, the taper angle α also increases. Therefore, in order to control the taper angle α within the above range, the film thickness of the metal oxide layer 150 is preferably 10 nm or more and 100 nm or less, and more preferably 20 nm or more and 50 nm or less.

[0028] 2. Method for Manufacturing Semiconductor Device 10 A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described with reference to FIGS. 3A to 3G.

[0029] Each of FIGS. 3A to 3G is a schematic cross-sectional view showing a manufacturing method of the semiconductor device 10 according to one embodiment of the present invention.

[0030] 3A shows the process up to the step of forming the light-shielding layer 110. For example, a metal film or the like is formed on the substrate 100 by a sputtering method. In addition, the metal film is processed into a predetermined pattern by using a photolithography method to form the light-shielding layer 110.

[0031] FIG. 3B shows the process up to the step of forming the oxide semiconductor layer 130. A silicon oxide film or a silicon nitride film is formed on the substrate 100 and the light shielding layer 110 by a CVD method to form the first insulating layer 120. An oxide semiconductor film is formed on the first insulating layer 120 by a sputtering method. The oxide semiconductor film has a thickness of, for example, 20 nm or more and 100 nm or less. The oxide semiconductor film is processed into a predetermined pattern by a photolithography method to form the oxide semiconductor layer 130. In order to improve the electrical characteristics of the semiconductor device 10, it is effective to perform a heat treatment on the oxide semiconductor layer 130. Therefore, the heat treatment may be performed after the oxide semiconductor film is formed or after the oxide semiconductor layer 130 is formed. The heat treatment may be performed in the air, in a dry air atmosphere, or in a nitrogen atmosphere. The temperature of the heat treatment is 200° C. or more and 600° C. or less, preferably 350° C. or more and 450° C. or less.

[0032] FIG. 3C shows the process up to the step of forming the metal film 260. An insulating film 240 such as a silicon oxide film or a silicon nitride film is formed on the first insulating layer 120 and the oxide semiconductor layer 130 by a CVD method. The thickness of the insulating film 240 is, for example, 50 nm or more and 300 nm or less. A metal oxide film 250 is formed on the insulating film 240 by a sputtering method. A metal film 260 is formed on the metal oxide film 250 by a sputtering method. The metal film 260 preferably includes an aluminum film, and more preferably has a stacked structure of a molybdenum film / aluminum film / molybdenum film. When the metal film 260 has a stacked structure of a molybdenum film / aluminum film / molybdenum film, for example, the thickness of the molybdenum film is 20 nm or more and 100 nm or less, and the thickness of the aluminum film is 300 nm or more and 700 nm or less.

[0033] 3D shows the process up to forming a resist layer 310 having a predetermined pattern. A resist film is formed on the metal film 260. The resist film is exposed using a photomask and then developed to form the resist layer 310 having the predetermined pattern.

[0034] FIG. 3E shows the process up to forming the metal oxide layer 150. The metal film 260 and the metal oxide film 250 are successively wet-etched using the resist layer 310 as a mask to form the gate electrode 160 and the metal oxide layer 150. Here, "successively wet-etching" means that a plurality of films are etched at once using the same etching solution. The etching solution preferably contains phosphoric acid, and more preferably contains phosphoric acid, nitric acid, and acetic acid (hereinafter, the etching solution used in this process is referred to as "etching solution containing phosphoric acid as the main component"). It is known that an etching solution containing phosphoric acid as the main component is used for aluminum films or molybdenum films. In contrast, an etching solution containing phosphoric acid as the main component has a high etching rate for a single metal oxide film. Therefore, it is difficult to control the etching of a single metal oxide film using an etching solution containing phosphoric acid as the main component. However, when a stacked structure in which the metal film 260 is formed on the metal oxide film 250 is etched using an etching solution mainly containing phosphoric acid, the etching rate of the metal oxide film 250 becomes lower than the etching rate of the metal film 260. Therefore, due to the difference in etching rate between the metal film 260 and the metal oxide film 250, side etching (or undercutting) of the metal oxide film 250 does not occur, as shown in FIG. 3E, and a structure is obtained in which the side surface of the metal oxide layer 150 protrudes from the side surface of the gate electrode 160. In addition, the taper angle of the side surface of the metal oxide layer 150 becomes smaller than the taper angle of the side surface of the gate electrode 160.

[0035] When the gate electrode 160 has a stacked structure of a molybdenum film / aluminum film / molybdenum film, the taper angle α of the side surface of the metal oxide layer 150 is preferably smaller than the taper angle of the side surface of the molybdenum film in contact with the metal oxide layer 150 of the gate electrode 160. In addition, the taper angle α of the side surface of the metal oxide layer 150 is preferably smaller than the taper angle of the side surface of the aluminum film.

[0036] 3F shows the process up to forming the gate insulating layer 140. The gate insulating layer 140 is formed by dry etching using the resist layer 310, the gate electrode 160, or the metal oxide layer 150 as a mask.

[0037] FIG. 3G shows the process up to the step of forming the second insulating layer 170. After the resist layer 310 is peeled off, an insulating film such as a silicon oxide film or a silicon nitride film is formed by a CVD method on the first insulating layer 120, the oxide semiconductor layer 130, the gate insulating layer 140, the metal oxide layer 150, and the gate electrode 160. At this time, in the region of the oxide semiconductor layer 130 in contact with the insulating film, oxygen defects are generated, or a high-concentration impurity region 132 is formed by adding impurities. In addition, in the region of the oxide semiconductor layer 130 overlapping with the gate insulating layer 140, a channel region 131 is formed. Furthermore, by using a photolithography method, an opening is formed at a predetermined position of the insulating film so as to expose the upper surface of the oxide semiconductor layer 130 (more specifically, the high-concentration impurity region 132), and the second insulating layer 170 is formed.

[0038] Thereafter, a metal film is formed and processed into a predetermined pattern using photolithography to form a source electrode 180 and a drain electrode 190 (see FIG. 1).

[0039] As described above, in the semiconductor device 10 according to this embodiment, the inclination of the surface connecting the upper surface of the gate insulating layer 140 and the side surface of the gate electrode 160 can be made gentle by forming the metal oxide layer 150 between the gate insulating layer 140 and the gate electrode 160. Therefore, the coverage of the second insulating layer 170 covering the oxide semiconductor layer 130 and the gate electrode 160 can be improved. In addition, the metal oxide layer 150 can be formed by successively wet etching together with the gate electrode 160. Therefore, the semiconductor device 10 can be manufactured at low cost because each electrode can be formed on a large-area substrate by using wet etching.

[0040] <Second embodiment> [1. Configuration of Semiconductor Device 10A] The configuration of a semiconductor device 10A according to one embodiment of the present invention will be described with reference to Fig. 4. Note that when the configuration of the semiconductor device 10A is similar to the configuration of the semiconductor device 10 described in the first embodiment, the description of the configuration of the semiconductor device 10A may be omitted.

[0041] Fig. 4 is a schematic cross-sectional view showing the configuration of a semiconductor device 10A according to one embodiment of the present invention. As shown in Fig. 4, the semiconductor device 10A includes a substrate 100, a light-shielding layer 110, a first insulating layer 120, an oxide semiconductor layer 130, a gate insulating layer 140A, a metal oxide layer 150, a gate electrode 160, a second insulating layer 170, a source electrode 180, and a drain electrode 190. The oxide semiconductor layer 130 includes a channel region 131 overlapping with the gate electrode 160 and a high-concentration impurity region 132A not overlapping with the gate electrode 160.

[0042] The gate insulating layer 140A covers the oxide semiconductor layer 130 and is provided on the first insulating layer 120 and the oxide semiconductor layer 130. That is, the side surface of the oxide semiconductor layer 130 is covered by the gate insulating layer 140A. The first insulating layer 120 has an opening that exposes a part of the upper surface of the oxide semiconductor layer 130 (more specifically, the high-concentration impurity region 132A). The source electrode 180 and the drain electrode 190 are in contact with the high-concentration impurity region 132A of the oxide semiconductor layer 130 through the opening of the second insulating layer 170 and the opening of the gate insulating layer 140A.

[0043] In the semiconductor device 10A, the side surface of the metal oxide layer 150 also protrudes from the side surface of the gate electrode 160 in a plan view. The taper angle α of the side surface of the metal oxide layer 150 is smaller than the taper angle β of the side surface of the gate electrode 160. That is, the side surface of the metal oxide layer 150 has a gentler inclination than the side surface of the gate electrode 160. Therefore, the coverage performance of the second insulating layer 170 covering the side surface of the gate electrode 160 is improved. As a result, moisture is prevented from penetrating into the oxide semiconductor layer 130 through the second insulating layer 170, and the reliability of the semiconductor device 10A can be improved.

[0044] [2. Method for Manufacturing Semiconductor Device 10A] A method for manufacturing a semiconductor device 10A according to one embodiment of the present invention will be described with reference to Figures 5A and 5B. Note that when the method for manufacturing the semiconductor device 10A is similar to the method for manufacturing the semiconductor device 10 described in the first embodiment, the description of the method for manufacturing the semiconductor device 10A may be omitted.

[0045] In the method for manufacturing the semiconductor device 10A, the steps from FIG. 3A to FIG. 3E are the same, so the description will be omitted here, and the subsequent steps will be described.

[0046] 5A and 5B are each a schematic cross-sectional view showing a manufacturing method of a semiconductor device 10A according to one embodiment of the present invention.

[0047] FIG. 5A shows the process up to forming the high-concentration impurity region 132A. After peeling off the resist layer 310, the gate electrode 160 or the metal oxide layer 150 is used as a mask to ion-implant an impurity element into the oxide semiconductor layer 130 through the insulating film 240, thereby forming the high-concentration impurity region 132A in a region of the oxide semiconductor layer 130 that does not overlap with the gate electrode 160. In addition, a channel region 131 is formed in a region of the oxide semiconductor layer 130 that overlaps with the gate electrode 160. As the impurity element, hydrogen, argon, phosphorus, boron, or the like can be used. However, the addition of the impurity element to the oxide semiconductor layer 130 mainly generates oxygen defects to control the conductivity type of the oxide conductor, so the type of the impurity element is not particularly limited. In addition, the concentration (dose) of the impurity element is, for example, 1×10 14 atoms / cm 2 5×10 or more 15 atoms / cm 2 In this case, the high-concentration impurity region 132A contains an impurity element of 5×10 13 atoms / cm 3 More than 2.5 x 10 15 atoms / cm 3The impurity elements are contained in the oxide semiconductor layer 130 at a concentration of about: The concentration of the impurity elements contained in the oxide semiconductor layer 130 can be measured by, for example, secondary ion mass spectrometry (SIMS).

[0048] 5B shows the process up to the step of forming the gate insulating layer 140A. An insulating film such as a silicon oxide film or a silicon nitride film is formed by a CVD method on the insulating film 240. Using a photolithography method, openings are made at predetermined positions of the insulating film and the insulating film 240 so as to expose the upper surface of the oxide semiconductor layer 130 (more specifically, the high-concentration impurity region 132A), and a second insulating layer 170 and a gate insulating layer 140A are formed.

[0049] Thereafter, a metal film is formed and processed into a predetermined pattern using photolithography to form a source electrode 180 and a drain electrode 190 (see FIG. 4).

[0050] As described above, in the semiconductor device 10A according to this embodiment, by forming the metal oxide layer 150 between the gate insulating layer 140 and the gate electrode 160, the inclination of the surface connecting the upper surface of the gate insulating layer 140 and the side surface of the gate electrode 160 can be made gentle. Therefore, the coverage of the second insulating layer 170 covering the gate electrode 160 can be improved. In addition, the metal oxide layer 150 can be formed by successively wet etching together with the gate electrode 160. Therefore, the semiconductor device 10 can be manufactured at low cost because each electrode can be formed on a large-area substrate by using wet etching.

[0051] The semiconductor device described in the first and second embodiments can be applied to liquid crystal display devices or OLED (Organic Light Emitting Diode) display devices, etc. In addition, since the semiconductor device described in the first and second embodiments can be manufactured using a large-area substrate, it can be applied not only to small and medium-sized display devices such as smartphones, but also to large display devices such as televisions.

[0052] Based on the semiconductor device described as the embodiment and example of the present invention, a person skilled in the art may add or remove components or modify the design, or add or omit processes or modify conditions, as long as the gist of the present invention is maintained. In addition, the above-mentioned embodiments can be combined with each other to the extent that no technical contradiction occurs.

[0053] Furthermore, even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0054] 10, 10A: semiconductor device, 100: substrate, 110: light shielding layer, 120: first insulating layer, 130: oxide semiconductor layer, 131: channel region, 132, 132A: high concentration impurity region, 140, 140A: gate insulating layer, 150: metal oxide layer, 160: gate electrode, 170: second insulating layer, 180: source electrode, 190: drain electrode, 240: insulating film, 250: metal oxide film, 260: metal film, 310: resist layer

Claims

1. A substrate; an oxide semiconductor layer on the substrate; a gate insulating layer including an opening on the oxide semiconductor layer; a metal oxide layer on the gate insulating layer; a gate electrode on the metal oxide layer; a source electrode and a drain electrode in contact with the oxide semiconductor layer through the opening; A semiconductor device, wherein a first side surface of the metal oxide layer protrudes beyond a second side surface of the gate electrode in a plan view.

2. The semiconductor device according to claim 1 , wherein a first taper angle of said first side surface is smaller than a second taper angle of said second side surface.

3. The semiconductor device according to claim 2 , wherein the first taper angle is equal to or greater than 30° and equal to or less than 70°.

4. 4. The semiconductor device according to claim 1, wherein the metal oxide layer has a thickness of 10 nm or more and 100 nm or less.

5. The semiconductor device according to claim 1 , wherein the metal oxide layer contains indium.

6. The gate electrode is a first metal layer in contact with the metal oxide layer; a second metal layer on the first metal layer; The semiconductor device according to claim 1 , wherein the second metal layer contains aluminum.

7. The semiconductor device according to claim 6 , wherein the first metal layer comprises molybdenum.

8. The semiconductor device according to claim 1 , wherein a side surface of the oxide semiconductor layer is covered with the gate insulating layer.

9. The semiconductor device according to claim 1 , wherein the substrate is a flexible substrate.

10. forming an oxide semiconductor layer over a substrate; forming a gate insulating film on the oxide semiconductor layer; forming a metal oxide film on the gate insulating film; forming a metal film on the metal oxide film; forming a resist layer on the metal film; forming a gate electrode and a metal oxide layer by successively wet-etching the metal film and the metal oxide film using the resist layer as a mask; patterning the gate insulating film to form a gate insulating layer including an opening; forming a source electrode and a drain electrode in contact with the oxide semiconductor layer through the opening.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the wet etching is performed using an etching solution containing phosphoric acid.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the wet etching is performed using an etching solution containing phosphoric acid, nitric acid, and acetic acid.

13. 13. The method for manufacturing a semiconductor device according to claim 10, wherein the first side surface of the metal oxide layer is formed so as to protrude from the second side surface of the gate electrode in a plan view.

14. 14. The method of claim 13, wherein a first taper angle of the first side surface is smaller than a second taper angle of the second side surface.

15. The method for manufacturing a semiconductor device according to claim 10 , wherein the metal oxide film contains indium.

16. The metal film is a first metal film in contact with the metal oxide film; a second metal film on the first metal film; 16. The method for manufacturing a semiconductor device according to claim 10, wherein the second metal film contains aluminum.

17. 17. The method of claim 16, wherein the first metal film contains molybdenum.

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