Semiconductor device driver circuit

Abstract

To provide a semiconductor device drive circuit capable of improving switching loss of a power switching device.SOLUTION: A semiconductor device drive circuit comprises: a first transistor and a second transistor which are connected in series and operate complementarily between a first voltage and a second voltage lower than the first voltage; a constant voltage generation part which operates between the first voltage and the second voltage and outputs an internal power supply voltage of a constant voltage in a stationary state; an internal power supply circuit which has a feedback part in which a node voltage of a connection node of the first transistor and the second transistor is inputted and which changes the internal power supply voltage output from the constant voltage generation part depending on a change in the node voltage; and a pre-driver which operates between the first voltage and the internal power supply voltage and drives the first transistor or the second transistor, wherein the node voltage is output as a gate voltage of a power switching device.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device driver circuit, and more particularly to a semiconductor device driver circuit that drives a power switching device. [Background technology]

[0002] When driving power switching devices such as insulated gate bipolar transistors (IGBTs), changing the output current of the drive circuit during switching is considered effective in improving switching characteristics such as switching loss and noise.One method for doing this is to change the gate voltage of the driver transistor, i.e., the output voltage of the pre-driver, according to the output voltage.

[0003] For example, Patent Document 1 discloses a pre-driver that monitors the output current of an output transistor controlled by the pre-driver and transitions the output voltage of the pre-driver between a low potential (L) and a high potential (H) at any timing depending on the output current. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-231117 A Summary of the Invention [Problem to be solved by the invention]

[0005] As disclosed in Patent Document 1, when controlling the output of the pre-driver to transition between L and H, there is a large change in the output current of the output transistor when the output of the pre-driver is L and when it is H, resulting in many unnecessary operations. In addition, a shift in the switching timing may increase the switching loss of the power switching device.

[0006] The present disclosure has been made to solve the above problems, and has an object to provide a semiconductor device driver circuit that can improve switching loss in a power switching device. [Means for solving the problem]

[0007] The semiconductor device driving circuit according to the present disclosure is a semiconductor device driving circuit for driving a power switching device, comprising: a first transistor and a second transistor connected in series and operating complementarily between a first voltage and a second voltage lower than the first voltage; a constant voltage generating unit operating between the first voltage and the second voltage and outputting an internal power supply voltage that is steadily constant; an internal power supply circuit having a feedback unit that receives an input of a node voltage of a connection node between the first transistor and the second transistor and changes the internal power supply voltage output from the constant voltage generating unit in accordance with changes in the node voltage; and a pre-driver operating between the first voltage and the internal power supply voltage and driving the first transistor or the second transistor, and outputs the node voltage as a gate voltage of the power switching device. Effect of the Invention

[0008] According to the semiconductor device driving circuit of the present disclosure, the output current of the first transistor or the second transistor, which is an output transistor, is changed during switching of the power switching device, thereby improving the switching loss of the power switching device. [Brief description of the drawings]

[0009] [Figure 1] 1 is a circuit diagram showing a configuration of a semiconductor device driving circuit according to a first embodiment of the present disclosure. [Diagram 2] 4 is a diagram illustrating an operation of the semiconductor device driving circuit according to the first embodiment of the present disclosure. FIG. [Diagram 3] 2 is a circuit diagram showing an example of a configuration of an internal power supply circuit; [Figure 4]11 is a circuit diagram showing a configuration of a semiconductor device driver circuit according to a second embodiment of the present disclosure. FIG. [Diagram 5] 11 is a diagram illustrating an operation of the semiconductor device driving circuit according to the second embodiment of the present disclosure. FIG. [Figure 6] 2 is a circuit diagram showing an example of a configuration of an internal power supply circuit; [Figure 7] 13 is a circuit diagram showing a configuration of a semiconductor device driver circuit according to a third embodiment of the present disclosure. FIG. [Figure 8] 13 is a diagram illustrating an operation of the semiconductor device driving circuit according to the third embodiment of the present disclosure. FIG. [Figure 9] 13 is a circuit diagram showing a configuration of a modified example of the semiconductor device driving circuit according to the third embodiment of the present disclosure. FIG. [Figure 10] FIG. 11 is a circuit diagram showing a configuration of a semiconductor device driving circuit according to a fourth embodiment of the present disclosure. [Figure 11] FIG. 13 is a diagram illustrating an operation of the semiconductor device driving circuit according to the fourth embodiment of the present disclosure. [Figure 12] 13 is a circuit diagram showing a configuration of a modified example of the semiconductor device driving circuit according to the fourth embodiment of the present disclosure. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Embodiment 1> Fig. 1 is a circuit diagram showing a configuration of a semiconductor device driver 100 according to a first embodiment of the present disclosure. As shown in Fig. 1, the semiconductor device driver 100 is configured as an integrated circuit (IC) that drives an IGBT1, which is a power device. The collector of the IGBT1 is connected to a main terminal MT that provides a main voltage VP via a freewheeling diode D1 and an inductor load L1 that are connected in parallel, and the emitter of the IGBT1 is connected to a ground potential GND.

[0011] In the semiconductor device driving circuit 100, a P-channel MOS transistor P12 serving as a source side output transistor and an N-channel MOS transistor N12 serving as a sink side output transistor are connected in series between a power supply line P to which a voltage VCC (first voltage) is supplied from a power supply terminal OP and a ground potential GND (second voltage).

[0012] The MOS transistors P12 and N12 operate complementarily, and a connection node ND0 between the MOS transistors P12 and N12 serves as an output node ND0 of the semiconductor device driver circuit 100, from which a gate voltage VG is output and input to the gate of the IGBT1.

[0013] The gate of the MOS transistor P12 receives the output voltage Vgp of the pre-driver 11. The pre-driver 11 has a P-channel MOS transistor P11 and an N-channel MOS transistor N11 connected in series between the power supply line P and the output line S of the internal power supply circuit 10.

[0014] The internal power supply circuit 10 is a circuit that operates between a voltage VCC and a ground potential GND, and includes a constant voltage generating unit 101 that outputs an internal power supply voltage VE that is normally a constant voltage, and a feedback unit 102 that receives a gate voltage VG and changes the internal power supply voltage VE output from the constant voltage generating unit 101 in response to changes in the gate voltage VG. The source of the MOS transistor N11 is connected to the output line S.

[0015] The gates of the MOS transistor P11 and the MOS transistor N11 are commonly connected and are supplied with an input signal IN. The input signal IN is also supplied to an inverter IV, and the output of the inverter IV is input to the gate of the MOS transistor N12.

[0016] Fig. 2 is a diagram showing a number of signal waveforms that explain the operation of the semiconductor device driver circuit 100. Fig. 2 shows, from top to bottom, a waveform diagram of an input signal IN, a waveform diagram of a gate voltage VG, a waveform diagram of an output voltage Vgp of the pre-driver 11, a waveform diagram of an internal power supply voltage VE of the internal power supply circuit 10, and a waveform diagram of an output source current Ig of the MOS transistor P12.

[0017] When the input signal IN changes from low level to high level, in the pre-driver 11, the MOS transistor P11 turns off and the MOS transistor N11 turns on, and the output voltage Vgp of the pre-driver 11 transitions from the voltage VCC to the internal power supply voltage VE of the internal power supply circuit 10.

[0018] This turns on the MOS transistor P12, causing the gate voltage VG to rise, and the internal power supply voltage VE to fall accordingly, causing the output voltage Vgp to fall following the internal power supply voltage VE. This increases the gate-source voltage of the MOS transistor P12, and therefore increases the output source current Ig of the MOS transistor P12.

[0019] The gate voltage VG increases from zero volts, passes through a period of constant voltage called the Miller period, then increases again, eventually becoming a constant voltage VCC. The Miller period corresponds to the period during which the gate-collector capacitance of IGBT1 is charged. To turn on IGBT1, the gate-collector capacitance needs to be charged, and the period for this charging is the Miller period.

[0020] In this way, the semiconductor device driving circuit 100 outputs the gate voltage VG which exhibits a waveform that increases from zero volts and becomes constant at the voltage VCC after a mirror period. The internal power supply circuit 10 uses this gate voltage VG as an input and adopts a configuration in which the current flowing inside changes in an analog manner, thereby making it possible to continuously change the output voltage Vgp of the pre-driver 11 which operates between the internal power supply voltage VE of the internal power supply circuit 10 and the voltage VCC, as shown in FIG. 2.

[0021] 2, the output source current Ig can be increased to a value higher than that at the start of switching when the mirror period begins, and the amount of current can be maintained during the mirror period. This is because the internal power supply voltage VE of the internal power supply circuit 10 decreases with an increase in the gate voltage VG, and the gate-source voltage of the MOS transistor P12 increases.

[0022] By increasing the output source current Ig during the mirror period, the gate charge speed of IGBT1 can be accelerated and the mirror period can be shortened.

[0023] This makes it possible to make the rate of fall dV / dt between the collector and emitter of IGBT1 steeper, thereby improving switching loss.

[0024] 3 is a circuit diagram showing an example of the configuration of the internal power supply circuit 10. As shown in FIG. 3, the internal power supply circuit 10 includes a current mirror circuit CM1 (first current mirror circuit) having a primary side circuit in which a constant current source CI and an N-channel MOS transistor N91 are connected in series between a power supply line P (first power supply line) that provides a voltage VCC and a power supply line N (second power supply line) that provides a ground potential GND, and a secondary side circuit in which a resistor element R1 (first resistor element) and an N-channel MOS transistor N92 are connected in series between the power supply line P and the power supply line N. The gates of the MOS transistor N91 and the MOS transistor N92 are commonly connected to the drain of the MOS transistor N91. A node ND1 between the MOS transistor N92 and the resistor element R1 is connected to the input of the amplifier AP via a signal line L. The constant voltage generating unit 101 is configured by the above circuit.

[0025] A current mirror circuit CM2 (second current mirror circuit) is provided, which has a primary circuit in which an N-channel MOS transistor N95 is connected between a node ND2 between the MOS transistor N92 and the resistive element R1 and the power supply line N, and a secondary circuit in which a resistive element R2 (second resistive element) and an N-channel MOS transistor N96 are connected between an input part IP of the internal power supply circuit 10 and the power supply line N. The gates of the MOS transistors N95 and N96 are commonly connected to the drain of the MOS transistor N96. The above circuit constitutes a feedback part 102.

[0026] The current mirror circuit CM1 passes a current corresponding to the current IE output by the constant current source CI through the MOS transistor N92. When this current passes through the resistor element R1, a voltage VEp is generated, and the amplifier AP is used as a follower circuit to output the internal power supply voltage VE.

[0027] The current mirror circuit CM2 passes a current according to the value of the gate voltage VG input to the input part IP through the MOS transistor N95. When the gate voltage VG rises from zero, the current flowing through the resistor element R2 increases as the gate voltage VG rises, and the current flowing through the resistor element R1 increases accordingly, so that the voltage VEp falls and the internal power supply voltage VE output from the amplifier AP falls.

[0028] <Embodiment 2> Fig. 4 is a circuit diagram showing a configuration of a semiconductor device driver 200 according to a second embodiment of the present disclosure. As shown in Fig. 4, the semiconductor device driver 200 is configured as an integrated circuit that drives an IGBT1, which is a power device. The collector of the IGBT1 is connected to a main terminal MT that provides a main voltage VP via a freewheeling diode D1 and an inductor load L1 that are connected in parallel, and the emitter of the IGBT1 is connected to a ground potential GND.

[0029] In the semiconductor device driving circuit 200, an N-channel MOS transistor N23 serving as a source side output transistor and an N-channel MOS transistor N23 serving as a sink side output transistor are connected in series between a power supply line P, which is supplied with a voltage VCC from a power supply terminal OP, and a ground potential GND.

[0030] The MOS transistors N23 and N22 operate complementarily, and a connection node ND0 between the MOS transistors N23 and N22 serves as the output node ND0 of the semiconductor device driver circuit 200, from which a gate voltage VG is output and input to the gate of the IGBT1.

[0031] The gate of the MOS transistor N23 receives the output voltage Vgp of the pre-driver 21. The pre-driver 21 has a P-channel MOS transistor P21 and an N-channel MOS transistor N21 connected in series between the output line S of the internal power supply circuit 20 and the ground potential GND.

[0032] The internal power supply circuit 20 is a circuit that operates between a voltage VCC and a ground potential GND, and includes a constant voltage generating unit 201 that outputs an internal power supply voltage VE that is normally a constant voltage, and a feedback unit 202 that receives a gate voltage VG and changes the internal power supply voltage VE output from the constant voltage generating unit 201 in response to a change in the gate voltage VG. The source of the MOS transistor P21 is connected to the output line S.

[0033] The gates of the MOS transistors P21 and N21 are connected in common and to the output of an inverter IV. An input signal IN is supplied to the inverter IV, and the output of the inverter IV is also input to the gate of the MOS transistor N22.

[0034] Fig. 5 is a diagram showing a number of signal waveforms for explaining the operation of the semiconductor device driver circuit 200. Fig. 5 shows, from the top to the bottom, a waveform diagram of the input signal IN, a waveform diagram of the gate voltage VG, a waveform diagram of the internal power supply voltage VE of the internal power supply circuit 20, a waveform diagram of the output voltage Vgp of the pre-driver 21, and a waveform diagram of the output source current Ig of the MOS transistor N23.

[0035] When the input signal IN changes from low level to high level, in the pre-driver 21, the MOS transistor P21 turns on and the MOS transistor N21 turns off, and the output voltage Vgp of the pre-driver 21 transitions from the ground potential GND to the internal power supply voltage VE of the internal power supply circuit 20. In addition, the MOS transistor N22 turns off due to the output of the inverter IV.

[0036] This turns on the MOS transistor N23, causing the gate voltage VG to rise, which in turn causes the internal power supply voltage VE to rise, causing the output voltage Vgp to follow suit and rise. This increases the gate-source voltage of the MOS transistor N23, and therefore increases the output source current Ig of the MOS transistor N23.

[0037] The gate voltage VG increases from zero volts, goes through a Miller period, increases again, and finally becomes constant at the voltage VCC. The Miller period corresponds to the period during which the gate-collector capacitance of IGBT1 is charged.

[0038] In this way, the semiconductor device driving circuit 200 outputs the gate voltage VG having a waveform that increases from zero volts and becomes constant at the voltage VCC after a mirror period. The internal power supply circuit 20 takes this gate voltage VG as an input and adopts a configuration in which the current flowing inside changes in an analog manner, thereby making it possible to continuously change the output voltage Vgp of the pre-driver 21, which operates between the internal power supply voltage VE of the internal power supply circuit 20 and the voltage VCC, as shown in FIG. 5.

[0039] 5, the output source current Ig can be increased to a value higher than that at the start of switching when the mirror period begins, and the amount of current can be maintained during the mirror period. This is because the internal power supply voltage VE of the internal power supply circuit 20 increases with the increase in the gate voltage VG, and the gate-source voltage of the MOS transistor P12 increases.

[0040] By increasing the output source current Ig during the mirror period, the gate charge speed of IGBT1 can be accelerated and the mirror period can be shortened.

[0041] This makes it possible to make the rate of fall dV / dt between the collector and emitter of IGBT1 steeper, thereby improving switching loss.

[0042] 6 is a circuit diagram showing an example of the configuration of the internal power supply circuit 20. As shown in FIG. 6, the internal power supply circuit 20 includes a current mirror circuit CM10 (first current mirror circuit) having a primary side circuit in which a P-channel MOS transistor P91 and a constant current source CI are connected in series between a power supply line P that provides a voltage VCC and a power supply line N that provides a ground potential GND, and a secondary side circuit in which a P-channel MOS transistor P92 and a resistor element R1 are connected in series between the power supply line P and the power supply line N. The gates of the MOS transistors P91 and P92 are commonly connected to the drain of the MOS transistor P91. A node ND10 between the MOS transistor P92 and the resistor element R1 is connected to the input of the amplifier AP via a signal line L.

[0043] Also provided is a current mirror circuit CM30 (third current mirror circuit) having a primary circuit having a MOS transistor P93, and a secondary circuit having a P-channel type MOS transistor P94 connected between the power supply line P and the signal line L. The gates of the MOS transistors P93 and P94 are commonly connected to the drain of the MOS transistor P93. The constant voltage generating unit 101 is configured by the above circuit.

[0044] Between the power supply line P and the power supply line N, a P-channel MOS transistor P93 and an N-channel MOS transistor N95 are connected in series.

[0045] Between the input part IP of the internal power supply circuit 20 and the power supply line N, there is provided a current mirror circuit CM20 (second current mirror circuit) having a primary side circuit in which a resistive element R2 and an N-channel MOS transistor N96 are connected, and a secondary side circuit having a MOS transistor N95. The gates of the MOS transistors N95 and N96 are commonly connected to the drain of the MOS transistor N96. The above circuit constitutes a feedback part 202.

[0046] The current mirror circuit CM10 passes a current corresponding to the current IE output by the constant current source CI through the MOS transistor P92. When this current passes through the resistor element R1, a voltage VEp is generated, and the amplifier AP is used as a follower circuit to output the internal power supply voltage VE.

[0047] The current mirror circuit CM20 passes a current according to the value of the gate voltage VG input to the input part IP through the MOS transistor N95. When the gate voltage VG rises from zero, the current flowing through the resistor element R2 increases with the rise in the gate voltage VG, and the current flowing through the MOS transistor P94 of the current mirror circuit CM30 increases accordingly, so that the voltage VEp rises and the internal power supply voltage VE output from the amplifier AP rises.

[0048] <Embodiment 3> Fig. 7 is a circuit diagram showing a configuration of a semiconductor device driving circuit 300 according to a third embodiment of the present disclosure. As shown in Fig. 7, the semiconductor device driving circuit 300 is configured as an integrated circuit that drives an IGBT1, which is a power device. Note that in Fig. 7, the same components as those in the semiconductor device driving circuit 100 described with reference to Fig. 1 are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0049] The collector of IGBT1 is connected to a main terminal MT which provides a main voltage VP via a freewheeling diode D1 and an inductor load L1 connected in parallel, and the emitter of IGBT1 is connected to a ground potential GND.

[0050] In the semiconductor device driving circuit 300, a P-channel MOS transistor P32 serving as a source side output transistor and a P-channel MOS transistor P33 serving as a sink side output transistor are connected in series between a power supply line P supplied with a voltage VCC from a power supply terminal OP and a ground potential GND.

[0051] The MOS transistors P32 and P33 operate complementarily, and a connection node ND0 between the MOS transistors P32 and P33 serves as an output node ND0 of the semiconductor device driver circuit 300, from which a gate voltage VG is output and input to the gate of the IGBT1.

[0052] The output voltage Vgn of the pre-driver 31 is input to the gate of the MOS transistor P33. The pre-driver 31 has a P-channel MOS transistor P31 and an N-channel MOS transistor N31 connected in series between the power supply line P and the output line S of the internal power supply circuit 10.

[0053] The internal power supply circuit 10 is a circuit that operates between a voltage VCC and a ground potential GND, receives a gate voltage VG, and outputs an internal power supply voltage VE. The source of the MOS transistor N31 is connected to the output line S.

[0054] The gates of the MOS transistors P31 and N31 are commonly connected, and the output of the inverter IV is input to the gate of the MOS transistor P32. An input signal IN is supplied to the inverter IV, and the output of the inverter IV is also input to the gate of the MOS transistor P32.

[0055] Fig. 8 is a diagram showing a number of signal waveforms for explaining the operation of the semiconductor device driver circuit 300. Fig. 8 shows, from the top to the bottom, a waveform diagram of the input signal IN, a waveform diagram of the gate voltage VG, a waveform diagram of the output voltage Vgn of the pre-driver 31, a waveform diagram of the internal power supply voltage VE of the internal power supply circuit 10, and a waveform diagram of the output sink current Ig' of the MOS transistor P33.

[0056] When the input signal IN changes from high level to low level, its inverted signal is input to the pre-driver 31, so that in the pre-driver 31, the MOS transistor P31 is turned off and the MOS transistor N31 is turned on, and the output voltage Vgn of the pre-driver 31 transitions from the internal power supply voltage VE of the internal power supply circuit 10 to the voltage VCC. Also, the MOS transistor P32 is turned off by the output of the inverter IV.

[0057] This turns on the MOS transistor P33, causing the gate voltage VG to drop, and the internal power supply voltage VE to rise accordingly, causing the output voltage Vgn to rise as well. This reduces the gate-source voltage of the MOS transistor P33, and therefore reduces the output sink current Ig' of the MOS transistor P33.

[0058] The gate voltage VG decreases from the voltage VCC, passes through a mirror period, decreases again, and finally becomes constant at the ground potential GND.

[0059] In this way, the semiconductor device driving circuit 300 outputs the gate voltage VG having a waveform that decreases from the voltage VCC and becomes constant at the ground potential GND after a mirror period. The internal power supply circuit 10 receives this gate voltage VG as an input and adopts a configuration in which the current flowing inside changes in an analog manner, thereby making it possible to continuously change the output voltage Vgn of the pre-driver 31, which operates between the internal power supply voltage VE of the internal power supply circuit 10 and the voltage VCC, as shown in FIG. 8.

[0060] 8, the output sink current Ig' can be reduced compared to when switching starts when the mirror period begins, and the current amount can be maintained during the mirror period. This makes it possible to suppress the surge voltage generated in the collector-emitter voltage Vce of IGBT1, and reduce switching losses.

[0061] <Modification> Fig. 9 is a circuit diagram showing a configuration of a semiconductor device driver 301 according to a modification of the third embodiment of the present disclosure. As shown in Fig. 9, the semiconductor device driver 301 includes an N-channel MOS transistor N33 connected between the output node ND0 and the ground potential GND, in addition to the configuration of the semiconductor device driver 300 shown in Fig. 7.

[0062] The MOS transistor N33 is a sink-side output transistor, and its gate is connected to the Q output of the SR flip-flop circuit FF. An inverted signal of the gate voltage VG is input to the S input of the SR flip-flop circuit FF via the inverter IV1, and an input signal IN is input to the R input. The rising edge of the input signal IN triggers the gate of the MOS transistor N33 to go from high to low. Here, by setting the threshold value of the inverter IV1 to near zero volts, the gate of the MOS transistor N33 goes from low to high and turns on, triggered by the gate voltage VG falling to near zero volts, that is, when it is detected that the gate voltage VG has reached a value near zero volts. This allows the voltage VE to be raised to the voltage VCC.

[0063] When the internal power supply voltage VE reaches near the voltage VCC, the gate-source voltage of the MOS transistor P33 falls below the threshold value of the MOS transistor P33 and the MOS transistor P33 turns off, thereby further reducing the output sink current Ig' of the MOS transistor P33 and further suppressing the surge voltage of the collector-emitter voltage Vce of the IGBT1. After the MOS transistor P33 turns off, the gate voltage VG drops and the MOS transistor N33 turns on, thereby preventing the gate voltage VG from rising due to the driving of the IGBT1.

[0064] <Fourth embodiment> Fig. 10 is a circuit diagram showing a configuration of a semiconductor device driving circuit 400 according to a fourth embodiment of the present disclosure. As shown in Fig. 10, the semiconductor device driving circuit 400 is configured as an integrated circuit that drives an IGBT1, which is a power device. Note that in Fig. 10, the same components as those in the semiconductor device driving circuit 200 described using Fig. 7 are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0065] The collector of IGBT1 is connected to a main terminal MT which provides a main voltage VP via a freewheeling diode D1 and an inductor load L1 connected in parallel, and the emitter of IGBT1 is connected to a ground potential GND.

[0066] In the semiconductor device driving circuit 400, a P-channel MOS transistor P42 serving as a source side output transistor and an N-channel MOS transistor N42 serving as a sink side output transistor are connected in series between a power supply line P, which is supplied with a voltage VCC from a power supply terminal OP, and a ground potential GND.

[0067] The MOS transistors P42 and N42 operate complementarily, and a connection node ND0 between the MOS transistors P42 and N42 serves as an output node ND0 of the semiconductor device driver circuit 400, from which a gate voltage VG is output and input to the gate of the IGBT1.

[0068] The gate of the MOS transistor N42 receives the output voltage Vgn of the pre-driver 41. The pre-driver 41 has a P-channel MOS transistor P41 and an N-channel MOS transistor N41 connected in series between the output line S of the internal power supply circuit 20 and the ground potential GND.

[0069] The internal power supply circuit 20 is a circuit that operates between a voltage VCC and a ground potential GND, receives a gate voltage VG, and outputs an internal power supply voltage VE. The source of the MOS transistor P41 is connected to the output line S.

[0070] The gates of the MOS transistor P41 and the MOS transistor N41 are commonly connected and are supplied with an input signal IN. The input signal IN is supplied to the inverter IV, and the output of the inverter IV is input to the gate of the MOS transistor P42.

[0071] Fig. 11 is a diagram showing a number of signal waveforms for explaining the operation of the semiconductor device driver circuit 400. Fig. 11 shows, from top to bottom, a waveform diagram of an input signal IN, a waveform diagram of a gate voltage VG, a waveform diagram of an internal power supply voltage VE of the internal power supply circuit 20, a waveform diagram of an output voltage Vgn of the pre-driver 41, and a waveform diagram of an output sink current Ig' of the MOS transistor N42.

[0072] When the input signal IN changes from high level to low level, in the pre-driver 41, the MOS transistor P41 turns on and the MOS transistor N41 turns off, and the output voltage Vgn of the pre-driver 41 transitions from the internal power supply voltage VE of the internal power supply circuit 20 to the ground potential GND. Also, the MOS transistor P42 turns off due to the output of the inverter IV.

[0073] This turns on the MOS transistor N42, causing the gate voltage VG to drop, and the internal power supply voltage VE to drop accordingly, causing the output voltage Vgn to also drop. This reduces the gate-source voltage of the MOS transistor N42, and therefore reduces the output sink current Ig' of the MOS transistor N42.

[0074] The gate voltage VG decreases from the voltage VCC, passes through a mirror period, decreases again, and finally becomes constant at the ground potential GND.

[0075] In this way, the semiconductor device driver circuit 400 outputs the gate voltage VG having a waveform that decreases from the voltage VCC and becomes constant at the ground potential GND after a mirror period. The internal power supply circuit 20 receives this gate voltage VG as an input and adopts a configuration in which the current flowing inside changes in an analog manner, thereby making it possible to continuously change the output voltage Vgn of the pre-driver 41, which operates between the internal power supply voltage VE of the internal power supply circuit 20 and the voltage VCC, as shown in FIG. 11.

[0076] Therefore, as shown in Fig. 11, when approaching the mirror period, the output sink current Ig' can be reduced from the time when switching starts, and the current amount can be maintained during the mirror period. Therefore, as shown in Fig. 11, the surge voltage generated in the collector-emitter voltage Vce of IGBT1 can be suppressed, and switching loss can be reduced.

[0077] <Modification> Fig. 12 is a circuit diagram showing a configuration of a semiconductor device driver 401 according to a modification of the fourth embodiment of the present disclosure. As shown in Fig. 12, the semiconductor device driver 401 includes an N-channel MOS transistor N44 connected between the output node ND0 and the ground potential GND, in addition to the configuration of the semiconductor device driver 400 shown in Fig. 10.

[0078] The MOS transistor N44 is a sink side output transistor, and its gate is connected to the Q output of the SR flip-flop circuit FF. The inverted signal of the gate voltage VG is input to the S input of the SR flip-flop circuit FF via the inverter IV1, and the input signal IN is input to the R input. The rising edge of the input signal IN triggers the gate of the MOS transistor N33 to go from high to low. Here, by setting the threshold value of the inverter IV1 to near zero volts, the gate of the MOS transistor N44 goes from low to high and turns on when the gate voltage VG falls to near zero volts, that is, when it is detected that the gate voltage VG has reached a value near zero volts. This allows the internal power supply voltage VE to fall to the ground potential GND.

[0079] When the internal power supply voltage VE reaches near the ground potential GND, the gate-source voltage of the MOS transistor N42 falls below the threshold value of the MOS transistor N42 and the MOS transistor N42 turns off, thereby further reducing the output sink current Ig' of the MOS transistor N42 and further suppressing the surge voltage of the collector-emitter voltage Vce of the IGBT1. After the MOS transistor N42 turns off, the gate voltage VG drops and the MOS transistor N44 turns on, thereby preventing the gate voltage VG from rising due to the driving of the IGBT1.

[0080] <Other application examples> The semiconductor device driver circuits of the first to fourth embodiments described above have been described as driver circuits for the IGBT 1, but this is merely one application example of the present disclosure and the present disclosure is not limited to this.

[0081] For example, the present invention can be applied to the drive circuits for each power switching device in a half-bridge output circuit that combines two power switching devices, the present invention can be applied to the drive circuits for each power switching device in a full-bridge output circuit that combines four power switching devices, and the present invention can be applied to the drive circuits for each power switching device in a three-phase inverter circuit that combines six power switching devices.

[0082] The present invention can also be applied to a drive circuit for a power switching device in a system that controls an inductive load such as a motor using a half-bridge output circuit, a full-bridge output circuit, or a three-phase inverter circuit.

[0083] Further, although an IGBT has been exemplified as a power switching device to be controlled, the present invention is not limited to this, and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) can also be used as a controlled device.

[0084] In addition, within the scope of the present disclosure, it is possible to freely combine the respective embodiments, and to appropriately modify or omit the respective embodiments.

[0085] The present disclosure described above will now be summarized as an appendix.

[0086] (Appendix 1) A semiconductor device driver circuit for driving a power switching device, comprising: a first transistor and a second transistor connected in series and operating in a complementary manner between a first voltage and a second voltage lower than the first voltage; an internal power supply circuit including a constant voltage generating section that operates between the first voltage and the second voltage and outputs an internal power supply voltage that is normally a constant voltage, and a feedback section that receives a node voltage of a connection node between the first transistor and the second transistor and changes the internal power supply voltage output from the constant voltage generating section in response to a change in the node voltage; a pre-driver that operates between the first voltage and the internal power supply voltage and drives the first transistor or the second transistor; A semiconductor device driver that outputs the node voltage as a gate voltage of the power switching device.

[0087] (Appendix 2) The first transistor is a P-channel MOS transistor, The pre-driver drives the P-channel MOS transistor, The internal power supply circuit includes: 2. The semiconductor device driver circuit according to claim 1, further comprising: a first input terminal for inputting a first voltage to the first gate electrode;

[0088] (Appendix 3) The second transistor is a P-channel MOS transistor, The pre-driver drives the P-channel MOS transistor, The internal power supply circuit includes: 2. The semiconductor device driver circuit according to claim 1, wherein the internal power supply voltage is increased in response to a decrease in the gate voltage.

[0089] (Appendix 4) A semiconductor device driver circuit for driving a power switching device, comprising: a first transistor and a second transistor connected in series and operating in a complementary manner between a first voltage and a second voltage lower than the first voltage; an internal power supply circuit including a constant voltage generating section that operates between the first voltage and the second voltage and outputs an internal power supply voltage that is normally a constant voltage, and a feedback section that receives a node voltage of a connection node between the first transistor and the second transistor and changes the internal power supply voltage output from the constant voltage generating section in response to a change in the node voltage; a pre-driver that operates between the internal power supply voltage and the second voltage and drives the first transistor or the second transistor; A semiconductor device driver that outputs the node voltage as a gate voltage of the power switching device.

[0090] (Appendix 5) The first transistor is an N-channel MOS transistor, The pre-driver drives the N-channel MOS transistor, The internal power supply circuit includes: 5. The semiconductor device driver circuit according to claim 4, wherein the internal power supply voltage is increased in response to an increase in the gate voltage.

[0091] (Appendix 6) The second transistor is an N-channel MOS transistor, The pre-driver drives the N-channel MOS transistor, The internal power supply circuit includes: 5. The semiconductor device driver circuit according to claim 4, wherein the internal power supply voltage is decreased in response to a decrease in the gate voltage. [Explanation of symbols]

[0092] 1 IGBT, 10, 20 internal power supply circuit, 11, 21, 31, 41 pre-driver, AP follower circuit, CM1, CM2, CM10, CM20, CM30 current mirror circuit, CI constant current source, N, P power supply line, R1, R2 resistive element, P12, P33, N12, N22, N23, N42, N43 MOS transistor, L signal line.

Claims

1. A semiconductor device driver circuit for driving a power switching device, comprising: a first transistor and a second transistor connected in series and operating in a complementary manner between a first voltage and a second voltage lower than the first voltage; an internal power supply circuit including a constant voltage generating section that operates between the first voltage and the second voltage and outputs an internal power supply voltage that is a constant voltage in a steady state; and a feedback section that receives a node voltage of a connection node between the first transistor and the second transistor and changes the internal power supply voltage output from the constant voltage generating section in response to a change in the node voltage; a pre-driver that operates between the first voltage and the internal power supply voltage and drives the first transistor or the second transistor; A semiconductor device driver that outputs the node voltage as a gate voltage of the power switching device.

2. The first transistor is a P-channel MOS transistor, The pre-driver drives the P-channel MOS transistor, The internal power supply circuit includes:

2. The semiconductor device driver according to claim 1, wherein said internal power supply voltage is decreased in response to an increase in said gate voltage.

3. The second transistor is a P-channel MOS transistor, The pre-driver drives the P-channel MOS transistor, The internal power supply circuit includes:

2. The semiconductor device driver according to claim 1, wherein said internal power supply voltage is increased in response to a decrease in said gate voltage.

4. A semiconductor device driver circuit for driving a power switching device, comprising: a first transistor and a second transistor connected in series and operating in a complementary manner between a first voltage and a second voltage lower than the first voltage; an internal power supply circuit including a constant voltage generating section that operates between the first voltage and the second voltage and outputs an internal power supply voltage that is a constant voltage in a steady state; and a feedback section that receives a node voltage of a connection node between the first transistor and the second transistor and changes the internal power supply voltage output from the constant voltage generating section in response to a change in the node voltage; a pre-driver that operates between the internal power supply voltage and the second voltage and drives the first transistor or the second transistor; A semiconductor device driver that outputs the node voltage as a gate voltage of the power switching device.

5. The first transistor is an N-channel MOS transistor, The pre-driver drives the N-channel MOS transistor, The internal power supply circuit includes:

5. The semiconductor device driver according to claim 4, wherein said internal power supply voltage is increased in response to an increase in said gate voltage.

6. The second transistor is an N-channel MOS transistor, The pre-driver drives the N-channel MOS transistor, The internal power supply circuit includes:

5. The semiconductor device driver according to claim 4, wherein said internal power supply voltage is decreased in response to a decrease in said gate voltage.

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