Semiconductor Device

Abstract

To provide a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics), and also to provide the semiconductor device including the transistor with high reliability.SOLUTION: A semiconductor device includes a dual-gate transistor in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a channel width direction of the transistor, a side surface of each of the first and second gate electrodes is at an outer side of a side surface of the oxide semiconductor film. The first or second gate electrode faces the side surface of the oxide semiconductor film via a gate insulating film provided between the first or second gate electrode and the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including a transistor having an oxide semiconductor film and a manufacturing method thereof. [Background technology]

[0002] A transistor (thin film transistor (TFT)) is made by using a semiconductor thin film formed on a substrate. The technology of constructing a transistor is attracting attention. It is widely used in electronic devices such as image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used, but other materials and Oxide semiconductors have been attracting attention as a new type of semiconductor.

[0003] For example, indium (In), gallium (Ga) and nickel are used as the active layer of a transistor. A transistor using an oxide semiconductor containing lead (Zn) has been disclosed (see Patent Document 1). .).

[0004] In addition, a technique for improving carrier mobility by forming an oxide semiconductor layer into a stacked structure is also known. are disclosed (see Patent Documents 2 and 3). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A [Patent Document 2] JP 2011-138934 A [Patent Document 3] JP 2011-124360 A Summary of the Invention [Problem to be solved by the invention]

[0006] One aspect of the present invention is to improve electrical properties (e.g., on-current, field effect mobility, frequency characteristics, etc.) To provide a semiconductor device having an excellent transistor, or a highly reliable transistor The present invention provides a semiconductor device having [Means for solving the problem]

[0007] According to one embodiment of the present invention, an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. A transistor having a dual gate structure in which a gate electrode is provided in the channel width direction of the transistor. In the present invention, the side surfaces of the first gate electrode and the second gate electrode are on the side of the oxide semiconductor film. It is a semiconductor device located outside the surface.

[0008] According to one embodiment of the present invention, an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. A transistor having a dual gate structure that can be used for a long period of time. In a log-log graph showing the amount of variation in the threshold voltage of a capacitor, the interval between the logarithmic scales on the horizontal and vertical axes is Similarly, the power approximation line of the threshold voltage fluctuation with respect to the stress time and the threshold voltage fluctuation The angle between the voltage and the 0V line is less than 30° and the stress time is 0.1 hours. The variation of the threshold voltage when the semiconductor device is subjected to stress is less than 0.2 V. This refers to the time during which a transistor is subjected to a load of voltage, temperature, etc.

[0009] According to one embodiment of the present invention, an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. A transistor having a dual gate structure that can be used for a long period of time. In a log-log graph showing the amount of variation in the threshold voltage of a capacitor, the interval between the logarithmic scales on the horizontal and vertical axes is The slope of the power approximation line of the threshold voltage variation is equal to or less than 0.5, and the stress time is The semiconductor device has a threshold voltage variation of less than 0.2 V in 0.1 hour.

[0010] The first gate electrode or the second gate electrode is The gate electrode and the oxide semiconductor film are connected to each other through a gate insulating film provided between the gate electrode and the oxide semiconductor film. It may be opposite the side surface.

[0011] The first gate electrode and the second gate electrode are disposed outside the oxide semiconductor film with an insulating film interposed therebetween. It is also acceptable to have them face to face in this manner.

[0012] The transistor may have a channel etch structure. In addition, the distance between the pair of electrodes on the oxide semiconductor film is set to 1 μm or more and less than 4 μm. can be done.

[0013] The oxide semiconductor film is In, M (M is Al, Ga, Y, Zr, La, Ce, or Nd ) and Zn, and the atomic ratio of In is equal to or greater than the atomic ratio of M. It can be formed with a tapping target. Effect of the Invention

[0014] According to one embodiment of the present invention, the electrical characteristics (e.g., on-current, field effect mobility, frequency characteristics, etc.) It is possible to provide a semiconductor device having a transistor having excellent characteristics. According to one embodiment, a semiconductor device including a highly reliable transistor can be provided. [Brief description of the drawings]

[0015] [Figure 1] 1A and 1B are diagrams illustrating reliability of a transistor. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Diagram 3] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 4] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a transistor. [Diagram 5] FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor. [Figure 6] FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 8] FIG. 1 illustrates a band structure of a transistor. [Figure 9] 1A and 1B are a block diagram and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 10] FIG. 1 is a top view illustrating one embodiment of a semiconductor device. [Figure 11] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Figure 13] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Figure 14] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Figure 15] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Figure 17] FIG. 1 is a diagram showing an electron microbeam diffraction pattern of an oxide semiconductor. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 20] FIG. 13 is a diagram illustrating the Vg-Id characteristics of a transistor. [Figure 21]FIG. 13 is a diagram illustrating the Vg-Id characteristics of a transistor after a GBT test. [Figure 22] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 23] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Diagram 25] FIG. 13 is a diagram illustrating ΔVth of a transistor versus stress time. [Figure 26] 1 is a cross-sectional view illustrating a structure of a transistor. [Figure 27] FIG. 13 is a diagram for explaining the results of calculating a current-voltage curve. [Figure 28] 11A and 11B are diagrams illustrating calculation results of a potential of a transistor. [Figure 29] FIG. 1 is a diagram illustrating a model. [Diagram 30] FIG. 1 is a diagram illustrating a model. [Diagram 31] FIG. 13 is a diagram for explaining the results of calculating a current-voltage curve. [Diagram 32] 1 is a cross-sectional view illustrating a structure of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments and examples. In the following embodiments and examples, the same parts or parts having similar functions are In the case of parts, the same reference numerals or the same hatch patterns are used in common among different drawings, and the repetition The explanation of the repetition will be omitted.

[0017] In each figure described in this specification, the size, thickness, or area of ​​each component is indicated by the following formula: The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0018] In addition, the terms "first," "second," "third," etc., used in this specification are used interchangeably to avoid confusion of components. The number is added for convenience and is not intended to be a numerical limit. The terms can be replaced with "second" or "third" as appropriate for explanation.

[0019] The function of the "source" and "drain" is to change the direction of the current during circuit operation. For this reason, in this specification, the terms "sauce" and "dressing" are used interchangeably. The terms "in" and "in" may be used interchangeably.

[0020] Voltage is the potential difference between two points, and potential is the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in a particle. Generally, the potential difference between a potential at a certain point and a reference potential (for example, ground potential) This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, potential may be read as voltage. In this specification, voltage may be read as potential.

[0021] In this specification, when an etching process is performed after a photolithography process, The mask formed in the photolithography process is removed.

[0022] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. Please refer to the following for explanation.

[0023] 2A to 2C are a top view and a cross-sectional view of a transistor 50 included in a semiconductor device. The transistor 50 shown in FIG. 2 is a channel-etched transistor. 2(A) is a top view of the transistor 50, and FIG. 2(B) is a top view of the transistor 50 along the dashed line A- FIG. 2(C) is a cross-sectional view taken along dashed line CD in FIG. 2(A). In FIG. 2A, for clarity, the substrate 11, the gate insulating film 17, the oxide insulating film 23, The oxide insulating film 24, the nitride insulating film 25, etc. are omitted.

[0024] The transistor 50 shown in FIG. 2B and FIG. 2C has a gate The electrode 15, the substrate 11, and the gate insulating film 17 formed on the gate electrode 15; The oxide semiconductor film 18 overlaps the gate electrode 15 via the insulating film 17. a pair of electrodes 21 and 22 in contact with the gate insulating film 17, an oxide semiconductor film 18, and a pair of A protective film 26 on the electrodes 21 and 22 and a gate electrode 14 overlapping the oxide semiconductor film 18 via the protective film 26. The protective film 26 has an oxide insulating film 23, an oxide insulating film 24, and It has a nitride insulating film 25 .

[0025] The transistor 50 shown in this embodiment has a plurality of gate electrodes. The transistor has a dual-gate structure including an oxide semiconductor film 18 between the gate and the gate electrodes. In the channel width direction shown in FIG. 1, an end of the gate electrode 29 is positioned outside the oxide semiconductor film 18. Alternatively, in the channel width direction, the gate electrode 29 is formed of an oxide film via the protective film 26. The oxide semiconductor film 18 is disposed on the side of the oxide semiconductor film 18 in the channel width direction. On the outside, the gate electrode 15 and the gate electrode 29 are covered with the gate insulating film 17 and the protective film 26. They face each other via.

[0026] FIG. 2(D) is an enlarged view of the dashed line 30 in FIG. 2(C). The positions of the ends of the electrode 15, the oxide semiconductor film 18, and the gate electrode 29 will be described.

[0027] As shown in FIG. 2D, the end of the oxide semiconductor film 18 and the end of the gate electrode 29 The distance between the end of the oxide semiconductor film 18 and the gate electrode 24 is d and the thickness of the protective film 26 is t. The distance d between the ends of the protective film 26 and the oxide semiconductor layer 29 is preferably equal to or smaller than the thickness t of the protective film 26. The distance d between the end of the conductive film 18 and the end of the gate electrode 29 is set to be equal to or smaller than the thickness t of the protective film 26. This allows the electric field of the gate electrode 29 to affect the end portion of the oxide semiconductor film 18. Therefore, the entire oxide semiconductor film 18 including the ends can be made to function as a channel.

[0028] At the edge of the oxide semiconductor film that is processed by etching or the like, the oxide semiconductor film is damaged during the processing. As a result, defects are formed and the material is contaminated by impurities. By providing the trace, the edge of the oxide semiconductor film is easily activated, and the n-type Therefore, in the present embodiment, the oxide semiconductor layer overlapping the gate electrode 15 is The end of the conductive film 18 is easily converted to n-type. If the region is provided between 21 and 22, the region becomes a path for carriers, resulting in a parasitic channel. However, as shown in FIG. 2C, a gate electrode is formed on the outside of the oxide semiconductor film 18. Since the end of the gate electrode 29 is located at the position, the oxide semiconductor This suppresses the generation of parasitic channels on or near the sides of the membrane 18. The drain current rises sharply at the threshold voltage, resulting in a transistor with excellent electrical characteristics. become.

[0029] In addition, by providing the gate electrode 15 and the gate electrode 29, the gate electrode 15 and By setting the gate electrode 29 at the same potential, a region in which carriers flow in the oxide semiconductor film 18 is The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 50 increases, the field effect mobility increases.

[0030] In addition, by providing the gate electrode 15 and the gate electrode 29, the electric field from the outside can be prevented. In order to have a function of shielding the gate electrode 29 from the substrate 11, the gate electrode 15, and the like, The charge of the charged particles or the like that is absorbed by the oxide semiconductor film 18 is not affected by the charge. (For example, applying a negative charge to the gate - GBT (Gate Bias-Tempera The degradation of the drain current is suppressed and the on-state current at different drain voltages is improved. The fluctuation of the voltage at the start of the current can be suppressed. This occurs when the gate electrode 29 and the gate electrode 5 are at the same potential or at different potentials.

[0031] The BT stress test is a type of accelerated test that detects the transitions that occur during long-term use. It is possible to evaluate the characteristic changes (i.e., aging) of the transistor in a short time. The amount of change in the threshold voltage of a transistor before and after stress testing is used to examine reliability. This is an important indicator. The smaller the change in threshold voltage before and after the BT stress test, the Therefore, it can be said that this is a highly reliable transistor.

[0032] Also, the gate electrode 15 and the gate electrode 29 are included. By making the potentials of the transistors 29 the same, the amount of variation in the threshold voltage is reduced. At the same time, the variation in the electrical characteristics of the transistors is reduced.

[0033] In addition, the transistor 50 is subjected to a +GBT stress test in which a positive charge is applied to the gate. The amount of variation in threshold voltage is small.

[0034] In the transistor 50 shown in this embodiment, a gate B that applies a positive charge to the gate Before and after the T stress test, the change in threshold voltage with respect to the stress time (ΔVth The power approximation line L1 representing the threshold voltage Vth is shown in Figure 1. If the amount of variation in is plotted on a graph, the plotted values ​​can be approximated by a power law approximation line. The power approximation line is a straight line on a log-log graph. The horizontal axis represents the logarithm of the stress time, and the vertical axis represents the logarithm of the amount of change in the threshold voltage. The conditions for the stress test were a board temperature of 60°C and a dark room (da rk environment), apply +30V to the gate voltage and leave it for an arbitrary time, for example, 1 hour. This is the condition under which a stress of 100 .mu.m is applied to the transistor.

[0035] In FIG. 1, the power approximation line L1 is a straight line on a double logarithmic graph, so the horizontal and vertical axes When the intervals between the graduations are equal, the power approximation line L 1 and the straight line when there is no change in threshold voltage with respect to stress time (ΔVth is 0V). That is, the angle θ between the straight line L2 with a slope of 0 shown by the dashed line in FIG. 1 is less than 30 degrees or 25 The intervals of the logarithmic scales on the horizontal and vertical axes are equal, for example, The stress time is 10 times longer at intervals from 0.01 to 0.1 hours, and on the vertical axis, ΔV This means that the interval between 0.01V and 0.1V, where th is 10 times larger, is equal.

[0036] The smaller the angle θ, the smaller the fluctuation in threshold voltage due to aging. It is a highly reliable transistor.

[0037] In addition, in FIG. 1, if the horizontal axis is x and the vertical axis is y, the power approximation line can be expressed by the following formula 1. Here, b and C are constants, and b corresponds to the slope of the power approximation line.

[0038]

number

[0039] The slope b of the power approximation line L1 of the transistor 50 shown in this embodiment is 0.5V / hr or less, or 0.4V / hr or less, and the stress time is 0.1 hours. Vth is less than 0.2V or less than 0.5V.

[0040] The smaller the slope b of the power approximation line L1, the smaller the fluctuation in threshold voltage due to aging. It is a highly reliable transistor. In addition, ΔVth when the stress time is 0.1 hours is The smaller the value, the higher the reliability of the transistor at the initial stage of operation. The slope b of L1 is 0.5 V / hr or less, or 0.4 V / hr or less, and the stress Transistors with ΔVth of less than 0.2 V or less than 0.5 V at 0.1 hour Sta is highly reliable.

[0041] In FIG. 2A, the width of the gate electrode 15 in the channel length direction is smaller than the width of the gate electrode 15 in the channel length direction. The width of the semiconductor film 18 is large, but the channel The width of the gate electrode 15 can be made larger than the width of the oxide semiconductor film 18 in the longitudinal direction. As a result, it is possible to block light irradiation from the substrate 11 side by the gate electrode 15. Therefore, fluctuations in the electrical characteristics of the transistor 51 can be suppressed. FIG. 3(B) is a top view of the transistor 51, and FIG. 3(A) is a top view of the transistor 51 between the dashed line AB in FIG. 3(C) is a cross-sectional view taken along dashed line CD in FIG. 3(A).

[0042] In this embodiment, the gate electrode 15 and the gate electrode 29 are connected to each other. However, the gate electrode 15 and the gate electrode 29 are not connected, and different potentials are applied to each of them. may be added.

[0043] Other configuration details of transistor 50 are described below.

[0044] There is no particular restriction on the material of the substrate 11, but it should be at least strong enough to withstand the subsequent heat treatment. It is necessary to have heat resistance. For example, glass substrate, ceramic substrate, quartz substrate, surface treatment substrate, etc. A fiber substrate or the like may be used as the substrate 11. Also, a single material such as silicon or silicon carbide may be used. Crystalline semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SO It is also possible to use a semiconductor substrate such as an I-substrate, and a semiconductor element is provided on the substrate. In addition, when a glass substrate is used as the substrate 11, Generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm), 8th Generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm), 1st By using large area substrates such as 2950mm x 3400mm, large display devices can be produced. can be produced.

[0045] In addition, a flexible substrate is used as the substrate 11, and the transistor 50 is directly formed on the flexible substrate. Alternatively, a release layer may be provided between the substrate 11 and the transistor 50. The layer is separated from the substrate 11 after a semiconductor device is partially or completely completed thereon, and then the layer is removed. In this case, the transistor 50 is placed on a substrate having poor heat resistance. It can also be transferred to a plate or flexible substrate.

[0046] The gate electrode 15 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. or an alloy containing the above-mentioned metal elements, It can be formed by using an alloy of a combination of metal elements. The metal element may be selected from one or more of the following: The electrode 15 may have a single-layer structure or a laminated structure of two or more layers. Single layer structure of aluminum film, double layer structure of aluminum film laminated on titanium film, titanium nitride Two-layer structure with a titanium film laminated on a titanium nitride film, and two-layer structure with a tungsten film laminated on a titanium nitride film. A two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film. A two-layer structure in which a copper film is laminated on a titanium film, and a titanium film and an aluminum film are laminated on the titanium film. There are three-layer structures, such as a titanium film on top of the laminated aluminum. Choose from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, a film of any of the elements mentioned above, an alloy film of a combination of a plurality of elements, or a nitride film may be used.

[0047] The gate electrode 15 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide with titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminate structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element may also be used.

[0048] The gate insulating film 17 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn metal An oxide, a silicon nitride, or the like may be used, and the insulating film is provided as a laminated layer or a single layer.

[0049] The gate insulating film 17 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium Silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium minate (HfAl x O y N z ), hafnium oxide, yttrium oxide and other high- The use of k-materials can reduce the gate leakage of transistors.

[0050] The thickness of the gate insulating film 17 is 5 nm or more and 400 nm or less, and 10 nm or more and 300 nm or less. , or 50 nm or more and 250 nm or less.

[0051] The oxide semiconductor film 18 is typically an In-Ga oxide film, an In-Zn oxide film, or an In -M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd).

[0052] When the oxide semiconductor film 18 is an In-M-Zn oxide film, the sum of In and M is When the atomic percentage of In is 100 atomic%, the atomic percentage of M is 25 atomic%. or more and M is less than 75 atomic %, or In is 34 atomic % or more and M is 6 Less than 6 atomic%.

[0053] The oxide semiconductor film 18 has an energy gap of 2 eV or more, 2.5 eV or more, or eV or more. In this way, by using an oxide semiconductor with a wide energy gap, The off-state current of the transistor 50 can be reduced.

[0054] The thickness of the oxide semiconductor film 18 is 3 nm or more and 200 nm or less, and more preferably 3 nm or more and 100 nm or less. , or 3 nm or more and 50 nm or less.

[0055] The oxide semiconductor film 18 is an In-M-Zn oxide film (wherein M is Al, Ga, Y, Zr, La, or C e, or Nd), the sputtering method used to deposit In-M-Zn oxide The atomic ratio of the metal elements in the target preferably satisfies In≧M and Zn≧M. The atomic ratio of metal elements in such a sputtering target is In:M:Zn=1:1. In:M:Zn=3:1:2 is preferable. The atomic ratios are calculated by taking into account the error of the metal elements contained in the sputtering target. The atomic ratio can vary within a range of ±40%. A high n content increases the on-state current of the transistor and enhances the field effect mobility. Therefore, the oxide semiconductor film 18 is formed by using a metal element having an atomic ratio of In:M:Zn=3:1:2. By using an In-M-Zn oxide sputtering target, Excellent transistors can be fabricated.

[0056] As the oxide semiconductor film 18, an oxide semiconductor film with low carrier density is used. For example, The oxide semiconductor film 18 has a carrier density of 1×10 17 pieces / cm 3 Below, 1×10 15 pieces / cm 3 Below, 1×10 13 pieces / cm 3 or less, or 1×10 11 pieces / cm 3 The following oxides A semiconductor film is used.

[0057] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the carrier density and impurity of the oxide semiconductor film 18 are controlled. By appropriately adjusting the concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. is preferred.

[0058] Note that the oxide semiconductor film 18 is an oxide semiconductor having a low impurity concentration and a low density of defect states. By using a thin film, it is possible to fabricate transistors with even better electrical properties. Here, it is preferable that the impurity concentration is low and the defect level density is low (there is little oxygen vacancy). High purity authentic or substantially high purity authentic. High purity authentic or substantially high purity authentic Some oxide semiconductors have a small number of carrier generation sources, so the carrier density can be reduced. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may In this case, the threshold voltage is rarely negative (also called normally-on). In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has a high density of defect states. The trap density may also be low due to the low concentration of high purity intrinsic or substantially The high-purity intrinsic oxide semiconductor film has a significantly small off-state current and a channel width of 1×10 6 Even if the device has a channel length L of 10 μm, the voltage between the source and drain electrodes In the drain voltage range of 1V to 10V, the off-state current was measured by the semiconductor parameter analyzer. Below the riser measurement limit, i.e. 1×10 -13 It is possible to obtain a characteristic of A or less. Therefore, the transistor in which the channel region is formed in the oxide semiconductor film has a change in electrical characteristics. In some cases, the transistor can have low resistance to electric fields and high reliability. Charges trapped in the top level take a long time to dissipate, and are treated as if they were fixed charges. Therefore, the channel is formed in the oxide semiconductor film having a high density of trap states. The electrical characteristics of the transistor in which the region is formed may become unstable. , hydrogen, nitrogen, an alkali metal, or an alkaline earth metal.

[0059] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. Oxygen vacancies are formed in the lattice from which oxygen has been removed (or in the portion from which oxygen has been removed). When hydrogen enters the electron carrier, it can generate electrons. When it bonds with oxygen, which bonds with a metal atom, it may generate electrons, which act as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen has normally-on characteristics. It's easy to become.

[0060] For this reason, it is preferable that the amount of hydrogen in the oxide semiconductor film 18 be reduced as much as possible. Specifically, the oxide semiconductor film 18 is subjected to secondary ion mass spectrometry (SIMS). The hydrogen concentration obtained by ion mass spectrometry (DIAMS) was 5×10 19 atoms / cm 3 Below, 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Below, 1×10 18 atoms / cm 3 Below, 5 x 10 17 at oms / cm 3 or less, or 1×10 16 atoms / cm 3 The following applies.

[0061] When the oxide semiconductor film 18 contains silicon or carbon, which is one of the group 14 elements, As a result, oxygen vacancies increase in the oxide semiconductor film 18, and the oxide semiconductor film 18 becomes n-type. The concentration of silicon and carbon in the semiconductor film 18 (concentration obtained by secondary ion mass spectrometry) ) to 2 x 10 18 atoms / cm 3 or less, or 2×10 17 atoms / cm 3 Below Below.

[0062] In addition, in the oxide semiconductor film 18, an alkali metal oxide was obtained by secondary ion mass spectrometry. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2× 10 16 atoms / cm 3 The following are the oxides of alkali metals and alkaline earth metals. When it bonds with a semiconductor, carriers may be generated, increasing the off-state current of the transistor. For this reason, the alkali metal or alkaline earth metal of the oxide semiconductor film 18 It is preferable to reduce the concentration of the genus.

[0063] In addition, when the oxide semiconductor film 18 contains nitrogen, electrons that serve as carriers are generated. The rear density increases and it becomes easier to make it n-type. As a result, A transistor having such an oxide semiconductor film tends to be normally on. It is preferable that the nitrogen content is reduced as much as possible. For example, in the secondary ion mass spectrometry, The resulting nitrogen concentration is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0064] The oxide semiconductor film 18 may have a non-single crystal structure. , CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline structure, microcrystalline structure (described below), or Among non-single crystal structures, the amorphous structure has the highest defect level density and CA AC-OS has the lowest defect state density.

[0065] The oxide semiconductor film 18 may have, for example, an amorphous structure. For example, the atomic arrangement is disordered and does not have crystalline components. Or, the oxide film has an amorphous structure. For example, it has a completely amorphous structure and does not have any crystalline parts.

[0066] Note that the oxide semiconductor film 18 may be divided into an amorphous region, a microcrystalline region, a polycrystalline region, and a polycrystalline region. The film may be a mixed film having two or more of the following regions: a region of a CAAC-OS structure, a region of a single crystal structure, and a region of a crystalline structure. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAA In some cases, the crystal structure may have two or more regions, either a C-OS region or a single crystal structure region. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAA In some cases, the material has a layered structure of two or more regions, either a C-OS region or a single crystal structure region. be.

[0067] The pair of electrodes 21 and 22 are made of aluminum, titanium, chromium, nickel, copper, yttrium, elemental metals consisting of aluminum, zirconium, molybdenum, silver, tantalum, or tungsten; Or an alloy containing this as a main component is used as a single layer structure or a laminate structure. A single-layer structure of an aluminum film containing titanium, a two-layer structure of an aluminum film laminated on a titanium film, Two-layer structure with aluminum film laminated on tungsten film, copper-magnesium-aluminum Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film, tungsten A two-layer structure in which a copper film is laminated on a titanium film, a titanium film or titanium nitride film, and a titanium film or In the method, an aluminum film or a copper film is laminated on a titanium nitride film, and a titanium film is further laminated on the aluminum film or a copper film. Or a three-layer structure forming a titanium nitride film, a molybdenum film or a molybdenum nitride film, and An aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and There is also a three-layer structure in which a molybdenum film or a molybdenum nitride film is formed on top of the above. Transparent conductive materials including indium oxide, tin oxide or zinc oxide may also be used.

[0068] The oxide insulating film 23 is an oxygen-permeable oxide insulating film. 2. Reducing damage to the oxide semiconductor film 18 when forming the oxide insulating film 24 to be formed later. It also functions as a membrane.

[0069] The oxide insulating film 23 has a thickness of 5 nm or more and 150 nm or less, or 5 nm or more and 50 A silicon oxide film, a silicon oxynitride film, or the like having a thickness of 0.1 nm or less can be used. In the present specification, a silicon oxynitride film is a film having a composition in which oxygen is more abundant than nitrogen. The term silicon nitride oxide refers to a film that contains more nitrogen than oxygen. Refers to the membrane.

[0070] In addition, it is preferable that the oxide insulating film 23 has a small amount of defects. Therefore, the spin of the signal at g=2.001 originating from the silicon dangling bond Density is 3×10 17 spins / cm 3 This is because the oxide insulation If the film 23 contains a large number of defects, oxygen will be bonded to the defects, and the oxide insulating film 2 This is because the amount of oxygen permeating through 3 decreases.

[0071] In addition, the number of defects at the interface between the oxide insulating film 23 and the oxide semiconductor film 18 is small. Preferably, typically, the ESR measurement shows that the oxide semiconductor film 18 has a defect-derived g=1 The spin density of the signal appearing at .93 is 1×10 17 spins / cm 3 Further detection It is preferably equal to or lower than the lower limit.

[0072] Note that in the oxide insulating film 23, all of the oxygen that has entered the oxide insulating film 23 from the outside is Some oxygen does not move outside the oxide insulating film 23 and remains in the oxide insulating film 23. As oxygen enters the oxide insulating film 23, the oxygen contained in the oxide insulating film 23 In some cases, oxygen may move in the oxide insulating film 23 due to the movement of oxygen to the outside.

[0073] When an oxide insulating film that transmits oxygen is formed as the oxide insulating film 23, the oxide insulating film 23 The oxygen desorbed from the oxide insulating film 24 provided on the oxide insulating film 23 is transported to the oxide insulating film 23 via the oxide insulating film 23. It can be transferred to the semiconductor film 18 .

[0074] An oxide insulating film 24 is formed so as to be in contact with the oxide insulating film 23. 4 is formed using an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. The oxide insulating film containing more oxygen than the stoichiometric composition is heated to remove the oxygen. A part of the element is released. The oxide insulating film contains more oxygen than the oxygen that satisfies the stoichiometric composition. In TDS analysis, the amount of oxygen released was 1.0 x 10 18 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 The oxide insulating film is as described above. do.

[0075] The oxide insulating film 24 has a thickness of 30 nm to 500 nm, or 50 nm or more. A silicon oxide film, a silicon oxynitride film, or the like having a thickness of 400 nm or less can be used.

[0076] In addition, it is preferable that the oxide insulating film 24 has a small amount of defects. Therefore, the spin of the signal at g=2.001 originating from the silicon dangling bond Density is 1.5×10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 Note that the oxide insulating film 24 has a thickness smaller than that of the oxide insulating film 23. Since the oxide insulating film 23 is located away from the oxide semiconductor film 18, the oxide insulating film 23 may have a higher defect density. stomach.

[0077] Further, oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, etc. are deposited on the oxide insulating film 24. By providing the nitride insulating film 25 having the blocking effect, Diffusion of oxygen to the outside and intrusion of hydrogen, water, etc. into the oxide semiconductor film 18 from the outside are prevented. The nitride insulating film can be a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or the like. The following films are available: aluminum film, aluminum oxide nitride film, etc. Instead of a nitride insulating film with a blocking effect of potassium earth metals, etc., oxygen, hydrogen, water, etc. An oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. may be provided. Examples of the oxide insulating film having a blocking effect include an aluminum oxide film and an aluminum oxynitride film. , gallium oxide film, gallium oxynitride film, yttrium oxide film, yttrium oxynitride film , hafnium oxide film, hafnium oxynitride film, etc.

[0078] The configuration of the protective film 26 is not limited to the above configuration, and may be an oxide insulating film or a nitride insulating film as appropriate. The film may be a single layer or a multilayer. Alternatively, a multilayer structure such as two layers or four layers may be used. It is possible.

[0079] Next, a manufacturing method of the transistor 50 shown in FIGS.

[0080] As shown in FIG. 4A, a gate electrode 15 is formed on a substrate 11. A gate insulating film 17 is formed.

[0081] Here, a glass substrate is used as the substrate 11.

[0082] The method of forming the gate electrode 15 will be described below. First, the sputtering method, the CVD method, and the evaporation method are used. A conductive film is formed by deposition or the like, and a photolithography process is performed on the conductive film using a first photomask. A mask is formed by a etching process. Next, a part of the conductive film is etched using the mask. This forms the gate electrode 15. After that, the mask is removed.

[0083] The gate electrode 15 may be formed by electrolytic plating, printing, ink jet printing, or the like instead of the above-mentioned method. It may be formed by a jet method or the like.

[0084] Here, a tungsten film having a thickness of 200 nm is formed by sputtering. A mask is formed by a photolithography process, and a tungsten film is formed using the mask. The gate electrode 15 is formed by dry etching.

[0085] The gate insulating film 17 is formed by a sputtering method, a CVD method, a vapor deposition method or the like.

[0086] The gate insulating film 17 is a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. When forming a silicon film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of deposition gases containing silicon include silane, disilane, Examples of oxidizing gases include trisilane, fluorinated silane, etc. Examples of oxidizing gases include oxygen, ozone, and nitrous oxide. , nitrogen dioxide, etc.

[0087] In addition, when a gallium oxide film is formed as the gate insulating film 17, MOCVD (Metal Organic Chemical Vapor Deposition (OCVD) method It can be formed by:

[0088] Here, the gate insulating film 17 is a silicon nitride film having a thickness of 400 nm and a silicon nitride film having a thickness of 50 nm. The silicon nitride film is formed by stacking a silicon oxynitride film having a thickness of 100 nm and a silicon oxynitride film having a thickness of 100 nm. The silicon oxynitride film is formed by the plasma CVD method using ammonia as the raw material gas. It is formed by the plasma CVD method using orthogonal and dinitrogen monoxide as raw material gases.

[0089] Next, as shown in FIG. 4B, an oxide semiconductor film 18 is formed on the gate insulating film 17. .

[0090] The method for forming the oxide semiconductor film 18 will be described below. Then, a second film is formed on the oxide semiconductor film. After forming a mask by a photolithography process using a photomask, By etching a part of the oxide semiconductor film, an element-isolated region is formed as shown in FIG. This forms the oxide semiconductor film 18. Then, the mask is removed.

[0091] The oxide semiconductor film that will later become the oxide semiconductor film 18 can be formed by sputtering, coating, pulse The layer can be formed by using a laser deposition method, a laser ablation method, or the like.

[0092] When an oxide semiconductor film is formed by a sputtering method, a power source for generating plasma The device may be an RF power supply device, an AC power supply device, a DC power supply device, or the like, as appropriate.

[0093] The sputtering gas is a mixture of a rare gas and oxygen, a rare gas (typically argon), In the case of a mixture of rare gas and oxygen, the ratio of oxygen to rare gas is It is preferable to increase the ratio.

[0094] The target may be appropriately selected depending on the composition of the oxide semiconductor film to be formed. .

[0095] In order to obtain a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film, Not only is it necessary to evacuate the inside of the chamber to a high vacuum, but it is also necessary to highly purify the sputtering gas. The oxygen and argon gases used for this purpose have dew points of -40°C or less, -80°C or less, and -100°C or less. By using a gas that has been highly purified to a temperature of −120° C. or lower, the oxide semiconductor film is This can prevent as much of the waste as possible from being taken in.

[0096] Here, we used an In-Ga-Zn oxide target (In:Ga:Zn=3:1:2) and An oxide semiconductor film was formed by a sputtering method using oxygen as a sputtering gas. A 35-nm-thick In-Ga-Zn oxide film is formed. Next, a mask is placed on the oxide semiconductor film. Then, a part of the oxide semiconductor film is selectively etched to form an oxide semiconductor film 18. Form.

[0097] Next, as shown in FIG. 4(C), a pair of electrodes 21 and 22 are formed.

[0098] The method for forming the pair of electrodes 21 and 22 will be described below. First, the sputtering method and the CVD method are used. A conductive film is formed by a method such as a deposition method or a vapor deposition method. Next, a photolithography method is performed on the conductive film using a third photomask. A mask is formed by a lithography process. Then, the conductive film is etched using the mask. This forms a pair of electrodes 21 and 22. After that, the mask is removed.

[0099] Here, a tungsten film having a thickness of 50 nm, an aluminum film having a thickness of 400 nm, and a A titanium film having a thickness of 200 nm is then laminated on the titanium film by sputtering. A mask is formed by a photolithography process, and a tungsten film and an aluminum film are formed by using the mask. The aluminum film and the titanium film are dry etched to form a pair of electrodes 21 and 22 .

[0100] Next, as shown in FIG. 4(D), on the oxide semiconductor film 18 and the pair of electrodes 21 and 22, The oxide insulating film 23 is formed. Next, the oxide insulating film 24 is formed on the oxide insulating film 23. .

[0101] After the oxide insulating film 23 is formed, the oxide insulating film 2 is successively removed without being exposed to the air. After the oxide insulating film 23 is formed, the source gas The oxide insulating film 24 is continuously formed by adjusting one or more of the flow rate, pressure, high frequency power, and substrate temperature. By forming the oxide insulating film 23 and the oxide insulating film 24 in In addition, the impurity concentration in the oxide insulating film 24 can be reduced. The amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced. It is possible.

[0102] The substrate placed in the evacuated processing chamber of the plasma CVD device was heated to 280°C or higher and 400°C. The raw material gas is introduced into the processing chamber to maintain the pressure in the processing chamber at 20 Pa or more and 25 0 Pa or less, or 100 Pa to 250 Pa or less, and high pressure is applied to the electrodes installed in the treatment chamber. Depending on the conditions of supplying the high-frequency power, the oxide insulating film 23 may be a silicon oxide film or an oxynitride film. A silicon film can be formed.

[0103] As the source gas for the oxide insulating film 23, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, Examples of oxidizing gases include trisilane, fluorinated silane, etc. Examples of oxidizing gases include oxygen, ozone, and nitrous oxide. , nitrogen dioxide, etc.

[0104] By using the above conditions, an oxide insulating film that transmits oxygen is formed as the oxide insulating film 23. In addition, by providing the oxide insulating film 23, the oxide insulating film In the formation step of 24, damage to the oxide semiconductor film 18 can be reduced.

[0105] The oxide insulating film 23 is placed in a vacuum evacuated processing chamber of a plasma CVD apparatus. The substrate is maintained at a temperature of 280° C. or higher and 400° C. or lower, and a source gas is introduced into the processing chamber. The pressure in the treatment chamber is set to 100 Pa or more and 250 Pa or less, and high-frequency power is applied to the electrode installed in the treatment chamber. Depending on the conditions for supplying oxygen, the oxide insulating film 23 may be a silicon oxide film or a silicon oxynitride film. A silicon film can be formed.

[0106] Under the film formation conditions, by setting the substrate temperature to the above temperature, the bonding strength between silicon and oxygen As a result, the oxide insulating film 23 is oxygen-permeable, dense, and hard. Oxide insulating film, typically, etching rate for 0.5% by weight hydrofluoric acid at 25°C Silicon oxide film or silicon oxynitride film with a deposition rate of 10 nm / min or less, or 8 nm / min or less A coating can be formed.

[0107] In addition, since the oxide insulating film 23 is formed while heating, the oxide semiconductor Hydrogen, water, etc. contained in the oxide semiconductor film 18 can be desorbed. The hydrogen is combined with oxygen radicals generated in the plasma to become water. During the film formation process, the substrate is heated, and the water generated by the combination of oxygen and hydrogen is That is, the oxide insulating film 23 is formed by the plasma CVD method. By forming the oxide semiconductor film 18, the amount of water and hydrogen contained in the oxide semiconductor film 18 can be reduced. do.

[0108] In addition, since heating is performed in the process of forming the oxide insulating film 23, the oxide semiconductor film 18 The heating time in an exposed state is short, and oxygen is released from the oxide semiconductor film by heat treatment. That is, the amount of oxygen vacancies in the oxide semiconductor film can be reduced. This can be done.

[0109] Furthermore, by setting the pressure in the treatment chamber to 100 Pa or more and 250 Pa or less, the oxide insulating film The water content in the 23 is reduced, which reduces the variation in the electrical characteristics of the transistor 50. It is possible to reduce the threshold voltage and suppress the fluctuation of the threshold voltage.

[0110] In addition, by setting the pressure in the treatment chamber to 100 Pa or more and 250 Pa or less, the oxide insulating film 23 When forming the oxide semiconductor film 18, damage to the oxide semiconductor film 18 can be reduced. In particular, the amount of oxygen vacancies in the oxide insulating film 23 can be reduced. Alternatively, the deposition temperature of the oxide insulating film 24 to be formed later is increased, typically to 220° C. or higher. By setting the temperature at a low level, part of oxygen contained in the oxide semiconductor film 18 is released, and oxygen vacancies are formed. In addition, in order to improve the reliability of the transistor, the oxide insulating film 2 to be formed later is By using the film formation conditions for reducing the amount of defects in 4, the amount of oxygen desorption is easily reduced. As a result, it may be difficult to reduce oxygen vacancies in the oxide semiconductor film 18. The pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less during the formation of the oxide insulating film 23. By reducing damage to the oxide semiconductor film 18 caused by the oxidation of the oxide insulating film 24, the oxide semiconductor film 18 can be prevented from being damaged. The oxygen vacancies in the oxide semiconductor film 18 can be reduced by the amount of oxygen desorption.

[0111] In addition, by increasing the amount of oxidizing gas to 100 times or more the amount of deposition gas containing silicon, The hydrogen content in the oxide insulating film 23 can be reduced. Since the amount of hydrogen mixed into the semiconductor film 18 can be reduced, the threshold voltage of the transistor can be reduced. The shift can be suppressed.

[0112] Here, the oxide insulating film 23 is formed by plasma deposition using silane and dinitrogen monoxide as raw material gases. A silicon oxynitride film with a thickness of 50 nm is formed by the micro-CVD method. It is possible to form a silicon oxynitride film through which oxygen can pass.

[0113] The oxide insulating film 24 is placed in a vacuum-evacuated processing chamber of a plasma CVD apparatus. The substrate is kept at a temperature of 180°C to 280°C or 200°C to 240°C. The raw material gas is introduced into the processing chamber to keep the pressure in the processing chamber at 100 Pa or more and 250 Pa or less, or 00 Pa to 200 Pa, and 0.17 W / cm2 to the electrode installed in the treatment chamber 2 End 0.5W / cm 2 or less than 0.25W / cm 2 More than 0.35W / cm 2 High frequency below Depending on the conditions of power supply, a silicon oxide film or a silicon oxynitride film is formed.

[0114] As the source gas of the oxide insulating film 24, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, Examples of oxidizing gases include trisilane, fluorinated silane, etc. Examples of oxidizing gases include oxygen, ozone, and nitrous oxide. , nitrogen dioxide, etc.

[0115] The oxide insulating film 24 is formed under the conditions of high frequency irradiation with the above power density in a processing chamber at the above pressure. Supplying microwave power increases the efficiency of decomposing the source gas in the plasma, and oxygen radicals are increased. As the source gas is added, the oxidation of the source gas proceeds, so that the oxygen content in the oxide insulating film 24 becomes stoichiometric. On the other hand, in the film formed at the substrate temperature, the composition of silicon and oxygen is Since the bonding strength is weak, some of the oxygen in the film is released by the heat treatment in the subsequent process. It contains more oxygen than the stoichiometric composition, and some of the oxygen is released by heating. In addition, the oxide insulating film 2 can be formed over the oxide semiconductor film 18. Therefore, in the process of forming the oxide insulating film 24, the oxide insulating film 2 3 serves as a protective film for the oxide semiconductor film 18. As a result, damage to the oxide semiconductor film 18 is prevented. Therefore, the oxide insulating film 24 can be formed by using high-frequency power with high power density while reducing the Cut.

[0116] In addition, in the deposition conditions of the oxide insulating film 24, the deposition gas containing silicon is By increasing the flow rate of the reactive gas, it is possible to reduce the number of defects in the oxide insulating film 24. Typically, ESR measurements reveal that the g value is 2.0 due to the dangling bonds of silicon. The spin density of the signal appearing in 01 is 6×10 17 spins / cm 3 Less than 3×10 17 s pins / cm 3 or less, or 1.5×10 17 spins / cm 3 The defect amount is less than or equal to As a result, the reliability of the transistor can be improved. This can be done.

[0117] Here, the oxide insulating film 24 is formed by plasma deposition using silane and dinitrogen monoxide as raw material gases. A silicon oxynitride film having a thickness of 400 nm is formed by the micro-CVD method.

[0118] Next, a heat treatment is performed. The temperature of the heat treatment is typically 150° C. or higher and 400° C. or lower. , 300°C or higher and 400°C or lower, or 320°C or higher and 370°C or lower.

[0119] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. The processing time can be reduced.

[0120] Heat treatment is carried out using nitrogen, oxygen, or ultra-dry air (water content less than 20 ppm, less than 1 ppm, or 10 ppb or less of air) or in an atmosphere of rare gas (argon, helium, etc.) In addition, the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. It is preferable.

[0121] By the heat treatment, part of oxygen contained in the oxide insulating film 24 is transferred to the oxide semiconductor film 18. By moving the oxygen vacancies, the amount of oxygen vacancies in the oxide semiconductor film 18 can be further reduced.

[0122] In the case where the oxide insulating film 23 and the oxide insulating film 24 contain water, hydrogen, or the like, Then, a nitride insulating film 25 having a blocking function is formed and a heat treatment is performed. Water, hydrogen, and the like contained in the oxide insulating film 23 and the oxide insulating film 24 are absorbed in the oxide semiconductor film 18. However, the oxidation of the oxide semiconductor film 18 is caused by the heating. It is possible to release water, hydrogen, and the like contained in the oxide insulating film 23 and the oxide insulating film 24. This reduces the variation in the electrical characteristics of the transistor 50 and suppresses the variation in the threshold voltage. It can be controlled.

[0123] Note that the oxide insulating film 24 is formed over the oxide insulating film 23 while being heated. By moving oxygen to the oxide semiconductor film 18, oxygen vacancies contained in the oxide semiconductor film 18 are reduced. Therefore, the heat treatment may not be performed.

[0124] Here, the heat treatment is performed in a mixed gas atmosphere of nitrogen and oxygen at 350° C. for 1 hour.

[0125] In addition, when the pair of electrodes 21 and 22 are formed, the conductive film is etched to form an oxide semiconductor. The oxide semiconductor film 18 is damaged, and the back channel of the oxide semiconductor film 18 (the oxide semiconductor film 18 In this case, oxygen vacancies occur on the surface opposite to the surface facing the gate electrode 15. The oxide insulating film 24 contains more oxygen than the oxygen that satisfies the stoichiometric composition. By applying this method, oxygen vacancies that occurred on the back channel side due to heat treatment can be repaired. This can reduce defects in the oxide semiconductor film 18. Therefore, the reliability of the transistor 50 can be improved.

[0126] Next, the nitride insulating film 25 is formed by sputtering, CVD or the like.

[0127] When the nitride insulating film 25 is formed by the plasma CVD method, The substrate placed in the evacuated processing chamber is heated to 300°C or higher and 400°C or lower, or 320°C or lower. A temperature of 370° C. or less is preferable because a dense nitride insulating film can be formed.

[0128] When a silicon nitride film is formed as the nitride insulating film 25 by the plasma CVD method, the silicon It is preferable to use a deposition gas containing carbon, nitrogen, and ammonia as the source gas. By using a small amount of ammonia as the source gas compared to nitrogen, ammonia is generated in the plasma. Ni dissociates and generates active species. The active species are contained in the deposition gas containing silicon. The bond between silicon and hydrogen and the triple bond between nitrogen are broken. As a result, silicon and nitrogen The bonding of silicon and hydrogen is promoted, resulting in fewer defects and a dense silicon nitride. On the other hand, the amount of ammonia relative to nitrogen in the source gas is If the amount is too large, the decomposition of the deposition gas containing silicon and nitrogen does not proceed, and silicon and hydrogen Bonds remain, resulting in a silicon nitride film with increased defects and a rough surface. For these reasons, the flow rate ratio of nitrogen to ammonia in the raw gas is set to 5 to 50. Alternatively, it is preferable to set it to 10 or more and 50 or less.

[0129] Here, the plasma CVD method is used with silane, nitrogen, and ammonia as raw material gases. A silicon nitride film is formed to a thickness of 100 nm.

[0130] Through the above steps, a film consisting of the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 is formed. A protective film 26 can be formed by the above process.

[0131] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150° C. or higher and 40° C. or lower. The temperature must be below 0°C, between 300°C and 400°C, or between 320°C and 370°C.

[0132] When the gate electrode 15 and the gate electrode 29 to be formed later are to be connected, the gate An opening is formed in the insulating film 17, the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25. Complete.

[0133] Next, as shown in FIG. 4(E), a gate electrode 29 is formed. The method is as follows: First, a conductive film is formed by sputtering, CVD, vapor deposition, etc. Then, a mask is formed on the conductive film by a photolithography process using a fourth photomask. Next, a part of the conductive film is etched using the mask to form a gate electrode 29. After that, the mask is removed.

[0134] As shown in FIG. 3C, the outer side of the oxide semiconductor film 18 in the channel width direction The gate electrode 29 is formed so that an end of the gate electrode 29 is positioned at the position indicated by the arrows.

[0135] Here, a 100 nm thick indium tin oxide (ITO) Next, a thin film is formed by a photolithography process. A mask is formed, and the ITO film having silicon oxide is wet etched using the mask. Then, the gate electrode 29 is formed. After that, a heat treatment may be performed.

[0136] Through the above steps, the transistor 50 can be manufactured.

[0137] A dual gate electrode having an oxide semiconductor film between a first gate electrode and a second gate electrode. A transistor having a gate structure, the first gate being disposed in a channel width direction of the transistor. The side surfaces of the first electrode and the second gate electrode are located outside the side surfaces of the oxide semiconductor film. By this, the electric field of the gate electrode 29 can be influenced on the end portion of the oxide semiconductor film 18. and the entire oxide semiconductor film 18 including its ends can function as a channel. As a result, it is possible to increase the on-state current of the transistor and improve the field effect mobility. It is possible.

[0138] In addition, the transistor described in this embodiment has a first gate electrode and a second gate electrode. Since the gate electrodes have a gate insulating layer, each gate electrode can block an electric field from the outside. As a result, the deterioration of the stress test is suppressed and the on-current at different drain voltages is improved. This makes it possible to suppress fluctuations in the start-up voltage, resulting in a transistor with excellent electrical characteristics. In addition, a semiconductor device having high reliability can be obtained. can.

[0139] <Modification 1, Regarding the Undercoat Insulating Film> In the transistor 50 of this embodiment, the substrate 11 and the gate electrode A base insulating film can be provided between the electrodes 15. The base insulating film can be made of silicon oxide. Silicon oxide nitride, silicon nitride, silicon oxide nitride, gallium oxide, hafnium oxide Examples of the oxides include aluminum oxide, yttrium oxide, aluminum oxide nitride, etc. The insulating film materials are silicon nitride, gallium oxide, hafnium oxide, and yttrium oxide. By using aluminum oxide or the like, impurities, typically alkali metals, The diffusion of water, hydrogen, and the like into the oxide semiconductor film 18 can be suppressed.

[0140] The base insulating film can be formed by a sputtering method, a CVD method, or the like.

[0141] <Modification 2: Gate insulating film> In the transistor 50 according to this embodiment, a gate insulating film 17 may be stacked as necessary. The gate insulating film 17 may have a layer structure. explain.

[0142] As shown in FIG. 5A, the gate insulating film 17 is made of a nitride insulating film 17a and an oxide insulating film. The gate electrode 15 may have a laminated structure in which the gate electrodes 17b and 17b are laminated in order from the gate electrode 15 side. By providing the nitride insulating film 17a on the electrode 15 side, impurities from the gate electrode 15, typically Hydrogen, nitrogen, an alkali metal, an alkaline earth metal, or the like moves to the oxide semiconductor film 18. This can prevent the following from happening:

[0143] In addition, by providing the oxide insulating film 17b on the oxide semiconductor film 18 side, the gate insulating film 17 In addition, the defect state density at the interface with the oxide semiconductor film 18 can be reduced. As a result, a transistor with little deterioration in electrical characteristics can be obtained. As the oxide insulating film 24, more oxygen than that satisfying the stoichiometric composition is used as the oxide insulating film b. When the oxide insulating film 17 is formed using an oxide insulating film containing This is more preferable since it is possible to further reduce the defect state density in the semiconductor layer.

[0144] As shown in FIG. 5B, the gate insulating film 17 is made up of a nitride insulating film 17c having few defects and The nitride insulating film 17d having high hydrogen blocking properties and the oxide insulating film 17b are formed on the gate electrode. The gate insulating film 17 may have a laminated structure in which the layers are laminated in order from the side of the gate insulating film 15. By providing the nitride insulating film 17c with a small amount of oxide, the dielectric strength of the gate insulating film 17 is improved. In addition, by providing the nitride insulating film 17d having high hydrogen blocking properties, Hydrogen from the gate electrode 15 and the nitride insulating film 17c moves to the oxide semiconductor film 18. It can be prevented.

[0145] An example of a method for forming the nitride insulating films 17c and 17d shown in FIG. The plasma CVD method uses a mixture of silane, nitrogen, and ammonia as the source gas. As a result, a silicon nitride film with few defects is formed as the nitride insulating film 17c. The gas was switched to a mixture of silane and nitrogen to reduce the hydrogen concentration and block hydrogen. A silicon nitride film capable of being etched is formed as the nitride insulating film 17d. By using this method, a nitride insulating film having few defects and a blocking property against hydrogen can be deposited. A layered gate insulating film 17 can be formed.

[0146] As shown in FIG. 5C, the gate insulating film 17 is made of a nitride having a high impurity blocking property. The insulating film 17e, the nitride insulating film 17c having few defects, and the nitride insulating film 17c having high hydrogen blocking properties A laminated structure in which an insulating film 17d and an oxide insulating film 17b are laminated in this order from the gate electrode 15 side. The gate insulating film 17 may be made of a nitride having a high impurity blocking property. By providing the insulating film 17e, impurities from the gate electrode 15, typically hydrogen, nitrogen, The alkali metal, the alkaline earth metal, or the like is prevented from migrating to the oxide semiconductor film 18. This can be done.

[0147] An example of a method for producing the nitride insulating films 17e, 17c, and 17d shown in FIG. 5(C) will be described below. First, a plasma was generated using a mixture of silane, nitrogen, and ammonia as the source gas. A silicon nitride film with high impurity blocking properties is formed by the CVD method as the nitride insulating film 17e. Next, the flow rate of ammonia is increased to form silicon nitride with fewer defects. The resulting film is formed as a nitride insulating film 17c. Next, the source gas is a mixed gas of silane and nitrogen. By switching to silicon nitride, which has a low hydrogen concentration and can block hydrogen, The nitride insulating film 17d is formed by using a silicon film. Also, a gate insulating film 17 is formed by laminating a nitride insulating film having an impurity blocking property. It is possible.

[0148] <Modification 3: Pair of Electrodes> The pair of electrodes 21 and 22 in the transistor 50 shown in this embodiment are elemental or non-elementary metals such as tantalum, titanium, aluminum, copper, molybdenum, chromium, or tantalum For the oxide semiconductor, a conductive material that easily bonds with oxygen, such as an alloy, can be used. The oxygen contained in the film 18 is bonded to the conductive material contained in the pair of electrodes 21 and 22 to form an oxide semiconductor. An oxygen vacancy region is formed in the conductive film 18. In addition, a pair of electrodes is formed in the oxide semiconductor film 18. In some cases, some of the constituent elements of the conductive material forming the electrodes 21 and 22 may be mixed in. As shown in FIG. 6, in the oxide semiconductor film 18, a region in contact with the pair of electrodes 21 and 22 The low resistance regions 20a and 20b are formed in the vicinity of each other. The gate insulating film 17 is formed between the pair of electrodes 21 and 22 and the gate insulating film 17. The low resistance regions 20a and 20b have high electrical conductivity, and therefore are in contact with the oxide semiconductor film 18 and a pair of electrodes. It is possible to reduce the contact resistance with 21 and 22, and increase the on-current of the transistor. It is possible to do this.

[0149] The pair of electrodes 21 and 22 are made of the conductive material that easily bonds with oxygen, titanium nitride, and nitrogen. Alternatively, the layer structure may be a laminate structure with a conductive material that is difficult to bond with oxygen, such as tantalum chloride or ruthenium. By using such a layered structure, the oxide insulating film 23 is In this way, it is possible to prevent the pair of electrodes 21 and 22 from being oxidized, and the pair of electrodes 21 and 22 can be highly It is possible to suppress the development of resistance.

[0150] <Modification 4: Oxide Semiconductor Film> In the method for manufacturing the transistor 50 described in this embodiment, After the formation of the oxide semiconductor film 18, the oxide semiconductor film 18 is exposed to plasma generated in an oxygen atmosphere to form an oxide semiconductor Oxygen can be supplied to the film 18. The oxidizing atmosphere can be oxygen, ozone, dinitrogen monoxide, etc. In the plasma treatment, the atmosphere is oxygen, nitrogen dioxide, etc. It is preferable to expose the oxide semiconductor film 18 to plasma generated without applying a bias. As a result, oxygen can be supplied to the oxide semiconductor film 18 without damaging it. As a result, the amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced. The etching process removes impurities, such as fluorine and chlorine, remaining on the surface of the oxide semiconductor film 18. It is possible to remove halogens, etc. Also, the plasma treatment is not heated to 300°C or higher. It is preferable to perform the treatment while keeping the oxygen in the plasma and the hydrogen contained in the oxide semiconductor film 18 bonded to each other. Since the substrate is heated, the water is released from the oxide semiconductor film 18. As a result, the amount of hydrogen and water contained in the oxide semiconductor film 18 can be reduced.

[0151] <Variation 5> The transistor 50 according to this embodiment requires that the substrate be kept at a temperature of 280° C. or higher and 400° C. or lower. By forming the oxide insulating film 23, hydrogen, water, and the like contained in the oxide semiconductor film 18 can be removed. On the other hand, after the oxide semiconductor film 18 shown in FIG. 0°C or higher but lower than the substrate distortion point, 200°C or higher but lower than 450°C, or 300°C or higher but lower than 450°C After the heat treatment, the substrate is kept at 180° C. to 260° C. while the oxide insulating film is formed. As a result, the content of hydrogen, water, and the like in the oxide semiconductor film 18 is It is possible to further reduce the charge and discharge current, and to fabricate a transistor with superior electrical characteristics. can be done.

[0152] The structures and methods described in this embodiment may be used in conjunction with structures and methods described in other embodiments and examples. and the like.

[0153] (Embodiment 2) In this embodiment, the number of defects in the oxide semiconductor film is further reduced compared to that in the first embodiment. A semiconductor device having a transistor capable of implementing the above-mentioned method will be described with reference to the drawings. The transistor described in this embodiment has a structure different from that in the first embodiment in that an oxide semiconductor film is stacked. The difference is that it has a multilayer film.

[0154] 7A and 7B are a top view and a cross-sectional view of a transistor 60 included in the semiconductor device. 7(B) is a cross-sectional view of the transistor 60 taken along dashed line AB in FIG. 7(C) is a cross-sectional view taken along dashed line CD in FIG. 7(A). In (A), for clarity, the substrate 11, the gate insulating film 17, the oxide insulating film 23, and the oxide insulating film 24 are shown. The insulating film 24, the nitride insulating film 25, etc. are omitted.

[0155] The transistor 60 shown in FIG. 7A to FIG. 7C has a gate An electrode 15, a gate insulating film 17, and a gate electrode 15 overlapping the gate insulating film 17. A multilayer film 20, a pair of electrodes 21 and 22 in contact with the multilayer film 20, a gate insulating film 17, and a multilayer film 20, a protective film 26 on the pair of electrodes 21 and 22, and a gate electrode 29 on the protective film 26; The protective film 26 includes an oxide insulating film 23, an oxide insulating film 24, and a nitride insulating film 25. The protective film 26 functions as a gate insulating film.

[0156] In the transistor 60 described in this embodiment, the multilayer film 20 includes the oxide semiconductor film 18 and The multilayer film 20 has a two-layer structure. A part of the oxide film 18 functions as a channel region. An oxide insulating film 23 is formed between the oxide semiconductor film 18 and the oxide insulating film 23. A semiconductor film 19 is provided. In addition, an oxide insulating film 23 is provided so as to be in contact with the oxide insulating film 23. 24 has been formed.

[0157] The oxide semiconductor film 19 is composed of one or more elements that constitute the oxide semiconductor film 18. Therefore, at the interface between the oxide semiconductor film 18 and the oxide semiconductor film 19, Therefore, the movement of carriers is not hindered at the interface. This increases the field effect mobility of the transistor.

[0158] The oxide semiconductor film 19 is typically an In-Ga oxide film, an In-Zn oxide film, or an In -M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), and The energy of the bottom of the conduction band is closer to the vacuum level than that of the oxide semiconductor film 18. The energy of the bottom of the conduction band of the oxide semiconductor film 19 and the bottom of the conduction band of the oxide semiconductor film 18 The difference in energy between the 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less That is, the electron affinity of the oxide semiconductor film 19 and the electron affinity of the oxide semiconductor film 18 are The difference between the or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

[0159] The oxide semiconductor film 19 contains In, and thus has high carrier mobility (electron mobility). Therefore, it is preferable.

[0160] The oxide semiconductor film 19 is formed by doping Al, Ga, Y, Zr, La, Ce, or Nd with In. By having a higher atomic ratio, the following effects can be obtained in some cases. (2) To increase the energy gap of the oxide semiconductor film 19. (3) It blocks impurities from the outside. (4) It has higher insulation properties than the oxide semiconductor film 18. (5) Al, Ga, Y, Zr, La, Ce, and Nd bond with oxygen. Since it is a metal element with a strong combined force, oxygen deficiency is unlikely to occur.

[0161] When the oxide semiconductor film 19 is an In-M-Zn oxide film, the sum of In and M is 100 When expressed as atomic %, the atomic ratio of In and M is less than 50 atomic %. and M is 50 atomic% or more, or In is less than 25 atomic% and M is 75 atomic% or more tomic% or more.

[0162] The oxide semiconductor film 18 and the oxide semiconductor film 19 are In-M-Zn oxide films (M is In the case of the oxide semiconductor film 18, the thickness of the oxide semiconductor film 18 is 100 nm, and the thickness of the oxide semiconductor film 18 is 100 nm. The M (Al, Ga, Y, Zr, La, Ce, or Nd ) is larger than the above atoms contained in the oxide semiconductor film 18. , 1.5 times or more, 2 times or more, or 3 times or more higher atomic ratio.

[0163] The oxide semiconductor film 18 and the oxide semiconductor film 19 are In-M-Zn oxide films (M is In the case of In: M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor film 18 is In:M:Zn=x2 :y2:z2 [atomic ratio], y1 / x1 is greater than y2 / x2, or y 1 / x1 is 1.5 times greater than y2 / x2. Or, y1 / x1 is greater than y2 / x2. is more than twice as large, or y1 / x1 is more than three times as large as y2 / x2. In this case, In the oxide semiconductor film, when y2 is equal to or greater than x2, a transistor using the oxide semiconductor film can be manufactured using the oxide semiconductor film. This is preferable because it can impart stable electrical characteristics to the transistor.

[0164] The oxide semiconductor film 18 is an In-M-Zn oxide film (wherein M is Al, Ga, Y, Zr, La, In the case of Ce or Nd), the target used for depositing the oxide semiconductor film 18 In this case, if the atomic ratio of metal elements is In:M:Zn=x1:y1:z1, 、 x1 / y1 is , 1 / 3 or more and 6 or less, and further 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less. It is more preferable that z1 / y1 is 1 or more and 6 or less. This makes it easier to form a CAAC-OS film as the oxide semiconductor film 18. Representative examples of atomic ratios of metal elements are In:M:Zn=1:1:1, In:M:Zn =1:1:1.2, In:M:Zn=3:1:2, etc.

[0165] The oxide semiconductor film 19 is an In-M-Zn oxide film (wherein M is Al, Ga, Y, Zr, La, In the case of Ce or Nd), the target used for depositing the oxide semiconductor film 19 In this case, the atomic ratio of metal elements is In:M:Zn=x2:y2:z2. 、 x2 / y2< x1 / y1, z2 / y2 is 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. Note that when z2 / y2 is greater than or equal to 1 and less than or equal to 6, the oxide semiconductor film 19 can be formed with a thickness of 100 nm. The CAAC-OS film is easily formed by the above. For example, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn= 1:3:6, In:M:Zn=1:3:8, etc.

[0166] Note that the atomic ratios of the oxide semiconductor film 18 and the oxide semiconductor film 19 are each calculated using an error. The atomic ratios listed above may vary by ±40%.

[0167] The oxide semiconductor film 19 is a film formed by forming an oxide insulating film 24 later. It also functions as a film for reducing damage to the film 18 .

[0168] The thickness of the oxide semiconductor film 19 is 3 nm or more and 100 nm or less, or 3 nm or more and 50 nm or less. Let us assume that.

[0169] In addition, like the oxide semiconductor film 18, the oxide semiconductor film 19 may have a non-single crystal structure. The non-single crystal structure may be, for example, a CAAC-OS, a polycrystalline structure, or a microcrystalline structure. structure, or amorphous structure.

[0170] The oxide semiconductor film 19 may have, for example, an amorphous structure. For example, the atomic arrangement is disordered and does not have crystalline components. Or, the oxide film has an amorphous structure. For example, it has a completely amorphous structure and does not have any crystalline parts.

[0171] Note that in each of the oxide semiconductor film 18 and the oxide semiconductor film 19, the region of the amorphous structure The regions are: microcrystalline region, polycrystalline region, CAAC-OS region, and single crystal region. The mixed film may have two or more regions, for example, an amorphous structure region, The region may be a microcrystalline region, a polycrystalline region, a CAAC-OS region, or a single crystal region. In some cases, the mixed film may have a single layer structure having two or more regions. The structure is divided into three regions: microcrystalline structure, polycrystalline structure, CAAC-OS, and single crystal structure. There are cases where two or more of the regions have a laminated structure.

[0172] Here, the oxide semiconductor film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23. Therefore, impurities are not generated between the oxide semiconductor film 19 and the oxide insulating film 23. Even if a trap state is formed due to a defect, the trap state and the oxide semiconductor film 18 As a result, electrons flowing through the oxide semiconductor film 18 are captured by the trap states. This makes it difficult for the transistor to be captured, making it possible to increase the on-state current of the transistor and also reducing the field effect. In addition, when an electron is captured in a trap level, the electron becomes a miliplex. This results in a shift in the threshold voltage of the transistor. However, since there is a gap between the oxide semiconductor film 18 and the trap level, It is possible to reduce the trapping of electrons in the top level, thereby reducing the variation of the threshold voltage. It is possible.

[0173] In addition, the oxide semiconductor film 19 can block impurities from the outside. It is possible to reduce the amount of impurities that move from the oxide semiconductor film 18 to the oxide semiconductor film 18. The oxide semiconductor film 19 is less likely to form oxygen vacancies. It is possible to reduce the impurity concentration and the amount of oxygen vacancies.

[0174] The oxide semiconductor film 18 and the oxide semiconductor film 19 are not simply stacked. Continuous junction (here, a structure in which the energy at the bottom of the conduction band changes continuously between each film) In other words, trap centers and recombination centers are formed at the interfaces of each film. The layer structure is designed so that there are no impurities that would create a defect level. When impurities are present between the organic semiconductor film 18 and the oxide semiconductor film 19, the energy band The continuity of the interface is lost, and carriers are trapped at the interface or recombine and disappear. Wow.

[0175] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. Each film is laminated in succession using a sputtering device without exposing it to the air. Each chamber in the sputtering apparatus is required for the oxide semiconductor film. In order to remove impurities such as water as much as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum pump (5×10 -7 Pa~1×10 -4It is preferable to use a temperature of up to about 10 Pa. Alternatively, a turbo molecular pump and cold trap can be combined to separate the chamber from the exhaust system. It is preferable to prevent the backflow of gases into the bar, especially gases containing carbon or hydrogen. stomach.

[0176] In place of the multilayer film 20, a transistor 65 shown in FIG. 7(D) may be formed by using a multilayer film 3. 4.

[0177] The multilayer film 34 includes an oxide semiconductor film 31, an oxide semiconductor film 18, and an oxide semiconductor film 19. That is, the multilayer film 34 has a three-layer structure. It functions as:

[0178] In addition, the gate insulating film 17 and the oxide semiconductor film 31 are in contact with each other. An oxide semiconductor film 31 is provided between the oxide semiconductor film 18 and the oxide semiconductor film 19 .

[0179] The multilayer film 34 and the oxide insulating film 23 are in contact with each other. That is, an oxide semiconductor film 18 is formed between the oxide semiconductor film 18 and the oxide insulating film 23. A semiconductor film 19 is provided.

[0180] The oxide semiconductor film 31 can be formed by using a material and a method similar to those of the oxide semiconductor film 19. This can be done.

[0181] The oxide semiconductor film 31 is preferably thinner than the oxide semiconductor film 18. By making the thickness of the body film 31 1 nm or more and 5 nm or less, or 1 nm or more and 3 nm or less, It is possible to reduce the amount of variation in the threshold voltage of the transistor.

[0182] In the transistor described in this embodiment, Therefore, the oxide semiconductor film 19 and the oxide insulating film Even if a trap level is formed by impurities and defects between the nuclei 23, the trap level There is a gap between the oxide semiconductor film 18 and the position of the oxide semiconductor film 18. This makes it difficult for electrons to be captured by the trap level, which increases the on-current of the transistor. In addition, the field effect mobility can be increased. When captured, the electrons become a fixed negative charge. This results in the transistor However, the threshold voltage varies depending on the distance between the oxide semiconductor film 18 and the trap level. Since the distance between the trap levels is large, it is possible to reduce the capture of electrons at the trap levels. Fluctuations in the threshold voltage can be reduced.

[0183] In addition, the oxide semiconductor film 19 can block impurities from the outside. It is possible to reduce the amount of impurities that move from the oxide semiconductor film 18 to the oxide semiconductor film 18. The oxide semiconductor film 19 is less likely to form oxygen vacancies. It is possible to reduce the impurity concentration and the amount of oxygen vacancies.

[0184] In addition, an oxide semiconductor film 31 is provided between the gate insulating film 17 and the oxide semiconductor film 18. The oxide semiconductor film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23. Therefore, the silicon in the vicinity of the interface between the oxide semiconductor film 31 and the oxide semiconductor film 18 is the concentration of silicon or carbon in the oxide semiconductor film 18, or the concentration of silicon or carbon in the oxide semiconductor film 19 The concentration of silicon or carbon in the vicinity of the interface between the oxide semiconductor film 19 and the oxide semiconductor film 18 is reduced. As a result, the absorption coefficient of the multilayer film 34, which is derived by the constant photocurrent measurement method, The number is 1 × 10 -3 / cm or less than 1×10 -4 / cm, and the localized level is extremely There are very few.

[0185] The transistor 65 having such a structure is formed by a multilayer film 34 including an oxide semiconductor film 18. Since there are very few defects in the Typically, it is possible to increase the on-current and improve the field effect mobility. Threshold voltage fluctuations during BT stress testing and optical BT stress testing, which are examples of testing Small quantity and high reliability.

[0186] <Band structure of transistor> Next, the multilayer film 20 provided in the transistor 60 shown in FIG. 7(A) and the multilayer film 20 in FIG. The band structure of the multilayer film 34 provided in the transistor 65 shown in FIG. do.

[0187] Here, as an example, the oxide semiconductor film 18 has an energy gap of 3.15 eV. The oxide semiconductor film 19 is made of In-Ga-Zn oxide, which has an energy gap of 3 The energy gap of the In-Ga-Zn oxide is 0.5 eV. Measure using a meter (HORIBA JOBIN YVON UT-300) can be done.

[0188] Energy difference between the vacuum level and the top of the valence band of the oxide semiconductor film 18 and the oxide semiconductor film 19 (also called ionization potential) were 8 eV and 8.2 eV, respectively. The energy difference between the vacuum level and the top of the valence band is measured by ultraviolet photoelectron spectroscopy (UPS). Violet Photoelectron Spectroscopy (PH Measurements can be performed using a VersaProbe (manufactured by IHI Corporation).

[0189] Therefore, the vacuum level and the energy at the bottom of the conduction band of the oxide semiconductor film 18 and the oxide semiconductor film 19 are The energy difference (also called electron affinity) is 4.85 eV and 4.7 eV, respectively.

[0190] FIG. 8A shows a schematic diagram of a part of the band structure of the multilayer film 20. The case where a silicon oxide film is provided in contact with the film 20 will be described. EcI1 indicates the energy of the conduction band minimum of the silicon oxide film, and EcS1 indicates the energy of the oxide semiconductor film. 18, and EcS2 is the energy of the conduction band minimum of the oxide semiconductor film 19. EcI2 indicates the energy at the bottom of the conduction band of the silicon oxide film. cI1 corresponds to the gate insulating film 17 in FIG. 7(B), and EcI2 corresponds to In this case, it corresponds to the oxide insulating film 23.

[0191] As shown in FIG. 8A, in the oxide semiconductor film 18 and the oxide semiconductor film 19, The energy at the lower band edge changes smoothly without any barrier. In other words, it changes continuously. This is because the multilayer film 20 contains elements common to the oxide semiconductor film 18, Oxygen moves between the oxide semiconductor film 18 and the oxide semiconductor film 19, forming a mixed layer. This can be said to be because

[0192] As shown in FIG. 8A, the oxide semiconductor film 18 of the multilayer film 20 serves as a well. In the transistor using 0, a channel region is formed in the oxide semiconductor film 18. In addition, since the energy of the conduction band minimum of the multilayer film 20 changes continuously, It can also be said that the oxide semiconductor film 18 and the oxide semiconductor film 19 are in continuous junction.

[0193] As shown in FIG. 8A, near the interface between the oxide semiconductor film 19 and the oxide insulating film 23, Although trap levels due to impurities or defects may be formed near the oxide semiconductor film 1 By providing the oxide semiconductor film 18, the trap level can be kept away from the oxide semiconductor film 18. However, when the energy difference between EcS1 and EcS2 is small, the oxide semiconductor film 18 The electrons can exceed the energy difference and reach the trap level. When the oxide is trapped, negative charges are generated at the oxide-insulating film interface, causing the transistor threshold voltage to rise. The voltage value is shifted to the positive direction. If the difference is 0.1 eV or more, or 0.15 eV or more, the threshold voltage of the transistor This is preferable because it reduces voltage fluctuations and provides stable electrical characteristics.

[0194] FIG. 8B is a schematic diagram showing a part of the band structure of the multilayer film 20. In this example, a silicon oxide film is provided in contact with the multilayer film 20. In addition, EcI1 shown in FIG. 8B is the minimum conduction band of the silicon oxide film. EcS1 represents the energy of the bottom of the conduction band of the oxide semiconductor film 18, and E cI2 indicates the energy of the bottom of the conduction band of the silicon oxide film. 7B), EcI2 corresponds to the gate insulating film 17, and EcI3 corresponds to the oxide insulating film 17 in FIG. It corresponds to the membrane 23 .

[0195] In the transistor shown in FIG. 7B, the multilayer film 20 is formed when the pair of electrodes 21 and 22 are formed. In some cases, the upper part of the oxide semiconductor film 19 is etched. The upper surface of the oxide semiconductor film 18 is in contact with the oxide semiconductor film 18 during the formation of the oxide semiconductor film 19. 19 mixed layers may form.

[0196] For example, the oxide semiconductor film 18 is an In- Ga-Zn oxide, or In-Ga-Z with In:Ga:Zn=3:1:2 [atomic ratio] n oxide as a sputtering target, and The semiconductor film 19 is an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn=1:3:2. , In-Ga-Zn oxide with In:Ga:Zn=1:3:4 [atomic ratio], or In: In-Ga-Zn oxide with an atomic ratio of Ga:Zn=1:3:6 was used as a sputtering target. In the case where the oxide semiconductor film is formed using the above-mentioned method, the oxide semiconductor film is formed to have a larger thickness than the oxide semiconductor film 18. Since the conductor film 19 contains a large amount of Ga, a GaOx layer or a In this case, a mixed layer containing more Ga than the oxide semiconductor film 18 can be formed.

[0197] Therefore, even when the oxide semiconductor film 19 is etched, the Ec The energy at the bottom of the conduction band on the I2 side becomes higher, resulting in the band structure shown in Figure 8(B). There are cases.

[0198] In the case where the band structure is as shown in FIG. 8(B), when observing the cross section of the channel region, The multilayer film 20 may appear to be composed of only the oxide semiconductor film 18. In reality, a mixture containing more Ga than the oxide semiconductor film 18 is formed on the oxide semiconductor film 18. Since a mixed layer is formed, the mixed layer can be regarded as a 1.5 layer. When the elements contained in the multilayer film 20 are measured by, for example, EDX analysis, the mixed layer is This can be confirmed by analyzing the composition above the oxide semiconductor film 18. For example, The composition in the upper portion of the oxide semiconductor film 18 has a higher Ga content than the composition in the oxide semiconductor film 18. This can be confirmed by the configuration.

[0199] FIG. 8C shows a schematic diagram of a part of the band structure of the multilayer film 34. A case where a silicon oxide film is provided in contact with the film 34 will be described. EcI1 indicates the energy of the conduction band minimum of the silicon oxide film, and EcS1 indicates the energy of the oxide semiconductor film. 18, and EcS2 is the energy of the conduction band minimum of the oxide semiconductor film 19. EcS3 represents the energy at the bottom of the conduction band of the oxide semiconductor film 31, and Ec I2 indicates the energy of the bottom of the conduction band of the silicon oxide film. Also, EcI1 is shown in FIG. 7(D). 7(D), EcI2 corresponds to the oxide insulating film 17. Equivalent to 23.

[0200] As shown in FIG. 8C, the oxide semiconductor film 31, the oxide semiconductor film 18, and the oxide semiconductor In the film 19, the energy of the conduction band minimum changes smoothly without any barrier. This is because the multilayer film 34 changes continuously from the oxide semiconductor film 1 8, and an oxide semiconductor film is formed between the oxide semiconductor film 18 and the oxide semiconductor film 31. Oxygen moves between the oxide semiconductor film 18 and the oxide semiconductor film 19 to form a mixed layer. It can be said that this is for the purpose.

[0201] As shown in FIG. 8C, the oxide semiconductor film 18 of the multilayer film 34 becomes a well, and the multilayer film 3 In the transistor using the semiconductor device 4, a channel region is formed in the oxide semiconductor film 18. In addition, since the energy of the conduction band minimum changes continuously in the multilayer film 34, The oxide semiconductor film 31, the oxide semiconductor film 18, and the oxide semiconductor film 19 are continuously joined together. It can also be said that.

[0202] Note that in the vicinity of the interface between the oxide semiconductor film 18 and the oxide insulating film 23, In the vicinity of the interface with the gate insulating film 17, a trap level due to impurities or defects is formed. However, as shown in FIG. 8C, the oxide semiconductor films 19 and 31 are provided. This allows the oxide semiconductor film 18 to be separated from the trap level. When the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are small, Electrons in the oxide semiconductor film 18 may exceed the energy difference and reach the trap level. When electrons are captured in the trap levels, negative charges are generated at the oxide insulating film interface, The threshold voltage of the transistor is shifted in the positive direction. Therefore, EcS1 and E The energy difference between EcS1 and EcS2 and between EcS1 and EcS3 is 0.1 eV or more. , or 0.15 eV or more, the fluctuation of the threshold voltage of the transistor is reduced, and the This is preferable because it results in stable electrical characteristics.

[0203] Note that the structures and methods described in this embodiment may be different from the structures and methods described in other embodiments. They can be used in appropriate combination.

[0204] (Embodiment 3) In this embodiment, in the transistor having a dual gate structure described in Embodiment 2, The electrical characteristics of a transistor when different gate electrodes are connected and at the same potential are shown in Figure 7. 26 to 31.

[0205] In this case, the gate electrode 15 and the gate electrode 29 shown in FIG. 7 are electrically short-circuited. The driving method in which the gate voltage is applied to the two gate electrodes is called Dual Gate Drive. In the Al Gate drive, the voltage of the gate electrode 15 and the voltage of the gate electrode 29 are always equal. It becomes.

[0206] Here, we calculated the electrical characteristics of the transistor. Figure 26 shows the transistor used in the calculation. The structure of the device is shown in Fig. 1. The calculation was performed using the device simulation software Atlas (Sil A VACO (manufactured by Vaco) was used.

[0207] The transistor of Structure 1 shown in FIG. 26(A) is a transistor of a dual gate structure. do.

[0208] In the transistor of Structure 1, an insulating film 203 is formed on a gate electrode 201. The oxide semiconductor film 205 is formed on the insulating film 203 and the oxide semiconductor film 205. A pair of electrodes 207 and 208 are formed, and the oxide semiconductor film 205 and the pair of electrodes 207 and 2 An insulating film 209 is formed on the semiconductor layer 08. A gate electrode 213 is formed on the insulating film 209. The gate electrode 201 and the gate electrode 213 are formed on the insulating film 203 and the insulating film 209. The connection is made at an opening (not shown) provided in the through hole.

[0209] The transistor of Structure 2 shown in FIG. 26(B) is a transistor of a single gate structure. .

[0210] In the transistor of Structure 2, an insulating film 203 is formed on a gate electrode 201. The oxide semiconductor film 205 is formed on the insulating film 203 and the oxide semiconductor film 205. A pair of electrodes 207 and 208 are formed, and the oxide semiconductor film 205 and the pair of electrodes 207 and 2 An insulating film 209 is formed on the substrate 08 .

[0211] In the calculation, the work function φ of the gate electrode 201 M was set to 5.0 eV. The oxide semiconductor film 203 was set to a thickness of 100 nm and had a dielectric constant of 4.1. 5 is assumed to be a single layer of In-Ga-Zn oxide film (In:Ga:Zn=1:1:1), Band gap E of In-Ga-Zn oxide film g 3.15 eV, electron affinity χ 4.6 eV, relative dielectric constant of 15, and electron mobility of 10 cm 2 / Vs, and the donor density N d 3×10 17 atoms / cm 3 The work function φ of the pair of electrodes 207 and 208 is set as follows: sd 4. The dielectric constant of the insulating film 209 was set to 6 eV, forming an ohmic junction with the oxide semiconductor film 205. The oxide semiconductor film 205 had a defect ratio of 4.1 and a thickness of 100 nm. Models such as recessed levels and surface scattering are not taken into account. The channel widths were set to 10 μm and 100 μm, respectively.

[0212] <Reduction of initial characteristic variations> By using dual gate drive like the transistor shown in Structure 1, the initial characteristics This is because the dual gate drive reduces the Id -Vg characteristic threshold voltage V th The amount of change in is smaller than that of the transistor shown in Structure 2. This is due to the fact that

[0213] Here, as an example, the negative shift in Id-Vg characteristics due to the semiconductor film becoming n-type is This article explains the

[0214] The total charge of the donor ions is Q(C), and the gate electrode 201, the insulating film 203, and The capacitance formed by the oxide semiconductor film 205 is C Bottom The oxide semiconductor film 205 The capacitance formed by the insulating film 209 and the gate electrode 213 is C Top In this case, the structure The V of the transistor shown in Structure 1 th The amount of change ΔV is shown in formula (2). Transistor V th The amount of change ΔV is shown in formula (3).

[0215]

number

[0216]

number

[0217] As shown in formula (2), the dual gate drive transistor shown in structure 1 Then, the capacitance between the donor ion and the gate electrode is C Bottom、and C Top The harmony of Therefore, the amount of variation in the threshold voltage is reduced.

[0218] In addition, in the transistors of Structure 1 and Structure 2, the drain voltage was 0.1 V and The results of calculating the current-voltage curves at 1 V and 1 V are shown in FIG. 27. FIG. 27(B) is a current-voltage curve of the transistor shown in Structure 1, and FIG. 27(C) is a current-voltage curve of the transistor shown in Structure 2. When the drain voltage Vd is 0.1 V, the current-voltage curve of the transistor shown in structure 1 is The threshold voltage of the transistor shown in structure 2 is -2.26V. It was -4.73V.

[0219] When dual gate drive is adopted, like the transistor shown in Structure 1, the threshold The amount of voltage fluctuation is reduced. This reduces the variation in electrical characteristics among multiple transistors. is also reduced at the same time.

[0220] In this case, the negative shift of the threshold voltage due to donor ions was considered. The fixed charges, mobile charges, or negative charges (acceptor charges) in the film 203 and the insulating film 209 The positive shift of the threshold voltage due to the electrons trapped in the junctions is also suppressed. Therefore, it is considered that the variation is reduced.

[0221] <- Suppression of deterioration during GBT stress testing> In addition, by using dual gate drive like the transistor shown in Structure 1, -G The degradation of the -GBT stress test can be reduced. The reason why the above problem can be reduced will be explained below.

[0222] The first reason is that the dual gate drive does not cause electrostatic stress. FIG. 28(A) shows a transistor having a structure 1, in which a gate electrode 201 and a gate The potential contours were plotted when −30 V was applied to each of the gate electrodes 213. In addition, FIG. 28(B) shows the potential in the AB cross section of FIG. 28(A). show.

[0223] The oxide semiconductor film 205 is an intrinsic semiconductor, and a negative voltage is applied to the gate electrodes 201 and 213. When the gate electrodes 201 and 213 are fully depleted, no charge exists between them. In this state, when the gate electrode 201 and the gate electrode 213 are set to the same potential, the gate electrode 201 and the gate electrode 213 are set to the same potential as shown in FIG. As shown in B), the gate electrode 201 and the gate electrode 213 are at a completely equal potential. Since the potentials are equal, the insulating film 203, the oxide semiconductor film 205, and the insulating film 209 are subjected to electrostatic stress. As a result, the mobile ions and the capacitances in the insulating films 203 and 209 are not generated. The occurrence of phenomena that cause degradation during -GBT stress testing, such as rear trapping and detrapping, do not.

[0224] The second reason is that the dual gate drive eliminates the need for external current to drive the FET. The problem is that the field is shielded. Here, a transistor having a structure 1 shown in FIG. 26(A) and In each of the transistors of the structure 2 shown in FIG. 26(B), the insulating film 209 or the gate A model in which charged particles in the air are adsorbed onto the electrode 213 is shown in FIG.

[0225] As shown in FIG. 29B, in the transistor shown in Structure 2, the surface of the insulating film 209 When a negative voltage is applied to the gate electrode 201, positively charged particles in the air are attracted to the The charged particles are adsorbed to the insulating film 209. As a result, as shown by the arrows in FIG. The electric field of the charged particles affects the interface of the oxide semiconductor film 205 with the insulating film 209, and the As a result, the threshold voltage is thought to shift negatively. can be.

[0226] On the other hand, as shown in FIG. 29(A), in the transistor shown in Structure 1, the gate electrode Even if positively charged particles are attached to the surface of the 213, they are not absorbed by the gel, as shown by the arrows in Figure 29(A). Since the gate electrode 213 blocks the electric field of positively charged particles, the electrical characteristics of the transistor are affected by positive charges. That is, when the gate electrode 213 is provided, the transistor is not affected by external charges. It is possible to electrically protect the transistor, and deterioration during -GBT stress testing is suppressed. .

[0227] For these two reasons, the -GBT transistor is the most suitable for dual gate drive transistors. Deterioration of stress tests is suppressed.

[0228] <Suppression of fluctuations in on-current rise voltage at different drain voltages> Here, in the case of structure 2, the on-current rise voltage at different drain voltages is This section explains the fluctuations and their causes.

[0229] The transistor shown in FIG. 30 has a gate insulating film 233 provided on a gate electrode 231. An oxide semiconductor film 235 is provided over the gate insulating film 233. A pair of electrodes 237 and 238 is provided. A gate insulating film 233, an oxide semiconductor film 235, and An insulating film 239 is provided on the pair of electrodes 237 and 238 .

[0230] In the calculation, the work function φ of the gate electrode 231 M The gain was set to 5.0 eV. The insulating film 233 is a 400 nm thick film having a dielectric constant of 7.5 and a 400 nm thick film having a dielectric constant of 4.1. The oxide semiconductor film 235 is an In-Ga-Z Assuming a single layer of n-oxide film (In:Ga:Zn=1:1:1), an In-Ga-Zn oxide film Band gap E g 3.15 eV, electron affinity χ 4.6 eV, relative dielectric constant 15, Child mobility 10cm 2 / Vs, and the donor density N d is 1×10 13 / cm 3 It was set as follows. The work function φ of the pair of electrodes 237 and 238 sd The oxide semiconductor film 235 The dielectric constant of the insulating film 239 is set to 3.9 and the thickness is set to 550 nm. Note that models such as defect states and surface scattering in the oxide semiconductor film 235 were not taken into consideration. The channel length and width of the transistor are set to 3 μm and 50 μm, respectively. μm.

[0231] Next, in the transistor shown in FIG. 30(A), positively charged particles are introduced onto the surface of the insulating film 239. The model of the adsorbed transistor is shown in FIG. 30(B) and FIG. 30(C). In B), a structure is assumed in which positive fixed charges are uniformly distributed on the surface of the insulating film 239. In FIG. 2(C), a structure in which positive fixed charges are partially assumed on the surface of the insulating film 239 is shown. .

[0232] The results of calculating the electrical characteristics of the transistors shown in FIGS. 30A to 30C are shown in FIG. Shown in Figures 31(A) to 31(C).

[0233] As shown in FIG. 31A, a positive fixed potential is formed in the insulating film 239 of the transistor shown in FIG. When a constant charge is not assumed, the drain voltage (Vd) is 1V and 10V, respectively. The rise voltages are almost the same.

[0234] On the other hand, as shown in FIG. 31B, the insulating film 239 of the transistor shown in FIG. If we assume that the positive fixed charges are uniform, the threshold voltage is shifted negatively. The drain voltages (Vd) are 1V and 10V, and the rise voltages are approximately the same.

[0235] As shown in FIG. 31C, the insulating film 239 of the transistor shown in FIG. When assuming a partial positive fixed charge, the drain voltage (Vd) is 1V and 10V, Each voltage rises differently.

[0236] On the other hand, in the transistor shown in Structure 1, the gate electrode 213 is provided. As described above in <Suppression of Deterioration in GBT Stress Test>, the gate electrode 213 is Since the electric field of the charged particles in the semiconductor substrate is shielded, the charged particles do not affect the electrical characteristics of the transistor. That is, the presence of the gate electrode 213 electrically protects the transistor from external charges. It is possible to measure the variation of the on-state current rise voltage at different drain voltages. It can be suppressed.

[0237] From the above, it is possible to apply an arbitrary voltage to each gate electrode by using a dual gate structure. Suppression of degradation in -GBT stress test and on-current rise at different drain voltages It is possible to suppress the fluctuation of the voltage rise. In addition, the dual gate structure has a gate electrode By applying the same voltage, the initial characteristic variation is reduced, and the deterioration of the GBT stress test is reduced. It is possible to suppress the on-state current rise voltage fluctuation at different drain voltages. be.

[0238] <The distance between the end of the gate electrode and the end of the oxide semiconductor film in the channel width direction and the threshold About the fluctuation of voltage value> FIG. 32 is a schematic cross-sectional view of the transistor shown in Structure 1 in the channel width direction. Each component in the schematic cross-sectional view of the transistor shown in FIG. 32 corresponds to each component of the structure 1 shown in FIG. The composition and scale are different.

[0239] In the channel width direction of the transistor shown in Structure 1, the gate electrode 201 and the The gate electrode 213 protrudes from the oxide semiconductor film 205 by a distance t2 in the channel width direction. However, a structure in which a gate electrode facing the side surface of the oxide semiconductor film 205 is not provided is referred to as Structure 3. (See Figure 32(A)).

[0240] At this time, the amount of charge Q when the transistor shown in structure 3 is driven in dual gate mode is (Cm 2 ) by V th The amount of fluctuation ΔV4 is expressed by the formula (4).

[0241]

number

[0242] In addition, V in a transistor th The situation where the amount of change in can be expressed by formula (4) is that of oxide semiconductors. The charge on the side of the membrane 205 is V th only if it is the main factor causing the shift. For example, the gate electrode 201 or the gate electrode 213 is formed by channeling from the oxide semiconductor film 205. When the oxide semiconductor film 205 does not protrude in the width direction, the amount of donor ions on the side surface of the oxide semiconductor film 205 is In the case of structure 3, the charge may cause a parasitic channel to form. According to 4), the effect of electric charge is suppressed.

[0243] In the above, the donor ions on the side surface of the oxide semiconductor film 205 are considered to be the source of the charges. However, the fixed charges in the insulating film, the insulating film interface, or the oxide semiconductor film may be Even if the electrons or holes are trapped in the trap level, they are V th This has caused a shift in A similar argument applies if the problem is the main cause of the

[0244] As a more generalized example of the structure 3, the gate electrode 201 and the gate electrode 213 are oxide semiconductors. The conductive film 205 has a width direction X B , X T Structure 4, which is sticking out only (See Figure 32(B).) At this time, C Bottom and C. Top are the formulas (5) and can be rewritten as equation (6).

[0245]

number

[0246]

number

[0247] X B , X T When changing, formula (5) and formula (6) respectively become X B =t1+t os , X T =t3+t osThe maximum value C shown in formula (7) Bottom Max and formula (8) C shown in Top Max Take.

[0248]

number

[0249]

number

[0250] Therefore, based on equation (4), V th To minimize the amount of variation in X B =t1 +t os , X T =t3+t os It would be fine to say so.

[0251] Note that the structures and methods described in this embodiment may be different from the structures and methods described in other embodiments. They can be used in appropriate combination.

[0252] (Embodiment 4) In this embodiment, a semiconductor device which is one embodiment of the present invention will be described with reference to drawings. Note that in this embodiment, a semiconductor device which is one embodiment of the present invention will be described using a display device as an example. do.

[0253] FIG. 9A shows an example of a semiconductor device. The semiconductor device shown in FIG. 1, a scanning line driving circuit 104, and a signal line driving circuit 106 are arranged in parallel or approximately in parallel. m scanning lines 107 are provided and the potentials of which are controlled by a scanning line driving circuit 104, The individual electrodes are arranged in parallel or approximately in parallel, and the potential is controlled by a signal line driver circuit 106. The pixel section 101 has n signal lines 109. The pixel array has a number of pixels 100. The pixels 100 are arranged parallel or approximately parallel to each other along the signal line 109. The capacitance lines 115 are arranged along the scanning lines 107. The scanning line driving circuit 104 and the signal line driving circuit 105 may be arranged in a row or substantially in parallel. The circuit 106 may be collectively referred to as a drive circuit section.

[0254] Each scanning line 107 corresponds to one of the pixels 100 arranged in m rows and n columns in the pixel section 101. The signal lines 109 are electrically connected to the n pixels 100 arranged in any row. is m pixels 10 arranged in any one of the columns of the pixels 100 arranged in m rows and n columns. 0. Both m and n are integers of 1 or more. is n pixels 10 arranged in any one of the rows of the pixels 100 arranged in m rows and n columns. 0. The capacitance lines 115 are arranged parallel to each other along the signal line 109. In the case where the pixels 100 are arranged in m rows and n columns, any one of the pixels 100 may be arranged in a matrix of m rows and n columns. The pixel array 100 is electrically connected to m pixels 100 arranged in a column.

[0255] 9B and 9C can be used for the pixel 100 of the display device shown in FIG. 9A. 2 shows an example of a circuit configuration.

[0256] The pixel 100 shown in FIG. 9B includes a liquid crystal element 121, a transistor 103, and a capacitor element 105 and has.

[0257] The potential of one of the pair of electrodes of the liquid crystal element 121 is appropriately set according to the specifications of the pixel 100. The alignment state of the liquid crystal element 121 is set by the written data. A common potential (common potential) is applied to one of a pair of electrodes of the liquid crystal element 121 of each pixel 100. In addition, one of the pair of electrodes of the liquid crystal element 121 for each pixel 100 in each row may be applied with may be given different potentials.

[0258] The liquid crystal element 121 controls the transmission or non-transmission of light by the optical modulation effect of the liquid crystal. The optical modulation effect of liquid crystals is achieved by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field). The liquid crystal element 121 is controlled by an electric field in a direction or an electric field in an oblique direction. These include nematic liquid crystals, cholesteric liquid crystals, smectic liquid crystals, and thermotropic liquid crystals. , lyotropic liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc.

[0259] The display device having the liquid crystal element 121 can be driven in, for example, a TN mode or a VA mode. ASM (Axially Symmetric Aligned Micro-ce) ll) mode, OCB (Optically Compensated Birefringence ngence) mode, MVA mode, PVA (Patterned Vertical Alignment mode, IPS mode, FFS mode, or TBA (Tran You can also use the symmetric bend alignment mode. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

[0260] Also, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal element may be configured by the liquid crystal that exhibits the blue phase. Since it is short and optically isotropic, alignment treatment is not required and viewing angle dependency is small.

[0261] In the configuration of the pixel 100 shown in FIG. One of the drain electrodes is electrically connected to the signal line 109, and the other is connected to a pair of the liquid crystal element 121. The gate electrode of the transistor 103 is electrically connected to the other of the scan lines 101 and 102. 07. The transistor 103 is turned on or off. This has the function of controlling the writing of data of the data signal.

[0262] In the configuration of the pixel 100 shown in FIG. 9B, one of a pair of electrodes of the capacitor 105 is The other end is electrically connected to a pair of electrodes of the liquid crystal element 121. The potential value of the capacitance line 115 depends on the specifications of the pixel 100. The capacitance element 105 serves as a storage capacitor for storing written data. It has all the functions.

[0263] For example, in a display device having the pixel 100 shown in FIG. 9B, the scanning line driving circuit 104 The pixels 100 in each row are selected in sequence, and the transistors 103 are turned on to output the data signal. Write the data.

[0264] The pixel 100 to which the data has been written is retained by turning off the transistor 103. By performing this process row by row, an image can be displayed.

[0265] In addition, the pixel 100 shown in FIG. 9C includes a transistor 1 for switching a display element. 33, a transistor 103 for controlling driving of the pixel, a transistor 135, and a capacitance element 105 and a light-emitting element 131.

[0266] A data signal is applied to one of the source electrode and the drain electrode of the transistor 133. The gate electrode of the transistor 103 is electrically connected to the signal line 109. The pixel is electrically connected to a scanning line 107 to which a scanning signal is applied.

[0267] The transistor 133 is turned on or off to transmit the data of the data signal. It has the function of controlling the writing of data.

[0268] One of the source electrode and the drain electrode of the transistor 103 functions as an anode line. The source electrode and the drain electrode of the transistor 103 are electrically connected to the wiring 137. The other end is electrically connected to one electrode of the light-emitting element 131. The gate electrode of the transistor 133 is connected to the other of the source electrode and drain electrode of the transistor 133, and the capacitance It is electrically connected to one electrode of the element 105 .

[0269] The transistor 103 is turned on or off to cause the light emitting element 131 to emit light. It has the function of controlling the flow of current.

[0270] One of the source and drain electrodes of the transistor 135 is provided with a data reference potential. The other of the source electrode and the drain electrode of the transistor 135 is connected to a wiring 139. , which is electrically connected to one electrode of the light-emitting element 131 and the other electrode of the capacitor 105. Furthermore, the gate electrode of the transistor 135 is connected to the scanning line 107 to which a gate signal is applied. are electrically connected.

[0271] The transistor 135 has a function of adjusting a current flowing through the light-emitting element 131. For example, When the internal resistance of the light emitting element 131 increases due to deterioration or the like of the light emitting element 131, the transistor The current flowing through the wiring 139 to which one of the source electrode and the drain electrode of the transistor 135 is connected is By monitoring, the current flowing through the light emitting element 131 can be corrected. The potential applied to 39 can be, for example, 0V.

[0272] One of a pair of electrodes of the capacitor 105 is a source electrode and a drain electrode of the transistor 103. The other electrode is electrically connected to the gate electrode of the transistor 133. The other of the pair of electrodes is the other of the source electrode and the drain electrode of the transistor 135, It is electrically connected to one electrode of the light emitting element 131 .

[0273] In the configuration of the pixel 100 shown in FIG. 9C, the capacitor element 105 It has a function as a storage capacitor for storing the

[0274] One of the pair of electrodes of the light emitting element 131 is a source electrode and a drain electrode of the transistor 135. the other electrode of the capacitor 105, and the source and drain electrodes of the transistor 103. The other of the pair of electrodes of the light emitting element 131 is electrically connected to the other of the pair of electrodes. It is electrically connected to a wiring 141 which functions as a cathode.

[0275] The light-emitting element 131 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light emitting element 131 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0276] A high power supply potential VDD is applied to one of the wiring 137 and the wiring 141, and a In the configuration shown in FIG. 9C, a high voltage is applied to the wiring 137. A power supply potential VDD is applied to the line 141, and a low power supply potential VSS is applied to the line 142.

[0277] In a display device having the pixel 100 shown in FIG. 9C, the image of each row is generated by a scanning line driving circuit 104. The elements 100 are selected in sequence, and the transistors 102 are turned on to write data of the data signal. Enter.

[0278] The pixel 100 to which the data has been written is retained by turning off the transistor 103. Furthermore, since the transistor 103 is connected to the capacitor 105, The data stored in the memory can be held for a long time. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 131 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0279] Next, a specific example of a liquid crystal display device using a liquid crystal element for the pixel 100 will be described. Here, a top view of the pixel 100 shown in FIG. 9(B) is shown in FIG. 10. The counter electrode and the liquid crystal element are omitted.

[0280] In FIG. 10, the conductive film 304c functioning as the scanning line is oriented in a direction substantially perpendicular to the signal line ( The conductive film 310d that functions as a signal line is provided so as to extend in a direction perpendicular to the plane of the drawing. The capacitor line extends in a direction substantially perpendicular to the scan line (vertical direction in the figure). The conductive film 310f extends in a direction parallel to the signal lines. The functioning conductive film 304c is electrically connected to the scanning line driver circuit 104 (see FIG. 9A). The conductive film 310d functions as a signal line and the conductive film 310f functions as a capacitance line. 10f is electrically connected to the signal line driver circuit 106 (see FIG. 9(A)).

[0281] The transistor 103 is provided in a region where the scanning line and the signal line intersect. The gate electrode 304c functions as a conductive film, and the gate insulating film 304b functions as a gate electrode. The oxide semiconductor film 308 in which the channel region is formed is formed on the gate insulating film. b, conductive films 310d and 310e functioning as source and drain electrodes, and an oxide semiconductor A protective film (not shown in FIG. 10) formed on the body film 308b and functioning as a gate electrode. The conductive film 304c also functions as a scanning line. A region overlapping with the oxide semiconductor film 308b functions as a gate electrode of the transistor 102. The conductive film 310d also functions as a signal line and overlaps with the oxide semiconductor film 308b. The region where the gate electrode is provided functions as a source electrode or a drain electrode of the transistor 102. In FIG. 10, the end of the scan line is closer to the end of the oxide semiconductor film 308b in the top view. Therefore, the scanning lines act as a light shielding film that blocks light from a light source such as a backlight. As a result, the oxide semiconductor film 308b included in the transistor is irradiated with light. In addition, the change in the electrical characteristics of the transistor can be suppressed. The conductive film 304c functioning as a gate electrode and the conductive film 316c functioning as a gate electrode are formed through an opening 364c. Connect at.

[0282] In addition, the conductive film 310e has a light-transmitting property that functions as a pixel electrode in the opening 364c. The conductive film 316b is electrically connected to the conductive film 316b.

[0283] The capacitor 105 is connected to a conductive film 310f that functions as a capacitor line in the opening 362. The capacitance element 105 is formed by a conductive film 3 formed on the gate insulating film. 08c, a dielectric film formed of a nitride insulating film provided on the transistor 103, and and a light-transmitting conductive film 316c that functions as a base electrode. Since the insulating film 308c has a light-transmitting property, the capacitor 105 has a light-transmitting property.

[0284] In this way, since the capacitor 105 has a light-transmitting property, the capacitor 105 is large in the pixel 100. Therefore, the aperture ratio can be increased, typically by 50%. 55% or more, or 60% or more, and the charge capacity is increased. For example, a semiconductor device having a high resolution, such as a liquid crystal display, can be obtained. In the device, the area of ​​the pixel is reduced, and the area of ​​the capacitance element is also reduced. In a semiconductor device with high image quality, the charge capacity stored in the capacitance element is small. However, since the capacitor 105 shown in this embodiment has a light-transmitting property, the capacitor By providing the second insulating film, it is possible to increase the aperture ratio while obtaining a sufficient charge capacity in each pixel. Typically, pixel densities are 200ppi or more, 300ppi or more, or even 500ppi or more. The present invention can be suitably used for semiconductor devices with high resolution of pi or more.

[0285] 10, the pixel 100 has a side parallel to the conductive film 310d that functions as a signal line. In comparison, the side parallel to the conductive film 304c functioning as the scanning line is longer, and The conductive film 310f functioning as a quantity line is parallel to the conductive film 310d functioning as a signal line. As a result, the area of ​​the conductive film 310f in the pixel 100 is reduced. It is possible to reduce the number of layers, which increases the aperture ratio. Since the conductive film 310f is in direct contact with the conductive film 308c without using a connection electrode, The aperture ratio can be further increased.

[0286] In addition, according to one embodiment of the present invention, the aperture ratio can be increased even in a high-resolution display device. This allows the light from light sources such as backlights to be used efficiently, and reduces the power consumption of the display device. The force can be reduced.

[0287] Next, a cross-sectional view taken along the dashed line CD in FIG. 10 is shown in FIG. In the embodiment, a driving circuit section including a scanning line driving circuit 104 and a signal line driving circuit 106 (top view omitted) A cross-sectional view of the liquid crystal display device according to the present embodiment is shown in FIG. This article explains:

[0288] The display device shown in this embodiment has a liquid crystal element between a pair of substrates (a substrate 302 and a substrate 342). 322 is clamped.

[0289] The liquid crystal element 322 is connected to a light-transmitting conductive film 316b above the substrate 302 to control the alignment. A liquid crystal layer 320 and a conductive film 350 are arranged in a liquid crystal display device. Note that the light-transmitting conductive film 316b is used as one electrode of the liquid crystal element 322. The conductive film 350 functions as the other electrode of the liquid crystal element 322 .

[0290] Thus, a liquid crystal display device is a device that has liquid crystal elements. The liquid crystal display device includes a driving circuit for driving a plurality of pixels. A control circuit, a power supply circuit, a signal generating circuit, a backlight module, etc., are arranged in It is also called a liquid crystal module.

[0291] In the driver circuit portion, a conductive film 304a functions as a gate electrode, and a gate insulating film The insulating film 305 and the insulating film 306 functioning as a channel region are formed in the oxide semiconductor film 30. 8a, the conductive films 310a and 310b functioning as a source electrode and a drain electrode The oxide semiconductor film 308a constitutes the transistor 102. The oxide semiconductor film 308a is provided over the gate insulating film.

[0292] In the pixel portion, a conductive film 304c functions as a gate electrode, and a gate insulating film The insulating film 305 and the insulating film 306 are formed on the gate insulating film. a conductive film 310 serving as a source electrode and a drain electrode; d, 310e, an insulating film 312, an insulating film 314, and a conductive film 31 functioning as a gate electrode. The oxide semiconductor film 308b is formed on the gate insulating film 6c. In addition, insulating films 312 and 314 are provided on the conductive films 310d and 310e. It is provided as a protective film.

[0293] In addition, a light-transmitting conductive film 316b functioning as a pixel electrode is formed between the insulating film 312 and the insulating film 316b. The insulating film 314 is connected to the conductive film 310e through an opening provided therein.

[0294] Also, a conductive film 308c functioning as one electrode and a dielectric film The insulating film 314 and the light-transmitting conductive film 316b functioning as the other electrode form a capacitor. 105. The conductive film 308c is provided on the gate insulating film.

[0295] In the driving circuit section, the conductive film 304a and the conductive film 304c are formed at the same time. 4b and the conductive film 31 The light-transmitting conductive film 310c is formed at the same time as the light-transmitting conductive film 316b. Connected via 6a.

[0296] The conductive film 304b and the light-transmitting conductive film 316a are The conductive film 310c and the light-transmitting conductive film 310b are connected to each other through an opening provided in the conductive film 310c. The insulating film 312 and the insulating film 314 are connected to each other through an opening provided therein.

[0297] Here, the components of the display device shown in FIG. 11 will be described below.

[0298] Conductive films 304a, 304b, and 304c are formed on the substrate 302. The conductive film 04a functions as a gate electrode of a transistor in the driver circuit portion. 304c is formed in the pixel portion 101 and functions as a gate electrode of a transistor in the pixel portion. The conductive film 304b is formed in the scanning line driver circuit 104 and is connected to the conductive film 310c. do.

[0299] For the substrate 302, the material of the substrate 11 shown in Embodiment 1 can be used as appropriate.

[0300] The conductive films 304a, 304b, and 304c may be the same as those of the gate electrode 15 shown in the first embodiment. Materials and manufacturing methods can be used as appropriate.

[0301] An insulating film 305, an insulating film 306, and an insulating film 307 are formed on the substrate 302 and the conductive films 304a, 304c, and 304b. The insulating film 305 and the insulating film 306 are formed on the transistor of the driving circuit section. The insulating film functions as a gate insulating film and a gate insulating film of a transistor in the pixel portion 101 .

[0302] The insulating film 305 is the nitride insulating film described in the gate insulating film 17 in the first embodiment. The insulating film 306 is preferably formed using the gate insulating film shown in Embodiment 1. It is preferable to form the insulating film by using the oxide insulating film described above with respect to the insulating film 17 .

[0303] Over the insulating film 306, oxide semiconductor films 308a and 308b and a conductive film 308c are provided. The oxide semiconductor film 308a is formed so as to overlap with the conductive film 304a. The oxide semiconductor film 3 functions as a channel region of the transistor in the driver circuit portion. The conductive film 308b is formed in a position overlapping with the conductive film 304c, and is a channel of a transistor in a pixel portion. The conductive film 308c functions as one electrode of the capacitor 105. It works.

[0304] The oxide semiconductor films 308a and 308b and the conductive film 308c are the same as those described in Embodiment 1. The material and the formation method of the oxide semiconductor film 18 described above can be used as appropriate.

[0305] The conductive film 308c is an oxide semiconductor film, similar to the oxide semiconductor films 308a and 308b. The film is a conductive film and contains impurities. The impurities include hydrogen. In addition, boron, phosphorus, tin, antimony, and rare gas elements are used as impurities instead of hydrogen. , alkali metals, alkaline earth metals, etc. may be contained.

[0306] The oxide semiconductor films 308a and 308b and the conductive film 308c serve as gate insulators. Specifically, the oxide semiconductor films 308a and 308b are formed on the insulating film, but have different impurity concentrations. The conductive film 308c has a higher impurity concentration than the oxide semiconductor film 308b. The hydrogen concentration in the membranes 308a and 308b is 5×10 19 atoms / cm 3 below, 5×10 18 atoms / cm 3 Below, 1×10 18 atoms / cm 3 Below, 5 x 10 17 atoms / cm 3 or less, or 1×10 16 atoms / cm 3 is less than or equal to the conductive The hydrogen concentration in the film 308c having the hydrogen permeability is 8×10 19 atoms / cm 3 That's it, 1 ×10 20 atoms / cm 3 or more, or 5×10 20 atoms / cm 3 That's all. In addition, compared with the oxide semiconductor films 308a and 308b, the conductive film 308c has a higher conductivity than the oxide semiconductor films 308a and 308b. The hydrogen concentration is doubled or even 10 times higher.

[0307] The conductive film 308c has a higher resistivity than the oxide semiconductor films 308a and 308b. The resistivity of the conductive film 308c is lower than that of the oxide semiconductor films 308a and 308b. Rate of 1 x 10 -8 1×10 times more -1 times or less, typically 1×10 -3 Ωcm or more 1×104 Less than Ωcm or resistivity of 1×10 -3 Ωcm or more 1×1 0 -1 It is preferable that the resistivity is less than Ωcm.

[0308] The oxide semiconductor films 308a and 308b are formed by forming the oxide semiconductor film 308a and the oxide semiconductor film 308b on the insulating film 306 and the insulating film 312. Since it is in contact with a film made of a material that can improve the interface characteristics with the conductor film, it is acid-resistant. The oxide semiconductor films 308a and 308b function as semiconductors. The transistor having 08b has excellent electrical characteristics.

[0309] On the other hand, the conductive film 308c is insulated in the opening 362 (see FIG. 14(A)). The insulating film 314 is in contact with the insulating film 314. The insulating film 314 is resistant to impurities from the outside, such as water, alkali metals, a film formed of a material that prevents an alkaline earth metal or the like from diffusing into the oxide semiconductor film; Further, hydrogen is contained in the insulating film 314. Thus, hydrogen in the insulating film 314 is absorbed in the oxide semiconductor films 308a and 308b. When hydrogen diffuses into an oxide semiconductor film formed at the same time, the hydrogen is converted into oxygen in the oxide semiconductor film. The insulating film 314 is formed by a plasma CVD method or the like. When the oxide semiconductor film is formed by a sputtering method or a plasma deposition method, oxygen vacancies are generated in the oxide semiconductor film due to exposure to plasma. Hydrogen contained in the insulating film 314 enters the oxygen vacancies, and the electrons acting as carriers are As a result, the oxide semiconductor film becomes highly conductive and functions as a conductor. In other words, the oxide semiconductor film 308a has high conductivity. The oxide semiconductor films 308a and 308b are mainly made of the same material and have a low hydrogen concentration. The metal oxide having the increased conductivity due to the higher temperature than b is treated as a conductive film 308c. Call.

[0310] However, one aspect of the embodiment of the present invention is not limited to this, and the conductive film 308c In some cases, it is possible that the insulating film 314 is not in contact with the insulating film 314 .

[0311] In addition, one aspect of the embodiment of the present invention is not limited to this, and the conductive film 308c is In some cases, the oxide semiconductor film 308a or 308b may be formed in a separate process. In that case, the conductive film 308c may be formed by removing the oxide semiconductor films 308a and 308b. For example, the conductive film 308c may be made of ITO. Alternatively, it may be formed using indium zinc oxide or the like.

[0312] The semiconductor device described in this embodiment includes a capacitor and an oxide semiconductor film. In addition, a light-transmitting conductive film that functions as a pixel electrode is formed. The other electrode of the capacitor element is used. Since the step of forming a conductive film is not required, the manufacturing steps of the semiconductor device can be reduced. Since the pair of electrodes is formed of a conductive film having a light-transmitting property, the light-transmitting property is obtained. As a result, the area occupied by the capacitive element can be increased while increasing the aperture ratio of the pixel.

[0313] The conductive films 310a, 310b, 310c, 310d, and 310e are the same as those shown in the first embodiment. The material and manufacturing method for the pair of electrodes 21 and 22 can be appropriately used.

[0314] The insulating film 306, the oxide semiconductor films 308a and 308b, the conductive film 308c, and An insulating film 312 and an insulating The insulating film 312 is an oxide semiconductor film, like the insulating film 306. It is preferable to use a material capable of improving the interface characteristics of the The oxide insulating film 24 can be formed by using a material and a method similar to those of the oxide insulating film 24 in Embodiment 1 as appropriate. As shown in Embodiment 1, the oxide insulating film 23 and the oxide insulating film may be stacked. good.

[0315] The insulating film 314, like the insulating film 305, is resistant to external impurities such as water and alkaline metals. It is preferable to use a material that prevents metals, alkaline earth metals, and the like from diffusing into the oxide semiconductor film. The material and the formation method of the nitride insulating film 25 shown in Embodiment 1 can be used as appropriate. do.

[0316] In addition, light-transmitting conductive films 316a and 316b and a gate electrode are formed over the insulating film 314. The conductive film 316a having a light-transmitting property is formed as an opening. The opening 364a (see FIG. 14C) is electrically connected to the conductive film 304b. The conductive film 310c is electrically connected to the portion 364b (see FIG. 14(C)). The conductive film 304b and the conductive film 310c function as a connection electrode. The conductive film 316b is in contact with the conductive film 310e in the opening 364c (see FIG. 14C). The conductive film is electrically connected to the pixel electrode and functions as a pixel electrode of the pixel. The conductive film 316b can function as one of a pair of electrodes of a capacitor. is electrically connected to the conductive film 304c in the opening 364c (see FIG. 10).

[0317] In order to form a connection structure in which the conductive film 304b and the conductive film 310c are in direct contact with each other, the conductive film 3 Before forming 10c, a patterning process is performed to form openings in the insulating film 305 and the insulating film 306. It is necessary to perform photolithography and form a mask, but the connection structure of FIG. However, as shown in FIG. 11, the conductive film 316b having a light-transmitting property is used. The conductive film 304b and the conductive film 310c are connected to each other. This eliminates the need to create a connection part where c is in direct contact, and reduces the number of photomasks by one. That is, the number of manufacturing steps of the semiconductor device can be reduced.

[0318] The light-transmitting conductive films 316a, 316b, and 316c are formed of tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc Conductive materials with light transmission such as lead oxide and indium tin oxide with added silicon oxide are used. It can be used.

[0319] In addition, a film having color (hereinafter, referred to as a color film 346) is formed on the substrate 342. The colored film 346 functions as a color filter. A light-shielding film 344 is formed on the substrate 342 and is adjacent to the light-shielding film 344. The colored film 346 does not necessarily have to be provided. For example, In some cases, such as when the device is black and white, the color film 346 may not be provided.

[0320] The colored film 346 may be any colored film that transmits light in a specific wavelength range. For example, A red (R) color filter that transmits light in the red wavelength range, and a green (G) color filter that transmits light in the green wavelength range. A green (G) color filter transmits light in the blue wavelength range, and a blue (B) color filter transmits light in the blue wavelength range. A filter or the like can be used.

[0321] The light-shielding film 344 may be made of a metal or other material as long as it has a function of blocking light in a specific wavelength range. Alternatively, an organic insulating film containing a black pigment or the like can be used.

[0322] In addition, an insulating film 348 is formed on the colored film 346. The insulating film 348 is planarized. The function of the colored film 346 is to prevent impurities contained therein from diffusing toward the liquid crystal element. It has the function of controlling

[0323] In addition, a conductive film 350 is formed on the insulating film 348. The conductive film 350 is The liquid crystal element has a function as the other of the pair of electrodes. An insulating film having a function as an alignment film is formed on the films 316a and 316b and the conductive film 350. It may be formed separately.

[0324] In addition, the conductive films 316a, 316b, and 316c each having a light-transmitting property and the conductive film 350 A liquid crystal layer 320 is formed between the two. The liquid crystal layer 320 is also covered with a sealant (not shown). The space between the substrate 302 and the substrate 342 is sealed using a sealing material. In order to prevent the intrusion of moisture or the like, it is preferable that the insulating layer is in contact with an inorganic material.

[0325] In addition, the conductive films 316a, 316b, and 316c each having a light-transmitting property and the conductive film 350 A spacer may be provided between them to maintain the thickness of the liquid crystal layer 320 (also called the cell gap).

[0326] Regarding a method for manufacturing an element portion provided on a substrate 302 shown in the semiconductor device shown in FIG. This will be explained with reference to FIG. 12 to FIG.

[0327] First, prepare a substrate 302. Here, a glass substrate is used as the substrate 302.

[0328] Next, a conductive film is formed on the substrate 302, and the conductive film is processed into a desired region. The conductive films 304a, 304b, and 304c are formed. The formation of c is performed by forming a mask by a first patterning in a desired region, and then covering the mask. It can be formed by etching the uncut areas (see FIG. 12(A)). .

[0329] The conductive films 304a, 304b, and 304c are typically formed by deposition or CVD. The insulating film can be formed by a method such as sputtering or spin coating.

[0330] Next, an insulating film 305 is formed on the substrate 302 and the conductive films 304a, 304b, and 304c. Then, an insulating film 306 is formed over the insulating film 305 (see FIG. 12A).

[0331] The insulating film 305 and the insulating film 306 are formed by a sputtering method, a CVD method, or the like. When the insulating film 305 and the insulating film 306 are successively formed in a vacuum, impurities are easily removed. This is preferable because it suppresses the inclusion of

[0332] Next, an oxide semiconductor film 307 is formed over the insulating film 306 (see FIG. 12B).

[0333] The oxide semiconductor film 307 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser deposition method, or the like. The thin film can be formed by using a method such as ablation.

[0334] Next, the oxide semiconductor film 307 is processed into a desired region to form an island-shaped oxide semiconductor film 3 The oxide semiconductor films 308a, 308b, and 308d are formed. The formation of 08d involves forming a mask by second patterning in a desired area, and then forming the mask The etching can be performed by etching the area not covered by the The etching process can be dry, wet, or a combination of both. (See FIG. 12(C)).

[0335] Next, a conductive film 3 is formed over the insulating film 306 and the oxide semiconductor films 308a, 308b, and 308d. 09 (see Figure 13(A)).

[0336] The conductive film 309 can be formed by, for example, a sputtering method.

[0337] Next, the conductive film 309 is processed into a desired region to form conductive films 310a, 310b, and 311. In addition, the conductive films 310a, 310b, 310c, 310d, and 310e are formed. The formation of 10d and 310e involves forming a mask by third patterning in a desired area. The regions not covered by the mask can be etched to form the etched region (FIG. 1). 3(B)).

[0338] Next, the insulating film 306, the oxide semiconductor films 308a, 308b, and 308d, and the conductive film 31 An insulating film 311 is formed so as to cover the layers 310a, 310b, 310c, 310d, and 310e. (See FIG. 13(C)).

[0339] The insulating film 311 can be formed by the same method as the oxide insulating film 23 and the oxide insulating film 24 described in Embodiment 1. The oxide layer can be formed by stacking under the same conditions. The insulating film 23 is formed while being heated, so that the oxide semiconductor films 308a, 308b, and 308 d) can be used to form a highly purified oxide semiconductor film by removing hydrogen, water, and the like contained in the oxide semiconductor film. can.

[0340] Next, the insulating film 311 is processed into a desired region to form an insulating film 312 and an opening 362. The insulating film 311 and the opening 362 are formed in a desired region by forming a fourth pattern. A mask is formed by etching, and the area not covered by the mask is etched. (See FIG. 14(A)).

[0341] Note that the opening 362 is formed so that the surface of the oxide semiconductor film 308d is exposed. The opening 362 can be formed by, for example, dry etching. However, the method for forming the opening 362 is not limited to this, and may be a wet etching method or the like. Alternatively, a combination of dry etching and wet etching may be used.

[0342] Thereafter, in the same manner as in the first embodiment, a heat treatment is performed to remove oxygen contained in the insulating film 311. Part of the oxygen is transferred to the oxide semiconductor films 308a and 308b. The amount of oxygen vacancies contained in 308b can be reduced.

[0343] Next, the insulating film 313 is formed over the insulating film 312 and the oxide semiconductor film 308d (FIG. 14 (See (B)).

[0344] The insulating film 313 is made of a material that is free of impurities from the outside, such as oxygen, hydrogen, water, alkali metals, It is preferable to use a material that prevents an alkaline earth metal or the like from diffusing into the oxide semiconductor film. , and preferably contains hydrogen, typically an inorganic insulating material containing nitrogen, such as a nitride The insulating film 313 may be formed by using, for example, a CVD method. It is possible.

[0345] The insulating film 314 is resistant to external impurities such as water, alkali metals, alkaline earth metals, etc. The film is formed of a material that prevents diffusion of hydrogen into the oxide semiconductor film and further contains hydrogen. Therefore, when hydrogen in the insulating film 314 diffuses into the oxide semiconductor film 308d, the oxide semiconductor In the film 308d, hydrogen combines with oxygen to generate electrons, which are carriers. The oxide semiconductor film 308d becomes highly conductive and becomes a conductive film 308c.

[0346] In addition, the silicon nitride film is preferably formed at a high temperature in order to enhance blocking properties. Preferably, the substrate temperature is, for example, 100° C. or higher and 400° C. or lower, or 300° C. or higher and 400° C. or lower. In addition, when the oxide semiconductor film 3 is formed at a high temperature, Oxygen is released from the oxide semiconductor used as 08a and 308b, and the carrier concentration increases. Since this phenomenon may occur, the temperature should be set at a level at which this phenomenon does not occur.

[0347] Next, the insulating film 313 is processed into a desired region to form an insulating film 314 and an opening 364. a, 364b, 364c, and 364d (see FIG. 10). , and openings 364a, 364b, and 364c are formed in desired areas by the fifth patterning. A mask is formed, and the area not covered by the mask is etched to form the (See FIG. 14(C)).

[0348] The opening 364a is formed so that the surface of the conductive film 304b is exposed. The opening 364b is formed so as to expose the conductive film 310c. The opening 364d is formed so that the conductive film 310e is exposed. Form it so that it is exposed.

[0349] The openings 364a, 364b, 364c, and 364d can be formed, for example, by A dry etching method can be used. However, the openings 364a, 364b, and 364 The method for forming 364c and 364d is not limited to this, and may be a wet etching method or a dry etching method. A combination of dry etching and wet etching may also be used.

[0350] Next, a layer is deposited on the insulating film 314 so as to cover the openings 364a, 364b, 364c, and 364d. A conductive film 315 is formed (see FIG. 15A).

[0351] The conductive film 315 can be formed by, for example, a sputtering method.

[0352] Next, the conductive film 315 is processed into a desired region to form a light-transmitting conductive film 316a, The conductive films 316a and 316b and the conductive film 316c are formed. The conductive film 316c is formed by forming a mask by a sixth patterning in a desired region. The regions not covered by the mask can be etched away (FIG. 15). (See (B)).

[0353] Through the above steps, a pixel portion having a transistor and a driver circuit portion are formed on the substrate 302. In the manufacturing process shown in this embodiment, the first to sixth patterned This means that transistors and capacitors can be formed simultaneously using six masks. do.

[0354] Note that in this embodiment, hydrogen contained in the insulating film 314 is diffused into the oxide semiconductor film 308d. The oxide semiconductor film 308d was dispersed to increase the conductivity. The oxide semiconductor film 308d is covered with a mask, and impurities, typically hydrogen, boron, or lithium, are introduced into the oxide semiconductor film 308d. Addition of tin, antimony, rare gas elements, alkali metals, alkaline earth metals, etc. The oxide semiconductor film 308d may be doped with hydrogen or boron to increase the conductivity. The method of adding elements such as phosphorus, tin, antimony, and rare gas elements is ion doping. On the other hand, when an alkali metal or an alkaline earth metal is added to the oxide semiconductor film 308d, As a method for adding a metal or the like, a method of exposing a solution containing the impurity to the oxide semiconductor film 308d is used. There is a law.

[0355] Next, the structure formed on the substrate 342 provided opposite the substrate 302 will be described below. Provide an explanation.

[0356] First, a substrate 342 is prepared. The substrate 342 is made of the same material as that of the substrate 302. Next, a light-shielding film 344 and a colored film 346 are formed on the substrate 342 (FIG. 16( See A).

[0357] The light-shielding film 344 and the colored film 346 are formed of various materials by a printing method, an ink-jet method, They are formed at desired positions by an etching method using photolithography technology.

[0358] Next, an insulating film 348 is formed on the light-shielding film 344 and the colored film 346 (see FIG. 16(B)). see).

[0359] The insulating film 348 is made of an organic insulating material such as an acrylic resin, an epoxy resin, or a polyimide. By forming the insulating film 348, for example, the colored film 34 It is possible to prevent impurities contained in the liquid crystal layer 6 from diffusing to the liquid crystal layer 320 side. However, the insulating film 348 is not necessarily required, and a structure in which the insulating film 348 is not formed may be used. Good too.

[0360] Next, a conductive film 350 is formed over the insulating film 348 (see FIG. 16C). As the conductive film 315, the materials shown in the conductive film 315 can be used.

[0361] Through the above steps, the structure formed on the substrate 342 can be formed.

[0362] Next, the insulating film 31 formed on the substrate 302 and the substrate 342, more specifically, on the substrate 302, 4. The conductive films 316a and 316b having light transmitting properties and the conductive film 35 formed on the substrate 342 0, an alignment film 318 and an alignment film 352 are formed on the alignment film 318 and the alignment film 352. The film can be formed by using a rubbing method, a photo-alignment method, or the like. A liquid crystal layer 320 is formed between the substrate 342 and the liquid crystal layer 320. or by bonding the substrate 302 and the substrate 342 together and then using the capillary phenomenon. An injection method for injecting liquid crystal can be used.

[0363] Through the above steps, the display device shown in FIG. 11 can be manufactured.

[0364] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0365] <Variation 1> A modified example of a liquid crystal display device using a liquid crystal element in the pixel 100 will be described. In the liquid crystal display device, the conductive film 308c is in contact with the insulating film 314. In this case, the opening 362 as shown in FIG. Since there is no need to provide a step, the steps on the surfaces of the light-transmitting conductive films 316a and 316b can be reduced. This makes it possible to reduce the alignment disorder of the liquid crystal material contained in the liquid crystal layer 320. In addition, a semiconductor device with high contrast can be manufactured.

[0366] In such a structure, in FIG. 12B, before the oxide semiconductor film 307 is formed, The insulating film 306 may be selectively etched to expose a portion of the insulating film 305 .

[0367] <Variation 2> In this embodiment mode and its modification, the insulating film 314, the light-transmitting conductive films 316a and 316b are b, or between the conductive film 316c and the alignment film 318, an acrylic resin, an epoxy resin, a polyimide resin, An organic insulating film such as an acrylic resin has high flatness. Therefore, the step on the surface of the light-transmitting conductive film 316b can be reduced. Therefore, it is possible to reduce the alignment disorder of the liquid crystal material contained in the liquid crystal layer 320. Therefore, a semiconductor device with high contrast can be manufactured.

[0368] (Embodiment 5) In this embodiment, a transistor included in the semiconductor device described in the above embodiment is In this section, one embodiment applicable to an oxide semiconductor film will be described.

[0369] The oxide semiconductor film is an oxide semiconductor having a single crystal structure (hereinafter referred to as a single crystal oxide semiconductor). , a polycrystalline oxide semiconductor (hereinafter referred to as a polycrystalline oxide semiconductor), oxide semiconductors having an amorphous structure (hereinafter referred to as microcrystalline oxide semiconductors) and amorphous oxide semiconductors having an amorphous structure (hereinafter referred to as The oxide semiconductor film may be formed of one or more of the following: Alternatively, the oxide semiconductor film may be an amorphous oxide semiconductor film. The oxide semiconductor may be a single crystal oxide semiconductor having a conductor and crystal grains. Conductor, CAAC-OS, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and amorphous oxide semiconductor The conductor will now be described.

[0370] <Single crystal oxide semiconductor> A single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states (few oxygen vacancies). ) an oxide semiconductor film. Therefore, the carrier density can be reduced. A transistor using a crystalline oxide semiconductor film rarely has normally-on electrical characteristics. In addition, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, Therefore, in the case of a transistor using a single crystal oxide semiconductor film, the number of carrier traps may be reduced. The transistor has small fluctuations in electrical characteristics and is highly reliable.

[0371] Note that the oxide semiconductor film has a high density when the number of defects is small. High crystallinity increases density. In addition, the oxide semiconductor film has a low concentration of impurities such as hydrogen. The density of the single crystal oxide semiconductor film is higher than that of the CAAC-OS film. The CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. The conductor film has a higher density than the microcrystalline oxide semiconductor film. The density is higher than that of an crystalline oxide semiconductor film.

[0372] <caac-os> The CAAC-OS film is one of the oxide semiconductor films having multiple crystal parts. The crystals in the AC-OS film have a c-axis orientation. The area of ​​the crystals in the C-OS film is 2500 nm 2 More than 5μm 2 Greater than or equal to 100 0μm 2 In addition, in a cross-sectional TEM image, the crystal portion is 50% or more, 80% or more , or 95% or more, the resulting thin film has physical properties close to those of a single crystal.

[0373] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed using a quartz-crystal microscope, clear boundaries between the crystals, i.e., the crystal boundaries, were clearly visible. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0374] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When the metal atoms are observed, it can be confirmed that they are arranged in layers in the crystal part. Each layer of the CAAC-OS film is formed on a surface on which the film is to be formed (also called a surface on which the film is to be formed) or on a concave surface on the upper surface. The shape reflects the convexity and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface. In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. " refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This also includes cases where the angle is between 85° and 95°.

[0375] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0376] When electron beam diffraction was performed on the CAAC-OS film, spots (bright spots) indicating orientation were observed. is observed.

[0377] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that...

[0378] X-ray diffraction (XRD) of CAAC-OS film The structure of the CAAC-OS film was analyzed using the out-of-plane method. In the analysis, a peak may appear at a diffraction angle (2θ) of around 31°. This peak is I Since it is assigned to the (00x) plane (x is an integer) of the nGaZn oxide crystal, The crystals of the OS film have a c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the surface on which the film is formed or the upper surface. It can be confirmed that there is.

[0379] On the other hand, in-p X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the lane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZn oxide crystal. In the case of a crystalline oxide semiconductor film, 2θ is fixed at about 56°, and the normal vector of the sample surface is aligned along the axis (φ When the sample is rotated around the (φ) axis while analyzing (φ scan), the results show that the bonds are equivalent to the (110) plane. In contrast, in the case of the CAAC-OS film, 2 Even when θ is fixed at around 56° and φ is scanned, no clear peak appears.

[0380] From the above, it is considered that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is in a plane parallel to the ab plane of the crystal.

[0381] The crystals are formed when the CAAC-OS film is formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0382] In addition, the crystallinity in the CAAC-OS film does not have to be uniform. When the crystalline part of the film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, The area near the surface may have a higher crystallinity than the area near the surface on which it is formed. When impurities are added to the AC-OS film, the crystallinity of the region to which the impurities are added changes, resulting in a partial In some cases, regions of differing crystallinity may be formed.

[0383] In addition, in the out-of-plane analysis of the CAAC-OS film, 2θ was 31°. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis are due to the presence of crystals that do not have the c-axis orientation in the CAAC-OS film. The CAAC-OS film shows a peak at 2θ of about 31° and a peak at 2θ of about 36°. It is preferable that there is no peak nearby.

[0384] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is preferably made of silicon or a transition metal element other than the main component of the oxide semiconductor film. An element such as ZnO that has a stronger bond to oxygen than a metal element that constitutes an oxide semiconductor film is an oxide. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Since the diameter (or molecular radius) of the ions is large, when the ions are contained inside the oxide semiconductor film, the oxide semiconductor film The impurities contained in the oxide semiconductor film are disturbed, which causes a decrease in crystallinity. Pure materials may act as carrier traps or carrier generation sources.

[0385] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0386] The low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small carrier generation source, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics (noise) in which the threshold voltage is negative. It is also called "marine". It is rare for it to become "high purity genuine" or "substantially high purity". The intrinsic oxide semiconductor film has few carrier traps. Transistors using the film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it were a fixed charge. In addition, a transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. There may be cases where this occurs.

[0387] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. Gender variation is small.

[0388] <Polycrystalline oxide semiconductor> In the polycrystalline oxide semiconductor film, crystal grains can be confirmed in the TEM image. The crystal grains contained in the crystalline oxide semiconductor film are, for example, 2 nm to 3 nm in a TEM image. 00 nm or less, 3 nm to 100 nm or 5 nm to 50 nm. In addition, in the case of a polycrystalline oxide semiconductor film, crystal grain boundaries cannot be confirmed in the TEM images. There may be cases where this occurs.

[0389] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation between the plurality of crystal grains is In addition, the polycrystalline oxide semiconductor film may be measured by using, for example, an XRD device. When performing out-of-plane analysis, single or multiple peaks may appear. For example, in the case of a polycrystalline IGZO film, the 2θ value indicating the orientation peaks at around 31°, and In some cases, multiple peaks may appear, indicating multiple types of orientation.

[0390] A polycrystalline oxide semiconductor film has high crystallinity and therefore may have high electron mobility. Therefore, a transistor using a polycrystalline oxide semiconductor film has high field-effect mobility. However, in the polycrystalline oxide semiconductor film, impurities may be segregated at grain boundaries. The grain boundaries of a polycrystalline oxide semiconductor film become defect states. Since a generation source or a trap state may occur, Compared with transistors using CAAC-OS films, the fluctuation in electrical characteristics is large and the reliability is low. In some cases, the transistor may have a low resistance.

[0391] <Microcrystalline oxide semiconductor> In the TEM image of the microcrystalline oxide semiconductor film, crystal parts can be clearly seen. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 to 3 nm or less. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called a T In EM images, grain boundaries may not be clearly visible.

[0392] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the out-of-plane method, the crystal planes are In addition, the peaks indicating the diameters larger than those of the crystals in the nc-OS film (e.g. When electron beam diffraction (also called selected area electron beam diffraction) is performed using an electron beam with a diameter of 50 nm or more, On the other hand, for the nc-OS film, the diffraction pattern is crystalline. The electron beam diameter is close to the size of the crystal part or smaller than the crystal part (for example, 1 nm to 30 nm). When electron diffraction (also called nanobeam electron diffraction) is performed, spots are observed. In addition, when nanobeam electron diffraction was performed on the nc-OS film, a circular (ring-shaped) ) Bright areas may be observed. When diffraction occurs, multiple spots may be observed within the ring-shaped area.

[0393] Figure 17 shows the nanobeam electron diffraction patterns of the sample with the nc-OS film at different measurement points. In this example, the sample was cut in a direction perpendicular to the surface on which the nc-OS film was formed. The slice is cut to a thickness of 10 nm or less. In this example, the electron beam has a diameter of 1 nm. The incident light was incident from a direction perpendicular to the cut surface of the sample. However, when nanobeam electron diffraction is performed, a diffraction pattern showing the crystal planes is obtained, but it is difficult to distinguish the specific direction. It was found that no orientation to the crystal plane was observed.

[0394] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, the crystal orientation is not regular between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0395] Note that the structures and methods described in this embodiment may be different from the structures and methods described in other embodiments. They can be used in appropriate combination.

[0396] (Embodiment 6) The oxide semiconductor film disclosed in the above embodiment can be formed by sputtering. However, it may be formed by other methods, for example, thermal CVD. OCVD(Metal Organic Chemical Vapor Deposit) tion method and ALD (Atomic Layer Deposition) method. is also good.

[0397] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no additional steps are required.

[0398] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing the reactants on the substrate. You may go.

[0399] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating the gas introduction sequence. For example, by switching each switching valve (also called high-speed valve), two or more types of The above source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. An inert gas (such as argon or nitrogen) is introduced simultaneously with or after the raw material gas. The second source gas is introduced. When an inert gas is introduced at the same time, the inert gas is It acts as a carrier gas, and even if an inert gas is introduced at the same time as the second source gas is introduced, In addition, the first source gas is discharged by evacuation instead of introducing an inert gas. After that, a second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first layer. The first layer is deposited on the second layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction sequence until the desired thickness is reached. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film is determined by the gas introduction. The thickness can be precisely adjusted by changing the number of times the sequence is repeated. This is suitable for producing miniature FETs.

[0400] Thermal CVD methods such as MOCVD and ALD have been disclosed in the embodiments described above. It is possible to form various films such as metal films, oxide semiconductor films, and inorganic insulating films. In the case of forming an nGaZnO film, trimethylindium, trimethylgallium, and Dimethyl zinc is used. The chemical formula for trimethyl indium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for lead is Zn(CH3)2. Using triethylgallium (chemical formula Ga(C2H5)3) instead of methylgallium It is also possible to use diethylzinc (chemical formula Zn(C2H5)2) instead of dimethylzinc. It is also possible.

[0401] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. A mixed compound layer such as an O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed. Instead of O3 gas, H2O gas obtained by bubbling with an inert gas such as Ar can be used. However, it is preferable to use O3 gas that does not contain H. In(CH3)3 gas is also used. Alternatively, In(C2H5)3 gas may be used. Ga(C2H5)3 gas may be used. Also, instead of In(CH3)3 gas, In( C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0402] Note that the structures and methods described in this embodiment may be different from the structures and methods described in other embodiments. They can be used in appropriate combination. EXAMPLES

[0403] In this example, the Vg-Id characteristics of a transistor and the measurement results of a gate BT stress test are shown. This article explains:

[0404] In this example, Samples 1 to 3 according to one embodiment of the present invention and Comparative Samples 4 to 6 were prepared. First, a manufacturing process of Sample 1 will be described. 18 for comparative samples 4 to 6, and FIG. 19 for comparative samples 4 to 6. Each will be explained.

[0405] (Sample 1) The sample 1 includes a substrate 511, a gate electrode 515 on the substrate 511, and a gate electrode 515 on the substrate 511. A gate insulating film 517 on the electrode 515 and a gate electrode The oxide semiconductor film 518 provided in a region overlapping with the electrode 515, the gate insulating film 517, and A pair of electrodes 521 and 522 over the oxide semiconductor film 518, a protective film 526 on the electrodes 521 and 522; and a gate electrode and a back gate electrode 527 provided in a region overlapping with the gate electrode 515 (see FIG. 18). .

[0406] Note that the protective film 526 is formed by adding the oxide insulating film 523, the oxide insulating film 524, and the nitride insulating film 525. The back gate electrode 527 was formed in a three-layer laminate structure of 525. As shown in FIG. 5B, the gate electrode 515 is approximately aligned with both ends of the gate electrode 515. As shown in FIG. 18C, the protective electrode 527 is connected to the oxide semiconductor film 51 via a protective film 526. It was formed to cover 8.

[0407] Next, a method for fabricating Sample 1 shown in FIG. 18 will be described below.

[0408] First, a glass substrate is used as a substrate 511, and a gate electrode 515 is formed on the substrate 511. Ta.

[0409] A tungsten film with a thickness of 200 nm is formed as the gate electrode 515 by the sputtering method. A mask is formed on the tungsten film by a photolithography process, and the mask is used to The tungsten film was then partially etched away.

[0410] Next, a gate insulating film 517 was formed on the gate electrode 515 .

[0411] The gate insulating film 517 is a silicon nitride film having a thickness of 400 nm and an oxide film having a thickness of 50 nm. A silicon nitride film was formed by laminating the silicon nitride film.

[0412] The silicon nitride film includes a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer structure of silicon nitride films was used.

[0413] The first silicon nitride film was prepared by using silane at a flow rate of 200 sccm and 2000 sccm The plasma CVD equipment was used with nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as raw material gases. The pressure in the treatment chamber was controlled to 100 Pa, and a high-frequency current of 27.12 MHz was applied. The source was used to supply 2000 W of power and the thickness was 50 nm. For the silicon nitride film, silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, Ammonia gas with a flow rate of 2000 sccm was used as the source gas for the plasma CVD equipment. The pressure in the treatment chamber was controlled to 100 Pa, and a high-frequency power source of 27.12 MHz was used. The third nitride layer was formed to a thickness of 300 nm by supplying a power of 2000 W to the GaN substrate. For the silicon film, silane at a flow rate of 200 sccm and nitrogen at a flow rate of 5000 sccm were used. It is supplied as a raw material gas to the processing chamber of the plasma CVD equipment, and the pressure in the processing chamber is controlled to 100 Pa. The thickness of the plate was 50 mm. The first silicon nitride film, the second silicon nitride film, and The substrate temperature was set to 350° C. when the third silicon nitride film was formed.

[0414] The silicon oxynitride film was prepared by using silane at a flow rate of 20 sccm and a Nitrous oxide was supplied as a raw material gas to the processing chamber of the plasma CVD device, and the pressure in the processing chamber was set at 4 The pressure was controlled at 0 Pa, and 100 W of power was supplied using a 27.12 MHz high-frequency power source. The silicon oxynitride film was formed at a substrate temperature of 350° C. did.

[0415] Next, an oxide semiconductor film 518 overlapping the gate electrode 515 with the gate insulating film 517 interposed therebetween is Formed.

[0416] Here, an oxide semiconductor film having a thickness of 35 nm is formed on the gate insulating film 517 by a sputtering method. was formed.

[0417] The oxide semiconductor film was formed by sputtering a target of In:Ga:Zn=3:1:2 (atomic ratio). The sputtering gas was oxygen at a flow rate of 100 sccm. The pressure in the treatment chamber was controlled to 0.6 Pa, and a 5 kW DC The oxide semiconductor film was formed by supplying electric power. Ta.

[0418] Next, a pair of electrodes 521 and 522 in contact with the oxide semiconductor film 518 were formed.

[0419] Here, a conductive film was formed over the gate insulating film 517 and the oxide semiconductor film 518. A 400 nm thick aluminum film is formed on a 50 nm thick tungsten film as a conductive film. A titanium film having a thickness of 200 nm was then formed on the aluminum film. A mask is formed on the conductive film by a etching process, and a part of the conductive film is etched using the mask. A pair of electrodes 521 and 522 was formed.

[0420] Next, the substrate is moved to a reduced pressure processing chamber, heated to 350° C., and then placed in the processing chamber. A high-frequency power of 150 W was supplied to the upper electrode using a 27.12 MHz high-frequency power source. The oxide semiconductor film 518 was exposed to oxygen plasma generated in a dinitrogen oxide atmosphere.

[0421] Next, a protective film 526 is formed over the oxide semiconductor film 518 and the pair of electrodes 521 and 522. Here, the protective film 526 was formed by using the oxide insulating film 523, the oxide insulating film 524, and the nitride semiconductor layer. A compound insulating film 525 was formed.

[0422] First, after the oxygen plasma treatment, the oxide insulating film 523 is continuously formed without exposure to air. As the oxide insulating film 523, a 50-nm-thick oxynitride film was formed. A silicon film is formed, and a silicon oxynitride film having a thickness of 400 nm is formed as an oxide insulating film 524. Formed.

[0423] The oxide insulating film 523 is formed by using silane at a flow rate of 20 sccm and monoxide at a flow rate of 3000 sccm. Dinitrogen was used as the source gas, the pressure in the processing chamber was 200 Pa, the substrate temperature was 350°C, and the The film was formed by the plasma CVD method in which high frequency power of 1000 Hz was supplied to parallel plate electrodes.

[0424] The oxide insulating film 524 is formed by silane at a flow rate of 160 sccm and monooxygen at a flow rate of 4000 sccm. Nitrous oxide was used as the source gas, the pressure in the processing chamber was 200 Pa, the substrate temperature was 220° C., and The film was formed by the plasma CVD method in which 0 W of high frequency power was supplied to the parallel plate electrodes. As a result, the mixture contains more oxygen than satisfies the stoichiometric composition, and some of the oxygen is removed by heating. A desorbing silicon oxynitride film can be formed.

[0425] Next, heat treatment is performed to remove water, nitrogen, and hydrogen from the oxide insulating film 523 and the oxide insulating film 524. At the same time, part of the oxygen contained in the oxide insulating film 524 is removed from the oxide semiconductor film 5 The sample was then fed to the furnace 18, where it was heat-treated at 350°C for 1 hour in a nitrogen and oxygen atmosphere. Ta.

[0426] Next, a 100-nm-thick nitride insulating film 525 was formed over the oxide insulating film 524. The insulating film 525 is made of silane at a flow rate of 50 sccm, nitrogen at a flow rate of 5000 sccm, and The source gas was ammonia gas at 100 sccm, the pressure in the processing chamber was 100 Pa, and the substrate temperature was The plasma CVD method was performed with a temperature of 350°C and a high-frequency power of 1000 W supplied to parallel plate electrodes. More formed.

[0427] Next, an oxide insulating film (not shown) was formed on the protective film 526. 0 sccm of organosilane gas, ethyl silicate (TEOS: chemical formula Si(OC2H5)4 ) and oxygen at a flow rate of 10,000 sccm were used as the source gas. The pressure in the processing chamber was 175 Pa, and the substrate temperature was The plasma CVD method was used with a temperature of 350°C and a high-frequency power of 3300 W supplied to parallel plate electrodes. It was formed by.

[0428] Next, a back gate electrode 527 was formed on the oxide insulating film on the protective film 526. The back gate electrode 527 is formed by sputtering an indium oxide film having a thickness of 100 nm. A conductive film of an indium-tin oxide compound (ITO-SiO2) was formed. The composition of the target was In2O3:SnO2:SiO2=85:10:5 [wt%]. After that, a heat treatment was performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0429] Through the above steps, Sample 1 of this example was fabricated.

[0430] (Sample 2) The structure of the oxide semiconductor film 518 in Sample 2 is different from that in Sample 1. The oxide semiconductor film 518 has a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film. did.

[0431] First, the first oxide semiconductor film was formed by sputtering a target of In:Ga:Zn=3: The target was 1:2 (atomic ratio), and oxygen was used as the sputtering gas at a flow rate of 100 sccm. into the processing chamber of the sputtering device, and the pressure in the processing chamber is controlled to 0.6 Pa. It was formed by supplying 5kW of DC power.

[0432] Next, a second oxide semiconductor film was formed in vacuum successively over the first oxide semiconductor film. The second oxide semiconductor film was formed by sputtering a target of In:Ga:Zn=1:3:2 ( The target was oxygen at a flow rate of 30 sccm and argon at a flow rate of 270 sccm. The gas is supplied to the processing chamber of the sputtering device as a sputtering gas, and the pressure in the processing chamber is The first oxide semiconductor was formed by controlling the pressure at 0.6 Pa and supplying a direct current of 5 kW. The substrate temperature was set to 170° C. when the oxide semiconductor film and the second oxide semiconductor film were formed.

[0433] The structure of Sample 2 was the same as that of Sample 1 except for the oxide semiconductor film 518. , can be formed by invoking the description of Sample 1.

[0434] (Sample 3) The structure of the oxide semiconductor film 518 in Sample 3 is different from that in Sample 1. Specifically, The oxide semiconductor film 518 is a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film. The structure is a stack of semiconductor films.

[0435] First, the first oxide semiconductor film was formed by sputtering a target of In:Ga:Zn=1: The target was 3:2 (atomic ratio), and oxygen was used at a flow rate of 30 sccm and 270 sccm Argon is supplied as a sputtering gas into a processing chamber of a sputtering device, The internal pressure was controlled at 0.6 Pa, and 5 kW of DC power was supplied to form the tube.

[0436] Next, a second oxide semiconductor film was formed in vacuum successively over the first oxide semiconductor film. The second oxide semiconductor film was formed by sputtering a target of In:Ga:Zn=3:1:2 ( The target was oxygen at a flow rate of 100 sccm and aluminum at a flow rate of 100 sccm. The gas is supplied to the processing chamber of the sputtering device as a sputtering gas, and the pressure in the processing chamber is The pressure was controlled at 0.6 Pa and a direct current of 5 kW was supplied to form the tube.

[0437] Next, a third oxide semiconductor film was successively formed over the second oxide semiconductor film in vacuum. The third oxide semiconductor film was formed by sputtering a target of In:Ga:Zn=1:3:2 ( The target was oxygen at a flow rate of 30 sccm and argon at a flow rate of 270 sccm. The gas is supplied to the processing chamber of the sputtering device as a sputtering gas, and the pressure in the processing chamber is The first oxide semiconductor was formed by controlling the pressure at 0.6 Pa and supplying a direct current of 5 kW. The substrate temperature during the formation of the oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film was set to 17°C. The temperature was set to 0°C.

[0438] The structure of Sample 3 was the same as that of Sample 1 except for the oxide semiconductor film 518. , can be formed by invoking the description of Sample 1.

[0439] (Sample 4) Sample 4 includes a substrate 511, a gate electrode 515 on the substrate 511, and a gate electrode 515 on the substrate 511. A gate insulating film 517 on the electrode 515 and a gate electrode The oxide semiconductor film 518 provided in a region overlapping with the electrode 515, the gate insulating film 517, and A pair of electrodes 521 and 522 over the oxide semiconductor film 518, a protective film 526 on the electrodes 521 and 522; and a gate electrode and a back gate electrode 528 provided in a region overlapping with the gate electrode 515 (see FIG. 19). .

[0440] Note that the protective film 526 is formed by adding the oxide insulating film 523, the oxide insulating film 524, and the nitride insulating film 525. The back gate electrode 528 was formed in a three-layer structure as shown in FIG. As shown in the figure, the insulating film 514 was formed so as to be located inside both ends of the oxide semiconductor film 518. As shown in FIG. 19C, the back gate electrode 528 is formed by an oxide film via a protective film 526. The semiconductor film 518 is formed so as to be located inside the semiconductor film 518. One end of the gate electrode 528 is formed so as to extend beyond the oxide semiconductor film 518. It is being formed.

[0441] Next, a method for manufacturing Sample 4 shown in FIG. 19 will be described below.

[0442] The manufacturing process up to the formation of the protective film 526 was the same as that of the sample 1 described above.

[0443] Next, an oxide insulating film (not shown) was formed on the protective film 526. 0 sccm of organosilane gas, ethyl silicate (TEOS: chemical formula Si(OC2H5)4 ) and oxygen at a flow rate of 10,000 sccm were used as the source gas. The pressure in the processing chamber was 175 Pa, and the substrate temperature was The plasma CVD method was used with a temperature of 350°C and a high-frequency power of 3300 W supplied to parallel plate electrodes. It was formed by.

[0444] Next, a back gate electrode 527 was formed on the oxide insulating film on the protective film 526. The back gate electrode 527 is formed by sputtering an indium oxide film having a thickness of 100 nm. A conductive film of an indium-tin oxide compound (ITO-SiO2) was formed. The composition of the target was In2O3:SnO2:SiO2=85:10:5 [wt%]. After that, a heat treatment was performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0445] Through the above steps, Sample 4 of this example was fabricated.

[0446] (Sample 5) The structure of the oxide semiconductor film 518 in Sample 5 is different from that in Sample 4. The oxide semiconductor film 518 has a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film. did.

[0447] First, the first oxide semiconductor film was formed by sputtering a target of In:Ga:Zn=3: The target was 1:2 (atomic ratio), and oxygen was used at a flow rate of 100 sccm. m of argon was supplied as a sputtering gas into the processing chamber of the sputtering device. The pressure inside the chamber was controlled at 0.6 Pa, and 5 kW of DC power was supplied to form the chamber.

[0448] Next, a second oxide semiconductor film was formed in vacuum successively over the first oxide semiconductor film. The second oxide semiconductor film was formed by sputtering a target of In:Ga:Zn=1:3:2 ( The target was oxygen at a flow rate of 30 sccm and argon at a flow rate of 270 sccm. The gas is supplied to the processing chamber of the sputtering device as a sputtering gas, and the pressure in the processing chamber is The first oxide semiconductor was formed by controlling the pressure at 0.6 Pa and supplying a direct current of 5 kW. The substrate temperature was set to 170° C. when the oxide semiconductor film and the second oxide semiconductor film were formed.

[0449] The structure of Sample 5 was the same as that of Sample 4 except for the oxide semiconductor film 518. , can be formed by invoking the description of Sample 4.

[0450] (Sample 6) The structure of the oxide semiconductor film 518 in Sample 6 is different from that in Sample 4. The oxide semiconductor film 518 is a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film. The structure is a stack of semiconductor films.

[0451] First, the first oxide semiconductor film was formed by sputtering a target of In:Ga:Zn=1: The target was 3:2 (atomic ratio), and oxygen was used at a flow rate of 30 sccm and 270 sccm Argon is supplied as a sputtering gas into a processing chamber of a sputtering device, The internal pressure was controlled at 0.6 Pa, and 5 kW of DC power was supplied to form the tube.

[0452] Next, a second oxide semiconductor film was formed in vacuum successively over the first oxide semiconductor film. The second oxide semiconductor film uses a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2 ( atomic ratio), supplies oxygen with a flow rate of 100 sccm and argon with a flow rate of 100 sccm as sputtering gases into the processing chamber of the sputtering apparatus, controls the pressure in the processing chamber to 0.6 Pa, and forms it by supplying 5 kW of DC power. Next, a third oxide semiconductor film was continuously formed on the second oxide semiconductor film in a vacuum. The third oxide semiconductor film uses a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:2 (

[0453] atomic ratio), supplies oxygen with a flow rate of 30 sccm and argon with a flow rate of 270 sccm as sputtering gases into the processing chamber of the sputtering apparatus, controls the pressure in the processing chamber to 0.6 Pa, and forms it by supplying 5 kW of DC power. The substrate temperature when forming the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film was set to 170 °C. For Sample 6, since the configurations other than the oxide semiconductor film 518 are the same as those of Sample 4, it can be formed by referring to the description of Sample 4. Note that Samples 1 to 6 prepared above are transistors with a channel length (L) of 6 μm and a channel width (W ) of 50 μm. <Vg-Id characteristics> Next, the Vg-Id characteristics were measured as the initial characteristics of the transistors of Samples 1 to 6. Here, the substrate temperature was set to 25 °C, the potential difference between the source and drain (hereinafter referred to as the drain voltage) was set to 1 V and 10 V, and the potential difference between the source and gate electrodes (hereinafter referred to as the gate voltage

[0454] is called).

[0455]

[0456] The current flowing between the source and drain when the voltage is changed from -15V to +20V ( The change in the Id-gate (Vg-Id) characteristic, which is called the drain current, was measured.

[0457] <Gate BT stress test> Next, the gate BT stress test (hereinafter, The GBT test conditions were as follows: the substrate temperature was 60°C, and the measurement In a dark room, a gate voltage of +30V is applied for 1 hour. The GBT test is a type of accelerated test, and it is It is possible to quickly evaluate the change in transistor characteristics (i.e., aging) caused by the use of It is important to check the amount of change in transistor characteristics before and after GBT testing. This is an important indicator for examining sexuality.

[0458] Figures 20 and 21 show the Vg-Id characteristics of the transistors of each sample and the Vg Fig. 20(A) shows the initial characteristics and the characteristics after GBT of Sample 1. Fig. 20(B) shows the initial characteristics and characteristics after GBT for sample 2, and Fig. 20(C) shows the initial characteristics of sample 3. Fig. 21(A) shows the initial characteristics and characteristics after GBT of sample 4. FIG. 21(B) shows the initial characteristics and characteristics after GBT of sample 5, and FIG. 21(C) shows the test The initial characteristics and the characteristics after GBT of sample 6 are shown in FIG.

[0459] In each of the graphs shown in FIG. 20 and FIG. 21, the horizontal axis represents the gate voltage Vg, and the first vertical axis represents the The first vertical axis represents the drain current Id, and the second vertical axis represents the field effect mobility μFE.

[0460] The horizontal axis is shown from -15 V to 20 V. The solid line indicates the drain voltage Vd of 1 The Vg-Id characteristic of the initial characteristics when V is 10V and the Vg-Id characteristic when the gate voltage Vg is 10V The initial field effect mobility versus gate voltage is shown. The dashed line indicates the drain voltage Vd The Vg-Id characteristics after GBT testing when the gate voltage Vg is 1V and 10V, and the This shows the field effect mobility after the GBT test for the gate voltage when the field effect Mobility results are given in the saturation region for each sample.

[0461] In addition, for each sample, 20 transistors with the same structure were fabricated on the substrate. In the graphs shown in Figs. 20 and 21, data for 20 transistors are overlapped. It shows.

[0462] 20 and 21, in the initial characteristics shown by the solid lines in Samples 1 to 6, It can be seen that good switching characteristics are obtained. On the other hand, the broken line indicates the results after the GBT test. In the characteristics of Samples 1 to 3, there is almost no change from the initial characteristics. or the fluctuation is very small (the dashed line is shown almost overlapping with the solid line). In the samples 4 to 6 shown in FIG. 21, the initial characteristics are shown by the solid line, whereas the G A large change in the characteristics after the GBT test was observed. The rising voltage is shifted to the negative direction. There are two peaks that change stepwise when the polarization direction is changed from the negative direction to the positive direction.

[0463] The large structures of Samples 1 to 3 according to one embodiment of the present invention and Samples 4 to 6 for comparison The difference is that the backgate electrodes (backgate electrode 527 and backgate electrode 528) In Samples 1 to 3 which are embodiments of the present invention, the back gate electrode The shape of the gate electrode 515 covers the oxide semiconductor film 518 and overlaps with an edge of the gate electrode 515. In other words, the side surfaces of the channel portion of the oxide semiconductor film 518 are connected to upper and lower gate electrodes (gate The structure is covered by the electrode 515 and the back gate electrode 527. Then, the upper and lower gate electrodes (gate electrodes) are formed on the outer periphery of the side surface of the channel portion of the oxide semiconductor film 518. The electrode 515 and the back gate electrode 527 are dielectrics (gate insulating film 517 and protective film 526 ) and faces each other through a gap.

[0464] On the other hand, in the comparative samples 4 to 6, the shape of the back gate electrode 528 is an oxide. It is formed inside the compound semiconductor film 518 .

[0465] After the GBT test, the oxide semiconductor film 518 was However, in the samples 1 to 3 of one embodiment of the present invention, The outer periphery of the side of the channel part of the compound semiconductor film 518 is connected to the upper and lower gate electrodes (gate electrode 515 The upper and lower gate electrodes 527 are covered with the back gate electrode 528. The electrodes prevent a parasitic channel that may occur in the outer periphery of the side surface of the channel portion of the oxide semiconductor film 518. This can eliminate parasitic channels or reduce the effects of parasitic channels. EXAMPLES

[0466] In this embodiment, the life expectancy of a device based on the degradation characteristics after a GBT test will be described. .

[0467] In this example, Sample 7, which is one embodiment of the present invention, was prepared. Samples 8 to 10 were also compared. As for sample 7, which is an embodiment of the present invention, see FIG. Materials 8 to 10 will be described with reference to Figures 23 and 24.

[0468] (Sample 7) The sample 7 includes a substrate 511, a gate electrode 515 on the substrate 511, and a gate electrode 515 on the substrate 511. A gate insulating film 517 on the electrode 515 and a gate electrode The oxide semiconductor film 518 provided in a region overlapping with the electrode 515, the gate insulating film 517, and A pair of electrodes 521 and 522 over the oxide semiconductor film 518, a protective film 526 on the electrodes 521 and 522; and a gate electrode and a back gate electrode 527 provided in a region overlapping with the gate electrode 515 (see FIG. 22). .

[0469] Note that the protective film 526 is formed by adding the oxide insulating film 523, the oxide insulating film 524, and the nitride insulating film 525. The back gate electrode 527 was formed in a three-layer laminate structure of 525. As shown in FIG. 5B, the gate electrode 515 is approximately aligned with both ends of the gate electrode 515. As shown in FIG. 22C, the protective electrode 527 is connected to the oxide semiconductor film 51 via a protective film 526. It was formed to cover 8.

[0470] The method for producing Sample 7 shown in FIG. 22 was the same as that for Sample 1 shown in Example 1. Therefore, sample 7 can be formed by applying the manufacturing method described in sample 1. This can be done.

[0471] (Sample 8) Sample 8 includes a substrate 511, a gate electrode 515 on the substrate 511, and a gate electrode 515 on the substrate 511. A gate insulating film 517 on the electrode 515 and a gate electrode An oxide semiconductor film 518 provided in a region overlapping with the electrode 515 and and has a pair of openings 550 and 552 reaching the oxide semiconductor film 518. A protective film 540 and a pair of electrodes provided on the protective film 540 and in contact with the oxide semiconductor film 518. a protective film 540 and a protective film 542 on the pair of electrodes 521 and 522; A backgate electrode is provided on the protective film 542 and in a region overlapping the gate electrode 515. and a port electrode 544 (see FIG. 23).

[0472] As shown in FIG. 23B, the end of the back gate electrode 544 is connected to the gate electrode 51. 23(C) 。 Also, the back gate electrode 544 is located inside both ends of the back gate electrode 544 shown in FIG. 5, the oxide semiconductor film 518 is covered with the protective films 540 and 542 interposed therebetween.

[0473] Next, the structure of Sample 8 shown in FIG. 23 will be described below.

[0474] A gate electrode 515 is provided on a substrate 511. The gate electrode 515 is a Mo The film is a laminated film of a -Ti film and a Cu film with a thickness of 315 nm.

[0475] A gate insulating film 517 is provided on the gate electrode 515. The gate insulating film 517 has a thickness of 30 The film is a laminated film consisting of a silicon nitride film with a thickness of 400 nm and a silicon oxide film with a thickness of 400 nm.

[0476] An oxide semiconductor film 518 is provided over the gate insulating film 517. The oxide semiconductor film 518 has a thickness The IGZO film is 50 nm thick.

[0477] A protective film 540 having openings 550 and 552 is provided on the oxide semiconductor film 518. Film 540 is a silicon oxide film having a thickness of 100 nm.

[0478] A pair of electrodes 521 and 522 are provided on a protective film 540 so as to cover the openings 550 and 552. The electrodes 521 and 522 are made of a Mo-Ti film having a thickness of 30 nm and a Cu film having a thickness of 425 nm. It is a laminated film.

[0479] A protective film 542 is provided on the protective film 540 and the electrodes 521 and 522. The protective film 542 has a thickness of The silicon oxide film is 325 nm thick.

[0480] A back gate electrode 544 is provided on the protective film 542. The back gate electrode 544 has a thickness It is a laminated film of a 30 nm Mo-Ti film and a 10 nm thick ITO film.

[0481] (Sample 9) Sample 9 includes a substrate 511, a gate electrode 515 on the substrate 511, and a gate electrode 515 on the substrate 511. A gate insulating film 517 on the electrode 515 and a gate electrode The oxide semiconductor film 518 provided in a region overlapping with the electrode 515, the gate insulating film 517, and A pair of electrodes 521 and 522 over the oxide semiconductor film 518, the oxide semiconductor film 518 and and a protective film 526 on the pair of electrodes 521, 522 (see FIG. 24).

[0482] Note that the protective film 526 is formed by adding the oxide insulating film 523, the oxide insulating film 524, and the nitride insulating film 525. It is formed with a three-layer laminate structure of 525.

[0483] Moreover, compared to sample 7, sample 9 has a structure in which a back gate electrode is not provided.

[0484] Next, a method for fabricating Sample 9 shown in FIG. 24 will be described below.

[0485] A gate electrode 515 was formed on a substrate 511. The gate electrode 515 had a thickness of 10 nm. A tungsten film with a thickness of 1.0 μm was used.

[0486] Next, a gate insulating film 517 was formed on the gate electrode 515. The silicon nitride film with a thickness of 400 nm and the silicon oxynitride film with a thickness of 50 nm are laminated. It was formed.

[0487] Next, an oxide semiconductor film 518 was formed over the gate insulating film 517. The IGZO film was a 35 nm thick film of In:Ga:Zn= A target with an atomic ratio of 1:1:1 was used.

[0488] Next, a pair of electrodes 521 and 522 were formed over the oxide semiconductor film 518. 22 is a tungsten film having a thickness of 50 nm, an aluminum film having a thickness of 400 nm, A laminated film of this and a titanium film having a thickness of 200 nm was used.

[0489] Next, a protective film 526 was formed over the oxide semiconductor film 518 and the electrodes 521 and 522. The protective film 526 is a silicon oxynitride film having a thickness of 50 nm and a silicon oxynitride film having a thickness of 400 nm. A silicon film and a silicon nitride film with a thickness of 100 nm were used. The silicon nitride film was formed at a substrate temperature of 350° C. The silicon nitride film was formed with a thickness of 400 nm. The silicon film and the 100 nm thick silicon nitride film were formed at a substrate temperature of 220°C.

[0490] Through the above steps, sample 9 was prepared.

[0491] (Sample 10) Sample 10 is a composite of Sample 9 and the oxide semiconductor film 518. The post-formation heat treatment is different.

[0492] Specifically, the oxide semiconductor film 518 of Sample 10 was a first oxide semiconductor film and a second oxide semiconductor film. The first oxide semiconductor film was a 35-nm-thick stack of the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film was an IGZO film. The second oxide semiconductor film was formed using a target having a thickness of 20 nm. The second oxide semiconductor film was an IGZO film having a composition of In:Ga:Zn=1:3:2. A target with an atomic ratio of 1:1 was used.

[0493] In addition, after the oxide semiconductor film 518 of Sample 10 was formed, it was heated at 450° C. for 1 hour in a nitrogen atmosphere. Heat treatment was carried out.

[0494] Sample 10 was fabricated by the above steps. Since this is similar to Sample 9 described above, Sample 10 can be prepared by incorporating the above description. .

[0495] The transistors of Samples 7, 9, and 10 have a channel length (L) of 6 μm. The channel width (W) is 50 μm. The transistor of sample 8 has a channel length (L) The channel size (W) is 10.2 μm and the channel width (W) is 82.6 μm.

[0496] <Device Lifetime Estimation in Plus GBT Test> Next, the positive GBT test was carried out on the samples 7 to 10 prepared above. The T-stress test conditions were a board temperature of 60°C and a dark room (dark environment). In the lower figure, a gate voltage of +30V was applied and the stress time was varied.

[0497] For samples 7, 9, and 10, the stress time was 1 The variation of the threshold voltage is 00 seconds, 500 seconds, 1500 seconds, 2000 seconds, and 3600 seconds. For sample 8, the stress time was set to 100 seconds, 300 seconds, 600 seconds, The amount of change in threshold voltage was measured for 1000 seconds, 1800 seconds, and 3600 seconds.

[0498] FIG. 25 shows the variation of the threshold voltage for each stress time for samples 7 to 10. The approximate curves obtained from the amount of movement are shown in Fig. 25. Note that the approximate curves shown in Fig. 25 are all power approximate lines. FIG. 25 is a double logarithmic graph, and in FIG. 25, the horizontal axis represents stress time expressed in logarithm. The vertical axis shows the logarithmic variation in threshold voltage (ΔVth). The double logarithmic graph shown has equal intervals between the logarithmic scales on the horizontal and vertical axes.

[0499] From the results shown in FIG. 25, it can be seen that the logarithmic stress time for sample 7, which is an embodiment of the present invention, The logarithmic approximation line of the threshold voltage fluctuation and the threshold voltage fluctuation of 0V The angle between the line and the stress time is about 17°. The variation in threshold voltage at this time is approximately 0.06 V. The slope of the power approximation line was 0.3119 V / hr.

[0500] The logarithmic stress time versus logarithmic threshold voltage for comparative sample 8 was also The angle between the power approximation line of the threshold voltage fluctuation and the line of 0V is close to 31°. The change in threshold voltage when the stress time was 0.1 hours was also is around 0.05 V. The slope of the power approximation line for sample 8 is 0.599 It was 3V / hr.

[0501] The logarithmic stress time versus logarithmic threshold voltage for comparative sample 9 was also The angle between the power approximation line of the threshold voltage fluctuation and the line of 0V is close to 24°. The change in threshold voltage when the stress time was 0.1 hours was also The slope of the power approximation line for sample 9 is 0.41 V / It was hr.

[0502] Also, the logarithmic threshold value for the logarithmic stress time of sample 10 for comparison is The angle between the power approximation line of the voltage fluctuation and the line where the threshold voltage fluctuation is 0V is 27°. The change in threshold voltage when the stress time is 0.1 hours is also shown. The slope of the power approximation line for sample 10 is 0.4 It was 153V / hr.

[0503] As shown in FIG. 25, sample 7 according to one embodiment of the present invention shows a logarithmic change in the stress versus time. The power approximation line of the logarithmic variation of the threshold voltage and the line where the variation of the threshold voltage is 0V are shown. The threshold voltage when the angle between the line and the The variation is less than 0.2 V. A semiconductor device using such a relationship has a large variation in threshold voltage. In Sample 7 of one embodiment of the present invention, the side surface of the channel formation region of the oxide semiconductor film is It was found that the amount of variation in transistor characteristics can be reduced by covering the upper and lower gate electrodes. It was.

Claims

1. a first conductive film on a substrate; a first insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween; having the first conductive film has a region that functions as a first gate electrode of a transistor; the oxide semiconductor film has a region which functions as a channel of the transistor, the second conductive film has a region that functions as a source electrode of the transistor, the third conductive film has a region that functions as a drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, an end portion of the first conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; an end portion of the fourth conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; the oxide semiconductor film contains indium, gallium, and zinc; the oxide semiconductor film has a first region in which a plurality of spots arranged in a circular shape are observed in a diffraction pattern obtained by nanobeam electron diffraction in which an electron beam is focused to a probe diameter of 1 nm; The first region comprises a nanocrystal.

2. a first conductive film on a substrate; a first insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween; A light-emitting element; having the first conductive film has a region that functions as a first gate electrode of a transistor; the oxide semiconductor film has a region which functions as a channel of the transistor, the second conductive film has a region that functions as a source electrode of the transistor, the third conductive film has a region that functions as a drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, one of the second conductive film and the third conductive film is electrically connected to one electrode of the light-emitting element; an end portion of the first conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; an end portion of the fourth conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; the oxide semiconductor film contains indium, gallium, and zinc; the oxide semiconductor film has a first region in which a plurality of spots arranged in a circular shape are observed in a diffraction pattern obtained by nanobeam electron diffraction in which an electron beam is focused to a probe diameter of 1 nm; The first region comprises a nanocrystal.

3. a first conductive film on a substrate; a first insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween; having the first conductive film has a region that functions as a first gate electrode of a transistor; the oxide semiconductor film has a region which functions as a channel of the transistor, the second conductive film has a region that functions as a source electrode of the transistor, the third conductive film has a region that functions as a drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, an end portion of the first conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; an end portion of the fourth conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; the first conductive film has a metal element selected from the group consisting of aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or an alloy containing the metal element; the fourth conductive film has a metal element selected from the group consisting of aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or has an alloy containing the metal element; the oxide semiconductor film contains indium, gallium, and zinc; the oxide semiconductor film has a first region in which a plurality of spots arranged in a circular shape are observed in a diffraction pattern obtained by nanobeam electron diffraction in which an electron beam is focused to a probe diameter of 1 nm; The first region comprises a nanocrystal.

4. a first conductive film on a substrate; a first insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween; A light-emitting element; having the first conductive film has a region that functions as a first gate electrode of a transistor; the oxide semiconductor film has a region which functions as a channel of the transistor, the second conductive film has a region that functions as a source electrode of the transistor, the third conductive film has a region that functions as a drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, one of the second conductive film and the third conductive film is electrically connected to one electrode of the light-emitting element; an end portion of the first conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; an end portion of the fourth conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; the first conductive film has a metal element selected from the group consisting of aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or an alloy containing the metal element; the fourth conductive film has a metal element selected from the group consisting of aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or has an alloy containing the metal element; the oxide semiconductor film contains indium, gallium, and zinc; the oxide semiconductor film has a first region in which a plurality of spots arranged in a circular shape are observed in a diffraction pattern obtained by nanobeam electron diffraction in which an electron beam is focused to a probe diameter of 1 nm; The first region comprises a nanocrystal.

5. a first conductive film on a substrate; a first insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween; having the first conductive film has a region that functions as a first gate electrode of a transistor; the oxide semiconductor film has a region which functions as a channel of the transistor, the second conductive film has a region that functions as a source electrode of the transistor, the third conductive film has a region that functions as a drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, an end portion of the first conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; an end portion of the fourth conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; the first conductive film has a region that functions as a light-shielding film, the oxide semiconductor film contains indium, gallium, and zinc; the oxide semiconductor film has a first region in which a plurality of spots arranged in a circular shape are observed in a diffraction pattern obtained by nanobeam electron diffraction in which an electron beam is focused to a probe diameter of 1 nm; The first region comprises a nanocrystal.

6. a first conductive film on a substrate; a first insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween; A light-emitting element; having the first conductive film has a region that functions as a first gate electrode of a transistor; the oxide semiconductor film has a region which functions as a channel of the transistor, the second conductive film has a region that functions as a source electrode of the transistor, the third conductive film has a region that functions as a drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, one of the second conductive film and the third conductive film is electrically connected to one electrode of the light-emitting element; an end portion of the first conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; an end portion of the fourth conductive film is located outside an end portion of the oxide semiconductor film in a channel width direction of the transistor; the first conductive film has a region that functions as a light-shielding film, the oxide semiconductor film contains indium, gallium, and zinc; the oxide semiconductor film has a first region in which a plurality of spots arranged in a circular shape are observed in a diffraction pattern obtained by nanobeam electron diffraction in which an electron beam is focused to a probe diameter of 1 nm; The first region comprises a nanocrystal.

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