Semiconductor Device

Abstract

To reduce circuit scale of a semiconductor device, or to improve drive capability of the semiconductor device.SOLUTION: A transistor with a channel region formed of oxide semiconductor is used as pull-down transistor. The oxide semiconductor has a bandgap of 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Therefore, hot carrier deterioration in the transistor can be suppressed. Thus, circuit scale of a semiconductor device with the pull-down transistor can be reduced. A gate of the pull-up transistor is put into a floating state by switching of the transistor. Higher purity of the oxide semiconductor can provide transistor off-current of 1aA / μm(1×10-18A / μm) or less. As a result, the drive capability of the semiconductor device can be improved.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to a display device. For example, a liquid crystal display device is exemplified. A display device in which pixels are selected by a pixel signal line and a source signal line to display an image is classified into a technical category. Also, semiconductor devices such as driver circuits used in display devices, display devices, etc. Electronic devices using this technology are also included as one of the technical fields. [Background technology]

[0002] A gate made of amorphous silicon transistors (also called a-Si TFTs) The development of gate driver circuits is currently underway. A transistor (pull-down transistor) that maintains the potential of the The problem is that the threshold voltage of the transistor (also called a transistor) shifts, causing malfunction. In order to solve this problem, during the period in which the potential of the gate line is kept low, A gate driver circuit is opened, in which the pull-down transistor is repeatedly turned on and off. As a result, the pull-down transistor This shortens the time that the pull-down transistor is on, which reduces the degradation of the pull-down transistor. It can be suppressed.

[0003] In addition, the gate driver circuit, which is made up of amorphous silicon transistors, A transistor that controls the timing of outputting a high voltage to the output line (a pull-up transistor A pull-up transistor has one of its source and drain connected to a clock signal. The other of the source and drain is connected to a gate signal line. The potential of the gate of the up-transistor is capacitively coupled to the high level of the clock signal. To achieve this, a pull-up transistor is used. The gate of the pull-up transistor must be left floating. All transistors connected to the port must be in the off state. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-207413 A [Patent Document 2] JP 2008-009393 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the conventional technology, in order for a pull-down transistor to repeatedly turn on and off, A circuit is required to control the conduction state of the pull-down transistor. There was a limit to how much the circuit scale of the device could be reduced. Even if all the transistors connected to the transistors are turned off, The charge held by the gate of the pull-up transistor was lost over time. Therefore, it has been difficult to lower the driving frequency of semiconductor devices such as gate driver circuits. As a result, the range of drive frequencies in which semiconductor devices can operate has become narrower. There was a limit to how much the driving capability of the semiconductor device could be improved.

[0006] In view of the above problems, one object of one embodiment of the present invention is to reduce the circuit scale of a semiconductor device. Another object of one embodiment of the present invention is to improve the driving capability of a semiconductor device. Note that it is not necessary for one embodiment of the present invention to achieve all of the above-described objects. . [Means for solving the problem]

[0007] The above-mentioned problem is solved by using an oxide as the pull-up transistor or the pull-down transistor. This can be solved by applying a transistor in which the channel region is formed from a nitride semiconductor. Note that the oxide semiconductor can be formed by removing impurities (such as hydrogen or water) that serve as electron donors (donors). ) is thoroughly removed to produce a highly purified oxide semiconductor.

[0008] The oxide semiconductor has a polarization constant of 2.0 eV or more, preferably 2.5 eV or more, and more preferably 3. Therefore, the oxide semiconductor has a band gap of 0 eV or more. In a transistor in which this is formed, impact ionization and avalanche breakdown are unlikely to occur. In other words, the carriers (electrons) in the oxide semiconductor are not easily accelerated. In a transistor in which the channel region is formed from a nitride semiconductor, the gate of carriers (electrons) Shift in the threshold voltage of transistors due to implantation into the insulating layer (so-called hot capacitance) This can suppress rear deterioration.

[0009] In addition, in a transistor in which a channel region is formed using the oxide semiconductor, Therefore, the off-current per 1 μm of channel width is 1 aA (1 × 10 -18 A) or less (this is expressed as 1 aA / μm).

[0010] That is, one aspect of the present invention is a liquid crystal display device comprising a plurality of gate signal lines, a plurality of source signal lines, and A pixel is disposed at each intersection of a gate signal line and a source signal line. and a gate driver circuit electrically connected to the first gate line. The first transistor, the second transistor, and an inverter circuit are provided. A first terminal of the first transistor is electrically connected to a first wiring. The second terminal of the second transistor is electrically connected to a second wiring, and the first terminal of the second transistor is A second terminal of the second transistor is electrically connected to a third wiring. The input terminal of the inverter circuit is electrically connected to the gate of the first transistor. The output terminal of the inverter circuit is electrically connected to the output of the second transistor. a gate of the first transistor and a gate of the second transistor, A channel region is formed of a nitride semiconductor, and the first transistor and the second transistor The display device has a transistor off-state current of 1 aA / μm or less.

[0011] Moreover, one aspect of the present invention is a liquid crystal display device including a plurality of gate signal lines, a plurality of source signal lines, and a pixel disposed at an intersection between the gate signal lines and the source signal lines; and a gate driver circuit electrically connected to the first A first transistor, a second transistor, and an inverter circuit. A first terminal of the first transistor is electrically connected to a first wiring, and a second terminal of the first transistor is electrically connected to a first wiring. The terminal is electrically connected to a second wiring, and the first terminal of the second transistor is a second terminal of the second transistor electrically connected to the wiring of the first transistor; The input terminal of the inverter circuit is electrically connected to the gate of the first transistor. The output terminal of the inverter circuit is electrically connected to the gate of the second transistor. a gate of the first transistor and a gate of the second transistor, The first transistor and the second transistor have a channel region formed of an oxide semiconductor. In the display device, the off-state current of the second transistor is 1 aA / μm or less.

[0012] Moreover, one aspect of the present invention is a liquid crystal display device including a plurality of gate signal lines, a plurality of source signal lines, and a pixel disposed at an intersection between the gate signal lines and the source signal lines; and a gate driver circuit electrically connected to the first A transistor, a second transistor, a third transistor, and an inverter circuit. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the transistor is electrically connected to a second wiring, and the second transistor The first terminal of the second transistor is electrically connected to a third wiring, and the second terminal of the second transistor is electrically connected to a third wiring. a first terminal of the third transistor electrically connected to the second wiring; The second terminal of the third transistor is electrically connected to the wiring of the first transistor. the gate of the third transistor is electrically connected to the gate of the fourth transistor; The input terminal of the inverter circuit is electrically connected to the first transistor. The output terminal of the inverter circuit is electrically connected to the gate of the second transistor. and the first transistor to the third transistor are electrically connected to a gate of A channel region is formed using an oxide semiconductor, and the first to third transistors This is a display device in which the off-state current of the transistor is 1 aA / μm or less.

[0013] Moreover, one aspect of the present invention is a liquid crystal display device including a plurality of gate signal lines, a plurality of source signal lines, and a pixel disposed at an intersection between the gate signal lines and the source signal lines; and a gate driver circuit electrically connected to the first A transistor, a second transistor, a third transistor, and an inverter circuit. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the transistor is electrically connected to a second wiring, and the second transistor The first terminal of the second transistor is electrically connected to a third wiring, and the second terminal of the second transistor is electrically connected to a third wiring. The first terminal of the third transistor is electrically connected to the second wiring. A second terminal of the third transistor is electrically connected to the third wiring. the gate of the third transistor is electrically connected to the gate of the fourth transistor; The input terminal of the inverter circuit is electrically connected to the first transistor. The output terminal of the inverter circuit is electrically connected to the gate of the second transistor. and the first transistor to the third transistor are electrically connected to a gate of A channel region is formed using an oxide semiconductor, and the first to third transistors This is a display device in which the off-state current of the transistor is 1 aA / μm or less.

[0014] Moreover, one aspect of the present invention is a liquid crystal display device including a plurality of gate signal lines, a plurality of source signal lines, and a pixel disposed at an intersection between the gate signal lines and the source signal lines; and a gate driver circuit electrically connected to the first a transistor, a second transistor, a third transistor, and a fourth transistor and an inverter circuit, and a first terminal of the first transistor is electrically connected to a first wiring. a second terminal of the first transistor electrically connected to a second wiring; A first terminal of the second transistor is electrically connected to a third wiring. A second terminal of the transistor is electrically connected to the second wiring, and the third transistor The first terminal of the third transistor is electrically connected to a fourth wiring. A terminal is electrically connected to the gate of the first transistor and to the gate of the third transistor. The gate of the fourth transistor is electrically connected to the fourth wiring, and the first terminal of the fourth transistor is is electrically connected to the third wiring, and a second terminal of the fourth transistor is The gate of the fourth transistor is electrically connected to the gate of the first transistor. The input terminal of the inverter circuit is electrically connected to the fifth wiring. The output terminal of the inverter circuit is electrically connected to the gate of the second transistor. the first transistor to the fourth transistor, The first transistor has a channel region formed of an oxide semiconductor, and the first transistor has a channel region formed of an oxide semiconductor. The display device has an off-state current of the transistor of No. 4 of 1 aA / μm or less.

[0015] Also, an electronic device is provided, comprising the above-mentioned display device and an operation switch for operating an image on the display device. An apparatus is also an aspect of the present invention.

[0016] In this specification, etc., anything explicitly stated as singular is understood to be singular. However, it is not limited to this, and multiple numbers are also possible. Where something is generally described as plural, it is preferable that it be plural. The term is not limited to the above, and may be singular.

[0017] In this specification, the terms first, second, third, etc. refer to various elements, members, regions, layers, sections, etc. It is used to describe one area in particular, distinguishing it from others. Hence the terms first, second, third, etc. The phrase does not limit the number of elements, members, regions, layers, areas, etc. "First" can be replaced with "second" or "third", etc. Effect of the Invention

[0018] One embodiment of the present invention is a transistor in which a channel region is formed using an oxide semiconductor. This applies the honour voltage to the pull-down transistor. Therefore, it functions as a pull-down transistor. This reduces the number of transistors that can function. The scale of the circuit for controlling the switching of the transistors can be reduced. As a result, the circuit scale of the semiconductor device having the pull-down transistor can be reduced. do.

[0019] In one embodiment of the present invention, a gate of a pull-up transistor is formed using an oxide semiconductor. The transistor that forms the channel region is switched on and off, causing the floating state. The gate of the pull-up transistor can retain the charge for a long period of time. Therefore, the driving frequency of the semiconductor device having the pull-up transistor can be reduced. In addition, the range of driving frequencies in which the semiconductor device can operate can be widened. As a result, the driving capability of the semiconductor device can be improved. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 illustrates a configuration of a circuit according to Embodiment 1. [Diagram 2] 1A and 1B are a timing chart for explaining the operation of the circuit according to the first embodiment and a schematic diagram for explaining the operation of the circuit according to the first embodiment; [Diagram 3] 3 is a schematic diagram for explaining the operation of the circuit according to the first embodiment; [Figure 4] 3 is a schematic diagram for explaining the operation of the circuit according to the first embodiment; [Diagram 5] FIG. 1 illustrates a configuration of a circuit according to Embodiment 1. [Figure 6] FIG. 1 illustrates a configuration of a circuit according to Embodiment 1. [Figure 7] FIG. 1 illustrates a configuration of a circuit according to Embodiment 1. [Figure 8] FIG. 1 illustrates a configuration of a circuit according to Embodiment 1. [Figure 9] 4 is a timing chart for explaining the operation of the circuit according to the first embodiment. [Figure 10] FIG. 1 illustrates a configuration of a circuit according to Embodiment 1. [Figure 11] FIG. 13 illustrates a configuration of a shift register circuit according to a second embodiment. [Figure 12] 10 is a timing chart for explaining the operation of the shift register circuit according to the second embodiment. [Figure 13] 1A to 1C are examples of diagrams illustrating a manufacturing process of a transistor according to Embodiment 3. [Figure 14] 13 illustrates a structure of a display device according to Embodiment 4. [Figure 15] 1 is a diagram illustrating an example of an apparatus embodying the technical concept of the present invention; [Figure 16] 1 is a diagram illustrating an example of an apparatus embodying the technical concept of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, an embodiment will be described with reference to the drawings. However, the embodiment may be different from the embodiment. The present invention can be implemented in any manner without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that various modifications may be made to the embodiments. The contents of the description should not be construed as being limited to the above. In the drawings, the same reference numerals are used to denote parts or parts having similar functions, and the same parts or parts having similar functions are denoted by the same reference numerals in different drawings. In the drawings, the size, layers, and other details of the parts having the same functions are omitted. The thickness or area of ​​the components may be exaggerated for clarity. Not limited to scale.

[0022] (Embodiment 1) In this embodiment, a circuit related to a display device which is one embodiment of the present invention will be described.

[0023] FIG. 1A shows a transistor 101, a transistor 102, a transistor 103, and a transistor 1 shows an example of a circuit configuration including a transistor 104, a transistor 105, and a circuit 200. The transistors that make up the circuit shown in A) are N-channel type. A transistor is turned on when the voltage difference between its gate and source is greater than the threshold voltage. It is a transistor.

[0024] Note that a semiconductor layer of a transistor included in the circuit illustrated in FIG. 1A is formed using an oxide semiconductor. The oxide semiconductor can be highly purified by sufficiently reducing the hydrogen concentration. , the carrier density is sufficiently small, and it is made intrinsic (i-type) or substantially intrinsic (i-type) This makes it possible to reduce the S value of the transistor. The off-state current of the transistor can be reduced. The withstand voltage of the transistor can be improved. The temperature characteristics of the transistor can be improved. The deterioration of the transistor can be suppressed. Specifically, the amount of shift in the threshold voltage of the transistor can be reduced.

[0025] Note that the above oxide semiconductor is used for the semiconductor layers of some transistors, and As the semiconductor layer of the transistor, a semiconductor other than the above oxide semiconductor (e.g., silicon (amorphous silicon) Silicon, microcrystalline silicon or polycrystalline silicon, organic semiconductors, etc. can be used. However, at least the source or drain of the transistor 101 is connected to the gate of the transistor 102. The above oxide semiconductor is used for the semiconductor layer of the transistor.

[0026] The connection relationship of the circuit shown in FIG. 1A will be described. The first terminal of the transistor 101 is A second terminal of the transistor 101 is connected to a wiring 111. A second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to the wiring 113. A second terminal of the transistor 103 is connected to the wiring 112. The second terminal of the transistor 103 is connected to the gate of the transistor 101. The gate of the transistor 103 is connected to the gate of the transistor 102. A first terminal of the transistor 104 is connected to the wiring 114. The second terminal is connected to the gate of the transistor 101. A first terminal of the transistor 105 is connected to a wiring 113. The second terminal of the transistor 105 is connected to the gate of the transistor 101. The gate of the transistor 105 is connected to the wiring 115. The output terminal of the circuit 200 is connected to the gate of the transistor 102. The gate of the transistor 101 is connected to a node 11. The gate of the register 102 is indicated as node 12. Note that the circuit 200 may be configured in any manner depending on its configuration. For example, the circuit 200 can be connected to the wiring 111. , the wiring 112, the wiring 113, the wiring 114, the wiring 115, the nodes 11 and 12 It is possible to connect to more than one.

[0027] The source and drain of a transistor may vary depending on the structure and operating conditions of the transistor. Therefore, it is difficult to identify which is the source and which is the drain. In this document, one of the source and the drain is referred to as a first terminal, and the other of the source and the drain is referred to as a second terminal. In order to distinguish this terminal, the other terminal will be referred to as the second terminal.

[0028] An example of the configuration of the circuit 200 will be described with reference to FIG. The transistor 201, the transistor 202, the transistor 203 and the transistor 204 are provided. A first terminal of the transistor 201 is connected to the wiring 116. A second terminal of the transistor 201 is connected to the node 12. A first terminal of the transistor 202 is connected to the wiring The second terminal of the transistor 202 is connected to the node 12. The gate of the transistor 202 is connected to the node 11. The first end of the transistor 203 is connected to the node 11. The second terminal of the transistor 203 is connected to the wiring 116. The gate of the transistor 203 is connected to a wiring 116. A first terminal of the transistor 204 is connected to the wiring 113. The terminal of the transistor 204 is connected to the gate of the transistor 201. Connected to node 11.

[0029] A clock signal is input to the wiring 111. The output of the circuit of this embodiment is connected to the wiring 112. A voltage V2 is supplied to the wiring 113. A star A start pulse is input to the wiring 115. A reset signal is input to the wiring 116. A voltage V1 is supplied to the wiring 111, the wiring 112, the wiring 114, and the wiring 115. For convenience, the H-level potential of the input signal is referred to as potential V1. For convenience, the potential of the L level of the signal input to the wiring 114 and the wiring 115 is referred to as a potential V2.

[0030] The wiring 111 transmits a clock signal, etc. from an external circuit such as a controller to the circuit of this embodiment. A wiring for transmitting signals, and functions as a signal line or a clock signal line. A line 112 transmits the output signal of the circuit of this embodiment to a pixel circuit or a circuit such as a demultiplexer. The wiring 113 is a wiring for transmitting the signal and functions as a signal line or a gate signal line. supplies a power supply voltage such as voltage V2 from an external circuit such as a power supply circuit to the circuit of this embodiment. The wiring 11 functions as a power supply line, a negative power supply line, or a ground line. 4 is a timing controller or other external circuit that transmits a timing signal to the circuit of this embodiment. The wiring 115 is a wiring for transmitting a start signal and functions as a signal line. A reset signal is input to the circuit of this embodiment from an external circuit such as a timing controller or another circuit. The wiring 116 is a wiring for transmitting signals and functions as a signal line. Wiring for supplying a power supply voltage such as voltage V1 from an external circuit such as a line to the circuit of this embodiment. and functions as a power supply line or a positive power supply line.

[0031] The transistor 101 functions as a switch that controls the electrical continuity between the wiring 111 and the wiring 112. In addition, the transistor 101 has a function of The transistor 10 has a function of controlling the timing at which the potential of the node 11 is increased. 2 has a function as a switch that controls the electrical connection between the wiring 113 and the wiring 112. do. The transistor 103 functions as a switch that controls the electrical continuity between the wiring 113 and the node 11. The transistor 104 is in a conductive state between the wiring 114 and the node 11. The transistor 104 has a function as a switch that controls the input terminal. It is connected to the line 114 and has a function as a diode with its output terminal connected to the node 11. The transistor 105 is a switch that controls the electrical continuity between the wiring 113 and the node 11. The transistor 201 functions as a conduction transistor between the wiring 116 and the node 12. The transistor 201 has a function as a switch that controls the state. The function of controlling the timing of increasing the potential of node 21 is achieved by capacitive coupling between the transistor and the gate. The transistor 202 controls electrical continuity between the wiring 113 and the node 12. The transistor 203 has a function as a switch that connects the node 12 and the wiring 116. The transistor 203 functions as a switch that controls the conduction state between the 116 and the output terminal of the diode connected to the node 21. The transistor 204 controls electrical continuity between the wiring 113 and the node 21. It functions as a control switch.

[0032] The circuit 200 controls the potential of the node 12 and the transistors 102 and 103. The circuit 200 also functions as a control circuit for controlling the conduction state of the node 11. The potential of the input terminal 11 is inverted and output to the node 12.

[0033] Next, an example of the operation of the circuits shown in FIG. 1(A) and FIG. 1(B) will be described with reference to the type shown in FIG. The following description will be given with reference to a timing chart. Here, the circuit shown in FIG. 1B will be used as an example. The timing chart in FIG. 2A includes a period A, a period B, a period C, and a period D. do.

[0034] In the period A, the potential of the wiring 111 (denoted as a potential V111) is V2, and the potential of the wiring 114 is V111. The potential of the wiring 115 (shown as potential V115) becomes V2. As a result, the transistor 104 is turned on, and the wiring 114 and the node 11 The transistor 105 is turned off. At this time, the circuit 200 The potential of the node 12 (referred to as potential V12) is set to V2. The transistor 103 is turned off, and the wiring 113 and the wiring 112 are not electrically connected to each other. This causes a state of non-conduction between the wiring 113 and the node 11. The potential of the wiring 114 is supplied to the node 11, and the potential of the node 11 (denoted as potential V11) starts to rise. Soon, the potential of node 11 becomes V2+Vth101 (Vth101 is the potential of transistor 10). This causes the transistor 101 to turn on, and the The line 111 and the wiring 112 are in a conductive state. Therefore, the potential of the wiring 111 is applied to the wiring 112. The potential of the wiring 112 (denoted as potential V112) becomes equal to V2 (see FIG. 2B). see).

[0035] After that, the potential of the node 11 continues to rise. Eventually, the potential of the node 11 reaches V1 -Vth104 (Vth104 is the threshold voltage of the transistor 104) is reached. As a result, the transistor 104 is turned off, and electrical continuity between the wiring 114 and the node 11 is interrupted. Therefore, the node 11 is in a floating state, and the potential of the node 11 is V1-Vth104 (V 1-Vth104 is higher than V2+Vth101) (Figure 3( See A).

[0036] In the period B, the potential of the wiring 111 becomes V1, the potential of the wiring 114 becomes V2, and The potential of the transistor 104 remains at V2. Therefore, the wiring 114 and the node 11 remain in a non-conductive state. The transistor 105 is in an off state. In this case, the wiring 113 and the node 11 remain in a non-conductive state. 00 leaves the potential of node 12 equal to V2. This causes transistor 102 The transistor remains in the off state, and the wiring 113 and the wiring 112 remain in a non-conducting state. The transistor 103 remains in an off state, and the wiring 113 and the node 11 remain in a non-conducting state. Therefore, since node 11 remains floating, the potential of node 11 is V1-Vt h104 remains equal to h104. This allows transistor 101 to remain on. The wiring 111 and the wiring 112 remain in a conductive state. Therefore, the potential of the wiring 112 starts to rise. Then, the node 11 becomes floating. Since the transistor 101 is in the ON state, the potential of the node 11 is The potential at node 11 starts to rise due to parasitic capacitance. Eventually, the potential at node 11 becomes V1 + Vth101 + V a (Va is a positive potential). As a result, the potential of the wiring 112 reaches a value equal to V1. (See Fig. 3(B)). This type of operation is called bootstrap operation. say.

[0037] In the period C, the potential of the wiring 111 becomes V2, the potential of the wiring 114 remains at V2, and The potential of the line 115 becomes V1. This causes the transistor 104 to remain in the off state. Therefore, the wiring 114 and the node 11 remain in a non-conductive state. The transistor 105 is in an on state. Therefore, the wiring 113 and the node 11 are electrically connected to each other. 3, and the potential of node 11 becomes equal to V2. This causes the transistor 101 is turned off, and the wiring 111 and the wiring 112 are not electrically connected. Path 200 makes node 12 equal to V1. This causes transistor 102 to The transistor 103 is turned on, and the wiring 113 and the wiring 112 are brought into electrical continuity. Therefore, the wiring 112 is in a conductive state, and the wiring 113 and the node 11 are in a conductive state. Since the potential of the line 113 is supplied, the potential of the wiring 112 becomes V2 (see FIG. 4A).

[0038] In the period D, the potential of the wiring 111 alternates between V1 and V2, and the potential of the wiring 114 is V 2, and the potential of the wiring 115 becomes V2. The transistor remains in the off state, and the wiring 114 and the node 11 remain in a non-conducting state. The transistor 105 is turned off, and the wiring 113 and the node 11 are not electrically connected to each other. The circuit 200 keeps the potential of the node 12 at V1. This causes the transistor 102 The transistor remains on, and the wiring 113 and the wiring 112 remain in a conductive state. The starter 103 remains on, and the line 113 and the node 11 remain in a conductive state. Therefore, the potential of the wiring 113 is still supplied to the node 11. The potential of the transistor 101 remains at V2. Therefore, the wiring 111 and the wiring 112 remain in a non-conducting state. Since the potential of the wiring 113 is still being supplied, the potential of the wiring 112 remains at V2 (FIG. 4 (See (B)).

[0039] Next, the operation of the circuit 200 will be described in detail. For example, when the potential of the node 11 is V2 +Vth202 (Vth202 is the threshold voltage of the transistor 202) or more, and V2 +Vth204 (Vth204 is the threshold voltage of the transistor 204) or more. As a result, the transistor 202 is turned on, and electrical continuity between the wiring 113 and the node 12 is established. The transistor 204 is turned on, and electrical continuity between the wiring 113 and the node 21 is established. At this time, the transistor 203 is turned on, and the wiring 116 and the node 21 are electrically connected. Therefore, the potential of the wiring 116 and the potential of the wiring 113 are supplied to the node 21. The potential of the node 21 (denoted as potential V21) is higher than V2 and lower than V1. The potential of the node 21 is determined by the current supply capability of the transistor 203 (for example, the channel length, channel width, mobility, etc.) and the current supply capability of the transistor 204. Here, the potential of node 21 is V2+Vth201 (Vth201 is transistor 2 01) (the threshold voltage of transistor 201). As a result, transistor 201 is turned off. Therefore, the wiring 116 and the node 12 are not electrically connected to each other. is supplied, and the potential of node 12 becomes equal to V2 (eg, during periods A and B).

[0040] On the other hand, for example, the potential of the node 11 is less than V2+Vth202 and V2+Vth As a result, the transistor 202 is turned off, and the wiring 11 The transistor 204 is turned off, and the wiring 11 is connected to the node 12. 3 and node 21 are in a non-conductive state. At this time, transistor 203 is in an on state. Therefore, the node 21 is connected to the wiring 116. The potential of node 21 is then increased. V1+Vth201+Vb (Vb is a positive potential). is turned on, and the wiring 116 and the node 12 are brought into electrical continuity. The potential of the wiring 116 is supplied to the node 12, and the potential of the node 12 becomes V1 (for example, during periods C and D). D).

[0041] As described above, the circuits shown in FIGS. 1A and 1B use the bootstrap operation. This allows the potential of the wiring 112 to be equal to the potential of the wiring 111. In the period B, the potential difference (Vgs) between the gate and source of the transistor 101 is Since it can be made larger, the rise time of V112 can be shortened.

[0042] In the conventional technology, the S value of the transistor is large. The time from when the potential of the output terminal 4 becomes V1 until the transistor 104 turns on becomes longer. In addition, since it is necessary to lengthen period A, it is difficult to increase the driving frequency. Also, the rise time of V112 was longer (the rise time of the output signal The length of the wiring 112 was long. Also, the load that could be connected to the wiring 112 was small. The channel width of the transistor 101 has become larger. Also, the layout area has become larger. was.

[0043] In contrast, in this embodiment, the S value of the transistor is small. For example, since the S value of the transistor 104 is small, the wiring 1 The time from when the potential of the transistor 104 becomes V1 until the transistor 104 is turned on is shortened. Therefore, the time of period A can be shortened. As another example, the S value of the transistor 101 is small. This makes it possible to shorten the rise time of V112. Even if a small load is connected, the load can be driven. Since the panel width can be reduced, the layout area can be reduced.

[0044] In the conventional technology, the off-state current of the transistor is large. As time passed, the amount of charge lost from node 11 was large. Also, the potential of node 11 was low. In addition, the potential of the node 11 is lowered to a potential at which the transistor 101 is turned on or higher. The time that the drive frequency could be maintained was shortened. Also, it was difficult to lower the drive frequency. In addition, the range of drive frequencies in which the device can operate is narrowed.

[0045] In contrast, in this embodiment, the off-state current of the transistor is small. For example, the transistor 103, the transistor 104, and the transistor The small off-current of the transistor 105 reduces the amount of charge lost from the node 11. Therefore, the decrease in the potential of the node 11 can be suppressed. The time during which the potential of the node 11 can be maintained at or above the potential at which the transistor 101 is turned on. This allows the drive frequency to be lowered, so the operation This makes it possible to widen the range of drive frequencies that can be used.

[0046] In the conventional technology, the transistors are easily deteriorated and the threshold voltage of the transistors shifts. The amount of current was large. This caused the transistor to repeatedly switch between on and off. In addition, two transistors were connected in parallel and these two transistors were switched. In addition, the circuitry for controlling the transistor conduction state became complicated. The number of transistors was also increasing. In order to achieve this, it was necessary to increase the channel width of the transistor. To suppress the degradation, it was necessary to increase the channel length of the transistor. The layout area had become larger.

[0047] In contrast, in this embodiment, the amount of shift in the threshold voltage of the transistor is small. For example, the transistor 102 and the transistor 103 can improve the driving capability. The small threshold voltage shift in 03 causes these transistors to turn on. Therefore, the transistors 102 and 103 can be turned on for a long time. The circuitry that controls the conduction state can be simplified. This reduces the number of transistors. This allows the layout area to be reduced. Since the amount of shift in the threshold voltage of the transistor 102 and the transistor 103 is small, This allows the channel width or length of the transistor to be reduced. In addition, the shift in the threshold voltage of the transistor is small. This makes it possible to extend the time during which the device can operate.

[0048] A circuit related to a display device which is one embodiment of the present invention is the circuit shown in FIG. There is no limitation to this, and various other circuit configurations can be used. An example of such a circuit is described below. Reveal.

[0049] For example, in the circuits shown in FIG. 1(A) and FIG. 1(B), as shown in FIG. 5(A), The input terminal of the transistor 112 can be connected to the wiring 112. The gate of the transistor 202 is connected to the wiring 112, and the gate of the transistor 204 is connected to the wiring 112. It is possible to realize the above. Note that FIG. 5A shows the circuit 20 in the circuit shown in FIG. 13 is a diagram showing a configuration in which an input terminal of 0 is connected to a wiring 112. FIG.

[0050] As another example, in the circuits shown in FIG. 1(A), FIG. 1(B) and FIG. 5(A), 1, the first terminal of the transistor 103 is connected to the wiring 112. The gate of the transistor 103 can be connected to the wiring 111. Since the time that the transistor 103 is on can be shortened, deterioration of the transistor 103 is suppressed. In addition, in the period B, the potential of the node 11 can be prevented from becoming too high. Therefore, a transistor (e.g., a transistor The transistor 101, the transistor 104, the transistor 105, or the transistors constituting the circuit 200 It is possible to prevent the destruction of the transistors or suppress the deterioration of the transistors. In the circuit shown in FIG. 1A, a first terminal of the transistor 103 is connected to a wiring 112. 1 is a diagram showing a configuration in which a gate of a transistor 103 is connected to a wiring 111. be.

[0051] As another example, in the circuits shown in FIGS. 1(A), 1(B), 5(A) and 5(B), As shown in FIG. 5C, the first terminal of the transistor 104 is connected to the wiring 116. FIG. 5C shows a circuit in which a transistor is 1 is a diagram showing a configuration in which a first terminal of 104 is connected to a wiring 116. FIG.

[0052] The circuits shown in Figs. 1(A), 1(B), 5(A), 5(B) and 5(C) include a transistor. Various elements such as transistors or capacitors can be provided. An example of such elements is described below. Reveal.

[0053] For example, in the circuits shown in Figs. 1(A), 1(B), 5(A), 5(B) and 5(C), As shown in FIG. 6A, the first terminal is connected to a wiring 113, and the second terminal is A transistor 121 is provided, the transistor 121 being connected to the line 112 and having a gate connected to the wiring 115. The transistor 121 is turned on in the period C, and the potential of the wiring 113 is increased. The potential is supplied to the wiring 112. Therefore, the fall time of V112 can be shortened. Note that FIG. 6A shows a configuration in which a transistor 121 is provided in the circuit shown in FIG. FIG.

[0054] As another example, FIGS. 1(A), 1(B), 5(A), 5(B), 5(C) and 6 In the circuit shown in (A), the first terminal is connected to the wiring 113 as shown in FIG. a transistor having a second terminal connected to the node 12 and a gate connected to the wiring 114; The transistor 122 is turned on in the period A. As a result, the potential of the wiring 113 is supplied to the node 12. The fall time of the transistor 103 can be shortened. Therefore, the potential of the node 11 reaches V1-Vth104. Since the timing can be advanced, period A can be shortened. The operating frequency can be increased. 13 is a diagram showing a configuration in which a resistor 122 is provided. FIG.

[0055] As another example, Figs. 1(A), 1(B), 5(A), 5(B), 5(C), and 6( In the circuit shown in FIG. 6(A) and FIG. 6(B), as shown in FIG. 6(C), the first terminal is connected to the wiring 1 16, a second terminal is connected to node 12, and a gate is connected to wiring 115. A transistor 123 may be provided. The transistor 123 is The potential of the wiring 116 is supplied to the node 12. Therefore, the rise time of V12 can be shortened. As a result, the timing at which the transistor 103 is turned on can be made earlier. Therefore, the timing at which the potential of the wiring 113 is supplied to the wiring 112 can be accelerated. The fall time of V112 can be shortened. 13 shows a configuration in which a transistor 123 is provided in the circuit shown in FIG.

[0056] As another example, Figs. 1(A), 1(B), 5(A), 5(B), 5(C), and 6( In the circuits shown in Figs. 6A, 6B and 6C, as shown in Fig. 7A, The first terminal is connected to the wiring 111, the second terminal is connected to the wiring 117, and the gate is connected to the node 11 a transistor 124 having a first terminal connected to the wiring 113 and a second terminal connected to the a transistor 125 connected to the wiring 117 and having a gate connected to the node 12; In this way, the potential of the wiring 117 can be changed at the time when the potential of the wiring 112 changes. For example, the wiring 112 and the wiring 11 One end of the wiring 112 and the wiring 117 may be connected to a load, and the other end of the wiring 112 and the wiring 117 may be connected to another circuit. Note that the transistor 125 can be omitted. 1 shows a configuration in which a transistor 124 and a transistor 125 are provided in the circuit shown in A). FIG.

[0057] As another example, Figs. 1(A), 1(B), 5(A), 5(B), 5(C), and 6( In the circuits shown in Figs. 6(A), 6(B), 6(C) and 7(A), In this way, a capacitor 126 is provided between the gate and the second terminal of the transistor 101. It is possible to provide a capacitor 12 between the gate and the second terminal of the transistor 124. 7B, a capacitor element 1 can be provided in the circuit shown in FIG. FIG. 2 is a diagram showing a configuration in which the switch 26 is provided.

[0058] The circuit 200 is not limited to the configuration shown in FIG. 1B and may have various other configurations. Another example of the configuration will be described. For example, as shown in FIG. The transistor 201 and the transistor 202 can be omitted. In circuit 200, as shown in FIG. 8B, the gate of transistor 203 is connected to node 1 2. In the circuit 200 shown in FIG. As shown in FIG. 1, the gate of the transistor 203 can be connected to the wiring 118. The wiring 118 is connected to a reverse signal (reverse clock signal) of the signal input to the wiring 111, or is out of phase with the signal input to the wiring 111 (for example, 180°, 90°, 45°, etc.) Therefore, the wiring 118 is a signal line, a clock signal line, However, the circuit 200 has a function as a clock signal line or an inverted clock signal line. As long as the function can be realized, the circuit 200 is not limited to the above-described configuration.

[0059] The above circuit is not limited to the timing chart shown in FIG. 2(A), and various other timing charts are also available. A timing chart can be used. An example of the timing chart will be described. For example, FIG. 9(A) As shown in FIG. 1, the signal input to the wiring 111 can be unbalanced. Therefore, in the period C, the potential of the wiring 115 is lower than the potential of the wiring 111 at the timing when the potential of the wiring 111 becomes V2. Since the timing when the potential becomes V1 can be delayed, the fall time of V112 can be As another example, as shown in FIG. The signal can be a multi-phase clock signal, which reduces power consumption. 9B shows a case where a four-phase clock signal is input to the wiring 111. FIG. 13 is a diagram showing an example of a timing chart.

[0060] The W / L (W: channel width, L: channel length) ratio of transistor 101 is 02. The W / L ratio of transistor 103, transistor 104, and transistor 105 is In particular, the W / L ratio of the transistor 101 is preferably larger than that of the transistor 104. It is preferably 1.5 times or more and 10 times or less of the W / L ratio. More preferably, it is 1.8 times. More preferably, it is 2 times or more and 4 times or less. The W / L ratio of the transistor 102 is preferably greater than the W / L ratio of the transistor 103 . This is because the load of the transistor 103 (e.g., the wiring 112) is larger than that of the transistor 102. This is because the load on the other end (e.g., node 11) is smaller. In particular, the W / The L ratio is preferably 1.5 times or more and 8 times or less than the W / L ratio of the transistor 103. More preferably, it is 2 times or more and 6 times or less. Even more preferably, it is 2 times or more and 5 times or less. In addition, the channel length of the transistor 102 and the channel length of the transistor 103 are At least one of them is preferably greater than the channel length of the transistor 105. , at least one of the channel length of the transistor 102 and the channel length of the transistor 103 Preferably, the first is greater than one and less than four times the channel length of the transistor 105. More preferably, it is 1.3 times or more and 3 times or less. Further preferably, it is 1.8 times or more. , less than 2.5 times.

[0061] The width of the wiring 111 is the channel width of the transistor 101, the channel width of the transistor 102, It is preferable that the width of the MOSFET is smaller than at least one of the width of the MOSFET and the channel width of the transistor 104. In addition, the width of the wiring 111 is larger than at least a part of the width of the wiring 116. It is preferred that the compound contains

[0062] The circuit described in this embodiment includes the following configuration as one embodiment of the present invention. A semiconductor device including a resistor 101, a transistor 102, and a circuit 200 (FIG. 10A) A semiconductor device including a transistor 101, a transistor 103, and a circuit 200. (See FIG. 10B). Transistor 101, transistor 102, and transistor 1 A semiconductor device including a transistor 101 and a circuit 200 (see FIG. 10C). A semiconductor device including a transistor 102, a transistor 104, and a circuit 200 (FIG. 10 (See (D)).

[0063] (Embodiment 2) In this embodiment, a shift register circuit according to a display device according to one embodiment of the present invention will be described. The shift register circuit of this embodiment includes the circuit described in the first embodiment. In addition, the shift register circuit of the present embodiment can be used in conjunction with a gate driver circuit and / or Alternatively, the present invention can be used in a driver circuit of a display device, such as a source driver circuit.

[0064] FIG. 11 shows N (N is a natural number) circuits 301 (referred to as circuits 301_1 to 301_N). 3 is a diagram showing a configuration example of a shift register circuit having the circuit 301 according to the first embodiment. FIG. 11 shows a circuit 301 shown in FIG. An example of when the circuit is used is shown below.

[0065] The connection relationship of the shift register circuit shown in FIG. 11 will be described. The circuit 301_i is connected to the wiring 31. 1_i, wiring 311_i−1, wiring 311_i+1, one of wiring 312 and wiring 313, and the wiring 314. Specifically, in the circuit 301_i, the wiring 112 is 311_i, the wiring 114 is connected to the wiring 311_i-1, and the wiring 115 is connected to the wiring 311_i+1, and the wiring 111 is connected to one of the wirings 312 and 313. The wiring 113 is connected to a wiring 314. When the line 312 is connected, the wiring 111 is connected to a wiring 313. Note that in the circuit 301_1, the wiring 114 is connected to a wiring 315. The circuit 301_N is different from the circuit 301_i in that the wiring 115 is The output terminal of the MEE circuit (represented as circuit 301_D) is connected to the circuit 301_i. Note that the circuit 301_D can have a structure similar to that of the circuit 301. In addition, a part of the configuration of the circuit 301 can be used.

[0066] The operation of the shift register circuit shown in FIG. 11 will be described with reference to the timing chart shown in FIG. This will be explained in light of the above.

[0067] The operation of the circuit 301_i will be described as an example. First, the potential of the wiring 311_i-1 (potential V3 11_i-1) becomes V1. Then, the circuit 301_i in the first embodiment The operation in the period A described above is performed, and the potential of the wiring 311_i (represented as potential V311_i) Then, the potential of the wiring 312 (denoted as potential V312) and the potential of the wiring 313 (represented as potential V313) is inverted. Then, the circuit 301_i in the first embodiment The operation in the period B described above is performed, and the potential of the wiring 311_i becomes V1. The potential of the wiring 312 and the potential of the wiring 313 are inverted, and the potential of the wiring 311_i+1 (potential V311 Then, the circuit 301_i becomes V1 as described in the first embodiment. The operation in the period C is performed, and the potential of the wiring 311_i becomes V2. 1_i is the same as that described in the first embodiment until the potential of the wiring 311_i-1 becomes V1 again. The operation in the period D is performed, and the potential of the wiring 311_i remains at V2. When the potential of the wiring 315 (shown as potential V315) becomes V1, the line 301_1 The circuit 301_N differs from the circuit 301_i in that it performs the same operation as the circuit 301_i. When the output signal of the circuit 301_i becomes V1, the operation in the period C is performed in the circuit 301_i. become.

[0068] As described above, the potential of the wiring 311_1 (denoted as potential V311_1) is changed to the potential of the wiring 311_N. The potential (represented as potential V311_N) can be set to V1 in turn. By being configured with the circuits described above, the shift register circuit shown in FIG. The same advantages as those of the circuit described in the first embodiment can be obtained.

[0069] The wiring 311 (one of the wirings 311_1 to 311_N) is provided with a shift register circuit. An output signal from the line 312 is input to the line 313. A clock signal is input to the line 313. is a clock signal having a different phase from the clock signal input to the wiring 312, or An inverted signal of the clock signal input to terminal 2 is input to terminal 314. A voltage V2 is supplied to wiring 314. A start signal is input to the wiring 315.

[0070] The wiring 311 transmits the output signal of the shift register circuit to a pixel circuit or a circuit such as a demultiplexer. The wiring 31 is a wiring for transmitting a signal and functions as a signal line or a gate signal line. 2 and wiring 313 are connected from an external circuit such as a controller to the shift register circuit of this embodiment. It is a wiring for transmitting signals such as clock signals, and is used as a signal line or clock signal line. The wiring 314 is a wiring for connecting an external circuit such as a power supply circuit to the shift register of this embodiment. This is the wiring for supplying a power supply voltage such as voltage V2 to the inverter circuit. It is also called a power supply line, a negative power supply line, or The wiring 315 functions as a ground line. A wiring for transmitting a start signal to the shift register circuit of the embodiment, and a signal line It has the function of

[0071] (Embodiment 3) In this embodiment, an example of a transistor included in the circuit described in embodiment 1 or 2 is Specifically, a transistor in which a channel region is formed of an oxide semiconductor will be described. An example of the structure and manufacturing process of the transistor will be described.

[0072] As for oxide semiconductors, the In-Sn-Ga-Zn-O oxide semiconductor, which is a quaternary metal oxide, is used. Conductors, ternary metal oxides such as In-Ga-Zn-O oxide semiconductors, In-Sn-Zn -O-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based oxide semiconductors Semiconductors made of Al-Ga-Zn-O oxides, or Sn-Al-Zn-O oxides In-Zn-O-based oxide semiconductors, which are binary metal oxides, and Sn-Zn- O-based oxide semiconductors, Al-Zn-O-based oxide semiconductors, Zn-Mg-O-based oxide semiconductors, S n-Mg-O oxide semiconductor, In-Mg-O oxide semiconductor, In-O oxide semiconductor The oxide semiconductors used are Sn-O-based oxide semiconductors or Zn-O-based oxide semiconductors. In addition, the oxide semiconductor may include SiO 2 An oxide semiconductor to which .beta. is added may be used.

[0073] In addition, the oxide semiconductor is InMO 3 (ZnO) m (m>0 and m is not a natural number) The following materials can be used, where M is selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, Ga and Co. 3 (ZnO) m (m>0 and m is natural Among oxide semiconductors with a structure represented by the formula (not a number), oxide semiconductors with a structure containing Ga as M are The conductor is called an In-Ga-Zn-O oxide semiconductor, and the thin film is called an In-Ga-Zn-O system. In addition, the oxide represented by In-Ga-Zn-O in this specification is The semiconductor material is InGaO 3 (ZnO) m (m>0 and m is not a natural number), and m The fact that is not a natural number can be confirmed using ICP-MS analysis or RBS analysis. .

[0074] FIG. 1 shows one embodiment of a method for manufacturing a transistor in which a channel region is formed using an oxide semiconductor. This will be explained with reference to 13.

[0075] 13A to 13D are diagrams illustrating an example of a cross-sectional structure of a transistor. The transistor 410 shown in FIG. 1 is a type of bottom gate structure called a channel etch type. be.

[0076] Although a transistor having a single gate structure is shown in FIG. 13D, The transistor may have a multi-gate structure having a plurality of channel regions.

[0077] Hereinafter, a process for fabricating a transistor 410 on a substrate 400 will be described with reference to FIGS. 13(A) to 13(D). Explain the process.

[0078] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 411 is formed through a process.

[0079] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In either case, it is necessary to have heat resistance sufficient to withstand the subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborosilicate glass can be used. In addition, if the temperature of the subsequent heat treatment is high, a glass substrate with a distortion point of 730°C or higher can be used. It is good to use.

[0080] An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 411. It has a function of preventing the diffusion of impurity elements from the substrate 400, and is a silicon nitride film, a silicon oxide film, The insulating layer is made of one or more films selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It can be formed in a laminated structure.

[0081] The gate electrode layer 411 may be formed of any of molybdenum, titanium, chromium, tantalum, tungsten, Metallic materials such as aluminum, copper, neodymium, and scandium, or alloys containing these as main components The material can be used to form a single layer or a laminate.

[0082] Next, the gate insulating layer 402 is formed over the gate electrode layer 411 .

[0083] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. The gate insulating layer may be formed of a single layer or a stacked layer. High-k materials such as hafnium (HfOx) and tantalum oxide (TaOx) can also be used. The thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. For example, the first gate insulating layer has a thickness of 50 nm or more and 200 nm or less, and the first gate insulating layer has a thickness of 50 nm or more and 200 nm or less. A second gate insulating layer having a thickness of 5 nm to 300 nm is laminated on the edge layer.

[0084] In this embodiment, the gate insulating layer 402 is formed by a plasma CVD method to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0085] In addition, a silicon oxynitride layer is formed as the gate insulating layer 402 by using a high density plasma device. Here, the high-density plasma device is 1×10 11 / cm 3 Plasma density above For example, a microwave power of 3kW to 6kW can be applied to the device. The insulating layer formed by the high density plasma device is Since it is possible to form a film of a constant thickness, it has excellent step coverage. The insulating layer obtained by this arrangement can be precisely controlled to a thin film thickness.

[0086] The insulating layer obtained by the high-density plasma device is different from that obtained by the conventional parallel plate type PCVD device. The film quality is significantly different from that of the insulating layer, and the etching rates are compared using the same etchant. In comparison, the insulating layer obtained by the parallel plate PCVD equipment is 10% or more The etching rate is slower than 0.0%, and the insulating layer obtained by the high-density plasma device can be said to be a dense layer. do.

[0087] Note that the oxide semiconductor (highly purified oxide) to be made i-type or substantially i-type in a later process Since semiconductors are extremely sensitive to interface states and interface charges, the interface with the gate insulating layer Therefore, the gate insulating layer (GI) in contact with the highly purified oxide semiconductor must be highly Therefore, high-density plasma CVD using microwaves (2.45GHz) is This is preferable because it allows the formation of a dense, high-quality insulating layer with high dielectric strength. The close contact between the semiconductor and the high-quality gate insulating layer reduces interface states and improves interface characteristics. It goes without saying that the film quality as a gate insulating layer is excellent. It is important to reduce the interface state density with the oxide semiconductor and form a good interface. It is.

[0088] Next, an oxide semiconductor film 43 having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 402. The oxide semiconductor film 430 is formed of an In-Ga-Zn-O system or an In-Zn-O system. In this embodiment, the oxide semiconductor film 430 is an In- A film is formed by sputtering using a Ga-Zn-O oxide semiconductor target. The cross-sectional view in FIG. 13A corresponds to the cross-sectional view in FIG. 13A. The reaction is carried out under an atmosphere of noble gas (typically argon), oxygen, or a mixture of noble gas (typically argon) and oxygen. It can be formed by sputtering in a mixed atmosphere.

[0089] Here, a metal oxide target containing In, Ga, and Zn (In 2 O3 :Ga 2 O 3 ZnO=1:1:1 [molar ratio]) was used, and the distance between the substrate and the target was set at 10 0 mm, pressure 0.2 Pa, direct current (DC) power supply 0.5 kW, argon and oxygen (argon: The film is formed in an atmosphere of oxygen = 30sccm:20sccm (oxygen flow rate ratio 40%). By using a pulsed direct current (DC) power supply, the amount of powdery material generated during film formation can be reduced, and the film thickness distribution can be improved. The thickness of the In-Ga-Zn-O film is preferably 5 nm to 200 nm. In this embodiment, an In—Ga—Zn—O-based metal oxide film is used as the oxide semiconductor film. A 20 nm thick In-Ga-Zn-O film was formed by sputtering using an In-Ga-Zn-O target. Next, the oxide semiconductor film 430 is formed into island-shaped oxide films by a second photolithography process. The resulting semiconductor layer is then processed into a compound semiconductor layer.

[0090] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and an oxide semiconductor is The layer was heated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to air. Therefore, the intrusion of water or hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 431 is obtained (FIG. 13(B)).

[0091] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Annealing) equipment, LRTA (Lamp Ra pid Thermal Annealing (RTA) equipment The LRTA device is a halogen laser annealing (HLTA) device. lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure nato The exposure to light (electromagnetic waves) emitted from lamps such as lithium lamps and high-pressure mercury lamps can cause The GRTA device is a device that uses high-temperature gas to heat materials. The gases include rare gases such as argon, or nitrogen, which can be treated by heat treatment. An inert gas that does not react with the material is used.

[0092] For example, the first heat treatment is performed by subjecting the substrate to a base in an inert gas heated to a high temperature of 650° C. to 700° C. The plate is moved and placed in the oven, heated for a few minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. Using GRTA, high-temperature heat treatment can be performed in a short time. become.

[0093] The atmosphere of the first heat treatment may be nitrogen, helium, neon, argon, or the like. It is preferable that the rare gas and dry air do not contain water, hydrogen, etc. The purity of nitrogen or rare gas such as helium, neon, or argon introduced into the device should be 6N (99 .9999%) or more, preferably 7N (99.99999%) or more (i.e. impurity concentration It is preferable to set the concentration to 1 ppm or less, and more preferably 0.1 ppm or less.

[0094] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 430 may be subjected to the first heat treatment. In that case, the semiconductor film 430 may be subjected to the second heat treatment after the first heat treatment. The substrate is then removed from the apparatus and subjected to a second photolithography process.

[0095] In addition, in the case where an opening is formed in the gate insulating layer 402, the process is performed in the oxide semiconductor film 430. This may be carried out before or after the dehydration or dehydrogenation treatment.

[0096] Note that the etching of the oxide semiconductor film 430 here is not limited to wet etching. Dry etching may also be used.

[0097] The etching gas for the oxide semiconductor film 430 used in the dry etching is a chlorine-containing gas. Gas (e.g., chlorine (Cl 2 ), boron trichloride (BCl 3 ) etc.) are preferred.

[0098] The etching solution for the oxide semiconductor film 430 used in the wet etching is phosphoric acid and acetic acid. and nitric acid, ammonia hydrogen peroxide solution (31% by weight hydrogen peroxide solution: 28% by weight ammonia hydrogen peroxide solution) Water: water = 5: 2: 2) can be used. In addition, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0099] Next, a metal conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer 431. The metal conductive film may be formed by sputtering or vacuum deposition. Aluminum (Al), Chromium (Cr), Copper (Cu), Tantalum (Ta), Titanium (Ti) , Molybdenum (Mo), Tungsten (W), Neodymium (Nd), Scandium (Sc) An element selected from the above, an alloy containing the above elements, or a combination of the above elements. Also, a nitride film of the above elements may be used. ), magnesium (Mg), zirconium (Zr), beryllium (Be), yttrium The metal conductive film may be made of one or more materials selected from (Y). The insulating film may have a single layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon A single-layer structure of titanium film, a two-layer structure of titanium film on aluminum film, and a titanium film on aluminum film Examples include a three-layer structure in which a titanium film is laminated on an aluminum film and then a titanium film is laminated on an aluminum film. can be.

[0100] When a heat treatment is performed after the formation of the metal conductive film, the metal conductive film is required to have heat resistance sufficient to withstand the heat treatment. It is preferable to have the

[0101] A resist mask is formed on the metal conductive film by a third photolithography process. After etching to form the source electrode layer 415a and the drain electrode layer 415b, The mask is removed (see FIG. 13(C)).

[0102] In this embodiment, a titanium film is used as the metal conductive film, and In is used as the oxide semiconductor layer 431. -Ga-Zn-O oxide was used, and ammonia hydrogen peroxide (ammonia, A mixture of water and hydrogen peroxide is used.

[0103] Note that in the third photolithography step, the oxide semiconductor layer 431 is only partially etched. In some cases, the oxide semiconductor layer is formed by etching so as to have a groove (a depression).

[0104] In order to reduce the number of photomasks and steps used in the photolithography process, The resist pattern is formed by a multi-tone mask, which is an exposure mask that allows the light to be projected at multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by ashing. This allows for multiple etching processes to be performed to create different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0105] Next, nitrous oxide (N 2 O), nitrogen (N 2 ), or argon (Ar) gas. The surface of the oxide semiconductor layer exposed by the plasma treatment is In addition, a mixture of oxygen and argon gas is used for plasma treatment. The theory may also be carried out.

[0106] After the plasma treatment, a metal oxide film is placed in contact with part of the oxide semiconductor layer 431 without being exposed to air. An oxide insulating layer 416 serving as a protective insulating film is formed.

[0107] The oxide insulating layer 416 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The layer 416 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the layer 416 . When hydrogen is contained in the oxide insulating layer 416, the hydrogen enters the oxide semiconductor layer and is oxidized. The back channel of the compound semiconductor layer 431 becomes low resistance (N-type), and a parasitic channel is formed. Therefore, the oxide insulating layer 416 is formed so as to contain as little hydrogen as possible. It is important that no hydrogen is used in the membrane process.

[0108] In this embodiment, a silicon oxide film having a thickness of 200 nm is sputtered as the oxide insulating layer 416. The substrate temperature during film formation should be between room temperature and 300°C. In the embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas (typically In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen, The target may be a silicon oxide target or a For example, a silicon target can be used to oxidize the acid. The silicon oxide film can be formed by sputtering in a nitrogen atmosphere.

[0109] Then, a second heating step is performed under an inert gas atmosphere, a dry air atmosphere, or an oxygen gas atmosphere. (preferably at 200° C. or higher and 400° C. or lower, for example at 250° C. or higher and 350° C. or lower) For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. When the heat treatment is performed, part of the oxide semiconductor layer (channel region) is in contact with the oxide insulating layer 416. As a result, oxygen is supplied to a part (channel region) of the oxide semiconductor layer.

[0110] Through the above steps, the oxide semiconductor layer is dehydrated or dehydrogenated. After the heat treatment, a part of the oxide semiconductor layer (channel region) is selectively made into an oxygen-excess state. Through the above steps, the transistor 410 is formed.

[0111] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the heating temperature may be increased from room temperature to 100°C or more and 200°C or less. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times.

[0112] A protective insulating layer may be further formed on the oxide insulating layer 416. For example, a protective insulating layer may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is used to form a protective insulating layer. This is a preferred method. The protective insulating layer is resistant to moisture, hydrogen ions, and OH - Contains impurities such as First, inorganic insulating films are used to block these substances from entering from the outside, and silicon nitride films and nitride films are used. An aluminum film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used. In this example, a protective insulating layer 403 is formed using a silicon nitride film (FIG. 13(D)). )reference).

[0113] In this embodiment, the oxide semiconductor layer of the transistor 410 contains hydrogen as an n-type impurity. The oxide semiconductor is then subjected to high-temperature treatment so that impurities other than the main component of the oxide semiconductor are not contained as much as possible. It is purified to make it true (type i) or substantially true. That is, instead of adding impurities to make it i-type, impurities such as hydrogen and water were removed as much as possible. It is characterized by being highly purified i-type (intrinsic semiconductor) or close to it. By doing so, the Fermi level (E f ) to the intrinsic Fermi level (E i to the same level as It is possible.

[0114] The band gap (Eg) of oxide semiconductors is 3.15 eV and the electron affinity (χ) is 4. The source and drain electrode layers are made of titanium (Ti The work function of the oxide semiconductor is approximately equal to the electron affinity (χ) of the oxide semiconductor. At the interface between the semiconductor and the semiconductor, no Schottky barrier is formed for electrons.

[0115] For example, if the channel width W of a transistor is 1×10 4 μm and the channel length L is 3 μm. Even if the off-state current is less than 10 -13 A or less, and the S value is 0.1V / dec ade (gate insulating layer thickness 100 nm).

[0116] In this way, it is possible to highly purify the oxide semiconductor so that it contains as few impurities as possible other than the main component. As a result, the transistor 410 can operate satisfactorily.

[0117] In order to suppress fluctuations in electrical characteristics, the oxide semiconductor described above is made to be free of hydrogen, moisture, and other factors that cause fluctuations. Impurities such as hydroxyl groups or hydrides (also called hydrogen compounds) are intentionally excluded, and impurities The oxygen, which is the main component of the oxide semiconductor, is reduced at the same time by the removal process. Since the oxide semiconductor is supplied to the semiconductor substrate, it is highly purified and electrically i-type (intrinsic) oxide semiconductor.

[0118] Therefore, the less hydrogen there is in the oxide semiconductor, the better. There are very few carriers in semiconductors (close to zero), with a carrier density of 1×10 12 / c m 3 Less than 1 x 10 11 / cm 3 That is, the carrier of the oxide semiconductor layer is less than 1000 nm. The carrier density is close to zero. Since there are very few carriers in the oxide semiconductor layer, In a transistor, the off-state current can be reduced. The smaller the off-state current, the better. The transistor has a current value of 100 aA or less per 1 μm of channel width (w). Preferably, it is 10 zA (zeptoamperes) or less, and more preferably, it is 1 zA or less. In addition, there is no pn junction and no hot carrier degradation, so the electrical characteristics of the transistors are Gender is not affected.

[0119] In this way, hydrogen contained in the oxide semiconductor layer is thoroughly removed, resulting in a highly purified oxide semiconductor layer. A transistor that uses an oxide semiconductor for the channel region has an extremely small off-state current. In other words, when the transistor is in a non-conducting state, the oxide semiconductor layer can be regarded as an insulator. On the other hand, the oxide semiconductor layer can be used to control the conduction state of a transistor. In this case, it is expected that the current supply capacity will be higher than that of a semiconductor layer formed of amorphous silicon. can be done.

[0120] In addition, in the case of a transistor including low-temperature polysilicon, The off-current of the transistor is estimated to be about 10,000 times larger than that of the transistor. Therefore, in the case of a transistor having an oxide semiconductor, low-temperature polysilicon is used. When the storage capacitance is the same (about 0.1 pF) compared to the transistors provided, the voltage is The duration can be extended by up to 10,000 times. For example, a video display can be made at 60 frames per second. When using a frame, the retention period for one signal write is 10,000 times longer, about 160 seconds. Even with a small number of image signal writes, still images can be displayed on the display unit. It is possible to provide guidance.

[0121] (Embodiment 4) In this embodiment, an example of a display device according to one embodiment of the present invention will be described.

[0122] FIG. 14A illustrates an example of a display device in which the shift register circuit of the second embodiment is used. The display device shown in FIG. 14A includes a timing controller 5360 and a source driver circuit. A gate driver circuit 5363_1 and a gate driver circuit 5363_2 are provided. The pixel portion 5364 includes a driver circuit 5361 for driving a source driver. A plurality of source signal lines 5371 are extended from the driver circuit 5362, and the gate driver A plurality of gate signal lines 5372 are connected to the circuit 5363_1 and the gate driver circuit 5363_2. A plurality of source signal lines 5371 and a plurality of gate signal lines 5372 are arranged. In each of the intersecting regions, pixels 5367 are arranged in a matrix.

[0123] The display device may include a lighting device and a control circuit for the lighting device. 5367 may have a liquid crystal element.

[0124] In addition, one of the gate driver circuit 5363_1 and the gate driver circuit 5363_2 is omitted. It can be omitted.

[0125] The timing controller 5360 supplies a control signal to the drive circuit 5361. 5361. For example, a timing controller The controller 5360 supplies a start signal SSP, a clock signal control signals such as SCK, inverted clock signal SCKB, video signal DATA, and latch signal LAT. The timing controller 5360 also supplies a gate driver circuit 5363 _1 and the gate driver circuit 5363_2 are supplied with a start signal GSP and a clock signal GCK , the inverted clock signal GCKB, and other control signals.

[0126] The source driver circuit 5362 outputs video signals to a plurality of source signal lines 5371. The image forming circuit is a circuit having a function of displaying an image and can be called a driver circuit or a signal line driver circuit. The image signal is input to the pixel 5367, and the display element constituting the pixel 5367 responds to the image signal. The resulting gradation is the same.

[0127] The gate driver circuit 5363_1 and the gate driver circuit 5363_2 drive the pixels 5 367 in sequence, and is called a driver circuit or a scanning line driver circuit. The timing for selecting the pixel 5367 is controlled by the gate driver circuit 5363. _1 and the gate driver circuit 5363_2 output a gate signal to the gate signal line 5372. This is done by:

[0128] In the display device shown in FIG. 14A, The driver circuit 5363_2 can be formed on the same substrate as the pixel portion 5364. 14(B) shows a gate driver circuit on the same substrate as the pixel portion 5364 (shown as substrate 5380). 5 shows an example in which a circuit 5363_1 and a gate driver circuit 5363_2 are formed. The substrate 5380 and an external circuit are connected via a terminal 5381 .

[0129] In the display device shown in FIG. 14A, a part of the source driver circuit 5362 (for example For example, switches, multiplexers, shift register circuits, decoder circuits, inverter circuits, A buffer circuit and / or a level shifter circuit, etc., are formed on the same substrate as the pixel portion 5364. FIG. 14C shows a pixel region 5364 on the same substrate (referred to as a substrate 5380). , the gate driver circuit 5363_1 and the gate driver circuit 5363_2 and the source driver A part (denoted as 5362a) of the source driver circuit 5362 is formed. Another portion (designated 5362b) is shown formed on a substrate different from substrate 5380. vinegar.

[0130] The shift register described in the second embodiment may be used as a driving circuit or a part of the driving circuit of the display device. In particular, the driver circuit of the display device may be the transistor circuit described in the third embodiment. When the transistor is used, the shift register circuit described in the second embodiment is used. By doing so, it is possible to improve the driving capability of the driving circuit. Alternatively, the resolution of the display device can be improved. Since the layout area of ​​the circuit can be reduced, the frame of the display device can be made smaller. can be done.

[0131] (Embodiment 5) In this embodiment, an example of an electronic device will be described.

[0132] 15(A) to 15(H) and 16(A) to 16(D) are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, and an LED. A lamp 5004, an operation key 5005 (including a power switch or an operation switch), a connection terminal Child 5006, sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (has the function of measuring flow rate, humidity, gradient, vibration, odor or infrared rays), microphone 5008, etc.

[0133] FIG. 15A shows a mobile computer, which includes, in addition to the above, a switch 5009, The portable terminal 5010 may have an infrared port 5010. FIG. A type of image reproducing device (for example, a DVD reproducing device) that, in addition to the above, also has a second display 15C shows a goog In addition to the above, the display includes a second display unit 5002, a support unit 5012, The game machine may have earphones 5013, etc. FIG. 15(D) shows a portable game machine. In addition to the above, the device may have a recording medium reading unit 5011, etc. In addition to the above, the projector includes a light source 5033, a projection lens 5034, etc. FIG. 15(F) shows a portable gaming machine, which, in addition to the above, has a second display unit. 15G shows a television receiver 5002, a recording medium reading unit 5011, etc. In addition to the above, the image processing device may include a tuner, an image processing unit, etc. 15(H) is a portable television receiver, capable of transmitting and receiving signals in addition to the above. FIG. 16(A) shows a display, and the above-mentioned In addition to the above, a support stand 5018 and the like can be provided. FIG. 16(B) shows a camera. In addition to the above, an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 16(C) is a computer, In addition, there is a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 16(D) shows a mobile phone, which includes the above-mentioned 2. Antennas, for One Seg (one segment partial reception service for mobile phones and mobile terminals) tuners, etc.

[0134] The electronic devices shown in FIGS. 15(A) to 15(H) and 16(A) to 16(D) are For example, various information (still images, videos, text images, etc.) Function to display on the display unit, touch panel function, calendar, date or time display, etc. Functions, functions to control processing by various software (programs), wireless communication functions, A function to connect to various computer networks using wireless communication functions, A function to transmit or receive various data using a program recorded on a recording medium The data can be read out and displayed on the display unit. In electronic devices with displays, one display unit is used primarily to display image information, and another A function that mainly displays text information on one display unit, or a function that takes parallax into account on multiple displays By displaying an image, it is possible to have a function of displaying a stereoscopic image. In electronic devices having an image receiving unit, the functions of taking still images, taking videos, and The function to automatically or manually correct the captured image, and to store the captured image on a recording medium (external or in the camera) It can have functions such as storing the captured image on a built-in memory and displaying the captured image on the display unit. Note that the electronic devices shown in FIGS. The functions that can be possessed by the are not limited to these, and the function can have various functions.

[0135] FIG. 16(E) shows an example in which a display device is integrated with a building. The device includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 50 25, etc. The display device is wall-mounted and integrated with the building, and requires a large installation space. It can be installed without the need for

[0136] FIG. 16(F) shows another example in which a display device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027, and the bather can see the The display panel 5026 becomes viewable.

[0137] In this embodiment, a wall and a unit bath are used as examples of structures. The manner in which the display device is installed is not limited to this, and the display device can be installed in various buildings.

[0138] Next, an example in which the display device is provided integrally with a moving object will be described.

[0139] FIG. 16G is a diagram showing an example in which the display device is installed in an automobile. 028 is attached to the body 5029 of the automobile, and is connected to the body of the automobile or the vehicle. The information input can be displayed on demand. It may be possible.

[0140] FIG. 16(H) is a diagram showing an example in which a display device is integrated into a passenger airplane. FIG. 16(H) shows a passenger airplane with a display panel 5031 installed on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 503. 0 and is attached to each other via a hinge portion 5032, and the expansion and contraction of the hinge portion 5032 causes The passenger can then view the display panel 5031. The display panel 5031 is operated by the passenger. This allows the device to display information.

[0141] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorail, etc.) They can be installed on a variety of things, including buildings, railways, ships, etc.

[0142] The electronic device described in this embodiment mode preferably includes the shift register circuit described in Embodiment 2. In particular, the shift register of the second embodiment is preferably used as a circuit for driving a display unit of an electronic device. It is preferable to mount a shift register circuit in the electronic device. By incorporating it as a circuit to drive the display unit, the area of ​​the drive circuit can be reduced. This allows the display unit to be enlarged, and the resolution of the display unit to be improved. . [Explanation of symbols]

[0143] 11 Nodes 12 nodes 21 Nodes 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 118 Wiring 121 Transistor 122 Transistor 123 Transistor 124 Transistor 125 Transistor 126 Capacitive element 200 circuits 201 Transistor 202 Transistor 203 Transistor 204 Transistor 301 Circuit 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Wiring 400 Substrates 402 Gate insulating layer 403 Protective insulation layer 410 Transistor 411 Gate electrode layer 415a Source electrode layer 415b Drain electrode layer 416 Oxide insulating layer 430 Oxide Semiconductor Film 431 Oxide Semiconductor Layer 5000 cabinet 5001 Display section 5002 2nd display section 5003 Speaker 5004 LED Lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Reader / Writer 5022 Case 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit Bath 5028 Display Panel 5029 Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5360 Timing Controller 5361 Circuit 5362 Circuit 5362a Circuit 5362b circuit 5363_1 Circuit 5363_2 Circuit 5364 Pixel section 5367 pixels 5371 Source signal line 5372 Gate signal line 5380 PCB 5381 Terminal

Claims

1. The transistor includes first to twelfth transistors, one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the first signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the first wiring; the other of the source and the drain of the tenth transistor is always electrically connected to the gate of the eighth transistor; the gate of the tenth transistor is always electrically connected to the first wiring; one of the source and the drain of the eleventh transistor is always electrically connected to the gate of the eighth transistor; the other of the source and the drain of the eleventh transistor is always electrically connected to the power supply line; a gate of the eleventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the twelfth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the twelfth transistor is always electrically connected to the power supply line; the gate of the twelfth transistor is always electrically connected to a second signal line; when the other of the source or the drain of the second transistor is in a conductive state with the gate signal line at least via a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line at least via the channel formation region of the second transistor, a potential at which the first transistor is turned on, a potential at which the third transistor is turned on, a potential at which the ninth transistor is turned on, and a potential at which the eleventh transistor is turned on are input to the gates of the first transistor, the third transistor, the ninth transistor, and the eleventh transistor via at least a channel formation region of the sixth transistor;

2. The transistor includes first to twelfth transistors, one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the first signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the first wiring; the other of the source and the drain of the tenth transistor is always electrically connected to the gate of the eighth transistor; the gate of the tenth transistor is always electrically connected to the first wiring; one of the source and the drain of the eleventh transistor is always electrically connected to the gate of the eighth transistor; the other of the source and the drain of the eleventh transistor is always electrically connected to the power supply line; a gate of the eleventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the twelfth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the twelfth transistor is always electrically connected to the power supply line; the gate of the twelfth transistor is always electrically connected to a second signal line; when the other of the source or the drain of the second transistor is in a conductive state with the gate signal line at least via a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line at least via the channel formation region of the second transistor, when the other of the source or the drain of the sixth transistor is in a state of conduction with the gate of the first transistor, the gate of the third transistor, the gate of the ninth transistor, and the gate of the eleventh transistor via at least a channel formation region of the sixth transistor, a potential at which the first transistor is turned on, a potential at which the third transistor is turned on, a potential at which the ninth transistor is turned on, and a potential at which the eleventh transistor is turned on are input to the gate of the first transistor, the gate of the third transistor, the gate of the ninth transistor, and the gate of the eleventh transistor via at least a channel formation region of the sixth transistor, a W / L ratio of the first transistor (where W is a channel width) is greater than a W / L ratio of the second transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the fifth transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the sixth transistor; A semiconductor device in which a W / L ratio of the first transistor is greater than a W / L ratio of the seventh transistor.

3. The transistor includes first to twelfth transistors, one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the first signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the first wiring; the other of the source and the drain of the tenth transistor is always electrically connected to the gate of the eighth transistor; the gate of the tenth transistor is always electrically connected to the first wiring; one of the source and the drain of the eleventh transistor is always electrically connected to the gate of the eighth transistor; the other of the source and the drain of the eleventh transistor is always electrically connected to the power supply line; a gate of the eleventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the twelfth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the twelfth transistor is always electrically connected to the power supply line; the gate of the twelfth transistor is always electrically connected to a second signal line; when the other of the source or the drain of the second transistor is in a conductive state with the gate signal line at least via a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line at least via the channel formation region of the second transistor, the clock signal line has a region whose wiring width is smaller than a channel width of the first transistor, the clock signal line has a region whose wiring width is smaller than a channel width of the second transistor, the clock signal line has a region whose wiring width is smaller than a channel width of the sixth transistor, The clock signal line has a region having a wiring width larger than that of the first wiring.

4. The transistor includes first to twelfth transistors, one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the first signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the first wiring; the other of the source and the drain of the tenth transistor is always electrically connected to the gate of the eighth transistor; the gate of the tenth transistor is always electrically connected to the first wiring; one of the source and the drain of the eleventh transistor is always electrically connected to the gate of the eighth transistor; the other of the source and the drain of the eleventh transistor is always electrically connected to the power supply line; a gate of the eleventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the twelfth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the twelfth transistor is always electrically connected to the power supply line; the gate of the twelfth transistor is always electrically connected to a second signal line; when the other of the source or the drain of the second transistor is in a conductive state with the gate signal line at least via a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line at least via the channel formation region of the second transistor, a W / L ratio of the first transistor (where W is a channel width) is greater than a W / L ratio of the second transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the fifth transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the sixth transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the seventh transistor; the clock signal line has a region whose wiring width is smaller than a channel width of the first transistor, the clock signal line has a region whose wiring width is smaller than a channel width of the second transistor, the clock signal line has a region whose wiring width is smaller than a channel width of the sixth transistor, The clock signal line has a region having a wiring width larger than that of the first wiring.

Images