Method for screening non-volatile memory cells - Patents.com

Abstract

A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and weak programming steps, screening any memory cells that exhibit a read current below a margin read current threshold M1 during the first read operation, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking step, and screening any memory cells that exhibit a read current below the margin read current threshold M1 during the second read operation.

Description

[Technical field]

[0001] (Related Applications) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 330,650, filed April 13, 2022, and U.S. Patent Application No. 17 / 858,185, filed July 6, 2022.

[0002] FIELD OF THEINVENTION The present disclosure relates to a method for screening non-volatile memory cells for data retention. [Background technology]

[0003] Non-volatile memory cells having a floating gate for storing charge are well known in the art. Referring to FIG. 1, a cross-sectional view of a conventional non-volatile memory cell 10 is shown. The memory cell 10 comprises a semiconductor substrate 12 of a first conductivity type, such as P-type. A first region 14 (also referred to herein as a drain or drain region) of a second conductivity type, such as N-type, is at or near the surface of the substrate 12. A second region 16 (also referred to herein as a source or source region), also of the second conductivity type, is spaced apart from the first region 14. The portion of the substrate 10 between the first region 14 and the second region 16 is a channel region 18. A word line gate (also referred to herein as a select gate) 20, which may be fabricated from polysilicon, is positioned above a first portion of the channel region 18. The word line gate 20 is spaced apart from the channel region 18 by an insulating layer 22 (e.g., silicon dioxide). A floating gate 24 (which may also be made of polysilicon) is directly adjacent to and spaced apart from the word line gate 20 and is positioned above another portion of the channel region 18. The floating gate 24 is separated from the channel region 18 by another insulating layer 30 (e.g., silicon dioxide). A control gate (also called a coupling gate) 26 (which may also be made of polysilicon) is positioned above the floating gate 24 and insulated therefrom by another insulating layer 32 (so that a voltage applied to the control gate 26 is capacitively coupled to the floating gate 24). An erase gate 28 (which may also be made of polysilicon) is on another side of the floating gate 24 and spaced apart therefrom. The erase gate 28 is positioned above and insulated therefrom the second region 16. The erase gate 28 is also directly adjacent to but spaced apart from the control gate 26. In operation of the memory cell 10, the charge stored on the floating gate 24 (or the absence of charge on the floating gate 24) controls the flow of current between the first region 14 and the second region 16 through the channel region 18. When the floating gate 24 has a charge (i.e., electrons) (i.e., the floating gate is negatively charged), the floating gate 24 is considered to be programmed.The floating gate 24 is considered to be erased when there is little or no electronic charge on the floating gate 24 (i.e., the floating gate is considered to be positively charged). The charge state of the floating gate 24 controls the conductivity of that portion of the channel region 18 that is underneath the floating gate 24, and the voltage applied to the word line gate 20 controls the conductivity of that portion of the channel region 18 that is underneath the word line gate 20.

[0004] The memory cell 10 operates as follows: During a programming operation, during which (electron) charge is stored on the floating gate 24, a first positive voltage is applied to the word line gate 20, causing the portion of the channel region 18 below the word line gate 20 to become conductive. A second positive voltage is applied to the control gate 26. A third positive voltage is applied to the second region 16. A current is applied to the first region 14. Electrons are attracted to the positive voltage of the second region 16. As they approach the floating gate 24, they experience an abrupt increase in the electric field caused by the voltage applied to the control gate 26, which is capacitively coupled to the floating gate 24, causing charge to be injected into the floating gate 24. Thus, programming occurs through the mechanism of hot electron injection.

[0005] During an erase operation in which (electron) charge is removed from the floating gate 24, a high positive voltage is applied to the erase gate 28. A negative or ground voltage can be applied to the control gate 26, the word line gate 20, or both. Charge is transferred from the floating gate 24 to the erase gate 28 by tunneling through an insulating layer between the floating gate 24 and the erase gate 28. In particular, the floating gate 24 can be formed with a sharp tip facing the erase gate 28, thereby facilitating Fowler-Nordheim tunneling of electrons from the tip at the floating gate 24, through the insulating layer between the floating gate 24 and the erase gate 28, and to the erase gate 28.

[0006] During a read operation, a first positive voltage is applied to the word line gate 20 to turn on the portion of the channel region 18 under the word line gate 20. A second positive voltage is applied to the control gate 26. A differential voltage is applied to the first region 14 and the second region 16. If the floating gate 24 is programmed, i.e., if the floating gate 24 stores electrons, the second positive voltage applied to the control gate 26 cannot overcome the negative potential induced by the electrons stored in the floating gate 24, and therefore the portion of the channel region 18 under the floating gate 24 remains non-conductive. Thus, no or a minimal amount of current flows between the first region 14 and the second region 16. This is sensed as a programmed (i.e., 0) state. On the other hand, if the floating gate 24 is erased, i.e., if the floating gate 24 is considered to be positively charged, then a second positive voltage applied to the control gate 26 (which is capacitively coupled to the floating gate 24) can cause the portion of the channel region 18 underneath the floating gate 24 to become conductive. Thus, current flows between the first region 14 and the second region 16. This is sensed as an erased (i.e., 1) state.

[0007] The memory cells 10 are typically formed in a semiconductor wafer as an array having multiple rows and columns of memory cells 10. After the memory cells 10 are fabricated in the wafer, the memory cells 10 in the wafer are subjected to testing to determine the ability of each memory cell 10 to retain its programmed or erased state, and in particular the ability or lack thereof of the floating gate 24 in each memory cell 10 to retain its charge state with respect to electrons. During testing, the memory cells 10 are first programmed to place charge (electrons) on the floating gate 24, or erased to remove most of the charge (electrons) from the floating gate 24. The memory cells 10 are then baked, which includes exposing the memory cells 10 to high temperatures for a particular period of time (as a non-limiting example, 250 degrees Celsius for three days). Finally, each memory cell 10 in the device is subjected to a read operation in which the read current from the memory cell 10 under test is compared to a read reference current.

[0008] Referring to FIG. 2, a graph of the standard deviation of the read current Ir distribution of various memory cells 10 set to different program states, i.e., different amounts of charge on their respective floating gates 24, is shown. A memory cell 10 in an erased state typically has a higher read current 40 compared to a read current 42 of a memory cell in a neutral charge state (i.e., having some charge on the floating gate), which in turn typically has a higher read current compared to a read current 44 of a memory cell in a programmed state (i.e., fully programmed with electrons on the floating gate). During normal use operation of a memory cell, the memory cell program state is determined by performing a read operation and comparing the memory cell's read current Ir (i.e., the current that flows through the channel region 18 when a normal use operation read voltage is applied) to a read reference current. A non-limiting example of the read reference current is about 30% of a typical read current for an erased memory cell. If the read current is above the read reference current, the memory cell is considered to be in an erased state. If the read current is below the read reference current, the memory cell is considered to be in a programmed state. Due to parameter variations of cells integrated in a memory array, the read current 42 of some cells in a neutral charge state may be higher than the read reference current and the read current 42 of some cells may be lower than the read reference current.

[0009] If a memory cell 10 has a charge leakage path through the dielectric surrounding the floating gate 24, the read current from such a defective memory cell 10 in the erased state will tend to decrease (as electrons leak into the floating gate) and have the characteristics of current 42. This condition cannot be detected after a high temperature bake if the read current from the defective memory cell 10 under test remains above the read reference current. Similarly, the read current from a defective memory cell 10 in the programmed state will tend to increase (as electrons leak out of the floating gate) and have the characteristics of current 42. This condition cannot be detected after a high temperature bake if the read current from the defective memory cell 10 under test remains below the read reference current.

[0010] Due to these characteristics of the non-volatile memory cells 10, testing of memory devices having memory cells 10 in the prior art included two operations. In the first operation, a first data pattern is stored in the memory cells, followed by a first bake operation, followed by a test operation to determine the read currents of the memory cells 10 and compare them to a read reference current. In the second operation, a second data pattern, which is the inverse of the first data pattern, is stored in the memory cells, followed by a second bake operation, followed by a test operation to determine the read currents of the memory cells 10 and compare them to a read reference current. The time to store the data pattern in the memory cells and the time to bake the device are substantial, which increases the cost of testing the memory devices. Also, even with the prior art two bake process, some defective memory cells 10 may not be detected as defective after data retention screening (i.e., testing to identify defective memory cells that cannot adequately maintain a programmed state to store data). For example, a defective memory cell 10 may have a read current 42 that is greater than the read reference current. In the first test, when a defective memory cell 10 is in an erased state, except for electrons that have leaked onto the floating gate, the read current from such a memory cell will decrease due to this leakage, but will still tend to have the characteristics of current 42, and therefore the read current will remain above the read reference current and the defective cell 10 will not be detected as defective. In the second test, when a defective cell 10 is in a programmed state, except for electrons that have leaked off the floating gate, the read current from such a cell will increase due to this leakage, but will still tend to have the characteristics of read current 42. However, if the leakage during the bake process is too slow, the read current from the defective cell 10 will not have time to increase above the read reference current during the bake process.Therefore, because the read reference current is typically close to the read current 42, the leakage of electrons during the bake process is typically slow and some defective cells 10 may remain undetected as defective after data retention screening.

[0011] There is a need to improve the efficiency of the data retention screening process for defective memory cells. Summary of the Invention

[0012] The above problems and needs are addressed by a method for screening memory cells, including erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and weak programming steps, screening any memory cells that exhibit a read current below a margin read current threshold M1 during the first read operation, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking step, and screening any memory cells that exhibit a read current below the margin read current threshold M1 during the second read operation.

[0013] A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and weak programming steps, screening any memory cells that exhibit a read current below a margin read current threshold M1 during the first read operation, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking step, and screening any memory cells that exhibit a read current below a margin read current threshold M2 during the second read operation, where the margin read current thresholds M1 and M2 are greater than a read reference current used to determine the erased state of the memory cells during a nominal read operation, and the margin read current threshold M2 is less than the margin read current threshold M1.

[0014] A method for screening memory cells includes the steps of strongly erasing the memory cells, each of the memory cells including a control gate; after the strongly erasing step, performing a first read operation on the memory cells including applying a first read voltage to the control gate that is below a nominal read voltage for the control gate; screening any memory cells that exhibit a read current below a margin read current threshold M1 during the first read operation; weakly programming the memory cells to a modified erased state; and after the weak programming step, screening the memory cells with a second read voltage that is below the nominal read voltage for the control gate and above the first read voltage. the step of performing a second read operation on the memory cells including applying a read voltage to the control gate of the memory cell; screening any memory cells that exhibit a read current below the margin read current threshold M1 during the second read operation; baking the memory cells after the second read operation; and after the baking step, performing a third read operation on the memory cells including applying a third read voltage to the control gate of the memory cell that is below the nominal read voltage on the control gate and greater than the second read voltage; and screening any memory cells that exhibit a read current below the margin read current threshold M1 during the third read operation.

[0015] The method includes the steps of: strongly erasing the memory cells, each of the memory cells including a control gate; performing a first read operation on the memory cells after the strongly erasing step, the first read operation including applying a first read voltage to the control gate that is below a nominal read voltage for the control gate; screening any memory cells that exhibit a read current below a margin read current threshold M1 during the first read operation; weakly programming the memory cells to a modified erased state; and weakly programming the memory cells after the weak programming step, the second read voltage to the control gate that is below the nominal read voltage for the control gate and greater than the first read voltage. 2. A method for screening memory cells, comprising: performing two read operations on the memory cells, screening any memory cells that exhibit a read current below a margin read current threshold M2 during the second read operation, baking the memory cells after the second read operation, performing a third read operation on the memory cells after the baking step, the third read operation including applying a third read voltage to the control gate that is below a nominal read voltage on the control gate and greater than the second read voltage, and screening any memory cells that exhibit a read current below a margin read current threshold M3 during the third read operation, the margin read current thresholds M1, M2, and M3 being greater than a read reference current used to determine an erased state of the memory cells during the nominal read operation, the margin read current threshold M3 being less than the margin read current threshold M2, and the margin read current threshold M2 being less than the margin read current threshold M1.

[0016] Other objects and features of the present disclosure will become apparent from a review of the specification, claims, and accompanying drawings.

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[0029] [Brief description of the drawings]

[0030] [Figure 1] 1 is a cross-sectional view of a conventional non-volatile memory cell. [Diagram 2] 4 is a graph showing the distribution of read currents for erased memory cells, neutral charge state memory cells, and programmed memory cells. [Diagram 3] 4 is a graph showing the distribution of read current as a function of control gate voltage for memory cells in different programmed states. [Figure 4] 4 is a graph showing the distribution of read current as a function of control gate voltage for memory cells in different programmed states. [Diagram 5] 1 is a graph showing the standard deviation distribution of threshold voltages of memory cells in different programmed states. [Figure 6] FIG. 2 is a flow diagram showing the operational steps of a first example of memory cell screening. [Figure 7] 7 is a graph showing the standard deviation distribution of threshold voltages of memory cells in different program states according to the first example of FIG. 6; [Figure 8]11 is a graph showing the standard deviation distribution of threshold voltages of memory cells in a modified erased state. [Figure 9] FIG. 11 is a flow diagram showing the operational steps of a second example of memory cell screening. [Figure 10] 10 is a graph illustrating the standard deviation distribution of threshold voltages of memory cells in different program states according to the second example of FIG. 9; [Figure 11] FIG. 11 is another flow diagram illustrating the operational steps of a second example of memory cell screening. [Figure 12] FIG. 11 is a flow diagram showing the operational steps of a third example of memory cell screening. [Figure 13] 13 is a graph showing the standard deviation distribution of threshold voltages of memory cells in different program states according to the third example of FIG. 12; [Figure 14] FIG. 11 is another flow diagram illustrating the operational steps of the third example of memory cell screening. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] It has been confirmed by the inventors that after high temperature bake operation, 0 to 1 failures (electrons leaking out of the floating gate) for the memory cells of FIG. 1 are encountered more frequently than 1 to 0 failures (electrons leaking into the floating gate). This means that baking programmed "0" state memory cells is more efficient for data retention screening (i.e., detection of leaky defective memory cells that cannot adequately maintain their programmed state over time) than baking erased "1" state memory cells. It has been found that the cell currents of memory cells in neutral charge state (which is the end stop for leaky bits) are mostly higher than the read reference current, and therefore approach the erased state rather than the programmed state. For this reason, data retention screening to detect excessively leaky and therefore defective memory cells from a programmed "0" state using a read operation with a margin read current threshold (referred to herein as margin 0) set closer to the programmed "0" state than the read reference current may be more efficient compared to data retention screening from an erased "1" state using a read operation with a margin read current threshold (referred to herein as margin 1, and margin read current threshold M1) set closer to the erased "1" state. Another reason data retention screening from a programmed "0" state may be more efficient is that the erase distribution (i.e., the distribution of read currents and threshold voltages of erased memory cells) is substantially wider compared to the program distribution (i.e., the distribution of read currents and threshold voltages of programmed memory cells) due to the less controllable Fowler-Nordheim tunneling mechanism used for erasure, while programming is based on a more controllable hot electron injection mechanism. Leaky defective memory cells are usually otherwise normal, i.e., they likely originate from the central portion of the erase or program read current distribution.Thus, a wider erase or program read current distribution requires that the margin read current threshold used in data retention screening to detect leaky memory cells be set further away from the distribution, resulting in a longer time for leaky memory cells to be detected as leakage occurs over time. In other words, in rare cases, leaky memory cells may experience a faster change of charge state from an erased "1" state compared to a programmed "0" state due to the strong asymmetry of leakage. There is a need to improve the efficiency of data retention screening.

[0032] The dependence of the memory cell read current Ir on the read voltage Vcg applied to the control gate 26 (CG) of the memory cell of FIG. 1 under otherwise normal use read operating conditions for various cell states is shown in FIG. 3. The curves in FIG. 3 show the read current characteristics of a leaky memory cell as a function of the read voltage Vcg applied to the control gate. Specifically, curve (a) corresponds to a memory cell immediately after an erase operation has been applied (i.e., an erased memory cell has a positive floating gate charge (positive Qfg)). Curve (b) corresponds to a memory cell immediately after a program operation has been applied (i.e., a programmed memory cell has a negative floating gate charge (negative Qfg)). Curve (c) corresponds to a neutral charge state of the floating gate (zero floating gate charge (Qfg=0)). Curves (d) and (e) correspond to the fault detection thresholds of the read current used for data retention screening of the erased state "1" and the programmed state "0", respectively. For example, if the read current characteristic curve of an erased memory cell shifts to the right from curve (a) beyond curve (d) (i.e., due to the floating gate charge leaking toward a neutral charge state), the memory cell is considered defective. Similarly, if the read current characteristic curve of a programmed memory cell shifts to the left from curve (b) beyond curve (e) (i.e., due to the loss of floating gate charge), the memory cell is considered defective.

[0033] Any change in the programming state of the floating gate (i.e., its charge state) results in a corresponding shift of the characteristic curve along the Vcg axis without changing the shape of the curve. In general, the floating gate charge (Qfg) of a leaky memory cell transitions to its neutral charge state under unbiased conditions. Thus, the read current Ir of the memory cell increases over time during the bake process if the memory cell starts in a programmed "0" state (indicated by the "electron charge loss" arrow) and decreases during the bake process if the memory cell starts in an erased "1" state (indicated by the "electron charge gain" arrow), both approaching the neutral charge state (Qfg=0), as shown in FIG. 3. Data retention failures can be more efficiently detected using margin 1 and margin 0 reference currents set above and below the normal read reference current accordingly. Specifically, "normal read" in FIG. 3 represents the read reference current during a nominal read operation (including using a nominal read voltage Vcg_read at the control gate) that defines the boundary between whether the memory cell is erased or programmed. As used herein, nominal read, program, and erase operations (including nominal voltages applied during these nominal operations) refer to read, program, and erase operations performed on memory cells to read, program, and erase data in / to / from the memory cells during normal use conditions of a memory device that includes the memory cells under the control of a controller that manages the read, program, and erase operations. Margin 1 represents the margin read current threshold (above the read reference current by a predetermined amount) below which an erased memory cell is considered defective. Similarly, Margin 0 represents the margin read current threshold (below the read reference current by a predetermined amount) below which a programmed memory cell is considered defective. Data retention efficiency can be improved by reducing the time to failure of leaky memory cells by setting Margin 0 below the read reference current (used for nominal read operations) and Margin 1 above.An additional method for reducing the time to failure of leaky memory cells is to apply a voltage to the control gate during a read operation that is higher than the nominal read voltage Vcg_read used for the nominal read operation for data retention screening of programmed "0" state memory cells and a voltage that is lower than the nominal read voltage Vcg_read used for the nominal read operation for data retention screening of erased "1" state memory cells.

[0034] One criterion for selecting the margin level can provide a guard band to account for cell-to-cell variation of read current of good (non-defective) programmed and erased memory cells in the array, as shown in FIG. 4. With a nominal read voltage Vcg_read on the control gate during a read operation, the lowest read current Ir after an erase operation in the memory array is greater than margin 1 by an amount A1, and the highest read current Ir after a program operation is less than margin 0 by an amount A0, as shown by arrows A1 and A0 in FIG. 4, respectively. The guard band can prevent good memory cells from being selected out from the tail of the inherent variation. As shown in FIG. 4, the cell-to-cell variation after an erase operation is wider than the cell-to-cell variation after a program operation.

[0035] FIG. 5 shows a schematic of memory cell array threshold voltage (Vtcg) distributions after erase and program operations. The cell threshold voltage Vtcg is the minimum read voltage applied to the control gate required to generate a certain level of read current (e.g., margin 0, normal read, margin 1) through the memory cell during a read operation. The post-erase Vtcg distribution in FIG. 5 corresponds to the control gate read voltage required for the cell current to match the margin 1 read current threshold. The post-program Vtcg distribution in FIG. 5 corresponds to the control gate read voltage required for the cell current to match the margin 0 read current threshold. The Vtcg equal to Vcg_read in FIG. 5 corresponds to the read reference current used to distinguish erased memory cells from programmed memory cells during a nominal read operation. The margin 1 and margin 0 read current thresholds are set to screen defective memory cells for data retention, so that they are outside the intrinsic distributions of the erased and programmed states, respectively. Because the Vtcg distribution after erasure is wider than the Vtcg distribution after programming, the efficiency of data retention screening for leaky memory cells in the erased state is lower (i.e., longer time to failure) compared to the programmed state due to electron leakage occurring over time.

[0036] The inventors have realized that data retention screening from an erased state "1" can be improved by compressing the erase distribution (i.e., distribution of margin 1 threshold voltages) of erased memory cells, which is accomplished by applying a weak programming operation after the erase operation so that the memory cells are in a corrected (i.e., compressed) erased state. Once the corrected (compressed) erased state is achieved, the margin read current threshold (Margin 1) can be set closer to the center of the erased state "1" distribution, thus improving the efficiency of data retention screening (i.e., reducing the time to failure of leaky memory cells that are more likely to arise from the center of the distribution). The Vtcg distribution can be compressed by applying several weak program operations with gradually incremented programming voltages and performing read verify operations between these weak program operations. As described in more detail below, additional techniques can be used in combination with the weak programming operations to identify defective leaky memory cells, which are described in more detail below. For example, to reduce yield loss caused by limited inherent negative Ir shift (or positive Vtcg shift) during high temperature bake that is not related to defect leakage from the floating gate, a lower Vcg_read operation can be performed before the bake operation compared to a higher Vcg_read after the bake operation. Another technique to compensate for the inherent Ir shift during the bake operation is to use a higher Margin1 level before the bake operation compared to a lower Margin1 level after the bake operation. As another technique, a stronger erase operation (compared to a nominal erase operation) can be applied first to move the final compacted erase distribution further away from the neutral charge state to further improve data retention screening for leaky memory cell detection. As yet another technique, the Vcg_read for verifying the strong erase operation can be set lower than the Vcg_read after the erase distribution is compacted by the weak program operation.Another technique may be to use a higher Margin 1 level for a read operation after an erase operation compared to the Margin 1 level for a read operation after a weak program operation.

[0037] 6-8 illustrate a first method, in which data retention screening involves compacting the distribution of threshold voltages Vtcg for erased memory cells by performing a weak program operation on the erased memory cells. As shown in FIG. 6, in step 1A of this example, the memory cells are erased using a nominal erase operation. In step 2A, the memory cells are weakly programmed using a weak program operation to compact the distribution of the memory cell's threshold voltages Vcg. After the weak program operation, the memory cells are in a modified erased state. FIG. 7 illustrates the threshold voltage distribution after the erase operation (line labeled "Erased State") and the more compact threshold voltage distribution after the weak program operation (line labeled "Modified Erased State"). To compress the erase distribution, a weak program can be applied, the conditions of which are selected to cause a larger shift in the median and lower portions of the standard deviation erase distribution while keeping the shift in the higher standard deviation portions of the erase distribution low, so that the memory cells in the corrected erased state are still below the threshold voltage Vcg associated with nominal operation and still exhibit a sufficiently high read current during nominal read operations, so that the memory cells in the corrected erased state are still considered erased (i.e., the goal is not to over-program the memory cells so that the cell current remains above the margin 1 level). A single weak program operation can significantly narrow the erase distribution, as shown in FIG. 7. In step 3A, a first screen read is performed in which the memory cells are read in a first read operation using a nominal read operation Vcg_read voltage on the control gate (also referred to herein as the nominal read voltage Vcg_read, the nominal read voltage for the control gate, Vcg_read nominal, and for this example the first read voltage) to screen out any memory cells having a read current below a margin read current threshold M1 as defective. As described above, the margin read current threshold M1 is greater than the read reference current that a memory cell exhibits when considered erased in a nominal read operation.As used herein, screen or screening refers to identifying any memory cells having a read current below the margin read current threshold M1 as defective, and screen read refers to the combination of a read operation and using the results of the read operation to identify any memory cells as defective. Then, in step 4A, a high temperature bake operation is performed (e.g., 250 degrees Celsius for 3 days). In step 5A, a second screen read is performed, where the memory cells are read with a second read operation using a Vcg_read nominal on the control gate, thereby screening out any memory cells having a read current below the margin read current threshold M1 as defective.

[0038] As shown in FIG. 8, the erased distribution of the threshold voltage Vtcg can be further narrowed by applying a weak program algorithm using pulses of program voltages, separated by read verify operations, where one or more program voltages are gradually incremented for each pulse, with read verify operations between the pulses, until the corrected erased state is achieved. The programming voltage increments can be selected based on the sort time budget and the duration of programming time per increment. The advantage of applying a programming algorithm with smaller voltage increments is that a more compact distribution can be achieved. However, programming can take longer, and therefore an optimization or tradeoff between narrower distribution and increased test time is contemplated when determining whether a single-pulse weak program operation or a multiple-pulse weak program operation should be used to achieve the desired corrected erased state of the memory cells.

[0039] 9-10 show a second method, where data retention screening uses different read operation conditions both before and after a bake operation relative to a nominal read operation. After the erase operation of step 1B and the weak program operation of step 2B (where the incremental program with read verify can provide a more compressed standard deviation distribution compared to one-step weak program) that places the memory cells in a modified erased state, a first screen read is performed in step 3B, where a first read operation is performed using a read voltage Vcg_read1 (also referred to as the first read voltage for this example) at the control gate that is less than Vcg_read nominal, thereby screening out any memory cells having a read current below the margin read current threshold M1 as defective. In step 4B, a high temperature bake operation is then performed (e.g., 250 degrees Celsius for 3 days). In step 5B, a second screen read is performed, where the memory cells are read in a second read operation using a read voltage Vcg_read2 (also referred to as the second read voltage for this example) at the control gate that is greater than Vcg_read1 and less than the nominal Vcg_read, thereby screening out any memory cells that have a read current below the margin read current threshold M1 as defective. This example is advantageous because weaker program conditions can be selected to increase the shift of the center of the erase distribution more than the upper edge of the standard deviation distribution with the highest Vtcg should be shifted to a minimum. The guard band provided between Vcg_read1 and Vcg_read2 accounts for inherent read current shift mechanisms that are not related to charge leakage from the floating gate through defects during the bake operation. Alternatively, or in addition to increasing the voltage applied to the control gate for the second screen readout relative to the first screen readout as described above, the second margin read current threshold M2 for the second screen readout may be smaller than the first margin read current threshold M1 for the first screen readout but still greater than the read reference current.If it is additional, in step 5B of FIG. 9, a second margin read current threshold M2 is used for screen readout instead of the first margin read current threshold M1, as shown in FIG.

[0040] 12-13 show a third method, where the data retention screen includes three read operations. In step 1C, the memory cells are erased using a strong erase operation, meaning that the erase voltage applied to the erase gate is higher than that applied during a nominal erase operation, or is applied for a longer period of time than during a nominal erase operation, or both, so that the memory cells are erased more deeply than during a nominal erase operation. In step 2C, a first screen read is performed in which a first read operation is performed using a read voltage Vcg_read1 (also referred to as the first read voltage for this example) at the control gate that is less than Vcg_read nominal, and any memory cells having a read current below a margin read current threshold M1 are screened out as defective. In step 3C, a weak programming operation is performed to bring the memory cells to a corrected erased state. In step 4C, a second screen read is performed, where the memory cells are read with a second read operation using a read voltage Vcg_read2 (also referred to as the second read voltage for this example) at the control gate that is greater than Vcg_read1 and less than the Vcg_read nominal, and any memory cells having a read current below the margin read current threshold M1 are screened out as defective. Then, in step 5C, a high temperature bake operation is performed (e.g., 250 degrees Celsius for 3 days). In step 6C, a third screen read is performed, where the memory cells are read with a third read operation using a read voltage Vcg_read3 (also referred to as the third read voltage for this example) at the control gate that is greater than Vcg_read2 and less than the Vcg_read nominal, and any memory cells having a read current below the margin read current threshold M1 are screened out as defective. In this example, the application of a deep erase and a first screen read before the weak program helps to account for any possible overshoot during the weak program.Instead of or in addition to increasing the voltage applied to the control gate in successive first, second and third screen readouts as described above, the margin read current threshold M1 for successive first, second and third screen readouts may be successively decreased. For example, the second margin read current threshold M2 for the second screen readout may be smaller than the first margin read current threshold M1 for the first screen readout, and the third margin read current threshold M3 for the third screen readout may be smaller than the second margin read current threshold M2 for the second screen readout, but all three margin read current thresholds M1, M2, M3 are still larger than the read reference current. If it is additional, as shown in FIG. 14, in step 4C of FIG. 12, the second margin read current threshold M2 is used for screen readout instead of the first margin read current threshold M1, and in step 6C of FIG. 12, the third margin read current threshold M3 is used for screen readout instead of the first margin read current threshold M1.

[0041] It will be understood that the present disclosure is not limited to the above-described examples illustrated herein, but encompasses any variations falling within the scope of any claims. For example, reference herein to the present disclosure or invention or examples is not intended to limit the scope of any claims or claim terms, but instead merely refers to one or more features that may be covered by one or more claims. The material, process, and numerical examples described above are merely illustrative and should not be considered as limiting the scope of the claims.

Claims

1. 1. A method for screening a plurality of memory cells, comprising: erasing the plurality of memory cells; weakly programming the plurality of memory cells to a modified erased state; performing a first read operation on the plurality of memory cells after the erasing and weak programming steps; screening any of the plurality of memory cells that exhibit a read current below a margin read current threshold M1 during the first read operation; baking the plurality of memory cells after the first read operation; performing a second read operation on the plurality of memory cells after the baking step; screening any of the plurality of memory cells that exhibit a read current below the margin read current threshold M1 during the second read operation.

2. 2. The method of claim 1, wherein the margin read current threshold M1 is greater than a read reference current used to determine the erased state of the plurality of memory cells during a nominal read operation.

3. Each of the plurality of memory cells includes a control gate; the performing the first read operation includes applying a first read voltage to the control gate equal to a nominal read voltage for the control gate; 2. The method of claim 1, wherein the performing the second read operation comprises applying the first read voltage to the control gate.

4. Each of the plurality of memory cells includes a control gate; the performing the first read operation includes applying a first read voltage to the control gate that is less than a nominal read voltage for the control gate; 2. The method of claim 1, wherein the performing the second read operation comprises applying a second read voltage to the control gate that is less than the nominal read voltage for the control gate and greater than the first read voltage.

5. 1. A method for screening a plurality of memory cells, comprising: erasing the plurality of memory cells; weakly programming the plurality of memory cells to a modified erased state; performing a first read operation on the plurality of memory cells after the erasing and weak programming steps; screening any of the plurality of memory cells that exhibit a read current below a margin read current threshold M1 during the first read operation; baking the plurality of memory cells after the first read operation; performing a second read operation on the plurality of memory cells after the baking step; screening any of the plurality of memory cells that exhibit a read current below a margin read current threshold M2 during the second read operation; The method, wherein the margin read current thresholds M1 and M2 are greater than a read reference current used to determine the erased state of the plurality of memory cells during a nominal read operation, and the margin read current threshold M2 is less than the margin read current threshold M1.

6. Each of the plurality of memory cells includes a control gate; the performing the first read operation includes applying a first read voltage to the control gate that is less than a nominal read voltage for the control gate; 6. The method of claim 5, wherein the performing the second read operation comprises applying a second read voltage to the control gate that is less than the nominal read voltage for the control gate and greater than the first read voltage.

7. 1. A method for screening a plurality of memory cells, comprising: hard erasing the plurality of memory cells, each of the plurality of memory cells including a control gate; performing a first read operation on the plurality of memory cells after the hard erasing step, the first read operation including applying a first read voltage to the control gate that is below a nominal read voltage for the control gate; screening any of the plurality of memory cells that exhibit a read current below a margin read current threshold M1 during the first read operation; weakly programming the plurality of memory cells to a modified erased state; performing a second read operation on the plurality of memory cells after the weak programming step, the second read operation including applying a second read voltage to the control gate that is less than a nominal read voltage on the control gate and greater than the first read voltage; screening any of the plurality of memory cells that exhibit a read current below the margin read current threshold M1 during the second read operation; baking the plurality of memory cells after the second read operation; performing a third read operation on the plurality of memory cells after the baking step, the third read operation including applying a third read voltage to the control gate that is less than the nominal read voltage on the control gate and greater than the second read voltage; screening any of the plurality of memory cells that exhibit a read current below the margin read current threshold M1 during the third read operation.

8. 8. The method of claim 7, wherein the margin read current threshold M1 is greater than a read reference current used to determine the erased state of the plurality of memory cells during a nominal read operation.

9. 1. A method for screening a plurality of memory cells, comprising: hard erasing the plurality of memory cells, each of the plurality of memory cells including a control gate; performing a first read operation on the plurality of memory cells after the hard erasing step, the first read operation including applying a first read voltage to the control gate that is below a nominal read voltage for the control gate; screening any of the plurality of memory cells that exhibit a read current below a margin read current threshold M1 during the first read operation; weakly programming the plurality of memory cells to a modified erased state; performing a second read operation on the plurality of memory cells after the weak programming step, the second read operation including applying a second read voltage to the control gate that is less than a nominal read voltage on the control gate and greater than the first read voltage; screening any of the plurality of memory cells that exhibit a read current below a margin read current threshold M2 during the second read operation; baking the plurality of memory cells after the second read operation; performing a third read operation on the plurality of memory cells after the baking step, the third read operation including applying a third read voltage to the control gate that is less than the nominal read voltage on the control gate and greater than the second read voltage; screening any of the plurality of memory cells that exhibit a read current below a margin read current threshold M3 during the third read operation; the margin read current thresholds M1, M2, and M3 being greater than a read reference current used to determine the erased state of the plurality of memory cells during a nominal read operation, the margin read current threshold M3 being less than the margin read current threshold M2, which is less than the margin read current threshold M1.

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