Inorganic / organic hybrid complementary semiconductor device and its manufacturing method

Abstract

To provide an inorganic / organic hybrid complementary type semiconductor device that can be manufactured at low cost, has excellent long-term stability, includes a p-type transistor and an n-transistor that operate with balance, and operates at a high speed.SOLUTION: An inorganic / organic hybrid complementary type semiconductor device includes a substrate, a p-type organic semiconductor single-crystal layer, an n-type amorphous metal oxide inorganic semiconductor layer between the substrate and the single-crystal layer, and a protective layer between the single-crystal layer and the inorganic semiconductor layer. The single-crystal layer is disposed so that, when a main surface of the single-crystal layer is viewed vertically, at least a part of the single-crystal layer overlaps with the inorganic semiconductor layer or the single-crystal layer does not overlap with the inorganic semiconductor layer. A distance between the single-crystal layer and the inorganic semiconductor layer is 1 mm or less. The inorganic semiconductor layer has an oxygen defect quantity distribution in a thickness direction, in which an oxygen defect quantity is larger on the single-crystal layer side than on the substrate side.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an inorganic / organic hybrid complementary semiconductor device and a method for making the same. [Background technology]

[0002] Semiconductor devices are expected to be the basic elements of electronic devices in the Internet of Things (IoT) society. In particular, complementary metal-oxide semiconductor (CMOS), which consists of p-type and n-type transistors, is the fundamental technology for current integrated circuits. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Takeda, Y. et al. Appl. Sci. 2018, 8, 1331 [Non-Patent Document 2] K. Hong, et al. Adv. Mater. 2014, 26, 7032 [Non-Patent Document 3] M. Uno, et al. Adv. Electron. Mater. 2015, 1, 1500178 [Non-Patent Document 4] KJ Baeg. et al. Org. Electron. 2013, 14, 1407 [Non-Patent Document 5] SH Kim, et al, IEEE Electron Device Lett. 2013, 34, 307 [Non-Patent Document 6] W. Smaal, et al, Org. Electron. 2012, 13, 1686 [Non-Patent Document 7] L. Herlogsson, et al. Adv. Mater. 2011, 23, 4684 Summary of the Invention [Problem to be solved by the invention]

[0004] However, there is still a need for inexpensive CMOS that can be manufactured on a large scale, as well as CMOS that has excellent long-term stability, a good balance between the operation of p-type and n-type transistors, and high speed operation.

[0005] The present invention has been made in consideration of the above circumstances, and has an object to provide a complementary semiconductor device that can be manufactured inexpensively, has excellent long-term stability, has a well-balanced operation between p-type transistors and n-type transistors, and operates at high speed. [Means for solving the problem]

[0006] The gist of the present invention is as follows. (1) Substrate, A p-type organic semiconductor single crystal layer, an n-type amorphous metal oxide inorganic semiconductor layer between the substrate and the p-type organic semiconductor single crystal layer; and A protective layer between the p-type organic semiconductor single crystal layer and the n-type amorphous metal oxide inorganic semiconductor layer. Including, the p-type organic semiconductor single crystal layer is disposed such that, when viewed from a direction perpendicular to a main surface of the p-type organic semiconductor single crystal layer, at least a portion of the p-type organic semiconductor single crystal layer overlaps the n-type amorphous metal oxide inorganic semiconductor layer, or such that the p-type organic semiconductor single crystal layer does not overlap the n-type amorphous metal oxide inorganic semiconductor layer; The distance between the p-type organic semiconductor single crystal layer and the n-type amorphous metal oxide inorganic semiconductor layer is 1 mm or less; the n-type amorphous metal oxide inorganic semiconductor layer has a distribution of oxygen vacancies in a thickness direction in which the amount of oxygen vacancies is greater on the p-type organic semiconductor single crystal layer side than on the substrate side; Inorganic / organic hybrid complementary semiconductor devices. (2) The inorganic / organic hybrid complementary semiconductor device according to the above (1), wherein the average thickness of the p-type organic semiconductor single crystal layer is 2 to 100 nm. (3) The p-type organic semiconductor single crystal film has a thickness of 0.0025 mm 2 The inorganic / organic hybrid complementary semiconductor device according to (1) or (2) above, having the above single domain. (4) The inorganic / organic hybrid complementary semiconductor device according to any one of (1) to (3) above, wherein the substrate is a flexible substrate. (5) The protective layer includes a first organic film and a second organic film, the first organic film is located on the n-type amorphous metal oxide inorganic semiconductor layer side, and the second organic film is located on the p-type organic semiconductor single crystal layer side; The first organic film is composed of an organic solvent-soluble polymer, and the second organic film is a vacuum-deposited film. The inorganic / organic hybrid complementary semiconductor device according to any one of (1) to (4) above. (6) The inorganic / organic hybrid complementary semiconductor device according to (5) above, wherein the first organic film has a thickness of 10 nm or more, and the second organic film has a thickness of 100 to 300 nm. (7) The inorganic / organic hybrid complementary semiconductor device according to (5) or (6) above, wherein the first organic film is a PMMA film and the second organic film is a parylene film. (8) providing a substrate; forming an n-type structure on the substrate; forming a protective layer over the n-type structure; and forming a p-type structure on said protective layer; A method for manufacturing an inorganic / organic hybrid complementary semiconductor device, comprising: forming the n-type structure preparing a precursor solution of an n-type amorphous metal oxide inorganic semiconductor containing a metal salt using a sol-gel method; applying the precursor solution onto the substrate to form a precursor film; and The precursor film is heat-treated at 350 to 400° C. to form an n-type amorphous metal oxide inorganic semiconductor layer. Including, The formation of the p-type structure includes forming a p-type organic semiconductor single crystal layer by using a coating method. Including, the p-type organic semiconductor single crystal layer is disposed such that, when viewed from a direction perpendicular to a main surface of the p-type organic semiconductor single crystal layer, at least a portion of the p-type organic semiconductor single crystal layer overlaps the n-type amorphous metal oxide inorganic semiconductor layer, or such that the p-type organic semiconductor single crystal layer does not overlap the n-type amorphous metal oxide inorganic semiconductor layer; The distance between the p-type organic semiconductor single crystal layer and the n-type amorphous metal oxide inorganic semiconductor layer is 1 mm or less; the n-type amorphous metal oxide inorganic semiconductor layer has a distribution of oxygen vacancies in a thickness direction in which the amount of oxygen vacancies is greater on the p-type organic semiconductor single crystal layer side than on the substrate side; A method for fabricating hybrid inorganic / organic complementary semiconductor devices. (9) The method for producing an inorganic / organic hybrid complementary semiconductor device according to (8) above, wherein applying the precursor solution to form the precursor film is carried out using a spin coating method. (10) Forming the protective layer preparing an organic solvent having a polymer dissolved therein; forming a first organic film on the n-type structure by applying an organic solvent having the polymer dissolved therein; and forming a second organic film, which is a vacuum deposition film, on the first organic film by using a chemical vapor deposition method; A method for producing the inorganic / organic hybrid complementary semiconductor device according to (8) or (9) above, comprising: (11) The formation of the p-type organic semiconductor single crystal layer forming a p-type organic semiconductor single crystal film on a hydrophilic and water-insoluble first substrate by using the coating method; and applying water or an aqueous solution to an interface between the first substrate and the p-type organic semiconductor single crystal film to separate the p-type organic semiconductor single crystal film from the first substrate and disposing the p-type organic semiconductor single crystal layer on a second substrate; Including, The second substrate is at least one of a gate insulating layer and an S / D electrode of the n-type structure, a protective layer, or a combination thereof; A method for producing an inorganic / organic hybrid complementary semiconductor device according to any one of (8) to (10) above. (12) The formation of the p-type organic semiconductor single crystal layer forming a p-type organic semiconductor single crystal film on a hydrophilic and water-insoluble third substrate by using the coating method; pressing the p-type organic semiconductor single crystal film against a protrusion of a stamp having a protrusion and a recess; applying water or an aqueous solution to an interface between the third substrate and the p-type organic semiconductor single crystal film to transfer the p-type organic semiconductor single crystal film to the protrusions; and The p-type organic semiconductor single crystal film transferred to the convex portion is pressed against a fourth substrate, and the p-type organic semiconductor single crystal film is transferred to the fourth substrate to obtain a patterned p-type organic semiconductor single crystal layer. Including, The fourth substrate is at least one of a gate insulating layer and an S / D electrode of the n-type structure, a protective layer, or a combination thereof; A method for producing an inorganic / organic hybrid complementary semiconductor device according to any one of (8) to (10) above. Effect of the Invention

[0007] According to the present invention, it is possible to provide a complementary semiconductor device that can be manufactured inexpensively, has excellent long-term stability, has a well-balanced operation between p-type transistors and n-type transistors, and operates at high speed. [Brief description of the drawings]

[0008] [Figure 1]FIG. 1 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-top-contact / bottom-gate-top-contact structure. [Diagram 2] FIG. 2 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-bottom-contact / bottom-gate-top-contact structure. [Diagram 3] FIG. 3 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-top-contact / bottom-gate-top-contact structure. [Figure 4] FIG. 4 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-bottom-contact / bottom-gate-top-contact structure. [Diagram 5] FIG. 5 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-top-contact / bottom-gate-bottom-contact structure. [Figure 6] FIG. 6 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-bottom-contact / bottom-gate-bottom-contact structure. [Figure 7] FIG. 7 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-top-contact / bottom-gate-bottom-contact structure. [Figure 8] FIG. 8 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-bottom-contact / bottom-gate-bottom-contact structure. [Figure 9] FIG. 9 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-top-contact / top-gate-top-contact structure. [Figure 10] FIG. 10 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-bottom-contact / top-gate-top-contact structure. [Figure 11] FIG. 11 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-top-contact / top-gate-top-contact structure. [Figure 12]FIG. 12 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-bottom-contact / top-gate-top-contact structure. [Figure 13] FIG. 13 is a schematic cross-sectional view of a complementary semiconductor device in which a top gate electrode of an n-type structure and a bottom gate electrode of a p-type structure are common, and a protective layer and a p-type gate insulating layer are common. [Figure 14] FIG. 14 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-top-contact / top-gate-bottom-contact structure. [Figure 15] FIG. 15 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-bottom-contact / top-gate-bottom-contact structure. [Figure 16] FIG. 16 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-top-contact / top-gate-bottom-contact structure. [Figure 17] FIG. 17 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-bottom-contact / top-gate-bottom-contact structure. [Figure 18] FIG. 18 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-top-contact / bottom-gate-top-contact structure. [Figure 19] FIG. 19 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-top-contact / top-gate-top-contact structure. [Figure 20] FIG. 20 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-top-contact / bottom-gate-bottom-contact structure. [Figure 21] FIG. 21 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-top-contact / top-gate-bottom-contact structure. [Figure 22] FIG. 22 is a schematic cross-sectional view of a complementary semiconductor device having a common protective layer and p-type gate insulating layer. [Diagram 23]FIG. 23 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-bottom-contact / bottom-gate-top-contact structure. [Figure 24] FIG. 24 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-bottom-contact / top-gate-top-contact structure. [Diagram 25] FIG. 25 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-bottom-contact / bottom-gate-bottom-contact structure. [Figure 26] FIG. 26 is a schematic cross-sectional view of a complementary semiconductor device having a bottom-gate-bottom-contact / top-gate-bottom-contact structure. [Figure 27] FIG. 27 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-top-contact / bottom-gate-top-contact structure. [Figure 28] FIG. 28 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-top-contact / top-gate-top-contact structure. [Figure 29] FIG. 29 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-top-contact / bottom-gate-bottom-contact structure. [Diagram 30] FIG. 30 is a schematic cross-sectional view of a complementary semiconductor device having a top-gate-top-contact / top-gate-bottom-contact structure. [Diagram 31] FIG. 31 is a schematic cross-sectional view of a complementary semiconductor device in which a protective layer and a gate insulating layer of a p-type structure are in common. [Diagram 32] Figure 32 shows the top gate-bottom contact / bottom gate-top contact structure. [Diagram 33] Figure 33 shows a top gate-bottom contact / top gate-top contact structure. [Diagram 34] Figure 34 shows a top gate-bottom contact / bottom gate-bottom contact structure. [Diagram 35]Figure 35 shows a top gate-bottom contact / top gate-bottom contact structure. [Diagram 36] FIG. 36 is a schematic diagram showing a method for preparing a precursor solution of an amorphous metal oxide inorganic semiconductor (AOS) using a sol-gel method. [Figure 37] FIG. 37 is a schematic diagram showing a method for forming an AOS layer by using a spin coating method. [Figure 38] FIG. 38 is a schematic diagram showing a patterning process using a photoradical initiator and a sodium carbonate developer. [Figure 39] FIG. 39 is a schematic diagram showing a method for forming source / drain electrodes (S / D electrodes) on an AOS layer by vapor deposition. [Diagram 40] FIG. 40 is a schematic diagram of an example of an n-type TFT including an AOS layer on which S / D electrodes are formed. [Diagram 41] FIG. 41 is a schematic cross-sectional view of the fabricated hybrid complementary semiconductor device. [Diagram 42] FIG. 42 is a perspective view showing a schematic diagram of the fabricated hybrid complementary semiconductor device. [Diagram 43] FIG. 43 is a photograph showing the appearance of the organic / inorganic hybrid complementary semiconductor device obtained in the example. [Diagram 44] FIG. 44 is a graph summarizing the output characteristics of the drain current versus the drain voltage when the gate voltage is changed from 0V to -10V in steps of -2V and from 0V to 10V in steps of 2V. [Diagram 45] FIG. 45 is a graph showing the transfer characteristics of the drain current with respect to the gate voltage of a p-type organic TFT, and the transfer characteristics of the drain current with respect to the gate voltage of an n-type inorganic TFT. [Diagram 46] FIG. 46 is a circuit diagram of an organic-inorganic hybrid complementary semiconductor inverter single element. [Figure 47] FIG. 47 shows the output characteristics of the output voltage when the input voltage is changed from 0 to 10V. [Figure 48] FIG. 48 is a graph evaluating the cause of the voltage amplification effect during switching. [Figure 49] FIG. 49 is a graph showing the relationship between the input voltage and the supply current. [Figure 50] FIG. 50 is a graph showing an evaluation of the noise margin. [Figure 51] FIG. 51 is a graph showing the initial characteristics of a hybrid complementary semiconductor device measured immediately after its fabrication and the characteristics after it was left in the air for five months. [Figure 52] FIG. 52 is a photograph showing the appearance of a hybrid complementary semiconductor device formed on a polyimide substrate that was peeled off from a glass supporter using the laser lift-off (LLO) method. [Figure 53] FIG. 53 is a schematic diagram showing a hybrid complementary semiconductor device formed on a polyimide substrate in a curved state. [Figure 54] FIG. 54 is a graph showing voltage transfer curve (VTC) characteristics of a hybrid complementary semiconductor device formed of an organic TFT and an inorganic TFT before and after the LLO treatment (before and after peeling). [Figure 55] Figure 55 is a photograph of a hybrid complementary semiconductor device formed on a polyimide substrate wrapped around the surface of a glass cylinder, and a graph showing the output characteristics when a hybrid complementary semiconductor device composed of an organic TFT and an inorganic TFT is placed on each surface of a cylinder with different curvature. [Figure 56] FIG. 56 shows a photograph of the ring oscillator, a circuit diagram, and an enlarged photograph of the area enclosed in a square. [Figure 57] FIG. 57 is a graph showing the evaluation of the inverter characteristics of a single hybrid complementary semiconductor device when VDD is 10V. [Figure 58] FIG. 58 is a graph showing the measured output voltage of the ring oscillator when VDD is 10V. [Figure 59] FIG. 59 shows the results of angle-resolved XPS measurements of O1s. [Figure 60] FIG. 60 is a graph showing the angle dependence of the ratio (ηM-OM) of MOM (metal oxide state) to the total O1s. [Figure 61] FIG. 61 is a graph showing the relationship between the concentration of the precursor solution and the thickness of the formed AOS layer. [Figure 62] FIG. 62 is a graph showing the relationship between the gate voltage and the drain current of TFTs in which the thickness of the AOS layer is changed. [Figure 63] FIG. 63 is a graph showing the characteristics of transistors fabricated using IZO thin films prepared by sintering at different temperatures, 350° C., 370° C., and 390° C. [Figure 64] Figure 64 shows the XRD measurement results of the IZO thin films obtained at each sintering temperature. [Figure 65] Figure 65 shows the results of total reflection FT-IR measurement of the IZO thin films obtained at each sintering temperature. [Figure 66] FIG. 66 is a schematic diagram of the angle-resolved XPS measurement method. [Figure 67] FIG. 67 is a schematic cross-sectional view showing the distribution of oxygen vacancies depending on the thickness of the AOS film. [Figure 68] FIG. 68 is a graph showing the thickness dependence of the ratio of each bond type to the total O1s from the substrate toward the outermost surface of the AOS film. [Figure 69] FIG. 69 shows an atomic force microscope (AFM) image and X-ray reflectivity measurement results of the IZO thin film before heat treatment. [Figure 70] FIG. 70 shows an AFM image and the results of X-ray reflectometry of the IZO thin film after heat treatment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The present disclosure relates to an inorganic / organic hybrid complementary semiconductor device comprising: a substrate; a p-type organic semiconductor single crystal layer; an n-type amorphous metal oxide inorganic semiconductor layer between the substrate and the p-type organic semiconductor single crystal layer; and a protective layer between the p-type organic semiconductor single crystal layer and the n-type amorphous metal oxide inorganic semiconductor layer, wherein the p-type organic semiconductor single crystal layer is disposed such that, when viewed from a direction perpendicular to a main surface of the p-type organic semiconductor single crystal layer, at least a portion of the p-type organic semiconductor single crystal layer overlaps the n-type amorphous metal oxide inorganic semiconductor layer or the p-type organic semiconductor single crystal layer does not overlap the n-type amorphous metal oxide inorganic semiconductor layer, the distance between the p-type organic semiconductor single crystal layer and the n-type amorphous metal oxide inorganic semiconductor layer is 1 mm or less, and the n-type amorphous metal oxide inorganic semiconductor layer has a distribution of oxygen defects in a thickness direction in which the amount of oxygen defects is greater on the p-type organic semiconductor single crystal layer side than on the substrate side.

[0010] The inorganic / organic hybrid complementary semiconductor device (hereinafter also referred to as a complementary semiconductor device) of the present disclosure is composed of an amorphous metal oxide inorganic semiconductor layer (hereinafter also referred to as an AOS layer) and an organic semiconductor single crystal layer, which are formed under atmospheric conditions using a solution process. Therefore, special equipment such as a high vacuum chamber used in a dry process is not required for the manufacture of the complementary semiconductor device of the present disclosure, and the manufacturing cost can be reduced compared to the conventional method. In particular, when a large area is desired, it is not necessary to enlarge a special equipment such as a high vacuum chamber, and the cost reduction effect is even greater than that of a dry process.

[0011] The complementary semiconductor device of the present disclosure also has excellent long-term stability and can exhibit substantially the same characteristics before and after being left in the air for five months.

[0012] Since the p-type transistor is made of an organic semiconductor single crystal and the n-type transistor is made of AOS, the operation of the p-type transistor and the n-type transistor are well balanced, allowing the complementary semiconductor device of the present disclosure to operate at high speed.

[0013] Since the AOS layer is formed by a solution process, oxygen vacancies occur on the surface of the AOS layer, and the amount of oxygen vacancies is distributed in the thickness direction (perpendicular to the main surface) of the AOS layer, as shown in Fig. 67. In other words, the state of oxygen vacancies differs between the substrate side and the surface side of the AOS layer. In a complementary semiconductor device, the AOS layer has a distribution of oxygen vacancies in the thickness direction, with the amount of oxygen vacancies being greater on the organic semiconductor single crystal layer side.

[0014] Therefore, the AOS layer formed by the solution process works particularly well when the thickness is preferably 4 to 7 nm, more preferably 5 to 6 nm. The oxygen vacancies on the surface are utilized to maximize the performance of the device. The AOS film formed by a dry process such as sputtering does not have such a distribution of oxygen vacancies. The thickness of the AOS layer can be adjusted by changing the metal ion concentration in the precursor solution, for example.

[0015] The distribution of oxygen vacancies in the thickness direction of the AOS layer was measured by angle-resolved X-ray photoelectron spectroscopy (XPS), which was used to measure the ratio of MOM (metal oxide) to the total O1s (η M-O-M ) can be evaluated. In an AOS layer having a distribution of oxygen vacancies in the thickness direction, the closer to the outermost surface of the AOS layer, the fewer the MOM (M:In or Zn) bonds.

[0016] As shown in Figure 66, angle-resolved XPS is a method of measuring the intensity of a sample by changing the angle (tilt angle θ) of the XPS detector (analyzer) with the vertical direction to the surface of the measurement sample as the reference (0°), as shown in the following equations 1 and 2:

number

number

[0017] The AOS layer is the inner η M-O-M η of the top surface M-O-M is preferably smaller by 10% or more, more preferably by 15% or more, and further preferably by 20% or more.

[0018] The AOS layer is preferably 0.0025 mm 2 More preferably, 0.005 mm 2 More preferably, 0.5 mm 2 More preferably, 2.0 mm or more 2 It has an area of ​​more than 100m2.

[0019] The AOS layer is preferably 0.5 cm 2 / V·s or more, preferably 3.0 cm 2 / V·s or more, and more preferably 5.0 cm 2 / V·s or more, and even more preferably 7.5 cm 2 / V·s or more, and even more preferably 10 cm 2 / V s or more. The mobility of the AOS layer can be calculated from the measurement results of the organic field-effect transistor.

[0020] There is no particular limitation on the type of inorganic semiconductor that constitutes the AOS layer, but for example, ZnO, In2O3, In-Zn-O (IZO), In-Ga-Zn-O (IGZO), etc. can be used.

[0021] Whether the AOS layer is amorphous or not can be confirmed by thin film X-ray diffraction.

[0022] The average film thickness of the organic semiconductor single crystal layer is preferably 2 to 100 nm, more preferably 4 to 20 nm. The upper limit of the average film thickness of the organic semiconductor single crystal layer may be 18 nm or less, 16 nm or less, 14 nm or less, 12 nm or less, 10 nm or less, or 8 nm or less. When the average film thickness of the organic semiconductor single crystal layer is within the above range, good device characteristics can be obtained. The average film thickness of the organic semiconductor single crystal layer can be measured using a stylus surface profiler or an atomic force microscope.

[0023] The organic semiconductor single crystal layer preferably has 1 to 50 molecular layers in the thickness direction, more preferably 1 to 10 molecular layers, even more preferably 1 to 5 molecular layers, even more preferably 1 to 4 molecular layers, even more preferably 1 to 3 molecular layers, and even more preferably 1 to 2 molecular layers. The organic semiconductor single crystal layer most preferably has 1 molecular layer, but may have 2 or more molecular layers in the thickness direction. The number of molecular layers of the organic semiconductor single crystal layer can be measured with an atomic force microscope.

[0024] The thickness of one molecular layer of the organic semiconductor single crystal layer is preferably 2 to 6 nm, more preferably 2 to 4 nm. The thickness of one molecular layer of the organic semiconductor single crystal layer can be measured by combining single crystal X-ray structure analysis and atomic force microscope observation.

[0025] The organic semiconductor single crystal layer is composed of a single domain or multiple domains, and preferably composed of a single domain. The domain of the organic semiconductor single crystal layer can be measured by single crystal X-ray diffraction. The organic semiconductor single crystal layer is preferably 0.0025 mm 2 More preferably, 0.005 mm 2 More preferably, 0.5 mm 2 More preferably, 2.0 mm or more 2 The single domain has a continuous area of ​​at least 100 nm. The area of ​​the single domain of the organic semiconductor single crystal layer may be the same as the above-mentioned preferred area of ​​the AOS. The area of ​​the organic semiconductor single crystal layer may be the same as the area of ​​the single domain.

[0026] It should be understood that the organic semiconductor single crystal layer in the complementary semiconductor device of the present disclosure may incorporate a separated organic semiconductor single crystal layer having a single domain with the above-mentioned preferred continuous area. For example, the organic semiconductor single crystal layer having the above-mentioned preferred continuous area single domain may be separated into a plurality of organic semiconductor single crystal layers and incorporated into the organic semiconductor device, and / or the unnecessary portion of the organic semiconductor single crystal layer having the above-mentioned preferred continuous area single domain may be etched by photolithography or the like, separated into a plurality of organic semiconductor single crystal layers and incorporated into the complementary semiconductor device. By separating each organic semiconductor single crystal layer in the complementary semiconductor device, it is possible to electrically isolate it from other elements. It can be confirmed that each separated organic semiconductor single crystal layer is obtained from a single crystal film with the same crystal axis direction by measuring with single crystal X-ray diffraction or electron beam diffraction or by observing with a polarizing microscope.

[0027] The organic semiconductor single crystal layer is preferably 0.5 cm 2 / V·s or more, preferably 3.0 cm 2 / V·s or more, and more preferably 5.0 cm 2 / V·s or more, and even more preferably 7.5 cm 2 / V·s or more, and even more preferably 10 cm 2 / V s or more. The mobility of the organic semiconductor single crystal layer can be calculated from the measurement results of the organic field-effect transistor.

[0028] There is no particular limitation on the type of organic semiconductor constituting the organic semiconductor single crystal layer, but for example, a polycyclic aromatic compound having four or more rings, or a polycyclic compound having four or more rings composed of one or more unsaturated five-membered heterocyclic compounds and multiple benzene rings can be used.

[0029] In addition, the organic semiconductor constituting the organic semiconductor single crystal layer is preferably a material with high self-condensation function, such as a p-type organic semiconductor Cn-DNBDT-NW having high mobility and represented by the following formula (1).

[0030] [ka] In formula (1), n ​​can be 1 to 14. The self-condensing function means that the molecules have a tendency to spontaneously aggregate and crystallize when precipitated from a solvent.

[0031] Other examples of the organic semiconductor constituting the organic semiconductor single crystal layer are shown in the following formulas (2) to (5).

[0032] [ka]

[0033] In formula (2), R3, R4, R5 and R6 are each independently a hydrogen atom or an alkyl group having 1 to 14 carbon atoms. The alkyl group may contain a heteroatom (typically selected from an oxygen atom and a sulfur atom), and the hydrogen atom in the alkyl group may be substituted with a substituent such as a halogen atom. Due to the self-aggregation ability, it is preferable that R4=R5, and it is preferable that R3=R6. From the viewpoint of solubility, it is preferable that R4 and R5 are hydrogen atoms, and R3 and R6 are each independently an alkyl group having 1 to 14 carbon atoms, or R3 and R6 are hydrogen atoms, and R4 and R5 are each independently an alkyl group having 1 to 14 carbon atoms. More preferably, R3 and R6 are hydrogen atoms, and R4 and R5 are each independently an alkyl group having 1 to 14 carbon atoms. Due to the self-aggregation ability, the alkyl group preferably has 4 to 12 carbon atoms, and more preferably 6 to 10 carbon atoms.

[0034] [ka]

[0035] In formula (3), R7, R8, R9 and R10 are each independently a hydrogen atom or an alkyl group having 1 to 14 carbon atoms. The alkyl group may contain a heteroatom (typically selected from an oxygen atom and a sulfur atom), and the hydrogen atom in the alkyl group may be substituted with a substituent such as a halogen atom. For reasons of self-aggregation ability, it is preferable that R7=R9, and it is preferable that R8=R10. From the viewpoint of solubility, it is preferable that R7 and R9 are hydrogen atoms, and R8 and R10 are each independently an alkyl group having 1 to 14 carbon atoms, or R8 and R10 are hydrogen atoms, and R7 and R9 are each independently an alkyl group having 1 to 14 carbon atoms. More preferably, R8 and R10 are hydrogen atoms, and R7 and R9 are each independently an alkyl group having 1 to 14 carbon atoms. For reasons of self-aggregation ability, the alkyl group preferably has 6 to 13 carbon atoms, and more preferably 8 to 10 carbon atoms.

[0036] [ka]

[0037] In formula (4), R11, R12, R13 and R14 are each independently a hydrogen atom or an alkyl group having 1 to 14 carbon atoms. The alkyl group may contain a heteroatom (typically selected from an oxygen atom and a sulfur atom), and the hydrogen atom in the alkyl group may be substituted with a substituent such as a halogen atom. Due to the self-aggregation ability, it is preferable that R11=R13, and it is preferable that R12=R14. From the viewpoint of solubility, it is preferable that R11 and R13 are hydrogen atoms, and R12 and R14 are each independently an alkyl group having 1 to 14 carbon atoms, or R12 and R14 are hydrogen atoms, and R11 and R13 are each independently an alkyl group having 1 to 14 carbon atoms. More preferably, R12 and R14 are hydrogen atoms, and R11 and R13 are each independently an alkyl group having 1 to 14 carbon atoms. Due to the self-aggregation ability, the alkyl group preferably has 5 to 12 carbon atoms, and more preferably 8 to 10 carbon atoms.

[0038] [ka]

[0039] In formula (5), R15, R16, R17 and R18 are each independently a hydrogen atom or an alkyl group having 1 to 14 carbon atoms. The alkyl group may contain a heteroatom (typically selected from an oxygen atom and a sulfur atom), and the hydrogen atom in the alkyl group may be substituted with a substituent such as a halogen atom. Due to the self-aggregation ability, it is preferable that R15=R17, and it is preferable that R16=R18. From the viewpoint of solubility, it is preferable that R16 and R18 are hydrogen atoms, and R15 and R17 are each independently an alkyl group having 1 to 14 carbon atoms, or R15 and R17 are hydrogen atoms, and R16 and R18 are each independently an alkyl group having 1 to 14 carbon atoms. More preferably, R16 and R18 are hydrogen atoms, and R15 and R17 are each independently an alkyl group having 1 to 14 carbon atoms. Due to the self-aggregation ability, the alkyl group preferably has 5 to 12 carbon atoms, and more preferably 8 to 10 carbon atoms.

[0040] Further examples of organic semiconductors constituting the organic semiconductor single crystal layer are shown in the following formulae (6) to (15). In the formulae (6) to (15), R can be a linear alkyl, a branched alkyl, a cyclic alkyl, a fluorinated linear or branched alkyl, triisopropylsilylethynyl, phenyl, or the like.

[0041] [ka]

[0042] [ka]

[0043] [ka]

[0044] [ka]

[0045] [ka]

[0046] [ka]

[0047] [ka]

[0048] [ka]

[0049] [ka]

[0050] [ka]

[0051] Whether or not the organic semiconductor single crystal layer is a single crystal can be confirmed by observing it with a transmission electron microscope (TEM).

[0052] The substrate used in the complementary semiconductor device of the present disclosure may be a substrate conventionally used in semiconductor processes, a flexible substrate, or the like, and is preferably a flexible substrate. The flexible substrate is a film-like substrate, and is preferably a polyimide substrate, a polyphenylene sulfide substrate, or a silicone substrate. The thickness of the substrate is preferably 0.001 to 1 mm, and more preferably 0.002 to 0.1 mm. By using a flexible substrate, the complementary semiconductor device of the present disclosure can exhibit substantially the same characteristics as in an unstrained state even when strained to a strain ε of preferably 0.03% or more, more preferably 0.04% or more, and even more preferably 0.08% or more. The strain ε (%) is expressed by the formula: ε=h s / 2R×100 (in the formula, h s is the thickness of the substrate on which the complementary semiconductor device is placed, and R is the bending radius. For example, when a complementary semiconductor device having a thickness of 200 nm placed on a polyimide substrate having a thickness of 10 μm is wrapped around a glass cylinder with a radius of 6 mm, the strain is calculated as ε (%) = 10 μm / (2 × 6 mm) × 100.

[0053] The distance between the organic semiconductor single crystal layer and the AOS layer is 1 mm or less, preferably 0.8 mm or less, more preferably 0.5 mm or less, even more preferably 0.3 mm or less, and even more preferably 0.1 mm or less. The distance between the organic semiconductor single crystal layer and the AOS layer refers to the shortest distance between the organic semiconductor single crystal layer and the AOS layer. When the distance between the organic semiconductor single crystal layer and the AOS layer is within the above range, high-speed operation of the complementary semiconductor device is possible, and the complementary semiconductor device can be highly integrated. When at least a part of the p-type organic semiconductor single crystal layer overlaps the n-type amorphous oxide inorganic semiconductor layer when viewed from a direction perpendicular to the main surface of the p-type organic semiconductor single crystal layer, as exemplified in FIG. 1, the distance between the organic semiconductor single crystal layer and the AOS layer corresponds to the thickness of the intermediate layer of the complementary semiconductor device. When the p-type organic semiconductor single crystal layer is arranged so that it does not overlap the n-type amorphous oxide inorganic semiconductor layer, as illustrated in Figure 18, the distance between the organic semiconductor single crystal layer and the AOS layer corresponds to the distance between the end of the organic semiconductor single crystal layer and the end of the AOS layer.

[0054] The protective layer is disposed between the AOS layer and the organic semiconductor single crystal layer. The protective layer may be adjacent to the AOS layer or not, but is preferably adjacent to the AOS layer. The protective layer may be adjacent to the organic semiconductor single crystal layer or not. The protective layer can protect the AOS layer from the influence of the manufacturing process of the complementary semiconductor device. The protective layer can also prevent components in the atmosphere, such as water and oxygen, from reacting with the AOS layer. This can prevent deterioration of the AOS layer and improve the long-term stability of the complementary semiconductor device. The protective layer can be disposed parallel to the main surface of the AOS layer, but in addition, it can be disposed so as to protect the end surface of the AOS layer.

[0055] The thickness of the protective layer is preferably 1000 nm or less, more preferably 500 nm or less, even more preferably 250 nm or less, even more preferably 100 nm or less, and even more preferably 75 nm or less. The lower limit of the thickness of the protective layer is preferably 25 nm or more. The thinner the protective layer is, the easier it is to form a protective layer with excellent surface flatness, and the deterioration of the characteristics of the complementary semiconductor device can be suppressed. By setting the lower limit of the thickness of the protective layer within the above range, a better barrier function can be obtained.

[0056] The protective layer preferably includes a first organic film and a second organic film, the first organic film being located on the n-type amorphous metal oxide inorganic semiconductor layer side and the second organic film being located on the p-type organic semiconductor single crystal layer side, the first organic film being composed of an organic solvent-soluble polymer, and the second organic film being a vacuum-deposited film.

[0057] The organic solvent-soluble polymer means a polymer that is soluble in an organic solvent, and includes those that are polymers or oligomers when dissolved in an organic solvent. The organic solvent is a solvent that can dissolve the organic solvent-soluble polymer but does not dissolve the AOS layer, such as butyl acetate, toluene, xylene, acetonitrile, etc.

[0058] The first organic film, which is made of an organic solvent-soluble polymer, can be formed on the AOS layer by a mild method called solution processing without damaging the AOS layer. The solution process does not use vacuum or radical reactions, so it is possible to avoid further formation of oxygen defects due to oxygen elimination, and has the advantage of being very low reactivity with the AOS layer. The solution process does not involve reactions that generate acids. Therefore, the first organic film can be formed directly on the AOS layer without causing substantial damage. The second organic film, which is a vacuum deposition film, is formed on the first organic film, so damage to the AOS layer caused by the vacuum process can be suppressed.

[0059] Chemical vapor deposition films (vacuum deposition films) such as parylene can be deposited by chemical vapor deposition (CVD), which does not require heating of the substrate. However, AOS layers are extremely sensitive to the environment and are easily damaged by the vacuum environment and radicals generated during deposition of the vacuum deposition film.

[0060] In contrast, by forming a first organic film containing an organic solvent-soluble polymer on the AOS layer by solution processing, the first organic film can be disposed without causing substantial damage to the AOS layer.

[0061] The first organic film can protect the AOS layer from radicals and the vacuum environment generated during the formation of the vacuum deposition film. Therefore, the second organic film can be formed on the first organic film without substantially damaging the AOS layer. The first organic film has a low density and therefore a low gas barrier performance, allowing oxygen to permeate to a certain extent. The density of the first organic film is preferably 0.4 to 1.3 g / cm. 3 , more preferably 0.5 to 1.2 g / cm 3 , and more preferably 0.6 to 1.1 g / cm 3 , and more preferably 0.7 to 1.0 g / cm 3 On the other hand, since the second organic film, which has a relatively high density, is located on top of the first organic film, moisture and oxygen cannot substantially pass through the protective layer. The density of the first organic film is calculated from X-ray reflectivity measurement. By fitting the X-ray reflectivity data, the film thickness and film density can be simultaneously estimated as fitting parameters.

[0062] The second organic film, which is a vacuum deposition film, is formed by a dry process, unlike the first organic film, which is formed by a solution process. Therefore, the second organic film is dense and has a high barrier effect. The density of the second organic film, which is a vacuum deposition film, is higher than the density of the first organic film containing an organic solvent-soluble polymer. The density of the second organic film is preferably 1.0 to 1.5 g / cm. 3 , more preferably more than 1.0 to 1.45 g / cm 3 The density of the second organic film is measured by ASTM D1505 or ASTM E1461.

[0063] The protective layer may have any shape and may be a protective film, a protective sheet, or the like.

[0064] The first organic film has a thickness of preferably 10 nm or more, more preferably 13 nm or more, and even more preferably 16 nm or more. By having the first organic film have the above-mentioned preferred thickness, damage to the AOS layer caused by the vacuum process and the radicals generated when the second organic film is vacuum-deposited can be further suppressed. The upper limit of the thickness of the first organic film is not particularly limited, and may be, for example, 1 mm or less, but since the total thickness of the complementary semiconductor device becomes large, the thickness of the first organic film is preferably small, and is preferably 1000 nm or less, more preferably 500 nm or less, and may be 100 nm or less, 50 nm or less, or 30 nm or less.

[0065] The second organic film has a thickness of preferably 100 to 300 nm, more preferably 120 to 200 nm. When the second organic film, which is a vacuum deposition film, has the above-mentioned preferred thickness, damage to the AOS layer caused by the manufacturing process of the complementary semiconductor device and damage to the AOS layer caused by long-term exposure of the complementary semiconductor device to the atmosphere can be further suppressed. In addition, although the vacuum deposition film is a relatively hard polymer film, the upper limit of the thickness of the second organic film is within the above-mentioned preferred range, the effect on flexibility when a complementary semiconductor device is formed on a flexible substrate can be reduced.

[0066] The organic solvent soluble polymer is preferably an acrylic polymer, a styrene polymer, a fluorine-based polymer, a thermally crosslinkable polymer, or a combination thereof.

[0067] The acrylic polymer is preferably polymethylmethacrylate (PMMA), polyadamantylmethacrylate (PADMA), or polycyclohexylmethacrylate (PCMA).

[0068] The styrenic polymer is preferably polystyrene, poly-α-methylstyrene (PαMS), poly-4-methylstyrene (PMS), or polyvinylphenol (PVP).

[0069] The fluoropolymer is preferably CYTOP® or Teflon® AF.

[0070] The thermally crosslinkable polymer is preferably an epoxy resin or a thermosetting cycloolefin polymer.

[0071] The vacuum deposition film is preferably parylene. Parylene is preferable because it is formed sequentially at about room temperature and has high density and uniformity. Parylene also includes its derivatives.

[0072] The protective layer is not limited to the above-mentioned configuration, and may preferably be a protective layer including a first organic film and an inorganic oxide insulator film (hereinafter referred to as a second protective layer). In the second protective layer, the first organic film is located on the n-type amorphous metal oxide inorganic semiconductor layer side, and the inorganic oxide insulator film is located on the p-type organic semiconductor single crystal layer side. The presence of the first organic film between the AOS layer and the inorganic oxide insulator film can suppress damage to the AOS layer when the inorganic oxide insulator film is formed.

[0073] The first organic film has the same structure as the first organic film described above, but has a thickness of preferably 50 nm or more, more preferably 75 nm or more, and even more preferably 100 nm or more. When the first organic film has the preferred thickness, damage to the AOS layer during the formation of the inorganic oxide insulator film can be further suppressed.

[0074] If an inorganic oxide insulator film such as an AlOx layer is formed directly on the AOS layer by atomic layer deposition (ALD), the AOS will deteriorate because the ALD process involves heating the substrate in a vacuum and using water.If an inorganic oxide insulator film is formed directly on the AOS layer by sputtering, the AOS will deteriorate because the sputtering process is a vacuum process.

[0075] The first organic film can protect the AOS layer from moisture accompanying the ALD method or the vacuum environment of the sputtering process. Therefore, an inorganic oxide insulator film can be formed on the first organic film without substantially damaging the AOS layer. The first organic film has a low density and therefore a low gas barrier performance, allowing oxygen to permeate to a certain extent. On the other hand, since an inorganic oxide insulator film having a dense structure is located on the first organic film, moisture and oxygen cannot substantially pass through the second protective layer.

[0076] Preferably, the protective layer further includes a second organic film, which is a vacuum-deposited film located between the first organic film and the inorganic oxide insulator film. By positioning the second organic film, which is a vacuum-deposited film, between the first organic film and the inorganic oxide insulator film, damage to the AOS layer during the formation of the inorganic oxide insulator film can be further suppressed. In addition, the AOS layer can be protected from the attack of radicals caused by the CVD process for forming the second organic film. When the second protective layer includes the second organic film, the preferred thickness of the first organic film may be thin or may be 10 nm or more.

[0077] The second organic film has the same configuration as the second organic film described above, but the thickness of the second organic film in the second protective layer is preferably 10 to 40 nm, more preferably 15 to 35 nm. Since the second organic film has a high density, it can obtain a barrier effect together with the inorganic oxide insulator even in the above preferred thickness range, so that the total thickness of the second protective layer can be reduced.

[0078] The second protective layer of the hybrid structure including the first organic film, the second organic film, and the inorganic oxide insulator film has a strong barrier effect, in which the first organic film including an organic solvent-soluble polymer and the second organic film, which is a vacuum deposition film, function as a buffer layer against damage caused by the ALD process or the sputtering process when forming the inorganic oxide insulator film.

[0079] The thickness of the inorganic oxide insulator film is preferably 5 to 100 nm, more preferably 15 to 75 nm, and even more preferably 25 to 55 nm. Since the inorganic oxide insulator film has a higher barrier effect than the second organic film composed of a polymer, the total thickness of the second protective layer can be reduced while exhibiting a good barrier effect within the above preferred thickness range. Since the inorganic oxide insulator film has a dense structure and is relatively hard, the thickness of the inorganic oxide insulator film is preferably 100 nm or less from the viewpoint of ensuring the flexibility of the electronic element or electronic device including the second protective layer.

[0080] When the second protective layer includes a first organic film containing an organic solvent-soluble polymer, a second organic film made of a vacuum deposition film, and an inorganic oxide insulator film, the total thickness of the second protective layer is preferably 100 nm or less, more preferably 90 nm or less, and even more preferably 80 nm or less. When the second organic film made of a vacuum deposition film is included, the total thickness of the second protective layer can be reduced. The lower limit of the thickness of the second protective layer is preferably 25 nm or more, more preferably 40 nm or more. By having the thickness of the second protective layer in the above preferred range, the thickness of the electronic element or electronic device having the second protective layer can be reduced while obtaining a good barrier function.

[0081] The inorganic oxide insulator of the inorganic oxide insulator film is preferably AlOx, HfOx, ZrOx, SiOx, TiOx, or a combination thereof. x may be a value that satisfies the stoichiometric composition or may not. The inorganic oxide insulator film has a high density and cannot be permeated by large molecules such as water molecules and oxygen in the air, so it has a high barrier effect against moisture and gas.

[0082] The second protective layer preferably has a three-layer hybrid structure of a PMMA layer as the first organic film, a parylene layer as the second organic film, and an AlOx layer as the inorganic oxide insulator film. The PMMA / parylene / AlOx hybrid three-layer protective layer can provide strong protection without degrading the performance of the AOS layer.

[0083] The gate insulating film, the gate electrode, and the source / drain electrodes (S / D electrodes) can be made of conventional materials.

[0084] The complementary semiconductor device of the present disclosure is composed of a p-type structure and an n-type structure. The following describes possible examples of the complementary semiconductor device in which the organic semiconductor single crystal layer is arranged so that the organic semiconductor single crystal layer and the AOS layer completely overlap each other when viewed from the direction perpendicular to the main surface of the organic semiconductor single crystal layer.

[0085] When an n-type transistor has a bottom gate-top contact structure, the p-type structure / n-type structure of the complementary semiconductor device can have the bottom gate-top contact / bottom gate-top contact structure of Fig. 1, the bottom gate-bottom contact / bottom gate-top contact structure of Fig. 2, the top gate-top contact / bottom gate-top contact structure of Fig. 3, or the top gate-bottom contact / bottom gate-top contact structure of Fig. 4. Taking Fig. 1 as an example, a gate electrode 20 of an n-type structure, a gate insulating layer 22, an n-type amorphous metal oxide inorganic semiconductor layer 24, and an S / D electrode 26 are disposed on a substrate 10, and a gate electrode 40 of a p-type structure, a gate insulating layer 42, a p-type organic semiconductor single crystal layer 44, and an S / D electrode 46 are disposed with a protective layer 30 sandwiched therebetween.

[0086] When the n-type transistor has a bottom-gate-bottom-contact structure, the p-type structure / n-type structure of the complementary semiconductor device can have the bottom-gate-top-contact / bottom-gate-bottom-contact structure of FIG. 5, the bottom-gate-bottom-contact / bottom-gate-bottom-contact structure of FIG. 6, the top-gate-top-contact / bottom-gate-bottom-contact structure of FIG. 7, or the top-gate-bottom-contact / bottom-gate-bottom-contact structure of FIG. 8.

[0087] When the n-type transistor has a top gate-top contact structure, the p-type structure / n-type structure of the complementary semiconductor device can have the bottom gate-top contact / top gate-top contact structure of Fig. 9, the bottom gate-bottom contact / top gate-top contact structure of Fig. 10, the top gate-top contact / top gate-top contact structure of Fig. 11, or the top gate-bottom contact / top gate-top contact structure of Fig. 12. When the n-type structure has a top gate structure and the p-type structure has a bottom gate structure like the structure of Fig. 9, the structure shown in Fig. 13 may be used in which the top gate electrode of the n-type structure and the bottom gate electrode of the p-type structure are common, and the protective layer and the p-type gate insulating layer are common. The same applies to the structure of Fig. 10.

[0088] When the n-type transistor has a top gate-bottom contact structure, the p-type structure / n-type structure of the complementary semiconductor device can have the bottom gate-top contact / top gate-bottom contact structure of Fig. 14, the bottom gate-bottom contact / top gate-bottom contact structure of Fig. 15, the top gate-top contact / top gate-bottom contact structure of Fig. 16, or the top gate-bottom contact / top gate-bottom contact structure of Fig. 17. When the n-type structure has a top gate structure and the p-type structure has a bottom gate structure as in the structures of Figs. 14 and 15, the top gate electrode of the n-type structure and the bottom gate electrode of the p-type structure may be common, and the protective layer and the p-type gate insulating layer may be common, as in the structure of Fig. 13.

[0089] Below, we will explain possible examples of complementary semiconductor devices in which the organic semiconductor single crystal layer is arranged so that the organic semiconductor single crystal layer does not overlap with the AOS layer when viewed from a direction perpendicular to the main surface of the organic semiconductor single crystal layer.

[0090] When the n-type transistor has a bottom gate-top contact structure, the n-type structure / p-type structure of the complementary semiconductor device can have the bottom gate-top contact / bottom gate-top contact structure of Fig. 18, the bottom gate-top contact / top gate-top contact structure of Fig. 19, the bottom gate-top contact / bottom gate-bottom contact structure of Fig. 20, or the bottom gate-top contact / top gate-bottom contact structure of Fig. 21. When the n-type structure has a top contact structure and the p-type structure has a bottom gate structure as in Fig. 18, the S / D electrodes of the n-type structure and the gate electrode of the p-type structure may be formed in the same layer of the same material to have a structure shown in Fig. 22 in which the protective layer and the p-type gate insulating layer are shared. The same applies to the structure in Fig. 20.

[0091] When the n-type transistor has a bottom-gate-bottom-contact structure, the n-type structure / p-type structure of the complementary semiconductor device can have the bottom-gate-bottom-contact / bottom-gate-top-contact structure of Figure 23, the bottom-gate-bottom-contact / top-gate-top-contact structure of Figure 24, the bottom-gate-bottom-contact / bottom-gate-bottom-contact structure of Figure 25, or the bottom-gate-bottom-contact / top-gate-bottom-contact structure of Figure 26.

[0092] When the n-type transistor has a top gate-top contact structure, the n-type structure / p-type structure of the complementary semiconductor device can have the top gate-top contact / bottom gate-top contact structure of Fig. 27, the top gate-top contact / top gate-top contact structure of Fig. 28, the top gate-top contact / bottom gate-bottom contact structure of Fig. 29, or the top gate-top contact / top gate-bottom contact structure of Fig. 30. When the n-type structure has a top gate structure and the p-type structure has a bottom gate structure as in Fig. 27, the gate of the n-type structure and the gate electrode of the p-type structure may be formed in the same layer using the same material to have a structure shown in Fig. 31 in which the protective layer and the p-type gate insulating layer are shared. The same applies to the structure in Fig. 29.

[0093] When the n-type transistor has a top gate-bottom contact structure, the n-type structure / p-type structure of the complementary semiconductor device can have the top gate-bottom contact / bottom gate-top contact structure of Fig. 32, the top gate-bottom contact / top gate-top contact structure of Fig. 33, the top gate-bottom contact / bottom gate-bottom contact structure of Fig. 34, or the top gate-bottom contact / top gate-bottom contact structure of Fig. 35. When the n-type structure has a top gate structure and the p-type structure has a bottom gate structure as in Fig. 32, the protective layer and the gate insulating layer of the p-type structure may be in common, as in Fig. 31. The same applies to the structure in Fig. 33.

[0094] 1 to 35, the AOS layer may be formed on a substrate, a gate insulating layer, a gate electrode, an S / D electrode, or a combination thereof. A protective layer, an S / D electrode, a gate insulating layer, a gate electrode, an organic semiconductor single crystal layer, or a combination thereof may be formed adjacent to the AOS layer.

[0095] The method disclosed herein is a method for manufacturing an inorganic / organic hybrid complementary semiconductor device, comprising: preparing a substrate; forming an n-type structure on the substrate; forming a protective layer on the n-type structure; and forming a p-type structure on the protective layer, wherein forming the n-type structure comprises preparing a precursor solution of an n-type amorphous metal oxide inorganic semiconductor containing a metal salt using a sol-gel method, applying the precursor solution onto the substrate to form a precursor film, and heat-treating the precursor film at 350 to 400° C. to form an n-type amorphous metal oxide inorganic semiconductor layer, and forming the p-type structure comprises forming a p-type organic semiconductor single crystal layer using a coating method, and forming the p-type structure comprises forming a p-type organic semiconductor single crystal layer using a coating method, and forming the p-type structure comprises forming a p-type organic semiconductor single crystal layer using a coating method. The present invention relates to a method for manufacturing an inorganic / organic hybrid complementary semiconductor device, in which the p-type organic semiconductor single crystal layer is arranged so that at least a part of the p-type organic semiconductor single crystal layer overlaps the n-type amorphous metal oxide inorganic semiconductor layer or the p-type organic semiconductor single crystal layer does not overlap the n-type amorphous metal oxide inorganic semiconductor layer when viewed from a direction perpendicular to the main surface of the p-type organic semiconductor single crystal layer, the distance between the p-type organic semiconductor single crystal layer and the n-type amorphous metal oxide inorganic semiconductor layer is 1 mm or less, and the n-type amorphous metal oxide inorganic semiconductor layer has a distribution of oxygen defects in the thickness direction in which the amount of oxygen defects is greater on the p-type organic semiconductor single crystal layer side than on the substrate side. The n-type structure and the p-type structure can have the above-mentioned exemplary configurations of the n-type structure and the p-type structure described with reference to Figures 1 to 35, respectively.

[0096] In the method of the present disclosure, a solution process is used as a film formation process for the amorphous metal oxide inorganic semiconductor layer (AOS layer) and the organic semiconductor single crystal layer. Since the AOS layer and the organic semiconductor single crystal layer can be formed in the atmosphere using a solution process, special equipment such as a high vacuum chamber used in a dry process is not required, and they can be manufactured at low cost. In particular, when a large area is desired, there is no need to enlarge a special equipment such as a high vacuum chamber, and the cost reduction effect is even greater than that of the dry process.

[0097] As a process for forming an AOS layer, first, a precursor solution of AOS is prepared using a sol-gel method as shown in FIG. 36. A metal salt is dissolved in water or an organic solvent, and then hydrolyzed and condensed to form a MOM structure, and the precursor is solated to prepare a precursor solution. For example, when an IZO layer is formed as the AOS layer, a precursor solution is prepared by mixing indium nitrate and zinc nitrate. M in FIG. 36 is a metal cation element contained in the AOS, and examples of the metal elements include In, Zn, Ga, Al, Sn, and Y. R is an alkyl group. Examples of X include chloride salts, nitrate salts, and acetate salts. The solvent can be a solvent in which oxygen can bond or crosslink to a metal ion, such as water, an aqueous solution, or an alcohol, and contains O and H, may contain C, and may further contain other elements such as N, F, and Cl. The solvent can be, for example, 2-methoxyethanol.

[0098] Next, the precursor solution is applied onto the substrate to form a thin film of the precursor. The method of applying the precursor solution is preferably a spin coat method, a bar coat method, a spray coat method, a dip coat method, an inkjet method, a flexographic printing method, or a gravure printing method, more preferably a spin coat method, a bar coat method, a spray coat method, a dip coat method, or an inkjet method, and even more preferably a spin coat method. FIG. 37 shows a schematic diagram of an embodiment in which the precursor solution is spin-coated onto the substrate to form a thin film of the precursor. The thin film of the precursor is soft-baked (heat-treated) to remove the solvent, and then hard-baked (heat-treated) to form a dense amorphous metal oxide inorganic semiconductor layer.

[0099] The spin-coating method has the advantage of good reproducibility in the deposition of the active layer and high uniformity of the processed film. The thin film formed by the spin-coating method before the heat treatment contains a large amount of impurities such as nitrogen used in the preparation of the precursor solution, and is completely different from that obtained by the dry process. However, the impurities such as nitrogen are released as gas by the heat treatment, and the parts where the impurities have disappeared can be bridged with oxygen.

[0100] The soft bake for removing the solvent is preferably carried out at 100 to 150° C. By carrying out the heat treatment at the above-mentioned preferred temperature, the solvent can be removed more satisfactorily.

[0101] The hard bake is performed at 350 to 400°C. By performing the heat treatment at a low temperature of 400°C or less, it is possible to form an amorphous metal oxide inorganic semiconductor layer without damaging the flexible substrate, even when the flexible substrate is included. In addition, a high heat treatment temperature makes it easier to form the MOM structure, increases the crystallinity, increases the shallow donor concentration, and improves the mobility, but if the temperature is too high, the on-state voltage (V ON ) tends to cause a negative voltage shift and a high off-current, which increases power consumption, so from this viewpoint as well, the heat treatment temperature is set to 400°C or less. If the heat treatment temperature is less than 350°C, organic residues are generated in the amorphous metal oxide inorganic semiconductor layer, and the organic residues act as electron traps, so the heat treatment temperature is set to 350°C or more.

[0102] The lower limit of the heat treatment temperature is preferably 355° C. or higher, more preferably 360° C. or higher, and even more preferably 365° C. or higher. The upper limit of the heat treatment temperature is preferably less than 400° C., more preferably 395° C. or lower, even more preferably 390° C. or lower, even more preferably 385° C. or lower, even more preferably 380° C. or lower, and even more preferably 375° C. or lower. By performing heat treatment within the above preferred temperature range, power consumption and organic residue can be further reduced.

[0103] The area of ​​the AOS layer formed by this method is preferably 2 mm 2 More preferably, 10 mm 2 More preferably, 100 mm 2 More preferably, 1000 mm 2 More preferably, 10,000 mm 2 The upper limit of the area of ​​the AOS layer is not particularly limited, but is limited by the size of the manufacturing equipment, for example, 10 m 2The AOS layer in the complementary semiconductor device of the present disclosure can have a large area as described above at low cost because it is formed by a solution process.

[0104] (Patterning of AOS layer) The AOS layer formed by solution processing is preferably patterned using a photoradical initiator and a sodium carbonate developer. Figure 38 shows a schematic diagram of the patterning operation using a photoradical initiator and a sodium carbonate developer.

[0105] The AOS layer formed by solution processing is very sensitive to external environments such as oxygen, water, and organic solvents. Photoacid generators and strong alkaline developers such as tetramethylammonium hydroxide (TMAH) used in conventional photolithography processes can damage the AOS layer. In contrast, by patterning using a photoradical initiator and a sodium carbonate developer (1% by mass Na2CO3 solution), which is a milder solvent than strong alkaline developers, fine patterning can be achieved without changing the properties of the AOS layer formed by solution processing.

[0106] As shown in Fig. 39, the metal constituting the S / D electrode can be evaporated through a shadow mask to form the S / D electrode on the AOS layer. Resist PDM may be used for patterning the S / D electrode. The metal constituting the S / D electrode can be, for example, Al.

[0107] FIG. 40 is a schematic diagram showing an example of an n-type TFT including an AOS (also called MOS) layer on which S / D electrodes are formed.

[0108] Preferably, forming the protective layer includes preparing an organic solvent having a polymer dissolved therein, applying the organic solvent having the polymer dissolved therein onto the n-type structure to form a first organic film, and forming a second organic film, which is a vacuum deposited film, on the first organic film by using a chemical vapor deposition method.

[0109] The organic solvent and the polymer can be mixed to prepare an organic solvent in which the polymer is dissolved. The concentration of the polymer can be changed depending on the desired thickness of the first organic film, and is, for example, 1 to 80 mg / mL, 2 to 70 mg / mL, or 3 to 60 mg / mL.

[0110] A first organic film is formed on the n-type structure by applying an organic solvent in which a polymer is dissolved. The application method is preferably a spin coating method, a bar coating method, a spray coating method, a dip coating method, an inkjet method, a flexographic printing method, or a gravure printing method, more preferably a spin coating method, a bar coating method, a spray coating method, a dip coating method, or an inkjet method, and further preferably a spin coating method.

[0111] A second organic film, which is a vacuum deposition film, is formed on the first organic film by using chemical vapor deposition (CVD). The second organic film, which is a vacuum deposition film, is formed by CVD. CVD is a light vacuum process, and is preferable in terms of film formation speed, processing area, denseness, and uniformity.

[0112] The organic semiconductor single crystal layer may be formed directly on the gate insulating layer, the S / D electrodes, the protective layer, or a combination thereof by using a coating method.

[0113] The coating method is a method in which an organic semiconductor is dissolved in an organic solvent to prepare an organic semiconductor solution, the organic semiconductor solution is coated on a substrate, and the organic solvent is evaporated to form a film. As the organic solvent, any organic solvent that has been conventionally used in the coating method can be used, such as toluene, dichlorobenzene, etc.

[0114] The area of ​​the organic semiconductor single crystal layer formed by the coating method is preferably 2 mm 2 More preferably, 10 mm 2 More preferably, 100 mm 2 More preferably, 1000 mm 2 More preferably, 10,000 mm 2The upper limit of the area of ​​the organic semiconductor single crystal layer is not particularly limited, but is limited by the size of the manufacturing equipment, for example, 10 m 2 Conventionally, when using the vapor phase growth method, the maximum thickness is 1 mm. 2 In contrast to the conventional method, which has only been able to obtain organic semiconductor single crystal films having an area of ​​about 100 nm, the organic semiconductor single crystal layer of the present method can have a large area as described above because it is formed by a solution process.

[0115] Preferably, forming the p-type organic semiconductor single crystal layer includes forming a p-type organic semiconductor single crystal film on a hydrophilic and water-insoluble first substrate by using a coating method, and applying water or an aqueous solution to the interface between the first substrate and the p-type organic semiconductor single crystal film to separate the p-type organic semiconductor single crystal film from the first substrate, and disposing the p-type organic semiconductor single crystal layer on a second substrate, the second substrate being at least one of a gate insulating layer and an S / D electrode of an n-type structure, a protective layer, or a combination thereof.

[0116] The p-type organic semiconductor single crystal film to be separated from the first substrate is disposed on the gate insulating layer, the S / D electrode, the protective layer, or a combination thereof to form an organic semiconductor single crystal layer. At least one of the gate insulating layer and the S / D electrode of the n-type structure, the protective layer, or a combination thereof is called the second substrate. The second substrate refers to a substrate located on a surface that contacts the p-type organic semiconductor single crystal layer when the p-type organic semiconductor single crystal layer is disposed. According to this method for forming an organic semiconductor single crystal layer, even if the second substrate has a hydrophobic, solvent-soluble, non-heat-resistant property, or a combination thereof, and further, even if the second substrate has a concave, convex, or concave-convex portion, an organic semiconductor single crystal layer having a thin film thickness can be easily disposed on the second substrate.

[0117] As the coating method, a method that has been conventionally used can be used, such as an edge casting method, a continuous edge casting method, a drop casting method, a spin coating method, a printing method (an inkjet method or a gravure printing method), a dispenser method, a spray method, a dip coating method, a die coater method, a roll coater method, a bar coater method, a blade coating method, or the like.

[0118] The first substrate is a hydrophilic substrate having a contact angle of water of preferably 20 degrees or less, more preferably 10 degrees or less. The first substrate is water-insoluble, and can be, for example, mica or glass. Since the first substrate is water-insoluble, when water or an aqueous solution is applied to the interface between the first substrate and the organic semiconductor single crystal film, the components of the first substrate do not dissolve and adhere to or react with the organic semiconductor single crystal film, and a high-purity organic semiconductor single crystal film can be obtained. Furthermore, when water or an aqueous solution is applied to the interface between the first substrate and the organic semiconductor single crystal film, the shape of the first substrate is maintained without being distorted, and the organic semiconductor single crystal film can be separated from the first substrate without distorting the shape of the organic semiconductor single crystal film. Water-insoluble means that the glass does not substantially dissolve, decompose, or swell in water or an aqueous solution. The glass is preferably one whose surface has been hydrophilized by UV / ozone treatment or a hydrophilic coating material or the like.

[0119] Water or an aqueous solution is applied to the interface between the first substrate and the organic semiconductor single crystal film, and the organic semiconductor single crystal film is separated from the first substrate. Since the molecules of the organic semiconductor single crystal film applied to the first substrate are hydrophobic, the water or aqueous solution enters between the hydrophilic first substrate and the hydrophobic organic semiconductor single crystal film molecules, and the organic semiconductor single crystal film can be separated from the first substrate.

[0120] The contact angle of water or an aqueous solution of the hydrophilic first substrate is smaller than the contact angle of water or an aqueous solution of the hydrophobic organic semiconductor single crystal film, and the difference in the contact angle of water or an aqueous solution between the first substrate and the organic semiconductor single crystal film is preferably 80 degrees or more, more preferably 90 degrees or more. The contact angle of the organic semiconductor single crystal film is preferably 100 to 120 degrees. By having the difference in contact angle between the hydrophilic first substrate and the hydrophobic organic semiconductor single crystal film within the above-mentioned preferred range, the organic semiconductor single crystal film can be more stably peeled off from the first substrate.

[0121] The method of applying water or an aqueous solution to the interface between the first substrate and the organic semiconductor single crystal film is not particularly limited, and may be a method of immersing the first substrate on which the organic semiconductor single crystal film has been formed in water or an aqueous solution, or a method of dropping water or an aqueous solution onto the interface between the first substrate and the organic semiconductor single crystal film using a dropper.

[0122] The method of applying water or an aqueous solution to the interface between the first substrate and the organic semiconductor single crystal film preferably includes immersing the first substrate on which the organic semiconductor single crystal film has been formed in water or an aqueous solution. By immersing the first substrate on which the organic semiconductor single crystal film has been formed in water or an aqueous solution, the organic semiconductor single crystal film is separated from the first substrate in the water or aqueous solution, and an organic semiconductor single crystal film that is free-standing (self-standing) in the water or aqueous solution can be obtained. The free-standing organic semiconductor single crystal film can be disposed on the second substrate.

[0123] Arranging the organic semiconductor single crystal film on the second substrate preferably includes applying water or an aqueous solution to the interface between the first substrate and the organic semiconductor single crystal film while arranging the second substrate so as to be in contact with the organic semiconductor single crystal film formed on the first substrate, thereby separating the organic semiconductor single crystal film from the first substrate and disposing the organic semiconductor single crystal film on the second substrate. By separating the organic semiconductor single crystal film from the first substrate while arranging the second substrate so as to be in contact with the organic semiconductor single crystal film in this manner, the organic semiconductor single crystal film can be transferred from the first substrate onto the second substrate.

[0124] Alternatively, disposing the organic semiconductor single crystal film on the second substrate preferably includes immersing the first substrate on which the organic semiconductor single crystal film is formed in water or an aqueous solution, separating the organic semiconductor single crystal film from the first substrate in the water or aqueous solution to obtain a free-standing organic semiconductor single crystal film, and disposing the organic semiconductor single crystal film on the second substrate in the water or aqueous solution. In this manner, by disposing the free-standing organic semiconductor single crystal film on the second substrate in the water or aqueous solution, the organic semiconductor single crystal film can be easily transferred from the first substrate to the second substrate.

[0125] More preferably, disposing the organic semiconductor single crystal film on the second substrate includes immersing the first substrate, the organic semiconductor single crystal film, and the second substrate in water or an aqueous solution while disposing the second substrate so as to be in contact with the organic semiconductor single crystal film formed on the first substrate, and transferring the organic semiconductor single crystal film from the first substrate to the second substrate. In this way, by separating the organic semiconductor single crystal film from the first substrate while disposing the second substrate so as to be in contact with the organic semiconductor single crystal film in water or an aqueous solution, the organic semiconductor single crystal film can be more easily transferred from the first substrate to the second substrate.

[0126] Patterning of the organic semiconductor single crystal film is not particularly limited and can be performed by a conventional method, but is preferably performed using a dry film photoresist. When a dry film photoresist is used, damage to the organic semiconductor single crystal film can be suppressed more than when a coating type photoresist containing an organic solvent is used.

[0127] Preferably, forming the p-type organic semiconductor single crystal layer includes forming a p-type organic semiconductor single crystal film on a hydrophilic and water-insoluble third substrate by using a coating method, pressing the p-type organic semiconductor single crystal film onto the convex portions of a stamp having convex portions and concave portions, applying water or an aqueous solution to the interface between the third substrate and the p-type organic semiconductor single crystal film to transfer the p-type organic semiconductor single crystal film onto the convex portions, and pressing the p-type organic semiconductor single crystal film transferred onto the convex portions onto a fourth substrate to transfer the p-type organic semiconductor single crystal film onto the fourth substrate to obtain a patterned p-type organic semiconductor single crystal layer, wherein the fourth substrate is at least one of an n-type gate insulating layer and an S / D electrode, a protective layer, or a combination thereof.

[0128] At least one of the gate insulating layer and the S / D electrodes of the n-type structure, the protective layer, or a combination of them is called the fourth substrate. The fourth substrate is the one located on the surface that contacts the p-type organic semiconductor single crystal layer when the p-type organic semiconductor single crystal layer is transferred and patterned from the stamp and the protrusion.

[0129] According to this method, if a mold is prepared in advance, photolithography is unnecessary, and the cost is low. Since the p-type organic semiconductor single crystal layer can be patterned simultaneously with the transfer onto the stamp, patterning can be performed in a short time. Since the p-type organic semiconductor single crystal layer is physically patterned using the unevenness of the stamp, there is no need to use a solvent or laser, and various p-type organic semiconductor single crystal layers can be patterned, making it highly versatile. Since the stamp is simply pressed against the fourth substrate, the fourth substrate is not damaged by a solvent or the like. For example, even if the fourth substrate is soluble in a solvent that dissolves organic materials, a patterned p-type organic semiconductor single crystal layer can be formed. Since the stamp only comes into contact with water or an aqueous solution and does not need to come into contact with a solvent or be heated, there is no swelling or shrinkage of the stamp due to the solvent or heat. For example, a film that has been applied in advance and turned into a single crystal can be patterned.

[0130] In this method, a water-resistant p-type organic semiconductor single crystal film is formed on a hydrophilic and water-insoluble third substrate by using a coating method. The coating method is a method in which an organic material is dissolved in an organic solvent to prepare an organic solution, the organic solution is applied onto a substrate, and the organic solvent is evaporated to form a film. As the organic solvent, organic solvents conventionally used in coating methods can be used, such as toluene and dichlorobenzene.

[0131] As the coating method, a method that has been conventionally used can be used, for example, an edge casting method, a continuous edge casting method, a drop casting method, a spin coating method, a printing method (an inkjet method or a gravure printing method), a dispenser method, a spray method, a dip coating method, a die coater method, a roll coater method, a bar coater method, a blade coating method, etc. can be used.

[0132] The third substrate is a hydrophilic substrate having a contact angle with water or an aqueous solution of preferably 20 degrees or less, more preferably 10 degrees or less. The third substrate may be a substrate having a hydrophilic surface or a substrate having a hydrophilic surface, and is preferably a glass substrate or mica, more preferably a glass substrate. The glass substrate is preferably Eagle glass. The hydrophilic treatment can be performed by subjecting the glass substrate to a UV / O3 treatment.

[0133] The third substrate is water-insoluble, and can be, for example, mica or glass. Since the third substrate is water-insoluble, when water or an aqueous solution is applied to the interface between the third substrate and the p-type organic semiconductor single crystal film, the components of the third substrate do not dissolve and adhere to or react with the p-type organic semiconductor single crystal film, and a high-purity p-type organic semiconductor single crystal film can be obtained. In addition, when water or an aqueous solution is applied to the interface between the third substrate and the p-type organic semiconductor single crystal film, the shape of the third substrate is maintained without being distorted, and the organic film can be separated from the third substrate without distorting the shape of the p-type organic semiconductor single crystal film. Water-insoluble means that the material does not substantially dissolve, decompose, or swell in water or an aqueous solution. The glass is preferably one that has been hydrophilized by UV / ozone treatment or a hydrophilic coating material or the like on the surface. The third substrate may be flexible.

[0134] Water or an aqueous solution is applied to the interface between the third substrate and the p-type organic semiconductor single crystal film, and the p-type organic semiconductor single crystal film is separated from the third substrate. The p-type organic semiconductor single crystal film may be a hydrophobic p-type organic semiconductor single crystal film. Water or an aqueous solution enters between the hydrophilic third substrate and the molecules of the hydrophobic p-type organic semiconductor single crystal film, and the p-type organic semiconductor single crystal film can be separated from the third substrate.

[0135] The water contact angle of the hydrophilic third substrate is smaller than the water contact angle of the hydrophobic p-type organic semiconductor single crystal film, and the difference in the water contact angle between the third substrate and the p-type organic semiconductor single crystal film is preferably 80 degrees or more, more preferably 90 degrees or more. The contact angle of the p-type organic semiconductor single crystal film is preferably 100 to 120 degrees. By having the difference in the contact angle between the hydrophilic third substrate and the hydrophobic p-type organic semiconductor single crystal film within the above-mentioned preferred range, the p-type organic semiconductor single crystal film can be more stably peeled off from the third substrate.

[0136] The method of applying water or an aqueous solution to the interface between the third substrate and the p-type organic semiconductor single crystal film is not particularly limited, and may be a method of dripping water or an aqueous solution onto the interface between the third substrate and the p-type organic semiconductor single crystal film using a water supplier such as a dropper, or a method of immersing the third substrate on which the p-type organic semiconductor single crystal film has been formed in water or an aqueous solution.

[0137] Hydrophobicity preferably refers to a contact angle of 80 degrees or more, more preferably 90 degrees or more, even more preferably 100 degrees or more, even more preferably 110 degrees or more, and even more preferably 150 degrees or more.

[0138] The distance between the top of the protrusions and the bottom of the recesses of the stamp is preferably 2 to 100 μm, more preferably 5 to 50 μm, even more preferably 7 to 40 μm, and even more preferably 10 to 30 μm. By having the distance between the top of the protrusions and the bottom of the recesses of the stamp within the above preferred range, physical patterning can be performed while preventing the recesses from coming into contact with the p-type organic semiconductor single crystal film and preventing the protrusions from breaking when the stamp and the p-type organic semiconductor single crystal film are pressed against each other.

[0139] The pressure when pressing the p-type organic semiconductor single crystal film against the convex portions of the stamp may be appropriately adjusted within a range in which the concave portions do not come into contact with the p-type organic semiconductor single crystal film and the convex portions do not break, and may be, for example, 5 to 200 kPa, 10 to 100 kPa, or 15 to 50 kPa.

[0140] The constituent material of the stamp is preferably a resin, preferably polydimethylsiloxane (PDMS) or polymethylmethacrylate (PMMA), more preferably PDMS. The constituent material of the stamp may have PDMS or PMMA as a main constituent. By using a stamp made of such a material, it is possible to successfully transfer the p-type organic semiconductor single crystal film to the convex parts of the stamp, and to successfully transfer the p-type organic semiconductor single crystal film from the convex parts of the stamp to the fourth substrate. The stamp may be hydrophobic. The stamp may include a support substrate of glass or film.

[0141] The supporting substrate is preferably a glass substrate, a polyethylene naphthalate (PEN) substrate, or a polyethylene terephthalate (PET) substrate.

[0142] A glass substrate, a PEN substrate, or a PET substrate (depending on the heat treatment temperature during stamp preparation) can be selected based on the pressing of the stamp material before curing and the ease of peeling from the stamp preparation mold after thermal curing. Using a flexible substrate as the base material of the stamp makes peeling easier.

[0143] A release layer may be formed on the surface of the stamp. The release layer is preferably CYTOP or a self-assembled monolayer (SAM), more preferably CTYOP. The self-assembled monolayer is, for example, decyltrimethoxysilane (DTS), triethoxy-1H,1H,2H,2H-heptadecafluorodecylsilane (F-SAM), or trimethoxy(2-phenylethyl)silane (β-PTS). Since DTS has a contact angle of about 101 degrees, F-SAM has a contact angle of about 110 degrees, and β-PTS has a contact angle of about 80 degrees, when transferring a p-type organic semiconductor single crystal film to a fourth substrate, the p-type organic semiconductor single crystal film can be more easily peeled off from the stamp and transferred. The SAM treatment can be performed by a gas phase method or a liquid phase method.

[0144] The patterned p-type organic semiconductor single crystal layer preferably includes 10 or more single crystal films, each of which has a thickness of 2 nm or more, a width of 500 nm or more, and a length of 500 nm or more, and the distance between adjacent single crystal films is 10 μm or more.

[0145] The number of single crystal films contained in the patterned p-type organic semiconductor single crystal layer is more preferably 50 or more, and even more preferably 100 or more. The width and length of the single crystal film can be more preferably 15 μm or more, and even more preferably 45 μm or more. The thickness of the single crystal film is more preferably 2 to 100 nm, and even more preferably 7 to 20 nm. The distance between adjacent single crystal films is more preferably 20 μm or more, and even more preferably 25 μm or more.

[0146] The upper limit of the width of the single crystal film is not particularly limited, but is, for example, 500 μm or less. The upper limit of the distance between the single crystal films is not particularly limited.

[0147] The organic semiconductor single crystal layer, the AOS layer, the protective layer, and the complementary semiconductor device formed by this method are the same as those described above for the complementary semiconductor device. The same also applies to the configurations of the gate electrode, the gate insulating film, and the S / D electrode. EXAMPLES

[0148] Example 1 (Making complementary semiconductor devices) A complementary semiconductor device shown in Fig. 41 and Fig. 42 was fabricated. Fig. 41 is a schematic cross-sectional view of the fabricated complementary semiconductor device, and Fig. 42 is a perspective view of the fabricated complementary semiconductor device. As shown in the cross-sectional view of Fig. 41, the S / D electrode of the n-type TFT and the gate electrode of the p-type TFT are arranged in the same layer, and a p-type organic TFT is arranged on an n-type inorganic TFT of IZO. A PMMA layer / parylene layer is arranged as a protective layer for the n-type inorganic TFT. This PMMA layer / parylene layer also functions as a gate insulating film for the p-type organic TFT, which also reduces the number of steps. The manufacturing method of the complementary semiconductor device is shown below.

[0149] (Preparation of AOS precursor solution by sol-gel method) A precursor solution of indium zinc oxide (IZO) was prepared by the sol-gel method shown in FIG. 36. 0.462 g of In(NO3)3-xH2O (Aldrich) was added to 10 mL of 2-methoxyethanol and stirred in air for 6 hours to obtain an indium precursor solution (0.1 M). 0.297 g of Zn(NO3)2-xH2O (Aldrich) was added to 10 mL of 2-methoxyethanol and stirred in air for 6 hours to obtain a zinc precursor solution (0.1 M). The obtained indium and zinc precursor solutions were mixed in a molar ratio of In:Zn=3:2 and stirred in air for 6 hours to prepare an IZO precursor solution.

[0150] (Preparation of PI substrate) Polyimide varnish (Upia (registered trademark)-ST, manufactured by Ube Industries, Ltd.) was spin-coated onto a 5 cm square glass support at 2000 rpm for 3 minutes, and then thermally cured on a hot plate in air under conditions of 110°C for 60 minutes, 150°C for 30 minutes, 200°C for 10 minutes, 250°C for 10 minutes, and 430°C for 10 minutes to form a polyimide substrate with a thickness of 10 μm.

[0151] (Formation of gate electrode and gate insulating film) A 5 / 25 / 5 nm thick Cr / Au / Cr gate electrode was formed on a polyimide substrate by depositing Cr / Au / Cr on a pattern formed with photoresist (TLOR, Tokyo Ohka Kogyo Co., Ltd.) and then removing the photoresist using the lift-off method. A 75 nm thick AlOx (alumina) gate insulating film was formed on the entire surface of the polyimide substrate and the formed gate electrode using the atomic layer deposition (ALD) method.

[0152] (Formation of AOS layer) The substrate on which the AlOx gate insulating film was formed was treated with a UV ozone cleaner (UV253H, manufactured by Filgen) for 10 minutes to remove organic residues and improve wettability.

[0153] As shown in FIG. 37, the prepared IZO precursor solution was spin-coated on the UV-treated substrate at 500 rpm for 5 seconds, then at 5000 rpm for 30 seconds to form an IZO intermediate film. The formed IZO intermediate film was then heat-treated at 150°C for 5 minutes in an air atmosphere, and further heat-treated at 370°C for 1 hour to form an AOS film (IZO film) with a thickness of 6 nm. The formed IZO film was subjected to photolithography using a photosensitive dielectric (PDM, Taiyo Ink Mfg. Co., Ltd.) and wet etching with a 1.75% by mass oxalic acid aqueous solution to form an IZO active layer, which is a patterned n-type semiconductor.

[0154] A photosensitive dielectric (PDM, Taiyo Ink Mfg. Co., Ltd.) was placed on the same layer as the substrate with the patterned IZO active layer and patterned by photolithography, and the patterned PDM was used as a shadow mask to form an n-type transistor S / D electrode and a p-type organic semiconductor gate electrode with a thickness of 60 nm by thermal evaporation and lift-off of Al. The laminate with the S / D electrodes formed was then heat-treated in air at 90°C for 3 hours and slowly cooled to room temperature.

[0155] (Formation of protective layer) A 13 nm thick PMMA layer and a 200 nm thick parylene layer were formed on the entire surface of the AlOx gate insulating film, the IZO layer, and the Al electrode, which served as both a protective layer for the IZO layer and a gate insulating film for the p-type organic transistor, to obtain an intermediate complementary semiconductor device.

[0156] The PMMA layer was formed by spin-coating a butyl acetate solution containing 0.56% by mass of PMMA (Mw=120,000) at 500 rpm for 5 seconds and 4000 rpm for 30 seconds, followed by heat treatment at 150° C. for 1 hour. Parylene was deposited by CVD vacuum deposition.

[0157] (Formation of p-type organic semiconductor single crystal layer) A single crystal layer of an organic semiconductor, C9-DMBDT-NW, which is a p-type semiconductor, was formed on the protective layer of the p-type transistor portion by the continuous edge casting method. The continuous edge casting method was performed as follows.

[0158] A natural mica substrate was prepared as a hydrophilic substrate. As an organic semiconductor, the following formula (16): [ka] A powder of p-type organic semiconductor C9-DNBDT-NW was prepared. 3-Chlorothiophene was used as a solvent, and 0.02 mass% of the organic semiconductor powder was dissolved in the solvent to prepare an organic semiconductor solution. The prepared organic semiconductor solution was applied by continuous edge casting onto a mica substrate heated to 100°C, and a thin film was formed with an average thickness of 12 nm and an area of ​​200 mm2. 2 The contact angle of water on the surface of the organic semiconductor single crystal film was 108 degrees.

[0159] An intermediate product of a complementary semiconductor device having a protective layer formed thereon was placed so that the protective layer was in contact with the organic semiconductor single crystal film formed on the mica substrate, and water was dropped onto the interface between the mica substrate and the organic semiconductor single crystal film to peel the organic semiconductor single crystal film from the mica substrate and transfer it onto the protective layer. The transferred organic semiconductor single crystal film was patterned by photolithography to form an organic semiconductor single crystal layer.

[0160] (Patterning of organic semiconductor single crystal films) The patterning of the organic semiconductor single crystal film was carried out as follows using a 5 μm-thick dry film resist (PDM, manufactured by Taiyo Ink Mfg. Co., Ltd.) as a photoresist.

[0161] A 30-nm-thick Au film was deposited on the organic semiconductor single crystal film by thermal evaporation, and a PMMA solution (Mw=120,000, 0.56% by mass, butyl acetate solution) was spin-coated at 500 rpm for 5 seconds and at 1000 rpm for 30 seconds. The resulting film was then heat-treated at 80°C for 10 minutes to form a 300-nm-thick PMMA film. A dry film resist was then laminated onto the PMMA film.

[0162] The dry film resist was patterned by photolithography, and the PMMA film was removed by O2 plasma treatment using the patterned dry film resist as a mask. Next, the Au film was patterned by etching using Aurum S-50790 (Kanto Chemical Co., Ltd.). Furthermore, the organic semiconductor single crystal film was patterned by O2 plasma treatment. Next, the PMMA film and the dry film resist were peeled off with acetonitrile, a mild photoresist remover.

[0163] (S / D electrode formation) A 60 nm thick Au film was deposited by thermal evaporation on the entire surface of the intermediate body of the complementary semiconductor device fabricated by the above method. Next, in the same manner as above, the formation of a PMMA film, lamination of a dry film resist, patterning of the dry film resist by photolithography, removal of the PMMA film by O2 plasma, patterning of the Au film using Aurum S-50790, and resist stripping using acetonitrile were performed to form an Au S / D electrode with a length of 0.2 mm, a width of 1 mm, and a height of 90 nm (excluding the wiring part). Next, the laminate with the S / D electrode formed was heat-treated at 90°C for 3 hours in air and slowly cooled to room temperature. In this way, a complementary semiconductor device with a p-type structure / n-type structure of bottom gate-top contact / bottom gate-top contact structure shown in Figure 41 was fabricated. The obtained complementary semiconductor device was placed on a polyimide substrate with a thickness of 10 μm, and the thickness excluding the polyimide substrate was about 380 nm.

[0164] Example 2 Complementary semiconductor devices with a channel width W of 200 μm and a channel length L of 100 μm, 80 μm, 60 μm, 40 μm, 20 μm, 10 μm, 7 μm, and 5 μm were fabricated in the same manner as in Example 1. The channel length L of the p-type organic TFT and the n-type inorganic TFT were set to be the same.

[0165] FIG. 43 shows an external view of the obtained organic / inorganic hybrid complementary semiconductor device. The upper photograph of FIG. 43 shows the external view of the complementary semiconductor device having a channel length L of 100 μm, 80 μm, 60 μm, 40 μm, 20 μm, 10 μm, 7 μm, and 5 μm, respectively. The lower photograph of FIG. 43 shows an enlarged view of the complementary semiconductor device having a p-type structure and an n-type structure with a channel length L of 40 μm, 20 μm, 10 μm, 7 μm, and 5 μm. The complementary semiconductor device is composed of an organic TFT located in the upper layer and an inorganic TFT located in the lower layer. The distance between the organic semiconductor single crystal layer and the AOS layer in the complementary semiconductor device shown in FIG. 43 was 100 μm.

[0166] Example 3 In the same manner as in Example 1, an organic / inorganic hybrid complementary semiconductor device consisting of an organic TFT with a W / L of 200 μm / 9 μm and an inorganic TFT with a W / L of 200 μm / 13 μm was fabricated and its characteristics were evaluated.

[0167] FIG. 44 is a graph summarizing the output characteristics of the drain current versus drain voltage for each of the p-type organic TFT and the n-type inorganic TFT included in the complementary semiconductor device when the gate voltage is changed from 0V to -10V in steps of -2V and from 0V to 10V in steps of 2V. The left diagram in FIG. 45 is a graph showing the transfer characteristics of the drain current versus the gate voltage of the p-type organic TFT, and the right diagram is a graph showing the transfer characteristics of the drain current versus the gate voltage of the n-type inorganic TFT. These measurements were performed after the complementary semiconductor device was fabricated. In the circuit diagram of the organic-inorganic hybrid complementary semiconductor inverter single element shown in FIG. 46, the source voltage and drain voltage of the TFT not being measured were set to be equipotential. For example, when measuring the p-type organic TFT, a drain voltage is applied to the output terminal of the complementary semiconductor inverter, but at the same time, the same voltage as the drain voltage of the p-type organic TFT is applied to the source voltage in the n-type inorganic TFT to prevent current from flowing through the n-type inorganic TFT.

[0168] The mobility of p-type organic TFT is 5.1 cm 2 V -1 s-1 The mobility of the n-type inorganic TFT is 4.0 cm 2 V -1 s -1 The off-current of the p-type organic TFT was 10 -11 A and on / off ratio is 10 8 The off-current of the n-type inorganic TFT is 10 -12 A and on / off ratio is 10 8 The threshold voltages of the p-type organic TFT and the n-type inorganic TFT were also almost the same. Thus, it was confirmed that the p-type organic TFT and the n-type inorganic TFT constituting the complementary semiconductor device of the present disclosure have a well-balanced operation and operate at high speed.

[0169] The inverter characteristics were evaluated for the organic-inorganic hybrid complementary semiconductor device single element obtained in Example 3. Fig. 46 is a circuit diagram of the organic-inorganic hybrid complementary semiconductor inverter single element.

[0170] FIG. 47 shows the output voltage characteristics of the complementary semiconductor device fabricated in Example 3 when the input voltage is changed from 0 to 10 V. Good rail-to-rail performance was obtained. FIG. 48 shows a graph evaluating the cause of the voltage amplification effect during switching of the complementary semiconductor device fabricated in Example 3. V DD When the input voltage was about 7V, a large voltage gain was obtained, with a voltage gain of 30 to 40V being obtained.

[0171] FIG. 49 shows a graph showing the relationship between the input voltage and the supply current of the complementary semiconductor device fabricated in Example 3. DD It was found that the static power consumption during standby was small, at 0.76 μW or less, when the input voltage was 7 V. FIG. 50 is a graph showing an evaluation of the noise margin of the complementary semiconductor device fabricated in Example 3. NM H is 2.7V, NM LThe noise margin was 1.9 V, and a large noise margin was obtained. Fig. 51 is a graph showing the initial characteristics of the complementary semiconductor device produced in Example 3 measured immediately after production and the characteristics after being left in air for 5 months. The initial characteristics and the characteristics after being left in air for 5 months showed substantially the same switching characteristics, and it was found to have good long-term stability.

[0172] (Flexible Evaluation) Figure 52 shows a photograph of the appearance of a complementary semiconductor device formed on a polyimide substrate prepared in the same manner as in Example 3 and peeled off from a glass supporter by the laser lift-off (LLO) method. More than 750 complementary inverters are integrated on a 5 cm square polyimide substrate. Figure 53 shows a schematic diagram of a curved complementary semiconductor device formed on a polyimide substrate.

[0173] FIG. 54 is a graph showing the voltage transfer curve (VTC) characteristics of a complementary semiconductor device composed of an organic TFT and an inorganic TFT with a W / L of 200 μm / 10 μm before and after LLO treatment (before and after peeling). DD It was found that when the input voltage was 4 V, 6 V, 8 V, and 10 V, the characteristics were almost the same before and after the LLO treatment, and the LLO treatment caused almost no damage to the complementary semiconductor device.

[0174] FIG. 55 shows a photograph of the appearance of the complementary semiconductor device formed on the polyimide substrate of FIG. 52, wound around the surface of a glass cylinder with a radius of 6.0 mm. FIG. 55 also shows a graph showing the output characteristics of complementary semiconductor devices fabricated in the same manner as in Example 3, which are composed of organic TFTs and inorganic TFTs with n-channel W / L of 50 μm / 24 μm and p-channel W / L of 210 μm / 19 μm, arranged on the surfaces of a flat substrate and cylinders with radii of 17.5 mm (distortion 0.03%), 12.0 mm (distortion 0.04%), and 6.0 mm (distortion 0.08%). The complementary semiconductor devices arranged on the flat substrate and on cylinders with different curvatures showed almost the same characteristics. A flexible complementary semiconductor device could be obtained by using a polyimide substrate as a flexible substrate.

[0175] (Ring oscillator characteristic evaluation) A five-stage ring oscillator (oscillating circuit) was fabricated by connecting five complementary semiconductor devices, each fabricated in the same manner as in Example 1, in a loop. Figure 56 shows an external photograph of the ring oscillator, a circuit diagram, and an external photograph enlarging the area enclosed in a square. The TFTs in each stage have the same dimensions, W / L=200μm / 4μm and ΔL=3μm for the p-channel and W / L=200μm / 8μm and ΔL=1.5μm for the n-channel. ΔL is the length of the overlapping portion between the gate electrode and the S / D electrode.

[0176] Figure 57 shows the V DD This graph shows the inverter characteristics of a single complementary semiconductor device at 10 V. Even with a short channel length, the inverter exhibits rail-to-rail characteristics, with both forward and reverse voltage sweeps of V M NM at 3.2V and symmetrical transition at 5V. H and 2.9V NM L This suggests that the FT-IRQ1000 has a high noise margin.

[0177] In Figure 58, V DD The graph shows the output voltage of the ring oscillator when the input is 10V. The oscillation frequency of the ring oscillator, f ROSC is 77kHz, and the following formula:

number

[0178] The ring oscillator characteristics of complementary semiconductor devices based on organic semiconductors and oxide semiconductors formed by previously reported solution processes and heat treatment at 400°C or less were compared from the viewpoint of scalable manufacturing and flexible circuits. Table 1 shows the evaluation results. All p-type semiconductors are organic semiconductors. The n-type semiconductors in Example 1 and Comparative Example 2 are amorphous oxides, and the rest are organic semiconductors. Example 1 in Table 1 is a five-stage ring oscillator in which five complementary semiconductor devices, each fabricated by the same method as Example 1, are connected in a loop. The delay time is V DD In order to compare the ring oscillator characteristics of each example, DD The conversion delay time when the voltage is adjusted to 10V is t 10V In Comparative Examples 1, 2, and 4 to 6, the inkjet method was used, in Comparative Example 3, the continuous edge casting method was used, and in Comparative Example 7, the spin coating method was used, and the p-type semiconductor and the n-type semiconductor were formed in the same layer, and no protective layer was used.

[0179] [Table 1]

[0180] Comparative Example 1 was prepared by the method reported in Takeda, Y. et al. Appl. Sci. 2018, 8, 1331. Comparative Example 2 was prepared by the method reported in K. Hong, et al. Adv. Mater. 2014, 26, 7032. Comparative Example 3 was prepared by the method reported in M. Uno, et al. Adv. Electron. Mater. 2015, 1, 1500178. Comparative Example 4 was prepared by the method reported in KJ Baeg. et al. Org. Electron. 2013, 14, 1407. Comparative Example 5 was prepared by the method reported in SH Kim, et al., IEEE Electron Device Lett. 2013, 34, 307. Comparative Example 6 was prepared by the method reported in W. Smaal, et al., Org. Electron. 2012, 13, 1686. Comparative Example 7 was prepared by the method reported in L. Herlogsson, et al., Adv. Mater. 2011, 23, 4684.

[0181] The ring oscillator made by connecting five complementary semiconductor devices prepared in Example 1 has a conversion delay time t 10V was found to be very small.

[0182] (Analysis of oxygen defect concentration distribution) Fig. 59 shows the results of angle-resolved XPS measurement of O1s of the AOS layer produced by the same method as in Example 1. Fig. 59(a) is a graph summarizing the measurement spectrum of O1s of the AOS layer formed in Example 1 when the tilt angle θ is set to 0°, 40°, 55°, 63°, and 70°. Fig. 59(b) to Fig. 59(f) are graphs obtained by decomposing and fitting the measurement spectrum measured at the tilt angle θ of 0°, 40°, 55°, 63°, and 70° into MOM having a peak at binding energy 529.7 eV, MO(H) having a peak at 531.1 eV, and MOR having a peak at 532.0 eV.

[0183] M stands for In or Zn. MOM stands for an oxide of stoichiometric composition in which oxygen bridges metal ions and there are no oxygen vacancies. MO(H) stands for a composition with oxygen vacancies containing oxygen or hydroxyl groups with unpaired electrons that do not bridge metal ions. MOR stands for a composition with oxygen vacancies containing oxygen from organic substances such as H2O, CO2, and alcohols that are bonded to metal ions.

[0184] Figure 60, Figure 68, and Table 2 show the ratio of MOM (metal oxide state) to the total O1s calculated by the above fitting (η M-O-M ) is shown as an angle dependence.

[0185] [Table 2]

[0186] The larger the tilt angle θ, the more surface selective it becomes, and the closer the composition to the surface of the AOS layer is, the higher the MOM bond ratio is. The ratio of MOM bonds is constant at about 50% inside the AOS film, but the ratio of MOM bonds decreases toward the surface of the AOS film, decreasing to about 40%, i.e., the ratio of MOM bonds decreases by about 20%. Thus, it was shown that the AOS layer has more oxygen defects near the surface than inside, and has a non-uniform chemical composition in the film thickness direction. In Figure 68, the three points at 5.5 nm on the horizontal axis represent the ratio of the integrated value of each MO species from the outermost AOS surface to a depth of 5.5 nm, and the three points at 2.8 nm represent the ratio of the integrated value of the MO species from the outermost surface to a depth of 2.8 nm. The fact that oxygen defects are present near the surface of the AOS layer from the beginning is also thought to contribute to the low change over time in complementary semiconductor devices.

[0187] (Reference Example 1: Example in which the thickness of the AOS layer was changed) A P-doped Si wafer substrate having a thermally oxidized SiO2 (thickness 100 nm) as a gate insulating film was ultrasonically cleaned in acetone and then 2-propanol for 10 minutes each, and then dried at 100°C for 10 minutes in air using a hot plate.

[0188] The above-mentioned washed and dried substrate was treated with a UV ozone cleaner (UV253H, manufactured by Filgen) for 10 minutes to remove organic residues and improve wettability.

[0189] Except for changing the concentration of the precursor solution, IZO films (AOS layers) of different thicknesses were formed in the same manner as in Example 1. FIG. 61 and Table 3 show the relationship between the concentration of the precursor solution and the thickness of the formed AOS layer. The thickness of the AOS layer was measured by X-ray reflectivity.

[0190] On the IZO film, source / drain (S / D) electrodes (Al, 40 nm) were formed and patterned by thermal evaporation using a metal mask. The IZO film was then patterned using an yttrium aluminum garnet (YAG) laser, and the IZO active layer was obtained by heat treatment at 90°C for 3 hours in air and then slowly cooling to room temperature.

[0191] On the gate insulating layer on which the IZO active layer and the S / D electrodes were formed, a butyl acetate solution (50 mg / mL) in which PMMA (Mw: 120,000) was dissolved was spin-coated at 500 rpm for 5 seconds and at 4000 rpm for 30 seconds, and then heat-treated at 150 °C for 2 hours to form a PMMA layer with a thickness of 100 nm. On the PMMA layer, AlOx with a thickness of 40 nm was deposited by the ALD method while keeping the substrate temperature at 110 °C to form a two-layer protective layer of PMMA layer / AlOx layer. In this way, a bottom-gate-top-contact n-type inorganic TFT with a protective layer and an IZO film was fabricated. The fabricated n-type inorganic TFT had a channel length (L) of 100 μm and a channel width (W) of 2000 μm.

[0192] [Table 3]

[0193] The TFT characteristics were evaluated for IZO formed with total metal ion concentrations of 0.05 M, 0.1 M, and 0.2 M. Figure 62 shows the relationship between the drain current and the gate voltage for TFTs with AOS layer thicknesses of 2.5 nm, 5.5 nm, and 11 nm, when the drain voltage was set to 2 V and 30 V.

[0194] When the AOS layer was 2.5 nm thick, the off-current was good, but the mobility was relatively low and hysteresis was observed. When the AOS layer was 5.5 nm thick, the off-current and mobility were good and no hysteresis was observed. When the AOS layer was 11 nm thick, the off-state was not obtained. The best TFT characteristics were obtained with a total metal ion concentration of 0.1 M and an AOS layer thickness of 5.5 nm.

[0195] (Reference example 2) The characteristics of an oxide thin film (IZO) formed in the same manner as in Reference Example 1 except for changing the heat treatment temperature, and an n-type TFT fabricated in the same manner as in Reference Example 1 using the oxide thin film were evaluated.

[0196] Figure 63 shows the characteristics of TFTs fabricated using IZO thin films sintered at different temperatures, 350°C, 370°C, and 390°C. Figure 64 shows the XRD measurement results of the IZO thin films obtained at each sintering temperature. Figure 65 shows the total reflection FT-IR measurement results of the IZO thin films obtained at each sintering temperature.

[0197] At each sintering temperature, IZO thin films with amorphous structure, high uniformity, and good properties were obtained. However, organic residues acting as electron traps were observed in the heat treatment at 350°C. Therefore, 370°C is considered to be optimal for this IZO system.

[0198] Figures 69 and 70 show atomic force microscope (AFM, Shimadzu SPM-9700HT) images and thickness measured by X-ray reflectivity of the IZO thin film before and after heat treatment at 370°C. After heat treatment, the surface roughness decreased from 4.3 nm to 0.2 nm, and the thickness was reduced by almost half from 14 nm to 5.5 nm. [Explanation of symbols]

[0199] 10 Substrate 20 Gate electrode of n-type structure 22 Gate insulating film of n-type structure 24 n-type amorphous metal oxide inorganic semiconductor layer 26 n-type structure S / D electrode 30 protective layer 40 p-type gate electrode 42 Gate insulating film of p-type structure 44 p-type organic semiconductor single crystal layer 46 p-type structure S / D electrode

Claims

1. substrate, A p-type organic semiconductor single crystal layer; an n-type amorphous metal oxide inorganic semiconductor layer between the substrate and the p-type organic semiconductor single crystalline layer; and A protective layer between the p-type organic semiconductor single crystal layer and the n-type amorphous metal oxide inorganic semiconductor layer. Including, the p-type organic semiconductor single crystal layer is disposed such that, when viewed from a direction perpendicular to a main surface of the p-type organic semiconductor single crystal layer, at least a portion of the p-type organic semiconductor single crystal layer overlaps the n-type amorphous metal oxide inorganic semiconductor layer, or such that the p-type organic semiconductor single crystal layer does not overlap the n-type amorphous metal oxide inorganic semiconductor layer; The distance between the p-type organic semiconductor single crystal layer and the n-type amorphous metal oxide inorganic semiconductor layer is 1 mm or less; the n-type amorphous metal oxide inorganic semiconductor layer has a distribution of oxygen vacancies in a thickness direction in which the amount of oxygen vacancies is greater on the p-type organic semiconductor single crystal layer side than on the substrate side; the protective layer includes a first organic film and a second organic film, the first organic film is located on the n-type amorphous metal oxide inorganic semiconductor layer side, and the second organic film is located on the p-type organic semiconductor single crystal layer side; The first organic film is composed of an organic solvent-soluble polymer, and the second organic film is a vacuum-deposited film. Inorganic / organic hybrid complementary semiconductor devices.

2. 2. The inorganic / organic hybrid complementary semiconductor device according to claim 1, wherein the average thickness of the p-type organic semiconductor single crystal layer is 2 to 100 nm.

3. The p-type organic semiconductor single crystal layer has a thickness of 0.0025 mm ２ 3. The inorganic / organic hybrid complementary semiconductor device according to claim 1 or 2, having the above single domain.

4. The inorganic / organic hybrid complementary semiconductor device according to any one of claims 1 to 3, wherein the substrate is a flexible substrate.

5. 2. The inorganic / organic hybrid complementary semiconductor device according to claim 1, wherein the first organic film has a thickness of 10 nm or more, and the second organic film has a thickness of 100 to 300 nm.

6. 6. The inorganic / organic hybrid complementary semiconductor device of claim 1 or 5, wherein the first organic film is a PMMA film and the second organic film is a parylene film.

7. Preparing the substrate; forming an n-type structure on the substrate; forming a protective layer over the n-type structure; and forming a p-type structure on said protective layer; A method for manufacturing an inorganic / organic hybrid complementary semiconductor device, comprising: forming the n-type structure preparing a precursor solution of an n-type amorphous metal oxide inorganic semiconductor containing a metal salt using a sol-gel method; applying the precursor solution onto the substrate to form a precursor film; and The precursor film is heat-treated at 350 to 400° C. to form an n-type amorphous metal oxide inorganic semiconductor layer. Including, The formation of the p-type structure includes forming a p-type organic semiconductor single crystal layer by using a coating method. Including, the p-type organic semiconductor single crystal layer is disposed such that, when viewed from a direction perpendicular to a main surface of the p-type organic semiconductor single crystal layer, at least a portion of the p-type organic semiconductor single crystal layer overlaps the n-type amorphous metal oxide inorganic semiconductor layer, or such that the p-type organic semiconductor single crystal layer does not overlap the n-type amorphous metal oxide inorganic semiconductor layer; The distance between the p-type organic semiconductor single crystal layer and the n-type amorphous metal oxide inorganic semiconductor layer is 1 mm or less; the n-type amorphous metal oxide inorganic semiconductor layer has a distribution of oxygen vacancies in a thickness direction in which the amount of oxygen vacancies is greater on the p-type organic semiconductor single crystal layer side than on the substrate side; forming the protective layer, preparing an organic solvent having a polymer dissolved therein; applying an organic solvent having the polymer dissolved therein onto the n-type structure to form a first organic film; and forming a second organic film, which is a vacuum deposition film, on the first organic film by using a chemical vapor deposition method; Including, A method for fabricating hybrid inorganic / organic complementary semiconductor devices.

8. 8. The method for producing an inorganic / organic hybrid complementary semiconductor device according to claim 7, wherein the step of applying the precursor solution to form the precursor film is performed using a spin coating method.

9. forming the p-type organic semiconductor single crystal layer, forming a p-type organic semiconductor single crystal film on a hydrophilic and water-insoluble first substrate by using the coating method; and applying water or an aqueous solution to an interface between the first substrate and the p-type organic semiconductor single crystal film to separate the p-type organic semiconductor single crystal film from the first substrate and disposing the p-type organic semiconductor single crystal layer on a second substrate; Including, The second substrate is at least one of a gate insulating layer and an S / D electrode of the n-type structure, the protective layer, or a combination thereof; A method for producing the inorganic / organic hybrid complementary semiconductor device according to claim 7 or 8.

10. forming the p-type organic semiconductor single crystal layer, forming a p-type organic semiconductor single crystal film on a hydrophilic and water-insoluble third substrate by using the coating method; pressing the p-type organic semiconductor single crystal film against a protrusion of a stamp having a protrusion and a recess; applying water or an aqueous solution to an interface between the third substrate and the p-type organic semiconductor single crystal film to transfer the p-type organic semiconductor single crystal film to the protrusions; and The p-type organic semiconductor single crystal film transferred to the convex portion is pressed against a fourth substrate, and the p-type organic semiconductor single crystal film is transferred to the fourth substrate to obtain a patterned p-type organic semiconductor single crystal layer. Including, The fourth substrate is at least one of a gate insulating layer and an S / D electrode of the n-type structure, the protective layer, or a combination thereof; A method for producing the inorganic / organic hybrid complementary semiconductor device according to claim 7 or 8.

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