Scalable high voltage control circuits using thin film electronic components.

Abstract

To provide scalable high-voltage control circuits.SOLUTION: A high-voltage switching device for driving an EMS actuator includes first transistors 120A-120J each having a first source, a first gate, a first drain, and one or more electrodes. The first transistors serve as an inverter. The device also includes second transistors 140A-140J each having a second source, a second gate, and a second drain. The first and second sources are connected together. The first and second drains are connected together. The second transistors serve as an output, a driver, or both. The one or more electrodes, the second gates, or combinations thereof serve as tapped drains that are configured to sample a stepped voltage of the second transistors.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] TECHNICAL FIELD The present teachings relate generally to microelectromechanical systems (MEMS), and more specifically to high voltage switching devices for driving MEMS actuators. [Background technology]

[0002] MEMS are small (e.g., microscopic) systems, especially those with moving parts. MEMS are fabricated from components that are 1 to 100 micrometers (μm) in size, and MEMS generally range in size from 20 micrometers to 1 millimeter (mm). MEMS usually include a central unit (e.g., a microprocessor) that processes data, and several components that interact with the environment (e.g., microsensors). Due to the large surface-area-to-volume ratio of MEMS, forces generated by ambient electromagnetic (e.g., electrostatic charge and magnetic moment) and hydrodynamics (e.g., surface tension and viscosity) are more important design considerations than with larger-scale mechanical devices.

[0003] MEMS typically use electrostatic, piezoelectric, or thermal actuation. Electrostatic actuation scales down to smaller sizes better than electromagnetic and thermal actuation. However, electrostatic actuation typically relies on higher voltages (e.g., several kV) to generate sufficient power than electromagnetic and thermal actuation. It is difficult to both generate and control such high voltages in microelectronic components with actuators of comparable size and weight. Summary of the Invention

[0004] The following presents a simplified summary in order to provide a basic understanding of some aspects of one or more embodiments of the present teachings. This summary is not an extensive overview and is not intended to identify key or critical elements of the present teachings or to delineate the scope of the disclosure. Rather, its primary purpose is merely to present one or more concepts in a simplified form as a prelude to the more detailed description that is presented later.

[0005] A device is disclosed. The device includes a first transistor having a first source, a first gate, a first drain, and one or more electrodes. The first transistor acts as an inverter. The device also includes a second transistor having a second source, a second gate, and a second drain. The first and second sources are connected together. The first and second drains are connected together. The second transistor acts as an output, a driver, or both. The one or more electrodes, the second gate, or a combination thereof, acts as a tapped drain configured to sample a step voltage of the second transistor.

[0006] Also disclosed is a switching device for driving an actuator. The switching device includes a first transistor configured to act as an inverter. The first transistor includes a first source, a first gate, a first drain, and a plurality of electrodes spaced apart from one another. The electrodes are located at least partially between the first gate and the first drain. The switching device also includes a second transistor configured to act as an output, a driver, or both. The second transistor includes a second source. The first and second sources are connected together. The second transistor also includes a second gate. The second transistor also includes a second drain. The first and second drains are connected together. The second transistor also includes a plurality of field plates spaced apart from one another. The field plates are located at least partially between the second source and the second drain. Each field plate is connected to one of the electrodes. The electrode, the second gate, or a combination thereof, serves as a tapped drain configured to sample the step voltage of the second transistor to provide a voltage for the field plate of the second transistor.

[0007] Also disclosed is a high voltage switching device for driving a microelectromechanical system (MEMS) actuator. The switching device includes a first transistor configured to act as an inverter. The first transistor includes a first source, a first gate, a first drain, and a plurality of electrodes spaced apart from one another across a high voltage drift region of an ungated channel of the first transistor. The electrodes and the ungated channel of the first transistor are located at least partially between the first gate and the first drain. The switching device also includes a second transistor configured to act as an output, a driver, or both. The second transistor includes a second source. The first and second sources are connected together. The second transistor also includes a second gate. The gate of the second gate is connected to one of the electrodes. The second transistor also includes a second drain. The first and second drains are connected together. The second transistor also includes a plurality of field plates spaced apart from one another across the ungated channel of the second transistor. The field plate is configured to distribute a high voltage substantially uniformly across the ungated channel of the second transistor. The field plate and the ungated channel of the second transistor are positioned at least partially between the second source and the second drain. Each field plate is connected to one of the electrodes. The electrode, the second gate, or a combination thereof serves as a tapped drain distributed between the first gate and the first drain. The tapped drain is configured to sample the step voltage of the second transistor to provide a voltage for the field plate of the second transistor. [Brief description of the drawings]

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present teachings and, together with the description, serve to explain the principles of the disclosure.

[0009] [Figure 1]1 illustrates a schematic diagram of a high-voltage switching device for driving a MEMS actuator, according to one embodiment.

[0010] [Diagram 2] 2 depicts an expanded view of a portion of FIG. 1 according to one embodiment.

[0011] [Diagram 3] 1 illustrates a circuit diagram of a first stage of a device according to one embodiment.

[0012] [Figure 4] 1 illustrates a circuit diagram of multiple (eg, four) stages of devices stacked together, according to one embodiment.

[0013] [Diagram 5] 1 depicts a schematic cross-sectional side view of a portion of a first stage of a device, according to one embodiment.

[0014] [Figure 6] 1 depicts a graph showing current-voltage characteristics of a first stage of a device according to one embodiment.

[0015] [Figure 7] 1 depicts a graph showing current-voltage characteristics of multiple stacked and / or cascaded stages (eg, four stages) of devices, according to one embodiment.

[0016] [Figure 8] 1 depicts a schematic cross-sectional side view of a portion of a first stage of a device, according to one embodiment.

[0017] [Figure 9] 13 depicts a graph illustrating the current-voltage characteristics of an optical switch of a device where an n+ doped a-Si:H layer is located at least partially between the S / D metal layer and the channel, according to one embodiment.

[0018] [Figure 10]8 depicts a graph showing the current-voltage characteristics of an optical switch when the S / D metal layer is at least partially positioned over (i.e., in direct contact with) the channel (shown on the right side of FIG. 8), according to one embodiment.

[0019] [Figure 11] 1 illustrates a schematic diagram of another high-voltage switching device for driving a MEMS actuator, according to one embodiment.

[0020] [Figure 12] 12 depicts an enlarged portion of FIG. 11, according to one embodiment.

[0021] [Figure 13] 12 depicts a schematic cross-sectional side view of a portion of the device shown in FIG. 11, according to one embodiment.

[0022] [Figure 14] 12 depicts a graph illustrating the transfer characteristic of the device of FIG. 11 according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Reference will now be made in detail to the exemplary embodiments of the present teachings, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same, similar or like parts.

[0024] The present disclosure relates to microelectromechanical systems (MEMS). A first embodiment of the MEMS may be or include an optical coupler (also referred to as an optocoupler). The optical coupler approach simplifies the interface and isolation to low voltage control circuits. The optical coupler approach may also cascade (e.g., stack) multiple stages to increase the voltage rating. The optical coupler approach may be less energy efficient since a light source is required to turn the device on and off. A second embodiment of the MEMS may be or include a two-stage inverter / buffer transistor structure, where an inverter thin-film transistor (TFT) and a buffer TFT are tightly integrated at the sub-device level. Such tight integration helps to distribute the high voltage evenly across the drain region of the buffer TFT so that a high voltage rating can be achieved.

[0025] Hydrogenated amorphous silicon (a-Si:H) based high-voltage (HiV)-TFTs, especially "offset gate" TFT architectures, can provide operating voltages of 200V to 500V or 300V to 400V. The offset gate TFT architecture can have a non-gated drift channel region, which provides a section of semiconductor to distribute the high voltage across the non-gated region to prevent any runoff processes due to high electric fields. The non-gated region can be scaled in length to maintain the same electric field with any voltage (e.g., E=V / L). In one embodiment, an 800V HiV-TFT can be built based on this design.

[0026] However, for scaling voltages above 800V, this approach becomes less and less effective. It is difficult to keep the high voltage evenly distributed throughout the non-gated region so that the high voltage does not concentrate locally and cause a runaway breakdown process. In addition, having a longer non-gated region can have a detrimental effect on the on-current. Non-gated channels are necessarily "resistive". The on-current of a TFT with a long non-gated channel may be small for the same channel width. Increasing the length of the non-gated channel length can dramatically reduce the on / off ratio. An 800V HiV-TFT can have an on / off ratio of about 3-4 orders of magnitude. The fundamental difficulty of a scalable high-voltage driver with a reliable scheme to implement the desired voltages over a wide range is to prevent the high voltages from concentrating in a small area of ​​the channel material or device, which would cause a runaway breakdown process.

[0027] To extend the operating voltage range, multiple discrete transistors can be cascaded. However, this is difficult to implement in a TFT circuit and has not been done so far. There are several differences between using discrete devices and TFT processes. Only N-type metal-oxide-semiconductor (NMOS) active devices are available in a-Si:H TFT processes. There are no P-type metal-oxide-semiconductor (PMOS) or bipolar devices available. Resistors limit the range of a-Si:H TFT processes and are usually considered an inefficient use of layout area. Carrying sub-circuits to provide multiple voltage rails to control the gates of cascaded transistor arrays is generally not available, since the sub-circuits are typically complex DC-DC converters that are beyond the capabilities of the TFT circuit.

[0028] FIG. 1 depicts a schematic diagram of a high-voltage switching device 100 for driving a MEMS actuator, according to one embodiment, and FIG. 2 depicts an expanded view of a portion of FIG. 1, according to one embodiment. The device 100 can include one or more optical switches (ten are shown: 110A-110J). The optical switches 110A-110J can be or include photodiodes (e.g., semiconductor diodes) that convert light into electrical current. In one embodiment, the semiconductors can be or include a-Si:H. The semiconductors can each include two terminal contacts. The terminal contacts can form a Schottky barrier to the semiconductor. The terminal contact material can be or include TiW, MoCr, Mo, Ito, or combinations thereof.

[0029] Device 100 may also include one or more first transistors (ten shown: 120A-120J). First transistors 120A-120J may be or may include TFTs. First transistors 120A, 120J may be long and narrow to provide a discharge path for the gate of a second transistor (introduced and described below). For example, first transistors 120A-120J may have a length of about 20 um to about 500 um and a width of about 3 um to about 10 um.

[0030] Each of the first transistors 120A-120J may include a source 122A, a gate 124A, and a drain 124A. As described in more detail below, each of the first transistors 120A-120J may be connected to a respective one of the optical switches 110A-110J. For example, the first transistor 120A may be connected to the optical switch 110A, and the first transistor 120B may be connected to the optical switch 110B, etc. The first transistors 120A-120J may have a W / L ratio that is less than 1. For example, the W / L ratio may be from about 0.1 to about 0.01.

[0031] The device 100 may also include one or more second transistors (ten shown: 140A-140J). The second transistors 140A-140J may be or may include HiV-TFTs. More specifically, the second transistors 140A-140J may be configured to operate at a higher voltage than the first transistors 120A-120J. For example, the first transistors 120A-120J may be rated for a voltage of about 10V to about 100V (e.g., 20V) and the second transistors 140A-140J may be rated for a voltage of about 200V to about 1000V (e.g., 400V). The second transistors 140A-140J may be shorter and wider / thicker than the first transistors 120A-120J. For example, the second transistors 140A to 140J may have a length of about 3 um to about 10 um and a width of about 10 um to about 1000 um.

[0032] Each of the second transistors 140A-140J may include a source 142A, a gate 144A, and a drain 144A. Each of the second transistors 140A-140J may be connected to a respective one of the optical switches 110A-110J and to a respective one of the first transistors 120A-120J. For example, the second transistor 140A may be connected to the optical switch 110A and the first transistor 120A, and the second transistor 140B may be connected to the optical switch 110B and the first transistor 120B, etc. The gates 144A-144J of the second transistors 140A-140B may be controlled by the optical switches 110A-110J. For example, each of the second transistors (e.g., 140A) may be controlled using a respective one of the optical switches (e.g., 110A) and / or a respective one of the first transistors (e.g., 120A) to cause the gate (e.g., 144A) of the second transistor (e.g., 140A) to be at the same potential as the source (e.g., 142A) of the second transistor (e.g., 140A). This may cause the second transistor (e.g., 140A) to be in an off state when the optical switch 110A is not illuminated.

[0033] The optical switch 110A, the first transistor 120A, and the second transistor 120A may form a first stage of the device 100, the optical switch 110B, the first transistor 120B, and the second transistor 120B may form a second stage of the device 100, etc. Thus, the device 100 may include multiple (e.g., 10) stages that are stacked and / or cascaded, which may help the device 100 achieve a higher (e.g., 10 times) operable voltage range than a single TFT can handle / withstand. For example, the optical switches 110A-110J and the second transistors 140A-140J may be cascaded in series to extend the operating voltage range of the device 100.

[0034] The device 100 may also include one or more pads (two are shown: 150A, 150B). The pads 150A, 150B may be metal pads configured to be used for probing using a probe station. The first pad 150A may be connected to the first stage (e.g., to the first transistor 120A and / or the second transistor 140A). The second pad 150B may be connected to the last (e.g., the tenth) stage (e.g., to the first transistor 120J and / or the second transistor 140J).

[0035] Device 100 may also include one or more pads (ten are shown: 160A-160J). A first pad 160A may be connected to a first stage (e.g., to first transistor 120A and / or second transistor 140A), and a second pad 160B may be connected to a second stage (e.g., to first transistor 120B and / or second transistor 140B), etc.

[0036] To turn on the device 100, a light source (e.g., an LED controlled by a low-voltage control circuit) illuminates the optical switch 110A-110J, which induces a photocurrent and biases the gate potential of the second transistor 140A-140J toward the drain voltage. This causes the second transistor 140A-140J to turn on. The first transistor 120A-120J may act as a load for the optical switch 110A-110J. A certain resistance is required for the photocurrent to induce a sufficient gate voltage to actuate the second transistor 140A-140J to the on state.

[0037] 3 illustrates a circuit diagram of a first stage of the device 100, according to one embodiment. As described above, the first transistor 120A may include a source 122A, a gate 124A, and a drain 126A, and the second transistor 140A may include a source 142A, a gate 144A, and a drain 146A. The drain 126A of the first transistor 120A may be connected to a first side of the optical switch 110A and to a gate 144A of the second transistor 140A. The source 122A of the first transistor 120A may be connected (e.g., at a common node 170A) to the gate 124A of the first transistor 120A and to the source 142A of the second transistor 140A. The drain 146A of the second transistor 140A may be connected to a second side of the optical switch 110A.

[0038] 4 depicts a circuit diagram 400 of multiple (e.g., four) stages of device 100 stacked together, according to one embodiment. As shown, optical switch 110A and drain 146A of second transistor 140A of the first stage may be connected to a common node 170B of the second stage, optical switch 110B and drain 146B of second transistor 140B of the second stage may be connected to a common node 170C of the third stage, and optical switch 110C and drain 146C of second transistor 140C of the third stage may be connected to a common node 170D of the fourth stage. Optical switches 110A-110D may be positioned close together into the illumination area to ensure light utilization and illumination uniformity. Optical switches 110A-110D may be grouped together and controlled by one (or more) light sources operated by low-voltage electronics.

[0039] 5 depicts a schematic cross-sectional side view of a portion of a first stage of device 100, according to one embodiment. The first stage may be formed using a rear channel etch stop a-Si:H TFT process. The first stage may include a gate dielectric layer (also referred to as a bottom nitride layer) 510, an interlevel dielectric (ILD) layer 512 positioned on the gate dielectric layer 510, and a (top) passivation layer 514 positioned on the ILD layer 512.

[0040] The first stage may also include optical switch 110A, first transistor 120A (not shown in FIG. 5), and second transistor 140A. Optical switch 110A may be at least partially located within ILD layer 512 and / or passivation layer 514. Optical switch 110A may be implemented in an S / D metal layer (six portions 120A-120F shown). As shown, a first side of optical switch 110A may be implemented in a first portion 520A of the S / D metal layer, and a second side of optical switch 110A may be implemented in a second portion 520B of the S / D metal layer. The first and second portions 520A and 520B of the S / D metal layer may be located within ILD layer 512. The first and second portions 520A and 520B of the S / D metal layer may be separated from one another (i.e., a portion of ILD layer 512 may be located between them). The second portion 520B of the S / D metal layer may be connected to a third portion 520C of the S / D metal layer, which may be at least partially located in the gate dielectric layer 510. The third portion 520C of the S / D metal layer may be located on and / or connected to a field plate 522 located in the gate dielectric layer 510. The third portion 520C of the S / D metal layer may be connected to a fourth portion of the S / D metal layer 520D, which is located in the ILD layer 512.

[0041] The n+ doped a-Si:H layer (five portions shown: 524A-524E) may be at least partially located within the ILD layer 512. As shown, a first portion 520A of the S / D metal layer may be at least partially located in a first portion 524A of the n+ doped a-Si:H layer, a second portion 520B of the S / D metal layer may be at least partially located in a second portion 524B of the n+ doped a-Si:H layer, and a fourth portion 520D of the S / D metal layer may be at least partially located in a third portion 524C of the n+ doped a-Si:H layer.

[0042] The second transistor 140A may include a source 142A, a gate 144A, and a drain 146A. The second transistor 140A may also include a field plate 530 offset from the gate 144A in the gate dielectric layer 510. The field plate 530 may be positioned between the gate 144A and the drain 146A. An ungated channel (e.g., offset region) 532 may be positioned in the gate dielectric layer 510. The ungated channel 532 may be positioned between the gate 144A and the field plate 530. The ungated channel 532 may also, or instead, be positioned between the gate 144A and the drain 146A. The field plate 530 and / or the ungated channel region 532 may be positioned near the drain 146A to extend the S / D operating range of about tens of volts to an operating range of several hundred volts. This is unique to the offset gate HiV-TFT architecture.

[0043] The second transistor 140A may also include a fifth portion 520E and a sixth portion 520F of the S / D metal layer. The fifth portion 520E and the sixth portion 520F of the S / D metal layer may be located within the ILD layer 512. The fifth portion 520E and the sixth portion 520F of the S / D metal layer may be separated from one another (i.e., a portion of the ILD layer 512 may be located between them). The fifth portion 520E and the sixth portion 520F of the S / D metal layer may have a stepped profile such that each advances closer to the passivation layer 514 as they move closer toward one another.

[0044] The second transistor 140A may also include a fourth portion 524D and a fifth portion 524E of the n+ doped a-Si:H layer. The fourth portion 524D and the fifth portion 524E of the n+ doped a-Si:H layer may be located within the ILD layer 512. The fourth portion 524D and the fifth portion 524E of the n+ doped a-Si:H layer may be separated from one another (i.e., a portion of the ILD layer 512 may be located between them). The fourth portion 524D and the fifth portion 524E of the n+ doped a-Si:H layer may have a stepped profile such that each advances closer to the passivation layer 514 as they move closer toward one another.

[0045] The second transistor 140A may also include a channel 540 (e.g., comprising a-Si:H) and a top nitride (T.Nit.) layer 542. The channel 540 may be located on the gate dielectric layer 510 and / or in the ILD layer 512. The channel 540 may be located at least partially between the fourth portion 524D and the fifth portion 524E of the n+ doped a-Si:H layer. The top nitride layer 542 may be located on the channel 540. The top nitride layer 542 may be located at least partially between the fourth portion 524D and the fifth portion 524E of the n+ doped a-Si:H layer. The channel 540 may have a width wider than the top nitride layer 542.

[0046] The source 142A may include the sixth portion 520F of the S / D metal layer, the fifth portion 524E of the n+ doped a-Si:H layer, the channel 540, and at least a portion of the top nitride layer 542. The drain 146A may include the fifth portion 520E of the S / D metal layer, the fourth portion 524D of the n+ doped a-Si:H layer, the channel 540, and at least a portion of the top nitride layer 542. The channel 540 and the top nitride layer 542 may be located at least partially between the source 142A and the drain 146.

[0047] In one embodiment, the isolated a-Si:H layer 520 of the optical switch 110A may be implemented with the same a-Si:H channel material. However, process modifications may need to be made to ensure that the optical switch 110A has a predetermined on / off ratio. This alternative implant is discussed later.

[0048] FIG. 6 shows a graph 600 illustrating the current-voltage characteristics of a first stage of the device 100 according to one embodiment, and FIG. 7 shows a graph 700 illustrating the current-voltage characteristics of multiple stacked and / or cascaded stages (e.g., four stages) of the device 100 according to one embodiment. Both graphs 600, 700 show one curve for a first (e.g., on) state of the device 100 and another curve for a second (e.g., off) state of the device 100. As can be seen from the graphs, when the device 100 has four stages, the device 100 can generate four times the voltage when compared to when the device 100 has a single stage. For example, the single stage embodiment works up to about 300V, and the multi-stage embodiment works up to about 1200V. The current limit of the single stage embodiment is set to 20 μA, and the current limit of the multi-stage embodiment is set to 50 μA. An on / off ratio of more than six orders of magnitude is shown for both the single and multi-stage embodiments.

[0049] Figure 8 depicts a schematic cross-sectional side view of a portion of a first level of device 100, according to one embodiment. The embodiment of Figure 8 is an alternative to the embodiment of Figure 5. In this embodiment, the first level may include a gate dielectric layer 510 and an interlevel dielectric (ILD) layer 512 positioned at the gate dielectric layer 510. The (top) passivation layer 514 may optionally be omitted.

[0050] The optical switch 110A may include two portions 820A, 820B of the S / D metal layer. The S / D metal layer portions 820A, 820B may have a stepped profile such that each advances further from the gate dielectric layer 510 as they move closer toward each other. The optical switch 110A may also include a channel 840 (e.g., comprising a-Si:H) and a top nitride layer 842. The channel 840 may be positioned on the gate dielectric layer 510 and / or in the ILD layer 512. The channel 840 may be positioned at least partially between the S / D metal layer portions 820A, 820B. The top nitride layer 842 may be positioned on the channel 840. The top nitride layer 842 may be positioned at least partially between the S / D metal layer portions 820A, 820B.

[0051] As mentioned above, the optical switch 110A and the second transistor 140A may share the same a-Si:H material layer, which may simplify the layer structure and process. As shown, the second transistor 140A (illustrated on the left) and the optical switch 110A (illustrated on the right) share a nearly identical structure, except that the optical switch 110A does not include a gate because the optical switch 110A is a two-terminal device. In addition, there is no n+ doped a-Si:H layer between the S / D metal layers 820A, 820B and the channel 840. This structure may require additional steps in construction compared to a conventional a-Si:H TFT process, which assumes that the S / D metal and the n+, a-Si:H are patterned in one step and share the same mask pattern.

[0052] However, Figures 9 and 10 illustrate the importance of separately using different contact structures for optical switch 110A and second transistor 140A.

[0053] Figure 9 depicts a graph 900 illustrating the current-voltage characteristics of optical switch 110A when an n+ doped a-Si:H layer is positioned at least partially between the S / D metal layer and the channel, according to one embodiment. More specifically, Figure 9 illustrates the current-voltage characteristics of an optical switch having a structure similar to optical switch 110A shown on the right side of Figure 8, except that an n+ doped a-Si:H layer is positioned between the S / D metal layer and the channel, similar to second transistor 140A shown on the left side of Figure 8. The on / off ratio of this device is less than 10, which is insufficient.

[0054] 10 depicts a graph 1000 illustrating the current-voltage characteristics of optical switch 110A when S / D metal layers 820A, 820B are at least partially positioned on (i.e., in direct contact with) channel 840 (shown on the right side of FIG. 8), according to one embodiment. The on / off ratio is improved from more than two orders of magnitude to over 1000. Similarly, without the n+ doped a-Si:H layer of second transistor 140A, second transistor 140A can have a very small on-current.

[0055] FIG 11 depicts a schematic diagram of another high voltage switching device 1100 for driving a MEMS actuator, according to one embodiment, and FIG 12 depicts an enlarged portion of FIG 11, according to one embodiment. The device 1100 may be or may include full electrical injection. One difference between the device 1100 shown in FIG 11 and the device 100 described with reference to FIGS 1-10 is that the device 1100 of FIG 11 is straightforwardly scalable to the multiple KV range.

[0056] The device 1100 may be or include a composite device. The device 1100 may include one or more transistors (two are shown: 1120, 1140). The first (e.g., top) transistor 1120 may be or include a TFT. For example, the first transistor 1120 may be or include a HiV-TFT having a source 1122, a gate 1124, and a drain 1126. The first transistor 1120 may be long and narrow. For example, the first transistor 1120 may have a length of about 20um to about 1000um and a width / thickness of about 3um to about 20um. The first transistor 1120 may act as an inverter (e.g., a first stage inverter). In the embodiment shown, unlike a conventional inverter circuit, there is no load resistor for the first transistor 1120.

[0057] The device 1100 may be operable between a first (e.g., off) state and a second (e.g., on) state. The device 1100 may be in the off (e.g., low current) state when the gate 1124 turns off the first transistor 1120. The device 1100 may be in the on (e.g., higher current) state when the gate 1124 turns on the first transistor 1120.

[0058] The second (e.g., lower) transistor 1140 may also be or include a TFT. For example, the second transistor 1140 may be or include a HiV-TFT having a source 1242, a gate 1144, and a drain 1146. The second transistor 1140 may be wider than the first transistor 1120. For example, the second transistor 1140 may have a width of about 20 um to about 1000 mm. The second transistor 1140 may serve as a driving and / or output transistor.

[0059] The sources 1122, 1142 may be connected (e.g., by metal), but the sources 1122, 1142 may not be shared (e.g., their semiconductor channels may be separated). Similarly, the drains 1126, 1146 may be connected (e.g., by metal), but the drains 1126, 1146 may not be shared (e.g., their semiconductor channels may be separated). The subcomponents of the transistors 1120, 1140 are tightly coupled such that the device 1100 is not a conventional inverter+output transistor. Rather, the device 1100 is a compound three-terminal device having a source, a gate, and a drain.

[0060] The first transistor 1120 may include one or more tap electrodes (five are shown: 1130A-1130E). The electrodes 1130A-1130E may be distributed throughout a high-voltage drift region of an ungated channel (also referred to as an ungated drift region) 1132 of the first transistor 1120. The electrodes 1130A-1130E of the first transistor 1120 may be positioned at least partially between the gate 1124 and the drain 1126. One of the electrodes 1130A may be connected to the gate 1144 of the second transistor 1140.

[0061] The second transistor 1140 may include one or more field plates (five shown: 1148A-1148E). The gate 1144 and field plates 1148A-1148E of the second transistor 1140 may be connected (e.g., directly) to the electrodes 1130A-1130E of the first transistor 1120. The field plates 1148A-1148E may be positioned at least partially between the gate 1144 and the drains 1126, 1146. The field plates 1148A-1148E may distribute high voltages substantially uniformly across the ungated channel (also referred to as the ungated drift region) 1152 of the second transistor 1140, which may reduce and / or prevent premature breakdown. As shown, the ungated channel 1132, 1152 may be positioned at least partially between the gates 1124, 1144 and the drains 1126, 1146. The operating voltage range of the device 1100 can be expanded by increasing the number of electrodes 1130A-1130E of the first transistor 1120 and / or by increasing the number of field plates 1148A-1148E of the second transistor 1140.

[0062] The source 1122, 1142, gate 1144, drain 1126, 1146, electrodes 1130A-1130E, or combinations thereof, may be made of a first material (e.g., S / D metal). The gate 1124, field plates 1148A-1148E, or combinations thereof, may be made of a second material (e.g., gate metal) that is different from the first material. The channel 1132, 1152 may be made of a third material (e.g., a:Si:H) that is different from the first and second materials.

[0063] 11, the device 1100 may be connected to one or more pads (four are shown: 1160A-1160D). The pads 1160A-1160D may be metal pads configured to be used for probing using a probe station. As shown, the pad 1160A may be connected to the source 1122, 1142, the pad 1160B may be connected to the gate 1144, and the pad 1160D may be connected to the drain 1126, 1146.

[0064] The first transistor 1120 may have a modified (e.g., non-conventional) structure. More specifically, in addition to the source 1122, gate 1124, and drain 1126, the first transistor 1120 may also include one or more tapped drains distributed along the ungated drift region 1132 between the gate 1124 and the drain 1126. The tapped drain may be or may include the gate 1144 and / or electrodes 1130A-1130E. The tapped drain may be configured to sample the step voltage of the second transistor 1140. The tapped drain may also, or instead, be configured to provide a field plate voltage for the second transistor 1140. In one embodiment, the tapped drain may be a field plate of the first transistor 1120. In another embodiment, the tapped drain may not be a field plate of the first transistor 1120.

[0065] In one embodiment, the electrode 1130 may act as a field plate and / or a drain of the first transistor 1120. In one embodiment, the gate 1144 may act as a field plate and / or a drain of the first transistor 1120. In one embodiment, the electrode 1130 may act as a field plate of the second transistor 1140.

[0066] Figure 13 depicts a schematic cross-sectional side view of a portion of device 1100 taken along line 13-13 in Figure 11, according to one embodiment. Although the cross-section is shown in Figure 11 as being through gate 1144, the cross-section could also, or instead, be taken through any one of electrodes 1130A-1130E.

[0067] The device 1100 may include a first (e.g., lower) metal layer 1310. The first metal layer 1310 may be made of the same type of metal as the gate 1124. The gate dielectric layer 1120 may be at least partially located on the first metal layer 1310. The second (e.g., upper) metal layer 1330 may be at least partially located on the gate dielectric layer 1120. The second metal layer 1330 may be made of the same type of metal as the drain 1126. In at least one embodiment, the metal layers 1310, 1330 may be made of the same type of metal. In another embodiment, the metal layers 1310, 1330 may be made of different types of metal. The second metal layer 1330 may include one or more legs (two shown: 1332, 1334) that extend at least partially through the gate dielectric layer 1120 toward the first metal layer 1310. In at least one embodiment, the legs 1332 , 1334 are positioned on and / or contact the first metal layer 1310 .

[0068] The channel 1340 may be at least partially located within the second metal layer 1330. The channel 1340 may be made of a:Si:H. The n+ layer 1350 may be at least partially located within the second metal layer 1330. The n+ layer 1350 may be at least partially located on and / or above the channel 1340. The n+ layer 1350 may be or may include an n+ doped a-Si:H layer. The top nitride layer 1360 may be at least partially located within the second metal layer 1330. The top nitride layer 1360 may be at least partially located between the channel 1340 and the n+ layer 1350. For example, the top nitride layer 1360 may be located above the channel 1340 and below the top nitride layer 1360.

[0069] A third metal layer 1370 may be located at least partially on and / or above the second metal layer 1330 and / or the n+ layer 1350. The third metal layer 1370 may be made of the same type of metal as the second metal layer 1330. In at least one embodiment, the layers 1330, 1370 may be the same layer.

[0070] 14 shows a graph 1400 illustrating the transfer characteristics of this device 1100, according to one embodiment. g At high gate input voltages (V < 2V), the device 1100 is in the “on” state with an on-current of over 10 uA (e.g., instrument compliance setting). g >2.5V), device 1100 is in the off state and leakage current can be several hundred pA at 1100V. In one embodiment, 1100V can be the highest voltage device 1100 can provide. The input voltage can be swept from -5V to +10V and the S / D drain can be set to the maximum voltage range of the measurement setup (e.g., 1100V). The current response is set to 10 μA. Device 1100 can achieve 4-5 orders of magnitude on / off.

[0071] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the present teachings are approximations, the numerical values ​​set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein should be understood to encompass any and all subranges contained therein. For example, a range of "less than 10" can include any and all subranges between (including) a minimum value of 0 and a maximum value of 10, i.e., any and all subranges having a minimum value of 0 or more and a maximum value of 10 or less, e.g., 1 to 5.

[0072] Although the present teachings are described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. For example, while a process is described as a series of acts or events, it may be understood that the present teachings are not limited by the order of such acts or events. Some acts may occur in different orders and / or simultaneously with other acts or events other than those described herein. Also, not all process steps may be required to implement a methodology in accordance with one or more aspects or embodiments of the present teachings. It may be understood that structural objects and / or processing steps may be added, or existing structural objects and / or processing steps may be removed or modified. Furthermore, one or more of the acts described herein may be performed in one or more separate acts and / or steps. Additionally, to the extent the terms "including," "includes," "having," "has," "with," or variations thereof are used in any of the detailed description and claims, such terms are intended to be inclusive in a manner similar to the term "comprising." The term "at least one" is used to mean that one or more of the listed items may be selected. Additionally, in the discussion and claims herein, the term "on" when used in reference to two materials, one "on" means at least some contact between the materials, while "on" means that the materials are in close proximity to one or more additional intervening materials, such that contact is possible, but not required, in some cases. Neither "on" nor "over" implies any directionality when used herein. The term "conformal" describes a coating material in which the angle of the underlying material is held by the conformal material. The term "about" indicates that the listed value may be altered slightly, as long as the change would not result in a process or structure incompatibility with the embodiment shown.The terms "couple," "coupled," "connect," "connection," "connected," "connected with," and "connecting" refer to "directly connected with" or "connected through one or more intermediate elements or members." Finally, the terms "exemplary" or "exemplary" indicate that the description is not meant to be ideal but is used as an example. Other embodiments of the present teachings will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the present teachings being indicated by the following claims.

Claims

1. A device, comprising: an optical switch configured to convert light into electrical current; a first transistor having a first source, a first gate, a first drain, and one or more electrodes, the first transistor acting as an inverter; a second transistor comprising a second source, a second gate, and a second drain, wherein the first and second sources are connected together and the first and second drains are connected together, the second transistor acting as an output, a driver, or both, and the one or more electrodes, the second gate, or a combination thereof acting as a tapped drain configured to sample a step voltage of the second transistor; an interlevel dielectric; a source-drain (S / D) metal layer located at least partially within the interlevel dielectric; the optical switch is located over a first portion and a second portion of the S / D metal layer, the first portion and the second portion being separated from one another by a portion of the interlevel dielectric.

2. 2. The device of claim 1 , wherein the one or more electrodes comprise a plurality of electrodes spaced apart from one another between the first gate and the first drain, the electrodes being positioned within a drift region of an ungated channel of the first transistor.

3. The device of claim 1 , wherein the first transistor is narrower than the second transistor.

4. 10. The device of claim 1, wherein the semiconductor channels of the first and second sources are separated such that the first and second sources are not shared.

5. 2. The device of claim 1, wherein the semiconductor channels of the first and second drains are separated such that the first and second drains are not shared.

6. 2. The device of claim 1 , wherein the first transistor comprises a first electrode and a second electrode spaced apart from each other, the second transistor comprises a first field plate and a second field plate spaced apart from each other, the first electrode connected to the first field plate and the second electrode connected to the second field plate.

7. The device of claim 6 , wherein the gate of the second transistor is connected to the first electrode.

8. 7. The device of claim 6, wherein the first and second field plates are positioned at least partially between the gate of the second transistor and the drain of the second transistor.

9. The device of claim 6 , wherein the first and second electrodes are distributed across a high-voltage drift region of an ungated channel of the first transistor.

10. The device of claim 9 , wherein the first and second electrodes are positioned between the gate and the drain of the first transistor.

11. A switching device for driving an actuator, comprising: an optical switch configured to convert light into electrical current; a first transistor coupled to the optical switch configured to act as an inverter, A first source; A first gate; A first drain; a first transistor comprising a plurality of electrodes spaced apart from one another, the plurality of electrodes being positioned at least partially between the first gate and the first drain; a second transistor configured to act as an output, a driver, or both; a second source, the first and second sources being connected together; and A second gate; a second drain, the first and second drains being connected together; and a second transistor comprising: a plurality of field plates spaced apart from one another, the field plates positioned at least partially between the second source and the second drain, each field plate connected to one of the electrodes, the electrode, the second gate, or a combination thereof acting as a tapped drain configured to sample a step voltage of the second transistor to provide a voltage for the field plate of the second transistor; a gate dielectric layer; an interlevel dielectric overlying the gate dielectric layer; a passivation layer located on the interlevel dielectric, the optical switch being at least partially located within the interlevel dielectric, within the passivation layer, or both; a source-drain (S / D) metal layer located at least partially within the interlevel dielectric; a switching device, the optical switch being located over the S / D metal layer, the optical switch being located over a first portion and a second portion of the S / D metal layer, the first portion and the second portion being separated from one another by a portion of the interlevel dielectric.

12. The switching device of claim 11 , wherein the gate of the second gate is connected to one of the electrodes.

13. The switching device of claim 11 , wherein the electrode is distributed throughout a high-voltage drift region of an ungated channel of the first transistor.

14. 12. The switching device of claim 11, wherein the field plate is configured to distribute a high voltage substantially uniformly across the non-gated channel of the second transistor.

15. 12. The switching device of claim 11, wherein an ungated channel of the first transistor is positioned at least partially between the gate of the first transistor and the drain of the first transistor, and an ungated channel of the second transistor is positioned at least partially between the source of the second transistor and the drain of the second transistor.

16. 1. A high voltage switching device for driving a microelectromechanical system (MEMS) actuator, comprising: an optical switch configured to convert light into electrical current; a first transistor coupled to the optical switch configured to act as an inverter, A first source; A first gate; A first drain; a first transistor comprising: a plurality of electrodes spaced apart across a high-voltage drift region of an ungated channel of the first transistor, the electrodes and the ungated channel of the first transistor being positioned at least partially between the first gate and the first drain; a second transistor configured to act as an output, a driver, or both; a second source, the first and second sources being connected together; and a second gate, the gate of the second gate being connected to one of the electrodes; and a second drain, the first and second drains being connected together; and a second transistor comprising: a plurality of field plates spaced apart from one another across an ungated channel of the second transistor, the field plates configured to distribute a high voltage substantially uniformly across the ungated channel of the second transistor, the field plates and the ungated channel of the second transistor being positioned at least partially between the second source and the second drain, each field plate being connected to one of the electrodes, the electrode, the second gate, or a combination thereof acting as a tapped drain distributed between the first gate and the first drain, the tapped drain being configured to sample a step voltage of the second transistor to provide a voltage for the field plate of the second transistor; a gate dielectric layer; an interlevel dielectric overlying the gate dielectric layer; a passivation layer located on the interlevel dielectric, the optical switch being at least partially located within the interlevel dielectric, within the passivation layer, or both; a source-drain (S / D) metal layer located at least partially within the interlevel dielectric; a high voltage switching device, the high voltage switching device being located above the S / D metal layer, the high voltage switching device being located above a first portion and a second portion of the S / D metal layer, the first portion and the second portion being separated from each other by a portion of the interlevel dielectric.

17. 17. The switching device of claim 16, wherein the first source, the second source, the second gate, the first drain, the second drain, and the field plate are made of a first material.

18. 20. The switching device of claim 17, wherein the first gate and the field plate are made of a second material different from the first material.

19. 20. The switching device of claim 18, wherein the non-gated channel of the first transistor and the non-gated channel of the second transistor are made of a third material different from the first and second materials.

20. 20. The switching device of claim 19, wherein the first material comprises a first metal, the second material comprises a second metal, and the third material comprises hydrogenated amorphous silicon (a-Si:H).

21. A gate dielectric layer, the interlevel dielectric being disposed on the gate dielectric layer; and 10. The device of claim 1, further comprising: a passivation layer located on the interlevel dielectric, the optical switch being at least partially located within the interlevel dielectric, within the passivation layer, or both.

22. The device described in claim 21, wherein the S / D metal layer also includes a third portion coupled to the second portion, the third portion being located within the gate dielectric layer.

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