Antifuse structures, antifuse arrays and memories

Abstract

The antifuse structure according to the embodiment of the present application includes a first unit and a second unit, the first unit includes a first selection transistor, a first antifuse unit, and a second antifuse unit, and the second unit includes a second selection transistor, a third antifuse unit, and a fourth antifuse unit, wherein the first unit and the second unit share an active area, a first extension portion and a second extension portion that are independent of each other extend on a first side of the active area, and a third extension portion and a fourth extension portion that are independent of each other extend on a second side of the active area, the first side and the second side are disposed opposite each other, the first antifuse unit is disposed on the first extension portion, the second antifuse unit is disposed on the second extension portion, the third antifuse unit is disposed on the third extension portion, and the fourth antifuse unit is disposed on the fourth extension portion. The antifuse structure can improve the distribution density of the antifuse units and meet the requirement of miniaturization.

Description

[Technical field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to a Chinese patent application filed with the China Patent Office on May 25, 2022, bearing application number 202210577084.X and entitled "Antifuse Structure, Antifuse Array and Memory", the entire contents of which are incorporated herein by reference.

[0002] This application relates to the field of integrated circuits, and more particularly to antifuse structures, antifuse arrays and memories. [Background technology]

[0003] In the semiconductor industry, fuse elements are widely used in integrated circuits for various applications. For example, an integrated circuit is designed with multiple circuit modules with the same functions as backups, and when one of the circuit modules fails, the fuse element blows the path between the circuit module and other functional circuits in the integrated circuit, and the failed circuit module is replaced by another circuit module with the same function.

[0004] With the continuous development of semiconductor technology, anti-fuse technology has attracted the attention of many inventors and manufacturers. Anti-fuse elements store information by changing from an insulating state to a conductive state. Writing information to an anti-fuse element is performed by dielectric breakdown caused by application of a high voltage. An anti-fuse memory cell has a capacitance characteristic before programming and no conductive channel is formed, but when a program breakdown occurs, a conductive channel is formed at both ends of the cell, allowing current to flow, and the magnitude of the conductive current is related to the programming effect.

[0005] For example, an anti-fuse structure usually includes an anti-fuse cell (AF cell) and a selection transistor (XADD). During writing, a high voltage (about 5.5-6V) is applied to the anti-fuse unit, the end of the corresponding bit line (BL) is set to 0V, and the selection transistor is turned on, so that the thin gate oxide of the anti-fuse unit is broken down under the high voltage, and the electrical resistance is greatly reduced, thereby achieving the purpose of writing.

[0006] As the size of a chip shrinks, the area of ​​the antifuse array also needs to shrink in order to save valuable space in the memory array; however, due to limitations in design rules and manufacturability requirements of the antifuse structure, the area of ​​the antifuse array cannot be reduced under the condition that the number of antifuse units does not change, and therefore the requirements for miniaturization of the chip cannot be met. Summary of the Invention

[0007] The present application provides an antifuse structure, an antifuse array, and a memory that can reduce the area of ​​the antifuse array under the condition that the number of antifuse units does not change.

[0008] The present application provides an antifuse structure, the antifuse structure comprising a first unit and a second unit, the first unit comprising a first selection transistor, a first antifuse unit and a second antifuse unit, the second unit comprising a second selection transistor, a third antifuse unit and a fourth antifuse unit, wherein the first unit and the second unit share an active area, a first extension portion and a second extension portion that are independent of each other extend on a first side of the active area, and a third extension portion and a fourth extension portion that are independent of each other extend on a second side of the active area, the first side and the second side are disposed opposite to each other, the first antifuse unit is disposed on the first extension portion, the second antifuse unit is disposed on the second extension portion, the third antifuse unit is disposed on the third extension portion, and the fourth antifuse unit is disposed on the fourth extension portion.

[0009] In one embodiment, the antifuse structure further comprises a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, a fifth gate structure, a sixth gate structure, a first doped region, a second doped region, and a third doped region, wherein the first gate structure is disposed on a surface of the active area, the second gate structure is disposed on a surface of the active area and spaced apart from the first gate structure, the third gate structure is disposed on a surface of the first extension, the fourth gate structure is disposed on a surface of the second extension, the fifth gate structure is disposed on a surface of the third extension, and the sixth gate structure is disposed on a surface of the fourth extension, the first doped region is disposed in the active area between the first gate structure and the second gate structure, and the second doped region is disposed in an active area on one side of the first gate structure away from the second gate structure. the third doped region is disposed in an active area, in the first extension and in the second extension on one side of the second gate structure away from the first gate structure, in the third extension and in the fourth extension, wherein the first gate structure, the first doped region and the second doped region constitute the first selection transistor, the third gate structure and the second doped region in the first extension constitute the first anti-fuse unit, the fourth gate structure and the second doped region in the second extension constitute the second anti-fuse unit, the second gate structure, the first doped region and the third doped region constitute the second selection transistor, the fifth gate structure and the third doped region in the third extension constitute the third anti-fuse unit, and the sixth gate structure and the third doped region in the fourth extension constitute the fourth anti-fuse unit.

[0010] In one embodiment, the first side and the second side are disposed opposite each other along a first direction, and the first gate structure and the second gate structure are arranged along the first direction.

[0011] In one embodiment, the third gate structure and the fourth gate structure are aligned along a second direction, the second direction being perpendicular to the first direction or forming an acute angle with the first direction.

[0012] In one embodiment, the fifth gate structure and the sixth gate structure are aligned along the second direction, and the second direction is perpendicular to the first direction or forms an acute angle with the first direction.

[0013] In one embodiment, the antifuse structure further comprises a bit line connection structure, the bit line connection structure being connected to a first doped region between the first gate structure and the second gate structure, and the first doped region can be connected to a bit line via the bit line connection structure.

[0014] In one embodiment, the antifuse structure further comprises a first connection structure and a second connection structure, the first connection structure is connected to the third gate structure, and the third gate structure can be connected to one programming line via the first connection structure, the first connection structure is located on one side of the first extension portion away from the second extension portion, the second connection structure is connected to the fourth gate structure, and the fourth gate structure can be connected to another programming line via the second connection structure, 2 A connecting structure is disposed on one side of the second extension portion away from the first extension portion.

[0015] In one embodiment, the third gate structure includes a third main area arranged corresponding to the first extension portion and a third sub-area protruding in a direction away from the second extension portion, and the first connection structure is connected to the third sub-area, the fourth gate structure includes a fourth main area arranged corresponding to the second extension portion and a fourth sub-area protruding in a direction away from the first extension portion, and the second connection structure is connected to the fourth sub-area.

[0016] In one embodiment, the antifuse structure further comprises a third connection structure and a fourth connection structure, the third connection structure is connected to the fifth gate structure, the fifth gate structure can be connected to one programming line via the third connection structure, the third connection structure is located on one side of the third extension portion away from the fourth extension portion, the fourth connection structure is connected to the sixth gate structure, the sixth gate structure can be connected to another programming line via the fourth connection structure, and the fourth connection structure is located on one side of the fourth extension portion away from the third extension portion.

[0017] In one embodiment, the fifth gate structure includes a fifth main area arranged corresponding to the third extension portion and a fifth sub-area protruding in a direction away from the fourth extension portion, and the third connection structure is connected to the fifth sub-area, the sixth gate structure includes a sixth main area arranged corresponding to the fourth extension portion and a sixth sub-area protruding in a direction away from the third extension portion, and the fourth connection structure is connected to the sixth sub-area.

[0018] In one embodiment, the first selection transistor and the second selection transistor are arranged symmetrically with respect to a first axis, the first anti-fuse unit and the third anti-fuse unit are arranged symmetrically with respect to the first axis, and the second anti-fuse unit and the 4 The anti-fuse units are disposed symmetrically with respect to the first axis.

[0019] An embodiment of the present application further provides an antifuse array comprising a plurality of the above-mentioned antifuse structures, wherein the plurality of antifuse structures are arranged in an array along a first direction and a second direction, and the first direction is perpendicular to the second direction or has an acute angle with the second direction.

[0020] In one embodiment, adjacent anti-fuse units of adjacent anti-fuse structures in the second direction share the same gate structure.

[0021] In one embodiment, the first selection transistors of the anti-fuse structures arranged along the second direction share the same gate structure, and the second selection transistors share the same gate structure.

[0022] An embodiment of the present invention further provides a memory including the above anti-fuse array.

[0023] In one embodiment, the memory further comprises a plurality of programming lines arranged along the first direction and extending along the second direction, a row of antifuse structures arranged along the second direction corresponds to four of the programming lines, and the four programming lines are respectively connected to the first antifuse unit, the second antifuse unit, the third antifuse unit and the fourth antifuse unit of the antifuse structure.

[0024] In one embodiment, the memory further comprises a plurality of bit lines arranged along a second direction and extending along a first direction, and a column of antifuse structures arranged along the first direction share the same bit line.

[0025] In the antifuse structure of the present embodiment, the first unit and the second unit share the same active area, thereby eliminating the gap between the active areas caused by the first unit and the second unit using different active areas, and reducing the area of ​​the antifuse structure; and since each unit has two antifuse units, which are respectively installed on independent extension portions, the number of antifuse units can be doubled in the same area; that is, when the designed number of antifuse units is the same, the antifuse structure of the present application only needs to occupy about half the area, thereby meeting the requirement of miniaturization. [Brief description of the drawings]

[0026] [Figure 1A] 1 is a schematic diagram of an antifuse structure according to some embodiments of the present application. [Figure 1B] FIG. 2 is a schematic diagram of an active area according to some embodiments of the present application. [Diagram 2] FIG. 1 is a schematic diagram of an antifuse array in accordance with some embodiments of the present application. [Diagram 3] FIG. 1 is a schematic diagram of a memory in accordance with some embodiments of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the antifuse structure, antifuse array, and memory according to the present application will be described in detail with reference to the drawings.

[0028] FIG. 1A is a schematic diagram of an antifuse structure according to some embodiments of the present application, and FIG. 1B is a schematic diagram of an active area according to some embodiments of the present application. Referring to FIG. 1A and FIG. 1B, the antifuse structure 10 comprises a first unit 101 and a second unit 102.

[0029] The first unit 101 includes a first selection transistor, a first anti-fuse unit, and a second anti-fuse unit, and the second unit 102 includes a second selection transistor, a third anti-fuse unit, and a fourth anti-fuse unit.

[0030] Here, the first unit 101 and the second unit 102 share an active area AA, a first extension portion AA1 and a second extension portion AA2 that are independent of each other extend on a first side of the active area AA, and a third extension portion AA3 and a fourth extension portion AA4 that are independent of each other extend on a second side of the active area AA, the first side and the second side are arranged opposite each other, the first antifuse unit is arranged on the first extension portion AA1, the second antifuse unit is arranged on the second extension portion AA2, the third antifuse unit is arranged on the third extension portion AA3, and the fourth antifuse unit is arranged on the fourth extension portion AA4.

[0031] In the antifuse structure of the present embodiment, the first unit 101 and the second unit 102 share the same active area AA, thereby eliminating the gap between the active areas AA caused by the first unit 101 and the second unit 102 using different active areas AA, and reducing the area of ​​the antifuse structure; and since each unit has two antifuse units, which are respectively installed on independent extension portions, the number of antifuse units can be doubled in the same area; that is, when the designed number of antifuse units is the same, the antifuse structure of the present application only needs to occupy about half the area, thereby meeting the requirement of miniaturization.

[0032] Continuing to refer to FIGS. 1A and 1B, structures of the first selection transistor, the first anti-fuse unit, the second anti-fuse unit, the second selection transistor, the third anti-fuse unit and the fourth anti-fuse unit will now be described in detail.

[0033] A first extension portion AA1 and a second extension portion AA2 extend on a first side of the active area AA, and a third extension portion AA3 and a fourth extension portion AA4 extend on a second side of the active area AA. The first side and the second side are disposed opposite to each other along a first direction (Y direction in the figure). For example, in this embodiment, the first side is the upper end of the active area AA, and the second side is the lower end of the active area AA.

[0034] The antifuse structure comprises a first gate structure G1. The first gate structure G1 is disposed on a surface of the active area AA. In some embodiments, the first gate structure G1 extends along a second direction. In this embodiment, the second direction is a horizontal direction X.

[0035] In some embodiments, the antifuse structure further comprises a first word line connection structure T1, and the first gate structure G1 is electrically connected to a peripheral control circuit via the first word line connection structure T1, i.e., the first word line connection structure T1 functions as a conductive plug for realizing an electrical connection between the first gate structure G1 and the peripheral control circuit.

[0036] The antifuse structure further comprises a second gate structure G2, which is disposed on the surface of the active area AA and spaced apart from the first gate structure G1. In some embodiments, the first gate structure G1 and the second gate structure G2 are connected to different word lines to realize separate control of the first unit 101 and the second unit 102.

[0037] In this embodiment, the first gate structure G1 and the second gate structure G2 extend along a second direction, the second gate structure G2 and the first gate structure G1 are spaced apart from each other along the first direction, and the first direction is perpendicular to the second direction or forms an acute angle with the second direction. Specifically, in this embodiment, the first direction is perpendicular to the second direction, for example, the second direction is a horizontal direction X-direction, and the first direction is a vertical direction Y-direction. In some other embodiments, the first direction forms an acute angle with the second direction, for example, the second direction is a horizontal direction X-direction, and the first direction is a direction that forms an acute angle with the horizontal direction.

[0038] In some embodiments, the antifuse structure further comprises a second word line connection structure T2, and the second gate structure G2 is electrically connected to a peripheral control circuit via the second word line connection structure T2, i.e., the second word line connection structure T2 functions as a conductive plug for realizing an electrical connection between the second gate structure G2 and a peripheral control circuit.

[0039] The antifuse structure further includes a third gate structure G3, which is disposed on a surface of the first extension AA1 and can be connected to a programming line. In some embodiments, the third gate structure G3 extends along a second direction, that is, the extension direction of the third gate structure G3 and the first gate structure G1 is the same. In the first direction, the third gate structure G3 is disposed apart from the first gate structure G1, and the third gate structure G3 is disposed on one side of the first gate structure G1 away from the second gate structure G2. The third gate structure G3 is disposed only on a surface of the first extension AA1, and is not disposed on a surface of the second extension AA2.

[0040] In this embodiment, the antifuse structure further includes a first connection structure T3, which is connected to the third gate structure G3, and the third gate structure G3 can be connected to a programming line located in an upper layer thereof through the first connection structure T3, that is, the first connection structure T3 functions as a conductive plug for realizing an electrical connection between the third gate structure G3 and a programming line located in an upper layer thereof.

[0041] In this embodiment, the first connection structure T3 is disposed on one side of the first extension portion AA1 away from the second extension portion AA2. Specifically, the third gate structure G3 includes a third main area G31 disposed corresponding to the first extension portion AA1 and a third sub-area G32 protruding in a direction away from the second extension portion AA2, that is, the third main area G31 and the first extension portion AA1 are disposed opposite to each other, the third sub-area G32 and the first extension portion AA1 are disposed intersecting with each other, and the first connection structure T3 is connected to the third sub-area G32 away from the second extension portion AA2.

[0042] The antifuse structure further includes a fourth gate structure G4. The fourth gate structure G4 is disposed on the surface of the second extension AA2 and can be connected to a programming line. In some embodiments, the fourth gate structure G4 extends along a second direction, that is, the extension direction of the fourth gate structure G4 is the same as the extension direction of the first gate structure G1. In the first direction, the fourth gate structure G4 is disposed apart from the first gate structure G1, and the fourth gate structure G4 is disposed on one side of the first gate structure G11 away from the second gate structure G2, and in the second direction, the fourth gate structure G4 is disposed apart from the third gate structure G3, and the fourth gate structure G4 is disposed only on the surface of the second extension AA2 and not on the surface of the first extension AA1. It can be understood that in some embodiments, the lengths of the third gate structure G3 and the fourth gate structure G4 along the second direction are both shorter than the length of the first gate structure G1 along the second direction.

[0043] In this embodiment, the antifuse structure further includes a second connection structure T4. The second connection structure T4 is connected to the fourth gate structure G4, and the fourth gate structure G4 can be connected to a programming line located in an upper layer thereof via the second connection structure T4. That is, the second connection structure T4 functions as a conductive plug for realizing an electrical connection between the fourth gate structure G4 and a programming line located in an upper layer thereof. In some embodiments, the third gate structure G3 and the fourth gate structure G4 are connected to different programming lines to realize separate control of the first antifuse unit and the second antifuse unit.

[0044] In this embodiment, the second connection structure T4 is disposed on one side of the second extension portion AA2 away from the first extension portion AA1. Specifically, the fourth gate structure G4 includes a fourth main area G41 disposed corresponding to the second extension portion AA2 and a fourth sub-area G42 protruding in a direction away from the first extension portion AA1, that is, the fourth main area G41 and the second extension portion AA2 are disposed opposite to each other, the fourth sub-area G42 and the second extension portion AA2 are disposed intersecting with each other, and the second connection structure T4 is connected to the fourth sub-area G42 away from the first extension portion AA1.

[0045] The antifuse structure further includes a fifth gate structure G5. The fifth gate structure G5 is disposed on a surface of the third extension portion AA3 and may be disposed on a programming line. In some embodiments, the fifth gate structure G5 extends along a second direction, that is, the extending direction of the fifth gate structure G5 is the same as the extending direction of the second gate structure G2. In the first direction, the fifth gate structure G5 is disposed apart from the second gate structure G2, and the fifth gate structure G5 is disposed on one side of the second gate structure G2 that is away from the first gate structure G1. The fifth gate structure G5 is disposed only on a surface of the third extension portion AA3 and is not disposed on a surface of the fourth extension portion AA4.

[0046] In this embodiment, the antifuse structure further includes a third connection structure T5. The third connection structure T5 is connected to the fifth gate structure G5, and the fifth gate structure G5 can be connected to a programming line located in an upper layer thereof through the third connection structure T5. That is, the third connection structure T5 functions as a conductive plug for realizing an electrical connection between the fifth gate structure G5 and the programming line located in an upper layer thereof.

[0047] In this embodiment, the third connection structure T5 is disposed on one side of the third extension portion AA3 away from the fourth extension portion AA4. Specifically, the fifth gate structure G5 includes a fifth main area G51 disposed corresponding to the third extension portion AA3, and a fifth sub-area G52 protruding in a direction away from the fourth extension portion AA4. That is, the fifth main area G51 and the third extension portion AA3 are disposed opposite to each other, the fifth sub-area G52 and the third extension portion AA3 are disposed intersecting with each other, and the third connection structure T5 is connected to the fifth sub-area G52 away from the third extension portion AA3.

[0048] The antifuse structure further includes a sixth gate structure G6. The sixth gate structure G6 is disposed on a surface of the fourth extension portion AA4 and may be disposed on a programming line. In some embodiments, the sixth gate structure G6 extends along a second direction, i.e., the extension direction of the sixth gate structure G6 is the same as the extension direction of the second gate structure G2. In the first direction, the sixth gate structure G6 is disposed apart from the second gate structure G2, and the sixth gate structure G6 is disposed on one side of the second gate structure G2 away from the first gate structure G1, and in the second direction, the sixth gate structure G6 is disposed apart from the fifth gate structure G5, and the sixth gate structure G6 is disposed only on the surface of the fourth extension portion AA4 and not on the surface of the third extension portion AA3. It can be understood that in some embodiments, the lengths of the fifth gate structure G5 and the sixth gate structure G6 along the second direction are both shorter than the length of the second gate structure G2 along the second direction.

[0049] In this embodiment, the antifuse structure further includes a fourth connection structure T6. The fourth connection structure T6 is connected to the sixth gate structure G6, and the sixth gate structure G6 can be connected to a programming line located in an upper layer thereof via the fourth connection structure T6. That is, the fourth connection structure T6 functions as a conductive plug for realizing an electrical connection between the sixth gate structure G6 and a programming line located in an upper layer thereof. In some embodiments, the fifth gate structure G5 and the sixth gate structure G6 are connected to different programming lines to realize separate control of the third antifuse unit and the fourth antifuse unit.

[0050] In this embodiment, the fourth connection structure T6 is disposed on one side of the fourth extension portion AA4 away from the third extension portion AA3. Specifically, the sixth gate structure G6 includes a sixth main area G61 disposed corresponding to the fourth extension portion AA4 and a sixth sub-area G62 protruding in a direction away from the third extension portion AA3, that is, the sixth main area G61 and the fourth extension portion AA4 are disposed opposite to each other, the sixth sub-area G62 and the fourth extension portion AA4 are disposed intersecting with each other, and the fourth connection structure T6 is connected to the sixth sub-area G62.

[0051] The antifuse structure further comprises a first doped region D1. The first doped region D1 is located in the active area AA between the first gate structure G1 and the second gate structure G2. In this embodiment, when the active area AA is a P-type well region, the first doped region D1 is an N-type doped region. In another embodiment, when the active area AA is an N-type well region, the first doped region D1 is a P-type doped region.

[0052] The antifuse structure further includes a bit line connection structure BLC, which is connected to a first doped region D1 between the first gate structure G1 and the second gate structure, and the first doped region D1 can be connected to a bit line via the bit line connection structure BLC. That is, the bit line connection structure BLC functions as a conductive plug for connecting the first doped region D1 and a bit line, and realizes an electrical connection between the bit line and the first doped region D1.

[0053] The antifuse structure further comprises a second doped region D2. The second doped region D2 is disposed in the active area AA on one side of the first gate structure G1 away from the second gate structure G2, in the first extension AA1, and in the second extension AA2. In this embodiment, the doping type of the second doped region D2 is the same as that of the first doped region D1 and opposite to that of the active area AA, and when the active area AA is a P-type well region, the second doped region D2 is an N-type doped region. In another embodiment, when the active area AA is an N-type well region, the second doped region D2 is a P-type doped region.

[0054] The antifuse structure further comprises a third doped region D3. The third doped region D3 is disposed in the active area AA on one side of the second gate structure G2 away from the first gate structure G1, in the third extension AA3, and in the fourth extension AA4. In this embodiment, the doping type of the third doped region D3 is the same as that of the first doped region D1 and opposite to that of the active area AA, and when the active area AA is a P-type well region, the third doped region D3 is an N-type doped region. In another embodiment, when the active area AA is an N-type well region, the third doped region D3 is a P-type doped region.

[0055] Here, the first gate structure G1 and the active area AA and the first doped region D1 and the second doped region D2 located thereunder constitute the first selection transistor. The second doped region D2 is located within the first extension AA1, and the third gate structure G3 and the second doped region D2 located thereunder constitute a first anti-fuse unit. The second doped region D2 is also located within the second extension AA2, and the fourth gate structure G4 and the second doped region D2 located thereunder constitute a second anti-fuse unit.

[0056] In this embodiment, the third main area G31 of the third gate structure G3 is used as an active area, and the third main area G31 and the second doped region D2 constitute the first anti-fuse unit, and the fourth main area G41 of the fourth gate structure G4 is used as an active area, and the fourth main area G41 and the second doped region D2 constitute the second anti-fuse unit.

[0057] The second gate structure G2 and the active area AA thereunder, the first doped region D1, and the third doped region D3 constitute a second selection transistor. The third doped region D3 is located within the third extension AA3, and the fifth gate structure G5 and the third doped region D3 thereunder constitute a third anti-fuse unit. The third doped region D3 is also located within the fourth extension AA4, and the sixth gate structure G6 and the third doped region D3 thereunder constitute a fourth anti-fuse unit.

[0058] In this embodiment, the fifth main area G51 of the fifth gate structure G5 is used as an effective area, and the fifth main area G51 and the third doped region D3 constitute the third anti-fuse unit; the sixth main area G61 of the sixth gate structure G6 is used as an effective area, and the sixth main area G61 and the third doped region D3 constitute the third anti-fuse unit.

[0059] In this embodiment, the first selection transistor and the second selection transistor are arranged symmetrically with respect to a first axis O, the first anti-fuse unit and the third anti-fuse unit are arranged symmetrically with respect to the first axis O, and the second anti-fuse unit and the fourth anti-fuse unit are arranged symmetrically with respect to the first axis O, which is beneficial to simplify the layout design of the anti-fuse structure and improve the utilization rate.

[0060] It can be understood that in the present embodiment, the first gate structure G1, the second gate structure G2, the third gate structure G3, the fourth gate structure G4, the fifth gate structure G5 and the sixth gate structure G6 all include a gate (not shown) and a gate dielectric layer (not shown) located between the gate and the active area AA, thereby realizing the basic function of a gate structure, where the material of the gate can be polysilicon (poly), and the material of the gate dielectric layer can be silicon oxide, high-K dielectric material, etc.

[0061] In the antifuse structure of some embodiments of the present application, the first unit 101 and the second unit 102 share the same active area AA, thereby eliminating the gap between the active areas AA caused by the first unit 101 and the second unit 102 using different active areas AA, and reducing the area of ​​the antifuse structure; and since each unit has two antifuse units, which are respectively installed on independent extension portions, the number of antifuse units can be doubled in the same area; that is, when the designed number of antifuse units is the same, the antifuse structure of the present application only needs to occupy about half the area, thereby meeting the requirement of miniaturization.

[0062] Some embodiments of the present application further provide an antifuse array, and referring to FIG. 2, FIG. 2 is a schematic diagram of an antifuse array, which includes a plurality of the above-mentioned antifuse structures. The plurality of the antifuse structures are arranged in an array along a first direction and a second direction, and the first direction is perpendicular to the second direction or has an acute angle with the second direction. In this embodiment, the first direction is a vertical direction Y direction, and the second direction is a horizontal direction X direction. FIG. 2 shows six antifuse structures, which are antifuse structures 20A, 20B, 20C, 20D, 20E and 20F, respectively, where three antifuse structures are arranged in a group along the second direction to form a row, and antifuse units in different rows are arranged along the first direction to form a column. For example, antifuse structures 20A, 20B, and 20C are arranged along the second direction to form a first row, antifuse structures 20D, 20E, and 20F are arranged along the second direction to form a second row, antifuse structures 20A and 20D are arranged along the first direction to form a first column, antifuse structures 20B and 20E are arranged along the first direction to form a second column, and antifuse structures 20C and 20F are arranged along the first direction to form a third column.

[0063] In the antifuse array according to the embodiment of the present application, the first unit 101 (see FIG. 1A) and the second unit 102 (see FIG. 1A) of the antifuse structure share the same active area AA, thereby eliminating the gap between the active areas AA caused by the first unit 101 and the second unit 102 using different active areas AA (see FIG. 1A and FIG. 1B), and reducing the area of ​​the antifuse structure. In addition, each unit has two antifuse units, which are respectively installed on independent extension portions, so that the number of antifuse units can be doubled in the same area. In other words, when the design number of antifuse units is the same, the antifuse array according to the present application only needs to occupy about half the area, thereby meeting the requirement of miniaturization.

[0064] In this embodiment, in the second direction (i.e., the horizontal direction X), adjacent antifuse units of adjacent antifuse structures share the same gate structure (or at least share the gates of the same gate structure), thus eliminating the gap that necessarily exists when using two gate structures, shortening the distance between adjacent antifuse structures, and further reducing the occupied space of the antifuse array.

[0065] For example, referring to FIG. 2, in the second direction (i.e., the horizontal direction X), antifuse structure 20A is adjacent to antifuse structure 20B, the second antifuse unit of antifuse structure 20A is adjacent to the first antifuse unit of antifuse structure 20B, the fourth antifuse unit of antifuse structure 20A is adjacent to the third antifuse unit of antifuse structure 20B, and the second antifuse unit of antifuse structure 20A and the first antifuse unit of antifuse structure 20B share the same gate structure 21. that is, the gate structure 21 extends from above the second extension portion AA2 (see FIG. 1A) of the antifuse structure 20A to above the first extension portion AA1 (see FIG. 1A) of the antifuse structure 20B, and the fourth antifuse unit of the antifuse structure 20A and the third antifuse unit of the antifuse structure 20B share the same gate structure 22, that is, the gate structure 22 extends from above the fourth extension portion AA4 (see FIG. 1A) of the antifuse structure 20A to above the third extension portion AA3 (see FIG. 1A) of the antifuse structure 20B.

[0066] 2, in the second direction (i.e., the horizontal direction X), antifuse structure 20B is adjacent to antifuse structure 20C, the second antifuse unit of antifuse structure 20B is adjacent to the first antifuse unit of antifuse structure 20C, the fourth antifuse unit of antifuse structure 20B is adjacent to the third antifuse unit of antifuse structure 20C, and the second antifuse unit of antifuse structure 20B and the first antifuse unit of antifuse structure 20C share the same gate structure 23. The fourth antifuse unit of the antifuse structure 20B and the third antifuse unit of the antifuse structure 20C share the same gate structure 24, i.e., the gate structure 24 extends from above the second extension portion AA2 (see FIG. 1A) of the antifuse structure 20B to above the first extension portion AA1 (see FIG. 1A) of the antifuse structure 20C, and the fourth antifuse unit of the antifuse structure 20B and the third antifuse unit of the antifuse structure 20C share the same gate structure 24, i.e., the gate structure 24 extends from above the fourth extension portion AA4 (see FIG. 1A) of the antifuse structure 20B to above the third extension portion AA3 (see FIG. 1A) of the antifuse structure 20C.

[0067] In this embodiment, since the second antifuse unit of antifuse structure 20A and the first antifuse unit of antifuse structure 20B share the same gate structure 21, only one connecting structure can be provided to electrically connect the gate structure to the corresponding programming line, thereby reducing the number of connecting structures. Similarly, only one connecting structure can be provided to electrically connect gate structure 22 to the corresponding programming line, electrically connect gate structure 23 to the corresponding programming line, and electrically connect gate structure 24 to the corresponding programming line.

[0068] In this embodiment, the first selection transistors of the antifuse structures arranged along the second direction share the same gate structure and the second selection transistors share the same gate structure, thus eliminating the gap that is inevitably present when using two gate structures, shortening the distance between adjacent antifuse structures, and further reducing the occupied space of the antifuse array.

[0069] 2, the first selection transistors of the antifuse structures 20A, 20B, 20C in the first row share the same gate structure 25 (at least share the gates of the same gate structure 25), the second selection transistors share the same gate structure 26 (at least share the gates of the same gate structure 26), the first selection transistors of the antifuse structures 20D, 20E, 20F in the second row share the same gate structure 27 (at least share the gates of the same gate structure 27), and the second selection transistors share the same gate structure 28 (at least share the gates of the same gate structure 28). It can be understood that the gates of the gate structures 25, 26, 27, 28 are all word lines (i.e., a portion of the word line is used as the gate of the selection transistor), and the word line is under the control of a peripheral control circuit to turn the first and second selection transistors on or off.

[0070] In this embodiment, the first selection transistors of the anti-fuse structures arranged along the second direction share the same gate structure, and therefore, by providing only one word line connection structure, the gate structure and the peripheral control circuit can be connected in correspondence with each other; similarly, the second selection transistors of the anti-fuse structures arranged along the second direction share the same gate structure, and therefore, by providing only one word line connection structure, the gate structure and the peripheral control circuit can be connected in correspondence with each other.

[0071] The present embodiment further provides a memory, and reference is made to Fig. 3, which is a schematic structural diagram of a memory according to some embodiments of the present disclosure, the memory comprising the above-mentioned anti-fuse array.

[0072] The memory further comprises a plurality of programming lines extending along the first direction (Y direction in the figure) and the second direction (X direction in the figure). Here, a row of antifuse structures arranged along the second direction corresponds to four of the programming lines, and the four programming lines are respectively connected to the first antifuse unit, the second antifuse unit, the third antifuse unit, and the fourth antifuse unit of the antifuse structure. It should be noted that the first antifuse unit, the second antifuse unit, the third antifuse unit, and the fourth antifuse unit of the same antifuse structure are respectively connected to different programming lines, thereby realizing individual control. In FIG. 3, the programming lines are drawn with dotted lines to clearly show the structure of the memory according to the embodiment of the present application. It can be understood that the programming lines and the antifuse structures may be provided in different structural layers.

[0073] For example, a row of antifuse structures arranged along the second direction (X-direction in the figure) includes antifuse structures 30A, 30B, 30C, 30D, 30E, and 30F, which correspond to four of the programming lines, which are programming line 31A, programming line 31B, programming line 31C, and programming line 31D, respectively.

[0074] The programming line 30A is connected to the first antifuse unit of antifuse structure 30A via connection structure 32A, to the second antifuse unit of antifuse structure 30B and the first antifuse unit of antifuse structure 30C via connection structure 32B, to the second antifuse unit of antifuse structure 30D and the first antifuse unit of antifuse structure 30E via connection structure 32C, and to the second antifuse unit of antifuse structure 30F via connection structure 32D.

[0075] The programming line 30B is connected to the second antifuse unit of antifuse structure 30A and the first antifuse unit of antifuse unit 30B via connection structure 32E, to the second antifuse unit of antifuse structure 30C and the first antifuse unit of antifuse structure 30D via connection structure 32F, and to the second antifuse unit of antifuse structure 30E and the first antifuse unit of antifuse structure 30F via connection structure 32G.

[0076] The programming line 30C is connected to the fourth antifuse unit of antifuse structure 30A and the third antifuse unit of antifuse unit 30B via connection structure 32H, to the fourth antifuse unit of antifuse structure 30C and the third antifuse unit of antifuse structure 30D via connection structure 32I, and to the fourth antifuse unit of antifuse structure 30E and the third antifuse unit of antifuse structure 30F via connection structure 32J.

[0077] The programming line 30D is connected to the third antifuse unit of antifuse structure 30A via connection structure 32K, to the fourth antifuse unit of antifuse structure 30B and the third antifuse unit of antifuse structure 30C via connection structure 32L, to the fourth antifuse unit of antifuse structure 30D and the third antifuse unit of antifuse structure 30E via connection structure 32M, and to the fourth antifuse unit of antifuse structure 30F via connection structure 32N.

[0078] In this embodiment, the memory further comprises a plurality of bit lines arranged along a second direction and extending along a first direction, and a column of anti-fuse structures arranged along the first direction share the same bit line, and the bit line is connected to the anti-fuse structures via a bit line connection structure BLC.

[0079] Specifically, as shown in FIG. 3, the memory includes a plurality of bit lines BL1, BL2, BL3, BL4, BL5, and BL6 arranged along a second direction (X direction in the figure) and extending along a first direction (Y direction in the figure). Antifuse structures in the same column share the same bit line, for example, when antifuse structures 30A and 30G arranged along the first direction form a column, the antifuse structures 30A and 30G share the same bit line BL1. The bit line BL1 is electrically connected to the antifuse structures 30A and 30G via bit line connection structures BLC, respectively. In FIG. 3, the bit lines are drawn with dotted lines to clearly show the structure of the memory according to the embodiment of the present application. It can be understood that the bit lines and the antifuse structures may be provided in different structural layers, and the bit lines and the programming lines may also be provided in different structural layers. In the memory according to the embodiment of the present application, when the designed number of anti-fuse units is the same, the anti-fuse array only needs to occupy about half the area, thus meeting the requirement of miniaturization.

[0080] It should be noted that what has been described above is only the preferred embodiments of the present application, and those skilled in the art may make some improvements or modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered as falling within the protection scope of the present application.

Claims

1. an antifuse structure comprising: a first unit, a second unit, a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, a fifth gate structure, a sixth gate structure, a first doped region, a second doped region, a third doped region, a first connecting structure, and a second connecting structure; the first unit includes a first selection transistor, a first anti-fuse unit and a second anti-fuse unit; the second unit includes a second selection transistor, a third anti-fuse unit and a fourth anti-fuse unit; the first unit and the second unit share an active area, a first extending portion and a second extending portion extending on a first side of the active area, the first extending portion and the second extending portion extending on a second side of the active area, the first side and the second side being disposed opposite each other along a first direction, the first antifuse unit being disposed on the first extending portion, the second antifuse unit being disposed on the second extending portion, the third antifuse unit being disposed on the third extending portion, and the fourth antifuse unit being disposed on the fourth extending portion, the first gate structure is disposed on a surface of the active area; the second gate structure is disposed on a surface of the active area and spaced apart from the first gate structure; the third gate structure is disposed on a surface of the first extension; the fourth gate structure is disposed on a surface of the second extension; the fifth gate structure is disposed on a surface of the third extension; the sixth gate structure is disposed on a surface of the fourth extension; the first doped region is disposed in an active area between the first gate structure and the second gate structure; the second doped region is disposed in an active area on one side of the first gate structure away from the second gate structure, in the first extension, and in the second extension; the third doped region is disposed in an active area on one side of the second gate structure away from the first gate structure, in the third extension, and in the fourth extension; a size in the second direction of an overlapping portion between the first gate structure and the active area is larger than a size in the second direction of an overlapping portion between the third gate structure and the first extension portion and is larger than a size in the second direction of an overlapping portion between the fourth gate structure and the second extension portion, a size in the second direction of an overlapping portion between the second gate structure and the active area is larger than a size in the second direction of an overlapping portion between the fifth gate structure and the third extension portion and is larger than a size in the second direction of an overlapping portion between the sixth gate structure and the fourth extension portion, the second direction is perpendicular to the first direction, the first gate structure, the first doped region, and the second doped region constitute the first selection transistor, the third gate structure and the second doped region in the first extension constitute the first anti-fuse unit, the fourth gate structure and the second doped region in the second extension constitute the second anti-fuse unit, the second gate structure, the first doped region, and the third doped region constitute the second selection transistor, the fifth gate structure and the third doped region in the third extension constitute the third anti-fuse unit, and the sixth gate structure and the third doped region in the fourth extension constitute the fourth anti-fuse unit, the first connection structure is connected to the third gate structure, and the third gate structure can be connected to one programming line via the first connection structure, the first connection structure being disposed on one side of the first extension portion away from the second extension portion; The antifuse structure, wherein the second connection structure is connected to the fourth gate structure, and the fourth gate structure can be connected to another programming line via the second connection structure, and the second connection structure is located on one side of the second extension portion away from the first extension portion.

2. the first gate structure and the second gate structure are arranged along the first direction; The antifuse structure of claim 1 .

3. the third gate structure and the fourth gate structure are arranged along the second direction, the fifth gate structure and the sixth gate structure are arranged along the second direction; The antifuse structure of claim 2 .

4. the antifuse structure further comprising a bit line connection structure; the bit line connection structure is connected to a first doped region between the first gate structure and the second gate structure, and the first doped region can be connected to a bit line via the bit line connection structure; The antifuse structure of claim 1 .

5. the third gate structure includes a third main area provided to correspond to the first extension portion and a third sub-area protruding in a direction away from the second extension portion, and the first connection structure is connected to the third sub-area; the fourth gate structure includes a fourth main area provided to correspond to the second extension portion and a fourth sub-area protruding in a direction away from the first extension portion, and the second connection structure is connected to the fourth sub-area. The antifuse structure of claim 1 .

6. the antifuse structure further comprises a third connecting structure and a fourth connecting structure; the third connection structure is connected to the fifth gate structure, and the fifth gate structure can be connected to one programming line via the third connection structure, and the third connection structure is disposed on one side of the third extension portion away from the fourth extension portion; the fourth connection structure is connected to the sixth gate structure, and the sixth gate structure can be connected to another programming line via the fourth connection structure, and the fourth connection structure is disposed on one side of the fourth extension portion away from the third extension portion; The antifuse structure of claim 1 .

7. the fifth gate structure includes a fifth main area provided to correspond to the third extension portion and a fifth sub-area protruding in a direction away from the fourth extension portion, and the third connection structure is connected to the fifth sub-area; the sixth gate structure includes a sixth main area provided to correspond to the fourth extension portion and a sixth sub-area protruding in a direction away from the third extension portion, and the fourth connection structure is connected to the sixth sub-area; The antifuse structure of claim 6.

8. the first selection transistor and the second selection transistor are symmetrically arranged with respect to a first axis, the first anti-fuse unit and the third anti-fuse unit are symmetrically arranged with respect to the first axis, and the second anti-fuse unit and the fourth anti-fuse unit are symmetrically arranged with respect to the first axis. The antifuse structure of claim 1 .

9. 1. An antifuse array comprising: A plurality of antifuse structures according to claim 1, The antifuse array, wherein the antifuse structures are arranged in an array along a first direction and a second direction, the first direction being perpendicular to the second direction.

10. adjacent antifuse units of adjacent antifuse structures in the second direction share the same gate structure; The first selection transistors of the anti-fuse structures arranged along the second direction share a same gate structure, and the second selection transistors of the anti-fuse structures share a same gate structure.

10. The anti-fuse array of claim 9.

11. A memory comprising the antifuse array of claim 9.

12. the memory further comprises a plurality of programming lines arranged along the first direction and extending along the second direction, a row of antifuse structures arranged along the second direction corresponding to four of the programming lines, the four programming lines being respectively connected to the first antifuse unit, the second antifuse unit, the third antifuse unit, and the fourth antifuse unit of the antifuse structure; The memory of claim 11.

13. The memory further comprises a plurality of bit lines arranged in a second direction and extending in a first direction, and a column of anti-fuse structures arranged in the first direction share the same bit line. The memory of claim 11.

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