Electro-optical devices and electronic equipment

Abstract

To provide an electro-optic device capable of appropriately inspecting a temperature detection circuit, and an electronic apparatus.SOLUTION: The electro-optic device comprises: a temperature detection element 11; and an electrostatic protection circuit 12 protecting the temperature detection element 11 from surge current. The electrostatic protection circuit 12 includes: a transistor Tr electrically connected in parallel to the temperature detection element 11; a first capacitive element C1 electrically connected to the transistor Tr; and a resistive element R3 electrically connected in parallel to the first capacitive element C1. Electrostatic capacitance of the first capacitive element C1 is greater than gate capacitance between a gate electrode 33t and a semiconductor layer composing the transistor Tr. A dielectric layer of the first capacitive element C1 is thicker than a gate insulation film of the transistor Tr. Accordingly, when charge up generated during a manufacturing process or surge current after the manufacturing process intrudes, the transistor Tr is more likely to cause breakdown than the first capacitive element C1, thus application of over-voltage can be detected.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to an electro-optical device provided with a temperature detection element, and to an electronic device. [Background technology]

[0002] An electro-optical device such as a liquid crystal device has a first substrate having pixel transistors and pixel electrodes in a display area, a second substrate having a common electrode facing the pixel electrodes, and an electro-optical layer provided between the first substrate and the second substrate, and applies a voltage according to an image signal between the pixel electrodes and the common electrode. In an electro-optical device configured in this way, for example, light from a light source irradiated from the second substrate side is modulated to display an image.

[0003] In electro-optical devices, the response speed of the electro-optical layer may change due to the influence of changes in the environmental temperature, and the display performance may change. Therefore, a technique has been proposed in which an image signal is corrected based on the result of detecting the temperature by a temperature detection element provided on the first substrate (see Patent Document 1). In the temperature detection circuit described in Patent Document 1, a constant current is passed through the temperature detection element, and a voltage between the anode and cathode of the temperature detection element is detected. In the temperature detection circuit described in Patent Document 1, an electrostatic protection circuit is provided that includes a transistor electrically connected in parallel with the temperature detection element, and two capacitance elements electrically connected in series between the anode wiring and the cathode wiring, and the connection node of the two capacitance elements is electrically connected to the gate electrode of the transistor. In addition, the connection node of the two capacitance elements is electrically connected to the cathode wiring via a resistance element. According to this electrostatic protection circuit, when a surge current due to static electricity enters from the anode wiring, the potential of the gate electrode rises and the transistor is turned on, so that the surge current can be released to the cathode wiring via the transistor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-184719 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the temperature detection circuit described in Patent Document 1, if a defect occurs in each element of the electrostatic protection circuit or the temperature detection element, the temperature detection cannot be performed properly and the electrostatic protection circuit cannot perform the specified protection function. For this reason, in the state of the first substrate alone or in the state of the electro-optical device, a voltage is applied from a probe in contact with each of the anode terminal and the cathode terminal, and the current is measured by a current detection means, thereby inspecting whether or not a defect occurs in the temperature detection circuit. Here, if a dielectric breakdown occurs in the anode-side capacitance element, a current in which a short-circuit current flowing through the anode-side capacitance element is superimposed is detected, so that the defect of the anode-side capacitance element can be detected. However, if a dielectric breakdown occurs in the cathode-side capacitance element, the short-circuit current of the cathode-side capacitance element cannot be detected because both electrodes of the cathode-side capacitance element are made to have the same potential by the resistance element, and there is a problem that the temperature detection circuit cannot be inspected properly. In this case, the resistance value of the resistance element becomes lower than the specified value in the electrostatic protection circuit, and thereafter, for example, when a surge enters from the anode terminal, the on-time of the transistor becomes shorter, and the specified protection function is not performed. [Means for solving the problem]

[0006] In order to solve the above problems, one aspect of the electro-optical device according to the present invention is to A temperature detection element; before a transistor electrically connected in parallel to the temperature detection element; a first capacitance element electrically connected in parallel to the first capacitance element; and a resistance element electrically connected in parallel to the first capacitance element. and an electrostatic protection circuit having a gate electrode, a semiconductor layer, and a front end. a gate insulating film provided between the semiconductor layer and the gate electrode; The resistor element is one end a first capacitance electrode electrically connected to the gate electrode; , the other of the resistor elements end and electrically connected to one of the source and drain regions of the semiconductor layer. a second capacitance electrode connected to the first capacitance electrode and a first capacitance electrode provided between the first capacitance electrode and the second capacitance electrode; a dielectric layer, and the capacitance of the first capacitance element is determined by the gate electrode and the semiconductor layer. The capacitance between the electrodes is larger than the capacitance between the electrodes.

[0007] Another aspect of the electro-optical device according to the present invention is a temperature detection element, and a capacitor connected in parallel to the temperature detection element. a transistor electrically connected to the first capacitance element; and an electrostatic protection circuit having a resistive element electrically connected in parallel to the first capacitive element; The transistor comprises a gate electrode, a semiconductor layer, and a gate electrode connected to the semiconductor layer. a gate insulating film provided between the electrodes of the first capacitance element and the first resistance element; end a first capacitance electrode electrically connected to the gate electrode; and end oh and a second capacitance electrode electrically connected to one of the source / drain regions of the semiconductor layer; a first dielectric layer provided between the first capacitance electrode and the second capacitance electrode, The first dielectric layer is thicker than the gate insulating film.

[0008] Another aspect of the electro-optical device according to the present invention includes a temperature detection element, an electrostatic protection circuit having a transistor electrically connected in parallel to the temperature detection element, a first capacitance element electrically connected to the transistor, and a resistance element electrically connected in parallel to the first capacitance element, and a display region in which a plurality of pixels each having a pixel electrode and a storage capacitor are arranged, the transistor having a gate electrode, a semiconductor layer, and a gate insulating film provided between the semiconductor layer and the gate electrode, the first capacitance element being electrically connected to one electrode of the resistance element and the gate electrode. the semiconductor layer includes a first capacitance electrode electrically connected to the other electrode of the resistance element, a second capacitance electrode electrically connected to the other electrode of the resistance element and one of the source-drain regions of the semiconductor layer, and a first dielectric layer provided between the first capacitance electrode and the second capacitance electrode, and the storage capacitance includes a first electrode in the same layer as the first capacitance electrode, a second electrode in the same layer as the second capacitance electrode, a second dielectric layer in the same layer as the first dielectric layer, a third electrode electrically connected to the second electrode, a fourth electrode electrically connected to the first electrode, and a third dielectric layer provided between the third electrode and the fourth electrode.

[0009] The electro-optical device according to the present invention is used in electronic equipment. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing an example of the configuration of an electro-optical device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is an explanatory diagram that illustrates a cross section of the electro-optical device illustrated in FIG. [Diagram 3] 2 is a circuit block diagram showing an electrical configuration of the electro-optical device shown in FIG. [Figure 4] 2 is a cross-sectional view illustrating a schematic configuration example of a pixel of the electro-optical device illustrated in FIG. [Diagram 5] 2 is an explanatory diagram of a temperature detection circuit of the electro-optical device shown in FIG. [Figure 6] 6 is an explanatory diagram of a case where a surge current enters the temperature detection circuit shown in FIG. 5. [Figure 7]6 is a plan view showing a schematic planar configuration of the temperature detection element shown in FIG. 5. [Figure 8] 8 is a cross-sectional view that diagrammatically shows a cross section of the temperature detection element shown in FIG. 7. [Figure 9] 6 is a plan view that illustrates a schematic planar configuration of the electrostatic protection circuit illustrated in FIG. 5. [Figure 10] 10 is a cross-sectional view that diagrammatically illustrates a cross section of the electrostatic protection circuit shown in FIG. 9. [Figure 11] 11 is an explanatory diagram showing an enlarged view of the first capacitive element shown in FIG. 10; [Figure 12] 11 is an explanatory diagram showing an enlarged view of the second capacitive element shown in FIG. 10; [Figure 13] 5A and 5B are explanatory diagrams showing the operation and effect of the electro-optical device according to the embodiment of the invention against a surge current. [Figure 14] 10A and 10B are explanatory diagrams showing a problem in detecting a short circuit in an electro-optical device according to a reference example of the present invention. [Figure 15] FIG. 5 is an explanatory diagram of an electro-optical device according to a second embodiment of the present invention. [Figure 16] FIG. 11 is an explanatory diagram of an electro-optical device according to a third embodiment of the present invention. [Figure 17] FIG. 11 is an explanatory diagram of an electro-optical device according to a fourth embodiment of the present invention. [Figure 18] 1 is a block diagram showing an example of the configuration of a projection display device to which the present invention is applied. [Figure 19] FIG. 19 is an explanatory diagram of the light path shift element shown in FIG. 18 . DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] An embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, each layer and each member is shown at a different scale so that each layer and each member can be recognized on the drawing. In addition, when describing the arrangement of layers formed on the first substrate, the upper layer side or the surface side means the side opposite to the side where the substrate body of the first substrate is located (the side where the counter substrate and the liquid crystal layer are located), and the lower layer side means the side where the substrate body of the first substrate is located. In describing the arrangement of layers formed on the second substrate, the upper layer side or the surface side means the side opposite to the side where the substrate body of the counter substrate is located (the side where the first substrate and the liquid crystal layer are located), and the lower layer side means the side where the substrate body of the second substrate is located. In addition, in the present invention, "planar view" means a state seen from the normal direction to the first substrate 10 or the second substrate 20.

[0012] 1. Embodiment 1-1. Specific configuration of the electro-optical device 100 FIG. 1 is a plan view showing a configuration example of an electro-optical device 100 according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram showing a cross section of the electro-optical device 100 shown in FIG. 1. The electro-optical device 100 shown in FIGS. 1 and 2 is a liquid crystal device and has a liquid crystal panel 100p. In the electro-optical device 100, the first substrate 10 and the second substrate 20 are bonded together with a sealant 107 with a predetermined gap therebetween, and the sealant 107 is provided in a frame shape along the outer edge of the second substrate 20. The sealant 107 is an adhesive made of a photocurable resin, a thermosetting resin, or the like, and is mixed with a gap material 107a such as glass fiber or glass beads for setting the distance between the two substrates to a predetermined value. In the electro-optical device 100, an electro-optical layer 50 made of a liquid crystal layer is provided in the area surrounded by the sealant 107 between the first substrate 10 and the second substrate 20. The sealant 107 has a discontinuous portion 107c formed therein to be used as a liquid crystal injection port, and the discontinuous portion 107c is sealed with a sealing material 108 after the liquid crystal material is injected. When the liquid crystal material is injected by a dropping method, the discontinuous portion 107c is not formed. The first substrate 10 and the second substrate 20 are both rectangular, and the display area 10a is provided as a rectangular area in the approximate center of the electro-optical device 100. Corresponding to this shape, the sealant 107 is also provided in an approximately rectangular shape, and the outside of the display area 10a is a peripheral area 10c in the shape of a rectangular frame.

[0013] In the display region 10a, when two sides extending in the first direction X are defined as a first side 10a1 and a second side 10a2, and two sides extending in the second direction Y are defined as a third side 10a3 and a fourth side 10a4, in the peripheral region 10c of the first substrate 10, a data line driving circuit 101 is provided between an end of the first substrate 10 and the first side 10a1 of the display region 10a, and a precharge circuit 105 is provided between the end of the first substrate 10 and the second side 10a2 of the display region 10a. In addition, a scanning line driving circuit 104 is provided between the end of the first substrate 10 and the third side 10a3 of the display region 10a, and between the end of the first substrate 10 and the fourth side 10a4 of the display region 10a.

[0014] The first substrate 10 has a translucent substrate body 10w such as a quartz substrate or a glass substrate, and on the side of one surface 10s of the first substrate 10 facing the second substrate 20, a plurality of pixel transistors and pixel electrodes 9a electrically connected to each of the plurality of pixel transistors are formed in a matrix in the display region 10a. A first alignment film 16 is formed on the upper layer side of the pixel electrodes 9a. On the side of the one surface 10s of the first substrate 10, in a rectangular frame region 10b extending along the outer edge of the display region 10a and the seal material 107, dummy pixel electrodes 9b formed simultaneously with the pixel electrodes 9a are formed in portions extending along each side of the display region 10a. The surface of the first substrate 10 opposite to the one surface 10s facing the second substrate 20 is marked with the symbol 10t.

[0015] The second substrate 20 has a light-transmitting substrate body 20w such as a quartz substrate or a glass substrate, and a common electrode 21 is formed on one surface 20s of the second substrate 20 facing the first substrate 10. The common electrode 21 is formed on substantially the entire surface of the one surface 20s of the second substrate 20. On the one surface 20s of the second substrate 20, a light-shielding layer 29 is formed on the lower layer side of the common electrode 21 in the frame region 10b, and a second alignment film 26 is laminated on the surface of the common electrode 21. A light-transmitting flattening film 22 is formed between the light-shielding layer 29 and the common electrode 21. The light-shielding layer 29 is formed as a border 29a extending along the frame region 10b, and the display region 10a is defined by the inner edge of the border 29a. The light-shielding layer 29 may be formed as a black matrix portion overlapping an inter-pixel region 10f sandwiched between adjacent pixel electrodes 9a. The parting 29a is formed at a position overlapping with the dummy pixel electrode 9b in plan view. The light-shielding layer 29 is made of a light-shielding metal film or black resin. The surface of the second substrate 20 opposite to the surface 20s facing the first substrate 10 is marked with the symbol 20t.

[0016] The first alignment film 16 and the second alignment film 26 are made of SiO XThe electro-optical device 100 is an inorganic alignment film made of an obliquely evaporated film of TiO2, MgO, Al2O3, etc. (x≦2), and is made of a columnar structure layer in which pillar-shaped bodies called columns are formed obliquely with respect to the first substrate 10 and the second substrate 20. Therefore, the first alignment film 16 and the second alignment film 26 align the nematic liquid crystal molecules with negative dielectric anisotropy used in the electro-optical layer 50 obliquely with respect to the first substrate 10 and the second substrate 20, and provide a pretilt to the liquid crystal molecules. In this way, the electro-optical device 100 is configured as a normally black VA (Vertical Alignment) mode liquid crystal device.

[0017] On the first substrate 10, outside the sealing material 107, inter-substrate conduction electrode portions 6t are formed at positions overlapping with four corner portions 24t of the second substrate 20. The inter-substrate conduction electrode portions 6t are electrically connected to a common potential line 6s, and the common potential line 6s is electrically connected to a terminal 102g for applying a common potential COM among the terminals 102. An inter-substrate conductive material 109 containing conductive particles is disposed between the inter-substrate conduction electrode portions 6t and the corner portions 24t, and the common electrode 21 of the second substrate 20 is electrically connected to the first substrate 10 side via the inter-substrate conduction electrode portions 6t and the inter-substrate conductive material 109. Therefore, the common potential COM is applied to the common electrode 21 from the first substrate 10 side. In addition to terminal 102g for applying a common potential, terminal 102 also includes a cathode terminal 102c electrically connected to the cathode wiring of a temperature detection circuit described later, and an anode terminal 102a electrically connected to the anode wiring of the temperature detection circuit.

[0018] The electro-optical device 100 of this embodiment is a transmissive liquid crystal device. Therefore, the pixel electrodes 9a and the common electrode 21 are formed of a light-transmitting conductive film such as an ITO (Indium Tin Oxide) film or an IZO (Indium Zinc Oxide) film. In such a transmissive liquid crystal device, for example, light from a light source incident from the second substrate 20 side is modulated while being emitted from the first substrate 10 to display an image.

[0019] The electro-optical device 100 can be used as a color display device for electronic devices such as mobile computers and mobile phones, and in this case, a color filter (not shown) is formed on the second substrate 20 or the first substrate 10. The electro-optical device 100 can also be used as an RGB light valve in a projection display device, which will be described later. In this case, no color filter is formed on each of the RGB electro-optical devices 100, since light of each color separated through, for example, a dichroic mirror for RGB color separation is incident on each of the RGB electro-optical devices 100 as projection light.

[0020] 1-2. Electrical configuration of the electro-optical device 100 FIG. 3 is a circuit block diagram showing the electrical configuration of the electro-optical device 100 shown in FIG. 1. In FIG. 3, the electro-optical device 100 includes a VA mode liquid crystal panel 100p, which includes a display area 10a in which a plurality of pixels 100a are arranged in a matrix in the central area. In the liquid crystal panel 100p, the first substrate 10 described with reference to FIG. 1 and FIG. 2, etc., includes a plurality of scanning lines 3a extending from the scanning line driving circuit 104 in the first direction X and a plurality of data lines 6a extending from the data line driving circuit 101 in the second direction Y on the inside of the display area 10a, and the pixels 100a are configured corresponding to the intersections of the scanning lines 3a and the data lines 6a. The plurality of data lines 6a are electrically connected to a precharge circuit 105 arranged on the second side 10a2 side of the display area 10a. Each of the pixels 100a includes a pixel transistor 30, which is a field effect transistor or the like, and a pixel electrode 9a electrically connected to the pixel transistor 30. A data line 6a is electrically connected to the source of the pixel transistor 30, a scanning line 3a is electrically connected to the gate of the pixel transistor 30, and a pixel electrode 9a is electrically connected to the drain of the pixel transistor 30. An image signal is supplied to the data line 6a, and a scanning signal is supplied to the scanning line 3a.

[0021] In each pixel 100a, the pixel electrode 9a faces the common electrode 21 of the second substrate 20 described with reference to FIG. 2 through the electro-optical layer 50 to form a liquid crystal capacitance 50a. In each pixel 100a, a storage capacitance 55 is added in parallel with the liquid crystal capacitance 50a to prevent fluctuations in the image signal stored in the liquid crystal capacitance. In this embodiment, in order to form the storage capacitance 55, a capacitance line 8a extending across the multiple pixels 100a is formed on the first substrate 10, and a common potential COM is supplied to the capacitance line 8a. The capacitance line 8a is provided so as to overlap at least one of the scanning line 3a and the data line 6a. FIG. 3 illustrates an example in which the capacitance line 8a overlaps both the scanning line 3a and the data line 6a. Although not shown, the capacitance line 8a is electrically connected to the common potential line 6s described in FIG. 1. In addition, in FIG. 3, the odd-numbered scanning lines 3a are driven by the scanning line driving circuit 104 arranged to the left of the display area 10a, and the even-numbered scanning lines 3a are driven by the scanning line driving circuit 104 arranged to the right of the display area 10a, but the same scanning lines 3a may be driven by the left and right scanning line driving circuits 104.

[0022] In the first substrate 10, a temperature detection circuit 1, which will be described later with reference to Fig. 5, etc., is configured outside the display region 10a. In addition, in the first substrate 10, an inspection region 17 for inspecting electrical characteristics of elements constituting the temperature detection circuit 1, etc., may be provided outside the display region 10a.

[0023] 1-3. Specific configuration of pixel 100a FIG. 4 is a cross-sectional view showing a schematic configuration example of a pixel 100a of the electro-optical device 100 shown in FIG. 1. As shown in FIG. 4, a lower light-shielding layer 2a made of a conductive film such as a metal silicide film, a metal film, or a metal compound film is formed on the first substrate 10. The light-shielding layer 2a is formed along the scanning line 3a. In this embodiment, the light-shielding layer 2a is made of a light-shielding film such as tungsten silicide (WSi). A light-transmitting insulating film 41 made of a silicon oxide film or the like is formed on the upper layer side of the light-shielding layer 2a, and a pixel transistor 30 having a semiconductor layer 31a is formed on the surface side of the insulating film 41. The light-shielding layer 2a prevents return light or the like incident from the substrate main body 10w side from entering the pixel transistor 30.

[0024] The pixel transistor 30 includes a semiconductor layer 31a and a gate electrode 33g made of a part of the scanning line 3a intersecting with the semiconductor layer 31a. A light-transmitting gate insulating film 32 made of a silicon oxide film or the like is provided between the semiconductor layer 31a and the gate electrode 33g. The thickness of the gate insulating film 32 is, for example, 80 nm to 100 nm. The semiconductor layer 31a is made of a polysilicon film or the like. The pixel transistor 30 has an LDD (Lightly Doped Drain) structure. More specifically, in the pixel transistor 30, the source region 31s includes a high concentration region 31s1 separated from the channel region 31g and a low concentration region 31s2 sandwiched between the channel region 31g and the high concentration region 31s1, and the drain region 31d includes a high concentration region 31d1 separated from the channel region 31g and a low concentration region 31d2 sandwiched between the channel region 31g and the high concentration region 31d1. In some cases, the light-shielding layer 2a is used as the scanning line 3a, and the gate electrode 33g is electrically connected to the light-shielding layer 2a via a contact hole (not shown) that penetrates the gate insulating film 32 and the insulating film 41.

[0025] On the upper layer side of the gate electrode 33g, light-transmitting insulating films 42, 43, 44, 45, 46, and 47 made of silicon oxide films or the like are laminated in this order, and the storage capacitor 55 described with reference to Fig. 3 is configured by utilizing the spaces between the insulating films 42, 43, 44, and 45. In this embodiment, the storage capacitor 55 includes a first storage capacitor 551 configured between the insulating film 42 and the insulating film 44, and a second storage capacitor 552 configured between the insulating film 43 and the insulating film 45, and the first storage capacitor 551 and the second storage capacitor 552 are electrically connected in parallel.

[0026] More specifically, the first electrode 4a is formed between the insulating film 42 and the insulating film 43. The insulating film 43 has an opening 43a formed by removing a part of the portion overlapping with the first electrode 4a in a plan view, and a part of the first electrode 4a is exposed from the insulating film 43 at the bottom of the opening 43a. An insulating film 48 and a second electrode 5a are sequentially stacked between the insulating film 43 and the insulating film 44, and the first electrode 4a and the second electrode 5a overlap with each other at the bottom of the opening 43a in a plan view via the insulating film 48. Therefore, the first electrode 4a and the second electrode 5a form a first storage capacitor 551 with the insulating film 48 as a dielectric film. The insulating film 43 protects the first electrode 4a when the second electrode 5a and the insulating film 48 are patterned. Therefore, the first electrode 4a and the second electrode 5a overlap with each other outside the opening 43a via the insulating films 43 and 48, whereas they overlap with each other inside the opening 43a via only the insulating film 48. Therefore, the portion where the first electrode 4a and the second electrode 5a overlap outside the opening 43a accounts for a small proportion of the capacitance of the first storage capacitor 551.

[0027] A third electrode 5b is formed between the insulating film 43 and the insulating film 44. In this embodiment, the second electrode 5a and the third electrode 5b are made of the same conductive film. Therefore, in this embodiment, the second electrode 5a and the third electrode 5b are the same electrode. The insulating film 44 has an opening 44a formed by removing a part of a portion that overlaps with the third electrode 5b (second electrode 5a) in a planar view, and a part of the third electrode 5b (second electrode 5a) is exposed from the insulating film 44 at the bottom of the opening 44a. An insulating film 49 and a fourth electrode 7a are laminated in this order between the insulating film 44 and the insulating film 45, and the third electrode 5b (second electrode 5a) and the fourth electrode 7a overlap with each other at the bottom of the opening 44a through the insulating film 49 in a planar view. Therefore, the third electrode 5b (second electrode 5a) and the fourth electrode 7a form a second storage capacitor 552 having the insulating film 49 as a dielectric film. The insulating film 44 protects the third electrode 5b (second electrode 5a) when the fourth electrode 7a and the insulating film 49 are patterned. Therefore, the third electrode 5b (second electrode 5a) and the fourth electrode 7a overlap with each other outside the opening 44a via the insulating films 44 and 49, whereas they overlap with each other inside the opening 44a via only the insulating film 49. Therefore, the portion where the third electrode 5b (second electrode 5a) and the fourth electrode 7a overlap with each other outside the opening 44a accounts for a small proportion of the capacitance of the second storage capacitor 552.

[0028] In this embodiment, the first electrode 4a is, for example, a conductive polysilicon film, and the thickness of the first electrode 4a is, for example, 100 nm. The insulating film 43 is, for example, a silicon oxide film, and the thickness of the insulating film 43 is, for example, 100 nm or more. The insulating film 48 is, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof. When the insulating film 48 is silicon oxide, the thickness of the insulating film 48 is, for example, 100 nm. When the insulating film 48 is silicon nitride, the relative dielectric constant is large, so that the capacitance of the first storage capacitor 551 can be made larger than when the insulating film 48 is silicon oxide. The conductive film constituting the second electrode 5a (third electrode 5b) is, for example, a conductive polysilicon film, and the thickness of the conductive film is, for example, 100 nm. The insulating film 44 is, for example, a silicon oxide film, and the thickness of the insulating film 44 is, for example, 100 nm or more. The insulating film 49 is, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof. When the insulating film 49 is silicon oxide, the thickness of the insulating film 49 is, for example, 100 nm. If the insulating film 49 is made of silicon nitride, the relative dielectric constant is large, and therefore the capacitance of the second storage capacitor 552 can be made larger than when the insulating film 49 is made of silicon oxide. The fourth electrode 7a is made of, for example, tungsten silicide, and has a film thickness of, for example, 150 nm. The fourth electrode 7a also functions as a light shielding film that suppresses light from entering the pixel transistor 30 from the pixel electrode 9a side.

[0029] In the first storage capacitor 551 and the second storage capacitor 552 thus configured, the conductive film constituting the third electrode 5b (second electrode 5a) is electrically connected to the drain region 31d of the pixel transistor 30 through a contact hole 43d penetrating the gate insulating film 32 and the insulating films 42 and 43. The relay electrode 6c formed between the insulating film 45 and the insulating film 46 is electrically connected to the first electrode 4a through a contact hole 45c penetrating the insulating films 43, 44, and 45, and is electrically connected to the fourth electrode 7a through a contact hole 45e penetrating the insulating film 45. Therefore, a storage capacitor 55 in which the first storage capacitor 551 and the second storage capacitor 552 are electrically connected in parallel is configured between the conductive film constituting the third electrode 5b (second electrode 5a) and the relay electrode 6c.

[0030] A data line 6a is formed between the insulating films 45 and 46, and the data line 6a is electrically connected to a source region 31s of the pixel transistor 30 via a contact hole 45s penetrating the gate insulating film 32 and the insulating films 42, 43, 44, and 45. A relay electrode 6d is formed between the insulating films 45 and 46, and the relay electrode 6d is electrically connected to a conductive film constituting the third electrode 5b (second electrode 5a) via a contact hole 45d penetrating the insulating films 44 and 45.

[0031] A capacitance line 8a and a relay electrode 8d are formed between the insulating film 46 and the insulating film 47. The capacitance line 8a is electrically connected to the relay electrode 6c through a contact hole 46c that penetrates the insulating film 46. The relay electrode 8d is electrically connected to the relay electrode 6d through a contact hole 46d that penetrates the insulating film 46. The surface of the insulating film 46 is planarized by a CMP (Chemical Mechanical Polishing) process or the like.

[0032] A pixel electrode 9a is formed on the upper layer of the insulating film 47. The pixel electrode 9a is electrically connected to the relay electrode 8d via a contact hole 47d that penetrates the insulating film 47. Therefore, the pixel electrode 9a is electrically connected to the conductive film that constitutes the third electrode 5b (second electrode 5a), and is further electrically connected to the drain region 31d of the pixel transistor 30.

[0033] 1.4-Temperature detection circuit 1 configuration Fig. 5 is an explanatory diagram of the temperature detection circuit 1 of the electro-optical device 100 shown in Fig. 1. Fig. 5 shows how temperature is detected by the temperature detection circuit 1. Fig. 6 is an explanatory diagram of a case where a surge current enters the temperature detection circuit 1 shown in Fig. 5.

[0034] 3, in the electro-optical device 100 of this embodiment, the first substrate 10 is provided with a temperature detection circuit 1 for detecting the temperature of the liquid crystal panel 100p outside the display region 10a. In this embodiment, the temperature detection circuit 1 is provided in a region adjacent to the data line driving circuit 101 in the first direction X and adjacent to the scanning line driving circuit 104 in the second direction Y. The temperature detection circuit 1 includes a temperature detection element 11 and an electrostatic protection circuit 12 for protecting the temperature detection element 11 from a surge current. In the first substrate 10, the temperature detection element 11 is disposed near the display region 10a, and the electrostatic protection circuit 12 is provided between the temperature detection element 11 and an end of the first substrate 10 where the terminals 102 are arranged.

[0035] As shown in FIG. 5, the temperature detection element 11 includes, for example, a plurality of diode elements D connected in series. FIG. 5 illustrates an example in which five diode elements D1 to D5 are electrically connected in series. With such a temperature detection element 11, the sensitivity of the forward voltage of the temperature detection element 11 to the temperature when a constant current flows can be set to approximately −10 mV / ° C. An anode wiring La extending from an anode terminal 102a is electrically connected to an anode 11a of the diode element D1 of the temperature detection element 11. A cathode wiring Lc extending from a cathode terminal 102c is electrically connected to a cathode 11c of the diode element D5 of the temperature detection element 11.

[0036] Therefore, when the electro-optical device 100 is mounted on an electronic device, a minute forward drive current It of about 10 nA to several μA is supplied from the temperature detection drive circuit 151 to the temperature detection element 11 of the temperature detection circuit 1 via the anode terminal 102a and the cathode terminal 102c through a flexible wiring board (not shown) connected to the first substrate 10. Here, the forward voltage of the temperature detection element 11, which is made up of five diode elements D1 to D5, changes with temperature with a substantially linear characteristic. Therefore, by detecting the voltage between the anode terminal 102a and the cathode terminal 102c, the temperature of the liquid crystal panel 100p can be detected. At that time, since the temperature detection element 11 is disposed in the vicinity of the display area 10a, the temperature detection element 11 can properly detect the temperature of the display area 10a. Therefore, if the image signal is corrected based on the temperature detection of the temperature detection circuit 1, the electro-optical device 100 can be driven under proper conditions corresponding to the temperature of the display area 10a, and a high-quality image can be displayed.

[0037] In this embodiment, the electrostatic protection circuit 12 includes a transistor Tr connected between an anode wiring La and a cathode wiring Lc, and the transistor Tr is electrically connected in parallel to the temperature detection element 11. One source-drain region 31i of the transistor Tr is connected between the cathode terminal 102c of the cathode wiring Lc and the cathode 11c of the diode element D5 of the temperature detection element 11, and the other source-drain region 31j of the transistor Tr is connected between the anode terminal 102a of the anode wiring La and the anode 11a of the diode element D1 of the temperature detection element 11. In this embodiment, the transistor Tr is an N-channel thin film transistor, similar to the pixel transistor 30.

[0038] In the electrostatic protection circuit 12, a first capacitance element C1 and a second capacitance element C2 are connected in series and electrically connected between an anode wiring La and a cathode wiring Lc. More specifically, one end of the first capacitance element C1 is electrically connected to the cathode wiring Lc, one end of the second capacitance element C2 is electrically connected to the anode wiring La, and the other end of the first capacitance element C1 and the other end of the second capacitance element C2 are electrically connected. Therefore, the first capacitance element C1 and the second capacitance element C2 are electrically connected in series between the anode wiring La and the cathode wiring Lc.

[0039] In addition, a second resistor R2 is inserted between the cathode terminal 102c and the connection position between the cathode wiring Lc and the first capacitor C1, and a first resistor R1 is inserted between the anode terminal 102a and the connection position between the anode wiring La and the second capacitor C2. In addition, a connection node Cn between the first capacitor C1 and the second capacitor C2 is electrically connected to a gate electrode 33t of the transistor Tr.

[0040] The electrostatic protection circuit 12 includes a resistive element R3 electrically connected in parallel to the first capacitive element C1. More specifically, the gate wiring Lg extending from the gate electrode 33t of the transistor Tr is electrically connected to a connection node Cn between the first capacitive element C1 and the second capacitive element C2, and is electrically connected to a cathode wiring Lc via the resistive element R3.

[0041] Therefore, the electrostatic protection circuit 12 has a transistor Tr electrically connected in parallel to the temperature detection element 11, a first capacitance element C1 electrically connected to the transistor Tr, and a resistance element R3 electrically connected in parallel to the first capacitance element C1. The electrostatic protection circuit 12 also has a second capacitance element C2 electrically connected in series to the first capacitance element C1. Therefore, when a surge current caused by static electricity enters from the anode terminal 102a, the electrostatic protection circuit 12 protects the temperature detection element 11 from static electricity. More specifically, in the electrostatic protection circuit 12, in a static state, the gate-source voltage of the transistor Tr is 0V, and the transistor Tr is off. In contrast, as shown in FIG. 6, when a surge current Is caused by static electricity enters from the anode terminal 102a, the voltage fluctuation is suppressed by the first resistance element R1, and the potential of the gate electrode 33t of the transistor Tr, which is the potential of the connection node Cn between the first capacitance element C1 and the second capacitance element C2, rises. Therefore, the transistor Tr is turned on, and the surge current Is flows to the cathode terminal 102c through the transistor Tr and the cathode wiring Lc. At that time, the first resistor R1 reduces the surge current Is entering from the anode terminal 102a, and the second resistor R2 reduces the surge current Is entering from the cathode terminal 102c. The period during which the transistor Tr is turned on is determined by the first capacitance element C1, the second capacitance element C2, the resistor R3, and the gate capacitance of the transistor Tr. After discharging, the gate-source voltage of the transistor Tr is returned to 0V by the resistor R3. Therefore, the surge current Is flowing to the temperature detection element 11 is suppressed by the electrostatic protection circuit 12, and the temperature detection element 11 can be protected. In FIG. 5, the first resistor R1 and the second resistor R2 generate a voltage drop due to the drive current It of the temperature detection element 11. However, since the drive current It is extremely small, the effect of the voltage drop due to the first resistor element R1 and the second resistor element R2 can be almost ignored.

[0042] 1-5. Detailed configuration of temperature detection element 11 Fig. 7 is a plan view showing a schematic planar configuration of the temperature detection element 11 shown in Fig. 5. Fig. 8 is a cross-sectional view showing a schematic cross section of the temperature detection element 11 shown in Fig. 7. Fig. 8 corresponds to the A1-A1' cross section in Fig. 7. Note that in Fig. 8, illustration of upper layers of the temperature detection element 11 formed on the first substrate 10 has been omitted to the extent that it does not interfere with explanation.

[0043] In this embodiment, in constructing the temperature detection element 11 shown in FIG. 5, as shown in FIG. 7 and FIG. 8, a plurality of semiconductor layers 31h separated from each other in an island shape are provided, and a diode element D is constructed using each of the plurality of semiconductor layers 31h. More specifically, an N-type region and a P-type region are provided in each of the plurality of semiconductor layers 31h. In this embodiment, the N-type region includes a high-concentration N-type region N+31n1 and a low-concentration N-type region N-31n2, the P-type region includes a high-concentration P-type region P+31p1 and a low-concentration P-type region P-31p2, and the connection portion between the low-concentration N-type region N-31n2 and the low-concentration P-type region P-31p2 constitutes a PN junction surface. Note that the configuration of the junction is not limited to this configuration.

[0044] Relay electrodes 6b that electrically connect the diode elements D are formed on the upper layer of the insulating film 45, and the multiple relay electrodes 6b are electrically connected to the high-concentration P-type region P+31p1 of the semiconductor layer 31h and the high-concentration N-type region N+31n1 of the adjacent semiconductor layer 31h via contact holes 45p and 45n that penetrate the gate insulating film 32 and the insulating films 42, 43, 44, and 45. In addition, the anode wiring La and the cathode wiring Lc are electrically connected to the two semiconductor layers 31h located at both ends of the semiconductor layer 31h via contact holes 45p and 45n that penetrate the gate insulating film 32 and the insulating films 42, 43, 44, and 45.

[0045] The semiconductor layer 31h is formed simultaneously in the same layer as the semiconductor layer 31a shown in Fig. 4, and therefore has the same thickness as the semiconductor layer 31a. The N-type region and the P-type region are formed by utilizing the manufacturing process of the driving transistors constituting the scanning line driving circuit and the like shown in Fig. 1 and the pixel transistors shown in Fig. 4. The relay electrodes 6b are in the same layer as, for example, the data lines 6a and the capacitance lines 8a shown in Fig. 4.

[0046] 1-6.Detailed configuration of electrostatic protection circuit 12 FIG. 9 is a plan view that shows a schematic planar configuration of the electrostatic protection circuit 12 shown in FIG. 5. FIG. 10 is a cross-sectional view that shows a schematic cross section of the electrostatic protection circuit 12 shown in FIG. 9. FIG. 10 corresponds to the B1-B1′ cross section of FIG. 9. FIG. 11 is an explanatory diagram showing an enlarged view of the first capacitance element C1 shown in FIG. 10. In FIG. 11, the planar configuration of the first capacitance element C1 is shown in the upper part, and the cross-sectional configuration of the first capacitance element C1 is shown in the lower part. FIG. 12 is an explanatory diagram showing an enlarged view of the second capacitance element C2 shown in FIG. 10. In FIG. 12, the planar configuration of the second capacitance element C2 is shown in the upper part, and the cross-sectional configuration of the second capacitance element C2 is shown in the lower part. In FIG. 10, FIG. 11, and FIG. 12, illustrations of upper layers of the first capacitance element C1 and the second capacitance element C2 formed on the first substrate 10 are omitted to the extent that does not interfere with the explanation.

[0047] As shown in FIG. 9 and FIG. 10, in the transistor Tr of the electrostatic protection circuit 12, a plurality of unit transistor elements Tr1 to Tr8 are formed using an integrally formed semiconductor layer 31t, and the plurality of unit transistor elements Tr1 to Tr8 are electrically connected in parallel to configure the transistor Tr. More specifically, a plurality of gate electrodes 33t are formed on the upper layer side of the semiconductor layer 31t, and each of the plurality of gate electrodes 33t overlaps the semiconductor layer 31t via a gate insulating film 32. A region of the semiconductor layer 31t that overlaps with the gate electrode 33t in a plan view is a channel region 31k. The transistor Tr is an N-channel type thin film transistor having an LDD structure. Therefore, one source-drain region 31i of the transistor Tr and the other source-drain region 31j each have high-concentration N-type regions 31i1, 31j1 spaced apart from the channel region 31k, and low-concentration N-type regions 31i2, 31j2 sandwiched between the channel region 31k and the high-concentration N-type regions 31i1, 31j1.

[0048] A plurality of source / drain electrodes 6i, 6j are formed on the upper layer of the gate electrode 33t, and the plurality of source / drain electrodes 6i, 6j are electrically connected to one source / drain region 31i and the other source / drain region 31j of the semiconductor layer 31t via contact holes 45i, 45j penetrating the gate insulating film 32 and the insulating films 42, 43, 44, 45. In addition, all of the plurality of gate electrodes 33t are electrically connected to the gate wiring Lg.

[0049] The semiconductor layer 31t is formed simultaneously in the same layer as the semiconductor layer 31a shown in Fig. 4, and therefore has the same thickness as the semiconductor layer 31a. One source-drain region 31i and the other source-drain region 31j are formed by utilizing the manufacturing process of the driving transistor constituting the scanning line driving circuit etc. shown in Fig. 1 and the pixel transistor shown in Fig. 4. The source-drain electrodes 6i, 6j are in the same layer as the data line 6a shown in Fig. 4, for example.

[0050] In Fig. 9, on the opposite side of the transistor Tr with respect to the cathode wiring Lc, a resistor element R3 is formed of a conductive polysilicon film in the same layer as the semiconductor layer 31a shown in Fig. 4. However, the resistor element R3, the first resistor element R1, and the second resistor element R2 are not limited to the conductive polysilicon film, and may be formed of a metal material such as tungsten silicide or aluminum.

[0051] 9, 10, and 11, in the electrostatic protection circuit 12, the first capacitance element C1 is formed between the insulating film 42 and the insulating film 45. More specifically, between the insulating film 42 and the insulating film 45, a first capacitance section C1a is formed by a first capacitance electrode 4e, a first dielectric layer 40a, and a second capacitance electrode 5e1, which are stacked in this order from the insulating film 42 side toward the insulating film 45 side. Furthermore, a second capacitance section C1b is formed by a third capacitance electrode 5e2, a second dielectric layer 40b, and a fourth capacitance electrode 7e, which are stacked in this order from the first capacitance section C1a side toward the insulating film 45 side.

[0052] In this embodiment, the second capacitance electrode 5e1 and the third capacitance electrode 5e2 are made of the same conductive film 5e. In other words, for convenience, the same electrode pattern is called the second capacitance electrode 5e1 or the third capacitance electrode 5e2. The first dielectric layer 40a is made of an insulating film 43 and an insulating film 48 that are stacked in order from the first capacitance electrode 4e side toward the second capacitance electrode 5e1 side. The second dielectric layer 40b is made of an insulating film 44 and an insulating film 49 that are stacked in order from the third capacitance electrode 5e2 side toward the fourth capacitance electrode 7e side. The insulating film 48 is patterned in the same shape as the conductive film 5e, and the insulating film 48 and the conductive film 5e overlap in a planar view. The insulating film 49 is patterned in the same shape as the fourth capacitance electrode 7e, and the insulating film 49 and the fourth capacitance electrode 7e overlap in a planar view.

[0053] 9 and 12, in the electrostatic protection circuit 12, the second capacitance element C2 is formed between the insulating film 42 and the insulating film 45. More specifically, between the insulating film 42 and the insulating film 45, a third capacitance section C2a is formed by a fifth capacitance electrode 4f, a third dielectric layer 40c, and a sixth capacitance electrode 5f1, which are stacked in this order from the insulating film 42 side toward the insulating film 45 side. Furthermore, a fourth capacitance section C2b is formed by a seventh capacitance electrode 5f2, a fourth dielectric layer 40d, and an eighth capacitance electrode 7f, which are stacked in this order from the third capacitance section C2a side toward the insulating film 45 side.

[0054] In this embodiment, the sixth capacitance electrode 5f1 and the seventh capacitance electrode 5f2 are made of the same conductive film 5f. In other words, for convenience, the same electrode pattern is called the sixth capacitance electrode 5f1 or the seventh capacitance electrode 5f2. The third dielectric layer 40c is made of an insulating film 43 and an insulating film 48 that are laminated in order from the fifth capacitance electrode 4f side toward the sixth capacitance electrode 5f1 side. The fourth dielectric layer 40d is made of an insulating film 44 and an insulating film 49 that are laminated in order from the seventh capacitance electrode 5f2 side toward the eighth capacitance electrode 7f side. The insulating film 48 is patterned in the same shape as the conductive film 5f, and the insulating film 48 and the conductive film 5f overlap in a planar view. The insulating film 49 is patterned in the same shape as the eighth capacitance electrode 7f, and the insulating film 49 and the eighth capacitance electrode 7f overlap in a planar view.

[0055] The first capacitance electrode 4e and the fifth capacitance electrode 4f are formed simultaneously in the same layer as the first electrode 4a shown in Fig. 4, and therefore have the same thickness as the first electrode 4a. The second capacitance electrode 5e1 (third capacitance electrode 5e2) and the sixth capacitance electrode 5f1 (seventh capacitance electrode 5f2) are formed simultaneously in the same layer as the second electrode 5a (third electrode 5b) shown in Fig. 4, and therefore have the same thickness as the second electrode 5a (third electrode 5b).

[0056] 9, 11, and 12, relay electrodes 6e, 6f, and 6g are formed on the upper layer of the insulating film 45. The relay electrode 6g is provided so as to overlap an end of the conductive film 5e of the first capacitance element C1 and an end of the conductive film 5f of the second capacitance element C2. Therefore, the relay electrode 6g is electrically connected to the conductive film 5e via a contact hole 45g1 penetrating the insulating films 44 and 45, and is electrically connected to the conductive film 5f via a contact hole 45g2 penetrating the insulating films 44 and 45.

[0057] 11, the relay electrode 6e is electrically connected to the first capacitance electrode 4e through a contact hole 45e1 that penetrates the insulating films 43, 44, and 45, and is electrically connected to the fourth capacitance electrode 7e through a contact hole 45e2 that penetrates the insulating film 45. Therefore, the first capacitance element C1 has a structure in which the first capacitance portion C1a and the second capacitance portion C1b are electrically connected in parallel.

[0058] 12, the relay electrode 6f is electrically connected to the fifth capacitance electrode 4f through a contact hole 45f1 penetrating the insulating films 43, 44, and 45, and is electrically connected to the eighth capacitance electrode 7f through a contact hole 45f2 penetrating the insulating film 45. Therefore, the second capacitance element C2 has a structure in which the third capacitance portion C2a and the fourth capacitance portion C2b are electrically connected in parallel.

[0059] Here, the relay electrode 6g constitutes a connection node Cn between the first capacitance element C1 and the second capacitance element C2, and is electrically connected to the gate wiring Lg through a contact hole 45g3 shown in FIG. 9. The relay electrode 6g is also electrically connected to one end of the resistance element R3 through a contact hole 45r1 shown in FIG. 9, and the cathode wiring Lc is electrically connected to the other end of the resistance element R3 through a contact hole 45r2 shown in FIG. 9. That is, the cathode wiring Lc and the connection node Cn are electrically connected through the resistance element R3. Therefore, in a static state, the cathode wiring Lc and the connection node Cn are at the same potential. Note that the first resistance element R1 and the second resistance element R2 shown in FIG. 5 and the like are both electrically connected to the anode wiring La and the cathode wiring Lc through contact holes (not shown) that penetrate the insulating film 45 and the like, similar to the resistance element R3.

[0060] In this embodiment, the sizes of the circuit elements are as follows, for example: However, these are not limited to the following conditions. Transistor Tr: channel width W=800 μm, channel length L=5 μm The capacitance of the first capacitance element C1=5 pF The capacitance of the second capacitance element C2=5 pF Resistance value of the first resistor element R1 = 10 kΩ Resistance value of the second resistor element R2 = 10 kΩ Resistance value of resistor element R3 = 500kΩ

[0061] 1-7. Characteristics of the first capacitance element C1, etc. In the electro-optical device 100 of this embodiment, in the electrostatic protection circuit 12 of the temperature detection circuit 1, the capacitance of the first capacitance element C1 is larger than the capacitance between the gate electrode 33t and the semiconductor layer 31t of the transistor Tr. In particular, in this embodiment, the first capacitance element C1 has a structure in which the first capacitance portion C1a and the second capacitance portion C1b are electrically connected in parallel, so that the capacitance of the first capacitance element C1 is larger than the capacitance between the gate electrode 33t and the semiconductor layer 31t.

[0062] Similarly, the capacitance of the second capacitance element C2 is larger than the capacitance between the gate electrode 33t and the semiconductor layer 31t of the transistor Tr. In particular, in this embodiment, the second capacitance element C2 has a structure in which the third capacitance portion C2a and the fourth capacitance portion C2b are electrically connected in parallel, so that the capacitance of the second capacitance element C2 is larger than the capacitance between the gate electrode 33t and the semiconductor layer 31t.

[0063] 11, the thickness t40a of the first dielectric layer 40a of the first capacitance element C1 is thicker than the thickness t32 of the gate insulating film 32 of the transistor Tr. In particular, in this embodiment, the first dielectric layer 40a of the first capacitance element C1 has a structure in which the insulating films 43 and 48 are stacked, so the thickness t40a of the first dielectric layer 40a is thicker than the thickness t32 of the gate insulating film 32 of the transistor Tr. In particular, in this embodiment, the second dielectric layer 40b of the first capacitance element C1 has a structure in which the insulating films 44 and 49 are stacked, so the thickness t40b of the second dielectric layer 40b is thicker than the thickness t32 of the gate insulating film 32 of the transistor Tr.

[0064] 12, the thickness t40c of the third dielectric layer 40c of the second capacitance element C2 is thicker than the thickness t32 of the gate insulating film 32 of the transistor Tr. In particular, in this embodiment, the third dielectric layer 40c of the second capacitance element C2 has a structure in which the insulating films 43 and 48 are stacked, so the thickness t40c of the third dielectric layer 40c is thicker than the thickness t32 of the gate insulating film 32 of the transistor Tr. In addition, the thickness of the fourth dielectric layer 40d of the second capacitance element C2 is thicker than the thickness t32 of the gate insulating film 32 of the transistor Tr. In particular, in this embodiment, the fourth dielectric layer 40d of the second capacitance element C2 has a structure in which the insulating films 44 and 49 are stacked, so the thickness of the fourth dielectric layer 40d is thicker than the thickness t32 of the gate insulating film 32 of the transistor Tr.

[0065] 1-8. Functions and Effects of the Present Invention Fig. 13 is an explanatory diagram showing the effect of an electro-optical device 100 according to an embodiment of the present invention on a surge current. Fig. 14 is an explanatory diagram showing a problem of detecting a short circuit in an electro-optical device 100 of a reference example of the present invention. Here, in the electro-optical device 100 of the reference example, the capacitance of the first capacitance element C1 is smaller than the capacitance between the gate electrode 33t and the semiconductor layer 31t, and both the thickness t40a of the first dielectric layer 40a and the thickness t40b of the second dielectric layer 40b of the first capacitance element C1 are smaller than the thickness of the gate insulating film 32 of the transistor Tr.

[0066] As described above, in this embodiment, the capacitance of the first capacitance element C1 is larger than the capacitance between the gate electrode 33t and the semiconductor layer 31t. Therefore, in the process of manufacturing the first substrate 10, when the same large charge is applied to the first capacitance element C1 and the gate electrode 33t of the transistor Tr, the voltage applied to the gate capacitance of the transistor Tr with a small capacitance is higher than the voltage applied to the first capacitance element C1 with a large capacitance. In addition, both the thickness t40a of the first dielectric layer 40a and the thickness t40b of the second dielectric layer 40b of the first capacitance element C1 are thicker than the thickness t32 of the gate insulating film 32 of the transistor Tr. In general, the thicker the dielectric film, the higher the withstand voltage. Therefore, the first capacitance element C1 is less likely to suffer dielectric breakdown than the transistor Tr. Therefore, if there is an abnormal process, the transistor Tr can be induced to be damaged as shown in FIG. 13. In other words, the damage only to the first capacitance element C1 that would otherwise be latent is made apparent as damage to the transistor Tr.

[0067] Therefore, by contacting the probes of the inspection circuit 152 with the anode terminal 102a and the cathode terminal 102c to apply an inspection voltage to the temperature detection circuit 1 and detecting an abnormal current caused by damage to the transistor Tr, it is possible to detect the occurrence of a malfunction in the temperature detection circuit 1.

[0068] In contrast, in the electro-optical device of the reference example, the capacitance of the first capacitance element C1 is smaller than the capacitance between the gate electrode 33t and the semiconductor layer 31t, and both the thickness t40a of the first dielectric layer 40a and the thickness t40b of the second dielectric layer 40b of the first capacitance element C1 are thinner than the thickness t32 of the gate insulating film 32 of the transistor Tr. In the case of such a configuration, the first capacitance element C1 and the second capacitance element C2 may be more easily destroyed than the transistor Tr during the manufacturing process of the first substrate 10. Alternatively, the first capacitance element C1 and the second capacitance element C2 may be more easily destroyed than the transistor Tr even with respect to a surge current expected after the completion of the first substrate 10. In particular, when the first capacitance element C1 is damaged and the transistor Tr is normal, it is difficult to detect the failure. This is because, as shown in the first case (a) of FIG. 14, the resistance element R3 is electrically connected in parallel to the first capacitance element C1, so that both electrodes of the first capacitance element C1 are at the same potential due to the resistance element R3. Therefore, the short-circuit current Is1 of the first capacitance element C1 becomes zero and cannot be detected, and it is not possible to properly check for an abnormality in the temperature detection circuit 1. In this case, the electrostatic protection circuit 12 becomes malfunctioning and does not perform the desired protection function.

[0069] In addition, in the electro-optical device of the reference example, if dielectric breakdown occurs in the second capacitive element C2 as shown in the second case (b) of Figure 14, when an inspection voltage is supplied from the inspection circuit 152 to the temperature detection circuit 1, the short-circuit current Is2 of the second capacitive element C2 can be detected, and it can be detected that a malfunction has occurred in the temperature detection circuit 1.

[0070] 2. Embodiment 2 Fig. 15 is an explanatory diagram of an electro-optical device 100 according to a second embodiment of the present invention. In Fig. 15, the planar configuration of the first capacitance element C1 is shown in the upper part, and the cross-sectional configuration of the first capacitance element C1 is shown in the lower part. Note that since the basic configuration of this embodiment is similar to that of the first embodiment, the same reference numerals are used for common parts and their description will be omitted.

[0071] As shown in FIG. 15, in this embodiment, the first capacitance element C1 is formed between the insulating film 42 and the insulating film 44. More specifically, between the insulating film 42 and the insulating film 44, the first capacitance electrode 4e, the insulating film 43, the insulating film 48, and the second capacitance electrode 5e1 are laminated in this order from the insulating film 42 side toward the insulating film 44 side. The insulating film 43 has an opening 43e that exposes a part of the first capacitance electrode 4e in a region overlapping with the first capacitance electrode 4e and the second capacitance electrode 5e1. Therefore, the first capacitance electrode 4e and the second capacitance electrode 5e1 overlap each other through the insulating film 48 inside the opening 43e, and the first dielectric layer 40a of the first capacitance element C1 is made of the insulating film 48. Here, the first capacitance element C1 is made of only the first capacitance portion C1a, and the second capacitance portion C1b described in the first embodiment is not provided.

[0072] In the case of the first embodiment, the first capacitance element C1 has a stack structure in which the first capacitance portion C1a and the second capacitance portion C1b are overlapped. Therefore, in the second capacitance portion C1b located above the first capacitance portion C1a, the thickness of the second dielectric layer 40b may be poor due to foreign matter attached to the second capacitance portion C1b before its formation, the surface shape of the film formed, etc., and the breakdown voltage may decrease. Therefore, in the second embodiment, the first capacitance element C1 is configured with only the first capacitance portion C1a. With this configuration, the number of manufacturing steps up to the formation of the first capacitance portion C1a is less than the number of manufacturing steps up to the formation of the second capacitance portion C1b, so that the probability of the breakdown voltage of the first capacitance element C1 decreasing can be reduced. Therefore, the first capacitance element C1 can be manufactured with a high yield and good breakdown voltage.

[0073] Therefore, in the electro-optical device 100, the storage capacitor 55 provided in each pixel 100a shown in Fig. 3 has a stacked structure in which the first storage capacitor 551 and the second storage capacitor 552 overlap as shown in Fig. 4, and is configured to prioritize the pixel aperture ratio. On the other hand, it is preferable that the capacitance element (particularly the first capacitance element C1) in the temperature detection circuit 1 has a non-stacked structure with only the first capacitance portion C1a without the second capacitance portion C1b, and is configured to prioritize voltage resistance performance. In this way, a bright electro-optical device 100 equipped with a highly reliable temperature detection circuit 1 can be obtained.

[0074] Furthermore, in the case of the first embodiment, the first capacitance portion C1a and the second capacitance portion C1b are stacked together, so that the three electrode layers constituting the first capacitance portion C1a and the second capacitance portion C1b appear to overlap when viewed in a plan view. Therefore, it is difficult to estimate the abnormal portion from the appearance observation. In other words, it is difficult to determine whether the problem is in the first capacitance portion C1a or the second capacitance portion C1b. However, if the configuration is such that there is only the first capacitance portion C1a, which is not stacked, as in the second embodiment, it is easy to estimate the abnormal portion from the appearance observation.

[0075] In addition, in this embodiment, the insulating film 48 constituting the first dielectric layer 40a may be thinner than the gate insulating film 32. For example, the thickness of the insulating film 48 is, for example, 85 nm, and the thickness of the gate insulating film 32 is, for example, 100 nm. Furthermore, the insulating film 48 may be a silicon nitride film having a higher relative dielectric constant than a silicon oxide film. In that case, it is easy to further increase the capacitance of the first capacitance element C1. Therefore, it is easy to make the capacitance of the first capacitance element C1 larger than the capacitance between the gate electrode 33t and the semiconductor layer 31t of the transistor Tr. Therefore, in the transistor Tr, the same effects as those of the first embodiment are achieved, such as the occurrence of dielectric breakdown before the occurrence of the first capacitance element C1.

[0076] In this embodiment, the insulating film 48 constituting the first dielectric layer 40a is formed to the outside of the opening 43e, and the insulating film 43 overlaps the end of the second capacitance electrode 5e1 outside the opening 43e. Therefore, the first capacitance electrode 4e and the second capacitance electrode 5e1 overlap each other outside the opening 43e through the insulating films 43 and 48. Therefore, the thickness of the insulating film interposed between the first capacitance electrode 4e and the second capacitance electrode 5e1 is thicker in the peripheral region overlapping the end of the first capacitance electrode 4e and the end of the second capacitance electrode 5e1 in a plan view than in the region inside the peripheral region where the first capacitance electrode 4e and the second capacitance electrode 5e1 overlap in a plan view. With this configuration, the electric field concentration at the end of the second capacitance electrode 5e1 is alleviated, and the withstand voltage of the first capacitance element C1 can be increased.

[0077] It is preferable to round the apex of the rectangular shape of the opening 43e. In this way, the second capacitance electrode 5e1 facing the first capacitance electrode 4e in the opening 43e does not have an acute angle in a plan view, so that the electric field concentration at the end of the second capacitance electrode 5e1 is alleviated. For example, the curvature of the apex of the opening 43e is set to R=1 um or more. Alternatively, the angle of the apex of the opening 43e may be configured to be greater than 90 degrees. In that case, the apex, which typically forms a right angle, is rounded. The configuration of the second capacitance element C2 is the same as that of the first capacitance element C1, so a description thereof will be omitted.

[0078] 3. Embodiment 3 Fig. 16 is an explanatory diagram of an electro-optical device 100 according to a third embodiment of the present invention. In Fig. 16, the planar configuration of the first capacitance element C1 is shown in the upper part, and the cross-sectional configuration of the first capacitance element C1 is shown in the lower part. Note that since the basic configuration of this embodiment is similar to that of the first embodiment, the same reference numerals are used for common parts and their description will be omitted.

[0079] As shown in FIG. 16, in the electrostatic protection circuit 12 in this embodiment, the first capacitance element C1 is formed between the insulating film 42 and the insulating film 44. More specifically, the first capacitance electrode 4e, the insulating film 43, the insulating film 48, and the second capacitance electrode 5e1 are laminated in this order from the insulating film 42 side toward the insulating film 44 side. In the insulating film 43, an opening 43e is formed in a region overlapping with the first capacitance electrode 4e and the second capacitance electrode 5e1 to expose a part of the first capacitance electrode 4e. Therefore, the first capacitance electrode 4e and the second capacitance electrode 5e1 overlap each other inside the opening 43e via the insulating film 48, and the first dielectric layer 40a of the first capacitance element C1 is made of the insulating film 48. Here, the first capacitance element C1 is made of only the first capacitance portion C1a, and the second capacitance portion C1b described in the first embodiment is not provided.

[0080] In this embodiment, the insulating film 48 constituting the first dielectric layer 40a is thicker than the gate insulating film 32. For example, the thickness t40a of the insulating film 48 is, for example, 100 nm, and the thickness t32 of the gate insulating film 32 is, for example, 85 nm. In general, the thicker the insulating film, the better the withstand voltage. Therefore, the withstand voltage of the first capacitance element C1 can be made higher than the withstand voltage between the gate electrode 33t and the semiconductor layer 31t of the transistor Tr. Therefore, in the transistor Tr, the same effects as those of the first embodiment, such as the occurrence of dielectric breakdown before the occurrence of the first capacitance element C1, are achieved.

[0081] In this embodiment, the insulating film 48 constituting the first dielectric layer 40a is formed to the outside of the opening 43e, and the insulating film 43 overlaps the end of the second capacitance electrode 5e1 outside the opening 43e. Therefore, the first capacitance electrode 4e and the second capacitance electrode 5e1 overlap each other outside the opening 43e through the insulating films 43 and 48. Therefore, the thickness of the insulating film interposed between the first capacitance electrode 4e and the second capacitance electrode 5e1 is thicker in the peripheral region overlapping the end of the first capacitance electrode 4e and the end of the second capacitance electrode 5e1 in a plan view than in the region inside the peripheral region where the first capacitance electrode 4e and the second capacitance electrode 5e1 overlap in a plan view. With this configuration, the electric field concentration at the end of the second capacitance electrode 5e1 is alleviated, and the withstand voltage of the first capacitance element C1 can be increased.

[0082] In this embodiment, the first capacitance element C1 is composed of only the first capacitance portion C1a, and does not include the second capacitance portion C1b described in the first embodiment. Also, the insulating film 48 constituting the first dielectric layer 40a is thicker than the gate insulating film 32. Even with this configuration, in this embodiment, it is possible to make the capacitance of the first capacitance element C1 larger than the capacitance between the gate electrode 33t and the semiconductor layer 31t of the transistor Tr.

[0083] For example, the relative dielectric constant of the silicon oxide film used for the insulating film 48 is 3.9, and the plane area of ​​the opening 43e is approximately 14,500 μm2. In this case, if the opening 43e is made to have a substantially rectangular shape of 145 μm×100 μm, it will be a size that can be arranged on the first substrate 10. In this configuration, the capacitance of the first capacitance element C1 is approximately 5 pF.

[0084] On the other hand, the transistor Tr is divided into eight unit transistor elements connected in parallel, and each individual element has a channel width W=100 μm and a channel length L=5 μm. If the relative dielectric constant of the gate insulating film 32 is 3.9, the thickness t32 of the gate insulating film 32 is 85 nm, and therefore the gate capacitance per unit transistor element is about 0.2 pF. Therefore, the gate capacitance of the transistor Tr is about 1.6 pF. Therefore, the capacitance of the first capacitance element C1 can be made larger than the capacitance between the gate electrode 33t and the semiconductor layer 31t of the transistor Tr.

[0085] 4. Embodiment 4 Fig. 17 is an explanatory diagram of an electro-optical device 100 according to a fourth embodiment of the present invention. Fig. 17 shows a schematic planar structure of the inspection area 17 shown in Fig. 3. Since the basic configuration of this embodiment is similar to that of the first embodiment, the same reference numerals are used for common parts and their description will be omitted.

[0086] The inspection area 17 shown in Fig. 3 is provided with a plurality of inspection elements TD formed simultaneously in the same layer as the temperature detection element 11, the transistor Tr, the resistive element R3, and the first capacitive element C1 constituting the temperature detection circuit 1 shown in Fig. 5, and a plurality of inspection terminals T1 to T9 electrically connected to the inspection elements TD. Note that the inspection terminals T1 to T9 may be different in size from the terminal 102 shown in Fig. 1 because an inspection probe is brought into contact with them.

[0087] According to this aspect, the electrical characteristics of the test element TD (11) corresponding to the temperature detection element 11 can be inspected using the test terminals T1 and T2. The electrical characteristics of the test element TD (Tr) corresponding to the transistor Tr can be inspected using the test terminals T3, T4, and T6. The electrical characteristics of the test element TD (R3) corresponding to the resistor element R3 can be inspected using the test terminals T5 and T6. The electrical characteristics of the test element TD (C1) corresponding to the first capacitor element C1 can be inspected using the test terminals T7, T8, and T9. In the case of the first embodiment, the test element TD (C1) corresponding to the first capacitor element C1 may be arranged in a stack structure imitating an actual configuration. Instead of the test element TD (R3) corresponding to the resistor element R3, a test element corresponding to the first resistor element R1 or the second resistor element R2 may be arranged.

[0088] 3, the inspection area 17 is arranged along a side corresponding to a corner of the electro-optical device 100 where the temperature detection element 11 and the electrostatic protection circuit 12 are arranged. With this configuration, the inspection area 17 and the same electric elements in the temperature detection element 11 and the electrostatic protection circuit 12 become workpieces with the same exposure range and are arranged in the vicinity. As a result, the inspection area 17 and the same electric elements in the temperature detection element 11 and the electrostatic protection circuit 12 can have similar electric characteristics. Therefore, an abnormality in the formation of each electric element can be detected from the measured values ​​of the electric elements in the inspection area 17. Also, the performance of the temperature detection circuit 1 can be estimated or managed.

[0089] 5.Examples of electronic device configurations Fig. 18 is a block diagram showing a configuration example of a projection type display device 1000 to which the present invention is applied. Fig. 19 is an explanatory diagram of the light path shift element 110 shown in Fig. 18. Note that polarizing plates and the like are omitted from Fig. 18. The projection type display device 1000 shown in Fig. 18 is an example of an electronic device to which the present invention is applied, and includes an illumination device 90, a separation optical system 70, three electro-optical devices 100R, 100G, and 100B, and a projection optical system 60. Each of the electro-optical devices 100R, 100G, and 100B is composed of the electro-optical device 100 described with reference to Figs. 1 to 17.

[0090] The illumination device 90 is a white light source, and for example, a laser light source or a halogen lamp is used. The separation optical system 70 includes three mirrors 71, 72, and 75, and dichroic mirrors 73 and 74. The separation optical system 70 separates the white light emitted from the illumination device 90 into three primary colors of red R, green G, and blue B. Specifically, the dichroic mirror 74 transmits light in the red R wavelength range and reflects light in the green G and blue B wavelength ranges. The dichroic mirror 73 transmits light in the blue B wavelength range and reflects light in the green G wavelength range. The light corresponding to red R, green G, and blue B is guided to the electro-optical devices 100R, 100G, and 100B, respectively.

[0091] The light modulated by the electro-optical devices 100R, 100G, and 100B is incident on the dichroic prism 61 from three directions. The dichroic prism 61 constitutes a synthesis optical system in which red R, green G, and blue B images are synthesized. Therefore, the projection lens system 62 can enlarge and project the synthesized image output from the light path shift element 110 onto a projection target member such as the screen 80, thereby displaying a color image on the projection target member such as the screen 80.

[0092] At this time, the control unit 150 can correct the image signals supplied to the electro-optical devices 100R, 100G, and 100B based on the temperature detection result by the temperature detection circuit 1. Therefore, even if the environmental temperature or the like fluctuates, a high-quality projection image can be displayed.

[0093] Furthermore, when adopting a configuration in which the light path shift element 110 shown by the dashed line is provided in the projection optical system 60 on the side from which light is emitted in the dichroic prism 61, and the resolution is increased by a technique of shifting the position at which the projection pixel is viewed every predetermined period, it becomes necessary to drive the liquid crystal layer at high speed. Even in this case, if a configuration is adopted in which the image signal supplied to the electro-optical devices 100R, 100G, and 100B is corrected based on the temperature detection result in the temperature detection circuit 1, or a configuration is adopted in which the temperature of the liquid crystal panel 100p of the electro-optical devices 100R, 100G, and 100B is adjusted, the electro-optical layer 50 made of a liquid crystal layer can be driven at high speed.

[0094] The light path shift element 110 is an optical element that shifts the light emitted from the dichroic prism 61 in a predetermined direction, as shown in Fig. 19. Fig. 19 illustrates an example in which the position of the projection pixel Pi, at which the light emitted from each pixel 100a of the liquid crystal panel 100p is visually recognized, is shifted by the light path shift element 110 by a distance equivalent to 0.5 pixel pitch (=P / 2) on one side X1 in the first direction X and by a distance equivalent to 0.5 pixel pitch (=P / 2) on one side Y1 in the second direction Y. The light path shift element 110 includes a light-transmitting plate, and the actuator 160 swings the light-transmitting plate around one or both of an axis extending in the first direction X and an axis extending in the second direction Y, thereby shifting the light path of the light emitted from each pixel 100a of the liquid crystal panel 100p to the light path LA and the light path LB.

[0095] 6. Other embodiments Incidentally, the projection display device may be configured to use an LED light source or the like that emits light of each color as the light source section, and supply each of the color lights emitted from the LED light source to a separate liquid crystal device.

[0096] The first capacitance element C1 and the second capacitance element C2 in the first to third embodiments may be electrically connected to each other. For example, in FIG. 15 of the second embodiment, the relay electrode 6e may be electrically connected to the gate line Lg, and the relay electrode 6g may be electrically connected to the cathode line Lc. The first capacitance element C1 may be a non-stacked capacitance element as in the second or third embodiment, and the second capacitance element C2 may be a stacked capacitance element. With this configuration, the withstand voltage of the first capacitance element C1, which is difficult to detect failure, can be increased, and when an abnormal voltage is applied, it can be detected as a failure of the transistor Tr. On the other hand, the second capacitance element C2, which is easy to detect failure, can be made compact with good layout efficiency in a plan view, so that the electrostatic protection circuit 12 can be easily arranged in the electro-optical device 100. By detecting failures of the transistor Tr or the second capacitance element C2, the manufacturing process can be improved promptly.

[0097] An electronic device equipped with the electro-optical device 100 to which the present invention is applied is not limited to the projection type display device 1000 of the above embodiment. For example, the present invention may be used in electronic devices such as a HUD (head-up display), an HMD (head-mounted display), a personal computer, a digital still camera, and a liquid crystal television. [Explanation of symbols]

[0098] 1... Temperature detection circuit, 2a... Light shielding layer, 3a... Scanning line, 4a... First electrode, 4e... First capacitive electrode, 4f... Fifth capacitive electrode, 5a... Second electrode, 5b... Third electrode, 5e, 5f... Conductive film, 5e1... Second capacitive electrode, 5e2... Third capacitive electrode, 5f1... Sixth capacitive electrode, 5f 2...Seventh capacitor electrode, 6a...Data line, 6i, 6j...Source / drain electrode, 6s...Common potential line, 7a...Fourth electrode, 7e...Fourth capacitor electrode, 7f...Eighth capacitor electrode, 8a...Capacitor line, 9a...Pixel electrode, 10...First substrate, 10a...Display area, 11...Temperature detection element , 11a...anode, 11c...cathode, 12...electrostatic protection circuit, 17...inspection area, 30...pixel transistor, 31a, 31h, 31t...semiconductor layer, 31i, 31j...source-drain region, 32...gate insulating film, 33g, 33t...gate electrode, 40a...first dielectric layer, 40b...second dielectric layer, 40c...third dielectric layer, 40d...fourth dielectric layer, 41, 42, 43, 44, 45, 46, 47, 48, 49...insulating film, 43a, 43e, 44a...opening, 50...electro-optical layer, 60...projection optical system, 61...dichroic Electro-optical device, 100a...pixel, 100p...liquid crystal panel, 102, 102g...terminal, 102a...anode terminal, 102c...cathode terminal, 104...scanning line driving circuit, 105...precharge circuit, 110...light path shift element, 150...controller, 151...temperature detection driving circuit, 152...inspection circuit, 160...actuator, 551...first holding capacitance, 552...second holding capacitance Capacitance, 1000... projection display device, D, D1 to D5... diode elements, C1... first capacitance element, C2... second capacitance element, R1... first resistive element, R2... second resistive element, R3... resistive element, TD... inspection element, C1a... first capacitance section, C1b... second capacitance section, C2a... third capacitance section, C2b... fourth capacitance section, La... anode wiring, Lc... cathode wiring, Cn... connection node, Lg... gate wiring, Is... surge current, It... drive current, Is1, Is2... short circuit current, Tr... transistor, Tr1 to Tr8... unit transistor elements

Claims

1. A temperature detection element; A transistor electrically connected in parallel to the temperature detection element; a first capacitance element electrically connected in parallel to the first capacitance element; and a resistor electrically connected in parallel to the first capacitance element. an electrostatic protection circuit having an element; Equipped with The transistor includes a gate electrode, a semiconductor layer, and a gate electrode between the semiconductor layer and the gate electrode. and a gate insulating film provided on the The first capacitance element is electrically connected to one end of the resistance element and the gate electrode. a first capacitance electrode, the other end of the resistor element, and one of the source and drain electrodes of the semiconductor layer; a second capacitance electrode electrically connected to the region; and a capacitance between the first capacitance electrode and the second capacitance electrode. a first dielectric layer disposed on the The capacitance of the first capacitance element is greater than the capacitance between the gate electrode and the semiconductor layer. An electro-optical device characterized by its large size.

2. 2. The electro-optical device according to claim 1, The thickness of the first dielectric layer is greater than the thickness of the gate insulating film. optical equipment.

3. A temperature detection element; A transistor electrically connected in parallel to the temperature detection element; a first capacitance element electrically connected in parallel to the first capacitance element; and a resistor electrically connected in parallel to the first capacitance element. an electrostatic protection circuit having an element; Equipped with The transistor includes a gate electrode, a semiconductor layer, and a gate electrode between the semiconductor layer and the gate electrode. and a gate insulating film provided on the The first capacitance element is electrically connected to one end of the resistance element and the gate electrode. a first capacitance electrode, the other end of the resistor element, and one of the source and drain electrodes of the semiconductor layer; a second capacitance electrode electrically connected to the region; and a capacitance between the first capacitance electrode and the second capacitance electrode. a first dielectric layer disposed on the The thickness of the first dielectric layer is greater than the thickness of the gate insulating film. academic equipment.

4. 4. The electro-optical device according to claim 1, The first capacitance element includes a third capacitance electrode electrically connected to the second capacitance electrode, and a fourth capacitance electrode electrically connected to the first capacitance electrode; and and a second dielectric layer provided between the first and second dielectric layers, The thickness of the first dielectric layer and the thickness of the second dielectric layer are both An electro-optical device having a thickness greater than that of an enclosure film.

5. 5. The electro-optical device according to claim 4, The first capacitance electrode, the second capacitance electrode, the third capacitance electrode, and the fourth capacitance electrode , at least partially overlapping in a plan view.

6. 6. The electro-optical device according to claim 4, The second capacitance electrode and the third capacitance electrode are formed of an integral conductive film. An electro-optical device comprising:

7. 7. The electro-optical device according to claim 1, The thickness of the insulating film interposed between the first capacitance electrode and the second capacitance electrode is In a peripheral region overlapping an end of the electrode and an end of the second capacitance electrode in a plan view, the peripheral region the first capacitance electrode and the second capacitance electrode are thicker than an area where the first capacitance electrode and the second capacitance electrode overlap each other in a plan view. An electro-optical device.

8. 8. The electro-optical device according to claim 1, a second capacitance element electrically connected in series with the first capacitance element; The second capacitance element includes a fifth capacitance electrode electrically connected to the first capacitance electrode, and a sixth capacitance electrode electrically connected to the other source / drain region of the conductor layer; and a third dielectric layer provided between the capacitance electrode and the sixth capacitance electrode. Electro-optical device.

9. 9. The electro-optical device according to claim 1, The transistor includes a plurality of unit transistor elements electrically connected in parallel. An electro-optical device comprising:

10. 10. The electro-optical device according to claim 1 , a display area in which a plurality of pixels, each of which has a pixel electrode and a storage capacitor, are arranged; The storage capacitor includes a first electrode in the same layer as the first capacitance electrode, and a second electrode in the same layer as the second capacitance electrode. an electro-optical device comprising: two electrodes; and a dielectric layer in the same layer as the first dielectric layer. 。

11. 11. The electro-optical device according to claim 1 , Each of the temperature detection element, the transistor, the resistance element, and the first capacitance element A plurality of testing elements arranged in the same layer, and a plurality of testing elements electrically connected to the testing elements. and a scanning terminal.

12. An electro-optical device comprising the electro-optical device according to any one of claims 1 to 11. Child equipment.

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