Non-volatile memory device

Abstract

To provide a nonvolatile memory device that applies voltage more intensively to a part of conductive layers that are stacked.SOLUTION: A nonvolatile memory device according to the present invention includes a peripheral circuit including a first active region and an element formed on the first active region, a second active region on the peripheral circuit, and a memory block including a memory cell formed on the second active region. The memory block includes a vertical structure including a pair of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer facing each other with a space therebetween along a first direction on the second insulating layer, a first vertical channel penetrating the second conductive layer, the second insulating layer, and the vertical structure in a second direction, and a second vertical channel penetrating the third conductive layer, the second insulating layer, and the vertical structure in the second direction. The second conductive layer and the third conductive layer are connected to a first penetration veer penetrating a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer, the vertical structure, and the second active region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a non-volatile memory device that applies a stronger voltage. [Background technology]

[0002] The nonvolatile memory device may have a three-dimensional structure. The three-dimensional nonvolatile memory device has a structure in which pairs of an insulating layer and a conductive layer are stacked. The conductive layer may be a cell transistor and a wiring connected to the cell transistor. In general, the higher the conductivity of the conductive layer, the better the performance of the nonvolatile memory device.

[0003] Due to process issues, some of the conductive layers of a non-volatile memory device may include a material having a lower conductivity than other conductive layers. A new apparatus or method is needed to prevent performance degradation of a non-volatile memory device that employs some conductive layers having a material having a lower conductivity than other conductive layers. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent No. 10-0582422 [Patent Document 2] U.S. Pat. No. 10,249,640 [Patent Document 3] U.S. Patent No. 10,177,224 [Patent Document 4] U.S. Pat. No. 9,099,347 [Patent Document 5] U.S. Pat. No. 10,134,747 [Patent Document 6] U.S. Patent No. 8,822,285 [Patent Document 7] U.S. Pat. No. 8,044,448 [Patent Document 8] U.S. Patent No. 10,290,581 [Patent Document 9] U.S. Patent No. 8,654,587 [Patent Document 10] U.S. Patent No. 7,679,133 [Patent Document 11] U.S. Pat. No. 8,553,466 [Patent Document 12] U.S. Patent No. 8,559,235 [Patent Document 13] US Patent Application Publication No. 2005 / 0254303 [Patent Document 14] US Patent Application Publication No. 2014 / 0027838 [Patent Document 15] US Patent Application Publication No. 2011 / 0233648 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned conventional technology, and an object of the present invention is to provide a non-volatile memory device in which a stronger voltage is applied to some of the stacked conductive layers. [Means for solving the problem]

[0006] A nonvolatile memory device according to an embodiment of the present invention includes a first active region, a peripheral circuit including an element formed on the first active region, a second active region on the peripheral circuit, and a memory block including memory cells formed on the second active region. The memory block includes a vertical structure on the second active region, the vertical structure including a pair of a first insulating layer and a first conductive layer extending along a first direction and stacked in a second direction perpendicular to an upper surface of the second active region, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer on the second insulating layer facing each other along the first direction and spaced apart from each other, a first vertical channel penetrating the second conductive layer, the second insulating layer, and the vertical structure in the second direction, and a second vertical channel penetrating the third conductive layer, the second insulating layer, and the vertical structure in the second direction. The second conductive layer and the third conductive layer are coupled with a first through via that penetrates an area of ​​the second insulating layer exposed between the second conductive layer and the third conductive layer, the vertical structure, and the second active area.

[0007] A non-volatile memory device according to an embodiment of the present invention includes a first active region, a peripheral circuit including at least three pass transistors formed on the first active region, a second active region on the peripheral circuit, and a memory block including memory cells formed on the second active region. The memory block includes a vertical structure including a pair of a first insulating layer and a first conductive layer extending along a first direction on the second active region and stacked in a second direction perpendicular to an upper surface of the second active region, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer on the second insulating layer facing each other and spaced apart from each other along the first direction, a first vertical channel penetrating the second conductive layer, the second insulating layer, and the vertical structure in the second direction, and a second vertical channel penetrating the third conductive layer, the second insulating layer, and the vertical structure in the second direction. The at least three pass transistors supply a common voltage to the second conductive layer and the third conductive layer through at least three through vias penetrating the second active region.

[0008] A non-volatile memory device according to an embodiment of the present invention includes a first active area, a peripheral circuit including elements formed on the first active area, a second active area on the peripheral circuit, and a memory block including memory cells formed on the second active area. The memory block includes a vertical structure including a pair of a first insulating layer and a first conductive layer extending along a first direction on the second active area and stacked in a second direction perpendicular to a top surface of the second active area, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer on the second insulating layer spaced apart and facing each other along the first direction, a fourth conductive layer and a fifth conductive layer on the second insulating layer spaced apart and facing each other along the first direction and parallel to the second conductive layer and the third conductive layer in a third direction perpendicular to the first direction and the second direction, a sixth conductive layer and a seventh conductive layer on the second insulating layer spaced apart and facing each other along the first direction and parallel to the fourth conductive layer and the fifth conductive layer in the third direction, and a vertical channel penetrating the vertical structure in the second direction. The second conductive layer and the third conductive layer are coupled to a first through via that penetrates the region of the second insulating layer exposed between the second conductive layer and the third conductive layer, the vertical structure, and the second active area, the fourth conductive layer and the fifth conductive layer are coupled to a second through via that penetrates the region of the second insulating layer exposed between the fourth conductive layer and the fifth conductive layer, the vertical structure, and the second active area, and the sixth conductive layer and the seventh conductive layer are coupled to a third through via that penetrates the region of the second insulating layer exposed between the sixth conductive layer and the seventh conductive layer, the vertical structure, and the second active area. Effect of the Invention

[0009] According to the present invention, a voltage is applied to two conductive layers separated by a through via between the two separated conductive layers, and thus a non-volatile memory device is provided that prevents performance degradation by applying a stronger voltage to some of the stacked conductive layers. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view illustrating a nonvolatile memory device according to an embodiment of the inventive concept; [Diagram 2]2 is a cross-sectional view taken along line II' in FIG. 1. [Diagram 3] 1 shows a plan view of another example of a non-volatile memory device. [Figure 4] 1 shows a plan view of another example of a non-volatile memory device. [Diagram 5] 5 is a cross-sectional view of the nonvolatile memory device of FIG. 4 taken along line II-II'. [Figure 6] 5 is a cross-sectional view taken along line III-III' in FIG. 4. [Figure 7] 13 shows another example of a cross-sectional view of a memory block. [Figure 8] FIG. 2 is another plan view of the nonvolatile memory device. [Figure 9] 4 shows a cross-sectional view taken along line IV-IV' in FIG. [Figure 10] 1 illustrates an example through-via configuration. [Figure 11] An example circuit diagram corresponding to the dotted box in FIG. 1 is shown. [Figure 12] 1 is a block diagram illustrating a non-volatile memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the following, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

[0012] Fig. 1 is a plan view showing a nonvolatile memory device according to an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II' in Fig. 1. Referring to Figs. 1 and 2, the nonvolatile memory device may include a peripheral circuit 100 and a memory block 200 on the peripheral circuit 100. For example, the nonvolatile memory device may include a cell over peri (COP) structure.

[0013] The peripheral circuit 100 may include a first active area 110 and elements (120, 130, 140) on the first active area 110. The first active area 110 may be formed in a semiconductor substrate. The elements (120, 130, 140) may include a first pass transistor 120, a second pass transistor 130, and a third pass transistor 140.

[0014] The first pass transistor 120 may include a gate 121, an insulating film 122, a first junction 123, and a second junction 124. The second pass transistor 130 may include a gate 131, an insulating film 132, a first junction 133, and a second junction 134. The third pass transistor 140 may include a gate 141, an insulating film 142, a first junction 143, and a second junction 144.

[0015] A first junction 123 of the first pass transistor 120 may be coupled to a first peripheral circuit via 181. The first peripheral circuit via 181 may be coupled to a wiring (not shown). A second junction 124 of the first pass transistor 120 may be coupled to a first through via 311. For example, the first through via 311 may be a THV (Through Hole Via).

[0016] A first junction 133 of the second pass transistor 130 may be coupled to a second peripheral circuit via 182. The second peripheral circuit via 182 may be coupled to a wiring (not shown). A second junction 134 of the second pass transistor 130 may be coupled to a second through via 312. For example, the second through via 312 may be a THV (Through Hole Via).

[0017] The first junction 143 of the third pass transistor 140 may be coupled to a third peripheral circuit via 183. The third peripheral circuit via 183 may be coupled to a wiring (not shown). The second junction 144 of the third pass transistor 140 may be coupled to a third through via 313. For example, the third through via 313 may be a THV (Through Hole Via).

[0018] The gate 121 of the first pass transistor 120, the gate 131 of the second pass transistor 130, and the gate 141 of the third pass transistor 140 may be coupled to a common wiring. The first peripheral circuit via 181, the second peripheral circuit via 182, and the third peripheral circuit via 183 may be coupled to a common wiring.

[0019] That is, the first pass transistor 120, the second pass transistor 130, and the third pass transistor 140 can transmit a common voltage of the common wiring to the first through via 311, the second through via 312, and the third through via 313, respectively, in response to a common control signal.

[0020] By way of example, only those elements of peripheral circuit 100 coupled to first through via 311, second through via 312, and third through via 313 are shown in Figure 2. Additional components not shown in Figure 2 may be added to peripheral circuit 100.

[0021] According to the characteristics of the components of the memory block 200, the memory block 200 may be divided into first to seventh regions (R1 to R7) along the first direction. However, the division into the first to seventh regions (R1 to R7) is for convenience of explanation and does not limit the technical idea and characteristics of the present invention.

[0022] The memory block 200 may include a second active area 210 and a vertical structure on the second active area 210. The vertical structure may include a pair of a first insulating layer 211 and a first conductive layer 221, a pair of a second insulating layer 212 and a second conductive layer 222, a pair of a third insulating layer 213 and a third conductive layer 223, a pair of a fourth insulating layer 214 and a fourth conductive layer 224, and a pair of a fifth conductive layer 225 and a fifth insulating layer 215, which are sequentially stacked on the second active area 210.

[0023] The vertical structure may extend along a first direction. For example, the vertical structure may be repeated along a second direction. On one side of the vertical structure in the second direction, a first word line cut 11 may be located, which separates the vertical structure from other vertical structures or other components. On the other side of the vertical structure in the second direction, a second word line cut 12 may be located, which separates the vertical structure from other vertical structures or other components.

[0024] A pair of a sixth insulating layer 216 and a sixth conductive layer 226 may be provided on the vertical structure. The sixth conductive layer 226 may include a first partial conductive layer 226a and a second partial conductive layer 226b that are spaced apart facing each other along a first direction. The first partial conductive layer 226a and the second partial conductive layer 226b may be spaced apart from each other along the first direction to expose the underlying sixth insulating layer 216 in a fourth region (R4). The fourth region (R4) may be, for example, a string selection line stair.

[0025] The first partial conductive layer 226a is divided into three (or more) conductive layers by a first string selection line cut 13 and a second string selection line cut 14 that proceed in a wavy manner along the first direction. The second partial conductive layer 226b is divided into three (or more) conductive layers by a third string selection line cut 15 and a fourth string selection line cut 16 that proceed in a wavy manner along the first direction. That is, the boundary along the second direction of the conductive layers belonging to the sixth conductive layer 226 may have a wavy manner proceeding along the first direction.

[0026] That is, depending on the viewpoint, the sixth conductive layer 226 may include six conductive layers divided by the first to fourth string selection line cuts (13 to 16) and the string selection line steer. Or, the sixth conductive layer 226 may include a first partial conductive layer 226a and a second partial conductive layer 226b divided by the string selection line steer. In addition, the sixth conductive layer 226 may include three conductive layers (or conductive lines) that are divided by the first to fourth string selection line cuts (13 to 16) and electrically connected and extended in the first direction.

[0027] In the third region (R3) and the fifth region (R5), the vertical channel 230 may penetrate the sixth conductive layer 226, the sixth insulating layer 216, and the vertical structure in the third direction. The vertical channel 230 may include first to ninth vertical channels (231 to 239). The vertical channels may form cell transistors (see FIG. 10) stacked in the third direction together with the first to sixth conductive layers (221 to 226).

[0028] For example, an information storage film including a silicon oxide film, a silicon nitride film, and a silicon oxide film may be formed between the first to sixth conductive layers (221 to 226) and the vertical channel 230. The first to sixth conductive layers (221 to 226) may be wiring (see FIG. 10) extending along a first direction to connect cell transistors.

[0029] For example, the string select line cut (13, 14, 15, or 16) may have a waveform to maintain a distance (distance on a plane in a first direction and a second direction) to the nearest vertical channel above a threshold value. Maintaining the distance above the threshold value prevents defects (e.g., a short between the string select line cut (13, 14, 15, or 16) and the vertical channel) from occurring during manufacturing of the non-volatile memory device.

[0030] In the second region (R2) and the sixth region (R6), the pairs of the first to sixth insulating layers and the first to sixth conductive layers may have lengths (lengths in the first direction) that decrease in the form of a stair along the third direction. The second region (R2) and the sixth region (R6) may be word line stair.

[0031] The first through via 311 may extend in the third direction from the first region (R1) through the second active region 210. The first through via 311 may be coupled to the first memory cell via 241 on the first conductive layer in the second direction among the conductive layers included in the first partial conductive layer 226a through the first upper conductive layer 271. The second through via 312 may extend in the third direction from the seventh region (R7) through the second active region 210. The second through via 312 may be coupled to the second memory cell via 242 on the first conductive layer in the second direction among the conductive layers included in the second partial conductive layer 226b through the second upper conductive layer 272.

[0032] The third through via 313 may extend in a third direction from the fourth region (R4) through the sixth insulating layer 216, the vertical structure, and the second active region 210. The third through via 313 may be coupled to a third memory cell via 243 on a first conductive layer in the second direction among the conductive layers included in the first partial conductive layer 226a and a fourth memory cell via 244 on a first conductive layer in the second direction among the conductive layers included in the second partial conductive layer 226b via a third upper conductive layer 273.

[0033] The fourth through via 314 extends in the third direction from the first region (R1) through the second active region 210. The fourth through via 314 is coupled to the fifth memory cell via 245 on the fifth conductive layer 225 through the fourth upper conductive layer 274. The fifth through via 315 extends in the third direction from the seventh region (R7) through the second active region 210. The fifth through via 315 is coupled to the sixth memory cell via 246 on the fifth conductive layer 225 through the fifth upper conductive layer 275.

[0034] The sixth through via 316 penetrates from the first region (R1) through the second active region 210 and is coupled to the seventh memory cell via 247 on the fourth conductive layer 224 through the sixth upper conductive layer 276. The seventh through via 317 penetrates from the seventh region (R7) through the second active region 210 and is coupled to the eighth memory cell via 248 on the fourth conductive layer 224 through the seventh upper conductive layer 277.

[0035] The eighth through via 318 passes through the second active region 210 from the first region (R1) and is coupled to the ninth memory cell via 249 on the third conductive layer 223 via the eighth upper conductive layer 278. The ninth through via 319 passes through the second active region 210 from the seventh region (R7) and is coupled to the tenth memory cell via 250 on the third conductive layer 223 via the ninth upper conductive layer 279.

[0036] The tenth through via 320 extends in the third direction from the first region (R1) through the second active region 210. The tenth through via 320 is coupled to an eleventh memory cell via 251 on a second conductive layer in the second direction among the conductive layers included in the first partial conductive layer 226a through a tenth upper conductive layer 280. The eleventh through via 321 extends in the third direction from the seventh region (R7) through the second active region 210. The eleventh through via 321 is coupled to a twelfth memory cell via 252 on a second conductive layer in the second direction among the conductive layers included in the second partial conductive layer 226b through an eleventh upper conductive layer 281.

[0037] The twelfth through via 322 extends in the third direction from the fourth region (R4) through the sixth insulating layer 216, the vertical structure, and the second active region 210. The twelfth through via 322 is coupled through the twelfth upper conductive layer 282 to a thirteenth memory cell via 253 on a second conductive layer in the second direction among the conductive layers included in the first partial conductive layer 226a, and a fourteenth memory cell via 254 on a second conductive layer in the second direction among the conductive layers included in the second partial conductive layer 226b.

[0038] The thirteenth through via 323 passes through the second active region 210 from the first region (R1) and is coupled to the fifteenth memory cell via 255 on the second conductive layer 222 via the thirteenth upper conductive layer 283. The fourteenth through via 324 passes through the second active region 210 from the seventh region (R7) and is coupled to the sixteenth memory cell via 256 on the second conductive layer 222 via the fourteenth upper conductive layer 284.

[0039] The fifteenth through via 325 passes through the second active region 210 from the first region (R1) and is coupled to the seventeenth memory cell via 257 on the first conductive layer 221 via the fifteenth upper conductive layer 285. The sixteenth through via 326 passes through the second active region 210 from the seventh region (R7) and is coupled to the eighteenth memory cell via 258 on the first conductive layer 221 via the sixteenth upper conductive layer 286.

[0040] The seventeenth through via 327 extends in the third direction from the first region (R1) through the second active region 210. The seventeenth through via 327 is coupled to the nineteenth memory cell via 259 on the third conductive layer in the second direction among the conductive layers included in the first partial conductive layer 226a through the seventeenth upper conductive layer 287. The eighteenth through via 328 extends in the third direction from the seventh region (R7) through the second active region 210. The eighteenth through via 328 is coupled to the twentieth memory cell via 260 on the third conductive layer in the second direction among the conductive layers included in the second partial conductive layer 226b through the eighteenth upper conductive layer 288.

[0041] The nineteenth through via 329 extends in the third direction from the fourth region (R4) through the sixth insulating layer 216, the vertical structure, and the second active region 210. The nineteenth through via 329 is coupled to a twenty-first memory cell via 261 on a third conductive layer in the second direction among the conductive layers included in the first partial conductive layer 226a and a twenty-second memory cell via 262 on a third conductive layer in the second direction among the conductive layers included in the second partial conductive layer 226b through a nineteenth upper conductive layer 289.

[0042] A first insulating material 201 is provided between the first to fifth conductive layers (221-225) and the third through via 313, the twelfth through via 322, and the nineteenth through via 329. The first insulating material 201 may be the same as or different from the first to sixth insulating layers (211-216).

[0043] In the third region (R3) and the fifth region (R5), a conductive line 340 is provided on the sixth conductive layer 226. To avoid unnecessarily complicating the drawing, two first and second conductive lines (341, 342) are shown as an example. For example, the two first and second conductive lines (341, 342) may correspond to one column of the vertical channel 230 in the second direction.

[0044] In one row of vertical channels 230 in the second direction, one conductive line (e.g., 341) is coupled to odd-numbered vertical channels through conductive line via 351. In one row of vertical channels 230 in the second direction, another conductive line (e.g., 342) is coupled to even-numbered vertical channels through conductive line vias (not shown).

[0045] Two rows of vertical channels extending along the second direction may be partitioned into one vertical channel group. The vertical channels may be arranged alternately along the second direction into two rows belonging to one vertical channel group. As shown in FIG. 1, one vertical channel group includes 12 (or more) vertical channels.

[0046] Due to process issues, the first through fifth conductive layers (221-225) may be manufactured by injecting a metal material such as tungsten through the first word line cut 11 and the second word line cut 12. However, when the sixth conductive layer 226 is to be manufactured by injecting a metal material, the conductive layer between the first string select line cut 13 and the second string select line cut 14 must be manufactured by injecting a metal material through the first string select line cut 13 and the second string select line cut 14.

[0047] Similarly, the conductive layer between the third string select line cut 15 and the fourth string select line cut 16 must be fabricated by injecting a metal material through the third string select line cut 15 and the fourth string select line cut 16.

[0048] The first to fourth string selection line cuts (13 to 16) have a smaller width (width in the first direction) than the first and second word line cuts (11, 12). Therefore, the metal material cannot be normally injected through the first to fourth string selection line cuts (13 to 16). The conductive layer between the first to fourth string selection line cuts (13 to 16) cannot be normally formed.

[0049] To solve this problem, the sixth conductive layer 226 can be fabricated using a material that can be deposited or grown, such as polysilicon. However, polysilicon has a significantly lower electrical conductivity than a metallic material, such as tungsten. Therefore, the performance of the memory block 200 can be degraded.

[0050] In the nonvolatile memory device according to the embodiment of the present invention, the sixth conductive layer 226 is divided into a first partial conductive layer 226a and a second partial conductive layer 226b through the string selection line steering in the fourth region (R4) to prevent the performance of the sixth conductive layer 226 from being degraded. Since the length of the sixth conductive layer 226 is reduced, the resistance of the sixth conductive layer 226 is reduced.

[0051] In addition, the nonvolatile memory device according to the embodiment of the present invention applies an additional voltage to the sixth conductive layer 226 through the through vias (313, 322, 329) that are perpendicular to the first and second word line cuts (11, 12) and that penetrate the vertical structures from the first to fourth string selection line cuts (13-16) and the vertical string selection line steer in the fourth region (R4). As a stronger voltage is applied to the sixth conductive layer 226, the performance degradation caused by the increased resistance of the sixth conductive layer 226 is compensated for.

[0052] 1, specific positions of the first to nineteenth through vias (311-329) are illustrated. However, the technical idea of ​​the present invention is not limited to the positions shown in Fig. 1. For example, the positions of the first to nineteenth through vias (311-329) may be adjusted or replaced along the second direction.

[0053] In addition, two or more through vias may be electrically connected (e.g., via a corresponding upper conductive layer and a corresponding memory cell via) to any one of the conductive layers belonging to the sixth conductive layer 226 separated by the string select line cut (13, 14, 15 or 16) and the string select line steer in the fourth region (R4) via the string select line steer in the fourth region (R4).

[0054] 1 and 2, two string select line cuts are described as being provided along the second direction in the sixth conductive layer 226. However, the number of string select line cuts disposed along the second direction in the sixth conductive layer 226 can be further increased.

[0055] 3 shows a plan view of another example of a non-volatile memory device. The embodiment of FIG. 3 is the same as that described with reference to FIG. 1 and FIG. 2, except for the first to fourth string selection line cuts (17 to 20) and the vertical dummy channel 300. Therefore, redundant description will be omitted, and components that unnecessarily complicate FIG. 3 will also be omitted.

[0056] Referring to FIG. 3, the first string selection line cut 17, the second string selection line cut 18, the third string selection line cut 19, and the fourth string selection line cut 20 extend in a straight line in a first direction.

[0057] A vertical channel group including two columns of vertical channels extending in the second direction may include 14 (or more) vertical channels. At least one of the vertical channels in each group may be a vertical dummy channel that overlaps with the first string select line cut 17 or the third string select line cut 19. At least another of the vertical channels in each group may be a vertical dummy channel that overlaps with the second string select line cut 18 or the fourth string select line cut 20.

[0058] When the vertical channels are positioned such that the vertical dummy channel overlaps the position of the string select line cut (17, 18, 19, or 20), the distance between the string select line cut (17, 18, 19, or 20) and the vertical channel (excluding the vertical dummy channel) closest to the string select line cut (17, 18, 19, or 20) is maintained above a threshold value. Thus, the string select line cut (17, 18, 19, or 20) does not need to have a waveform.

[0059] FIG 4 shows a plan view of another example of a nonvolatile memory device. FIG 5 is a cross-sectional view of the nonvolatile memory device of FIG 4 taken along line II-II'. FIG 6 is a cross-sectional view of the nonvolatile memory device of FIG 4 taken along line III-III'. Except for the portion corresponding to the string selection line steering in the fourth region (R4), the nonvolatile memory devices of FIG 4, FIG 5 and FIG 6 are the same as the nonvolatile memory devices of FIG 1 and FIG 2. Therefore, a duplicated description will be omitted.

[0060] 4, 5, and 6, the sixth insulating layer 216 and the fifth conductive layer 225 may be separated to face each other along the first direction in the string selection line steer of the fourth region (R4) and spaced apart from each other. The fifth conductive layer 225 may be divided into a first partial conductive layer 225a and a second partial conductive layer 225b.

[0061] In the string selection line steer of the fourth region (R4), in addition to the third through via 313, the twelfth through via 322, and the nineteenth through via 329 for the sixth conductive layer 226, a twentieth through via 330 for the fifth conductive layer 225 may be provided. The twentieth through via 330 is connected to the twenty-third memory cell via 263 on the first partial conductive layer 225a of the fifth conductive layer 225 through the twentieth upper conductive layer 290, and is connected to the twenty-fourth memory cell via 264 on the second partial conductive layer 225b. A second insulating material 202 may be provided between the twentieth through via 330 and the first to fourth conductive layers (221 to 224).

[0062] The peripheral circuit 100 may include a fourth pass transistor 150 that supplies a voltage to the fourth through via 314, a fifth pass transistor 160 that supplies a voltage to the fifth through via 315, and a sixth pass transistor 170 that supplies a voltage to the twentieth through via 330.

[0063] The fourth pass transistor 150 may include a gate 151, an insulating film 152, a first junction 153, and a second junction 154. The fifth pass transistor 160 may include a gate 161, an insulating film 162, a first junction 163, and a second junction 164. The sixth pass transistor 170 may include a gate 171, an insulating film 172, a first junction 173, and a second junction 174.

[0064] The first junction 153 of the fourth pass transistor 150 is coupled to a fourth peripheral circuit via 184. The fourth peripheral circuit via 184 may be coupled to a wiring (not shown). The second junction 154 of the fourth pass transistor 150 may be coupled to a fourth through via 314.

[0065] A first junction 163 of the fifth pass transistor 160 is coupled to a fifth peripheral circuit via 185. The fifth peripheral circuit via 185 is coupled to a wiring (not shown). A second junction 164 of the fifth pass transistor 160 is coupled to a fifth through via 315.

[0066] A first junction 173 of the sixth pass transistor 170 is coupled to a sixth peripheral circuit via 186. The sixth peripheral circuit via 186 is coupled to a wiring (not shown). A second junction 174 of the sixth pass transistor 170 is coupled to a twentieth through via 330.

[0067] A gate 151 of the fourth pass transistor 150, a gate 161 of the fifth pass transistor 160, and a gate 171 of the sixth pass transistor 170 are connected to a common wiring. A fourth peripheral circuit via 184, a fifth peripheral circuit via 185, and a sixth peripheral circuit 186 are connected to a common wiring.

[0068] That is, the fourth pass transistor 150, the fifth pass transistor 160, and the sixth pass transistor 170 can transmit a common voltage of the common wiring to the fourth through via 314, the fifth through via 315, and the twentieth through via 330, respectively, in response to a common control signal.

[0069] Because the fifth conductive layer 225 is not separated by string select line cuts (13, 14, 15, or 16), a single through via is provided in the string select line steer in the fourth region (R4), allowing a strong voltage to be applied to the fifth conductive layer 225. However, multiple through vias for the fifth conductive layer 225 may be provided in the string select line steer in the fourth region (R4) to electrically couple (e.g., via corresponding upper conductive layers and corresponding memory cell vias) with the first partial conductive layer 225a and the second partial conductive layer 225b.

[0070] Fig. 7 shows another example of a cross-sectional view of the memory block 200. The cross-sectional view of Fig. 7 is the same as the cross-sectional view of the memory block 200 of Fig. 2 except for the third through via 313. Therefore, duplicated reference symbols will be omitted, and duplicated descriptions will be omitted.

[0071] Referring to FIG. 7, a vertical structure may be disposed between a first word line steer (WLS1) and a second word line steer (WLS2). One pair of insulating layers and conductive layers may form one floor. The vertical structure may form first to fifth floors (F1 to F5). A sixth floor (F6) in which a string select line steer (SSLS) is provided may be located on the vertical structure.

[0072] The third through via 313 of the string select line steer (SSLS) may be electrically insulated from the conductive layers of the first to fifth layers (F1 to F5) by an insulating film (IL) surrounding the third through via 313. As an example, the insulating film (IL) may envelop and hide the third through via 313 only up to a specific position between the fifth layer (F5) and the third upper conductive layer 273 along the third direction.

[0073] For example, as described with reference to Figures 4, 5 and 6, the string selection line steers (SSLS) can be extended such that conductive layers from multiple layers are spaced apart facing each other along a first direction.

[0074] Figure 8 is a plan view of another example of a non-volatile memory device. Figure 9 shows a cross-sectional view along line IV-IV' in Figure 8. Figures 8 and 9 are the same as the memory block 200 in Figures 1 and 2, except that two string select line steers (SSLS1, SSLS2) and corresponding through vias (313, 331) are provided. Therefore, duplicated reference symbols are omitted and duplicated descriptions are omitted.

[0075] 8 and 9, the sixth layer (F6) conductive layer (e.g., sixth conductive layer 226) is a first string selection line steer (SSLS1) and a second string selection line steer (SSLS2). That is, the sixth layer (F6) conductive layer is divided into nine conductive layers by the first and second string selection line steers (SSLS1, SSLS2) and the string selection line cuts (13, 14, 15, 16, 21, 22).

[0076] In the first string select line steer (SSLS1), a third through via 313, a twelfth through via 322, and a nineteenth through via 329 are provided, similar to the fourth region (R4) in Figures 1 and 2. The third through via 313, the twelfth through via 322, and the nineteenth through via 329 are connected to corresponding conductive layers in the conductive layers belonging to the first partial conductive layer 226a (conductive layers separated by string select line cuts (13, 14)) and corresponding conductive layers in the conductive layers belonging to the second partial conductive layer 226b (conductive layers separated by string select line cuts (15, 16)) via corresponding upper conductive layers and memory cell vias, respectively.

[0077] Each of the third through via 313, the twelfth through via 322, and the nineteenth through via 329 may be electrically connected to a corresponding pass transistor (e.g., 140) of the peripheral circuit 100 through the vertical structure and the second active area 210.

[0078] A second string select line steer (SSLS2) is provided with a 21st through via 331, a 22nd through via 332, and a 23rd through via 333. The 21st through via 331, the 22nd through via 332, and the 23rd through via 333 are respectively connected to corresponding conductive layers in the conductive layers belonging to the second partial conductive layer 226b (conductive layers separated by string select line cuts (15, 16)) and corresponding conductive layers in the conductive layers belonging to the third partial conductive layer 226c (conductive layers separated by string select line cuts (21, 22)) via corresponding upper conductive layers and memory cell vias.

[0079] Each of the twenty-first through via 331 , the twenty-second through via 332 , and the twenty-third through via 333 passes through the vertical structure and the second active region 210 and is electrically connected to a corresponding pass transistor (eg, 180 ) of the peripheral circuit 100 .

[0080] A plurality of string select line steers may be provided along the first direction as described with reference to Figures 8 and 9. When a plurality of string select line steers are provided, each conductive layer separated by the string select line steers and the string select line cuts may be supplied with voltages via two pass transistors.

[0081] The conductive layers of the sixth layer (F6) may be separated from each other in the second direction by string select line cuts (13, 14, 15, 16, 21, 22) and electrically connected through the upper conductive layer and the memory cell via to form conductive lines extending in the first direction. As described with reference to Figures 1 and 2, when one string select line steer is provided, each of the conductive lines receives voltages from three pass transistors.

[0082] When two string select line steering are provided as described with reference to Figures 8 and 9, each conductive line can be supplied with voltages from four pass transistors, i.e., when k string select line steering are provided (k is a positive integer), each conductive line can be supplied with voltages from (k+2) pass transistors.

[0083] As an example, the total number of vertical channels penetrating the vertical structure may be n. When i string select line cuts are provided along the second direction and j string select line steers are provided along the first direction, the number of vertical channels (m) belonging to each conductive layer separated by the string select line cuts and string select line steers is calculated by the following formula:

[0084]

number

[0085] As described with reference to Figures 4, 5 and 6, no string select line cuts may be provided from a particular layer, and string select line steers may be provided, in which case the number of vertical channels belonging to each conductive layer separated by the string select line cuts of the corresponding layer may be "n / (i+1)".

[0086] Because the vertical structure has a steered shape, the length in the first direction of each conductive layer separated by the string selection line steer can be less than “1 / (i+1)” of the length in the first direction of each conductive layer not separated by the string selection line steer.

[0087] Fig. 10 shows the shape of a through via 400 as an example. Referring to Figs. 1, 2 and 10, due to process characteristics, the through via (e.g., 410 or 420) increases in cross-sectional area (cross-sectional area along the plane of the first direction and the second direction) as it proceeds in the third direction. In addition, since the depth of a hole that can be formed at one time is limited, the through via 400 may include multiple levels (410, 420). The cross-sectional area of ​​each of the multiple levels (410, 420) may increase as it proceeds in the third direction.

[0088] By way of example, the configuration of through via 400 may be similarly applied to other structures extending in a third direction, such as peripheral circuit vias, vertical channels, and / or memory cell vias.

[0089] For example, in a 92-layer vertical structure, the cross-sectional area of ​​the top stage of the vertical channel is about 25% larger than the cross-sectional area of ​​the bottom stage, while the length in the first direction of the bottom stage conductive layer (e.g., 221) in the 92-layer vertical structure is about 7% larger than the length in the first direction of the top stage conductive layer (e.g., 251).

[0090] When the cross-sectional area of ​​the vertical channel increases, the cross-sectional area of ​​the conductive layer of the corresponding layer decreases, for example, in the plane in the second and third directions. The decrease in the cross-sectional area leads to a decrease in the conductivity of the conductive layer. The degree to which the resistance increases toward the upper layer of the vertical structure (the increase in resistance due to the increase in the cross-sectional area of ​​the vertical channel) is greater than the degree to which the resistance decreases toward the upper layer of the vertical structure (the decrease in resistance due to the decrease in the length of the conductive layer in the first direction).

[0091] In order to compensate for this increase in resistance and improve the performance of the non-volatile memory device, a structure can be applied that extends the string selection line steers to the upper layers of the vertical structures to reduce resistance, as described with reference to Figures 4, 5 and 6.

[0092] Figure 11 shows an example of a circuit diagram corresponding to the dotted box (DB) in Figure 1. Referring to Figures 1, 2 and 11, a plurality of cell strings (CS) may be disposed on a second active area 210. The plurality of cell strings (CS11, CS12, CS21, CS22, CS31, CS32) may be commonly connected to a common source line (CSL) formed on (or within) the second active area 210.

[0093] The cell strings (CS11, CS21, CS31) may be connected to a first bit line (BL1), and the cell strings (CS12, CS22, CS32) may be connected to a second bit line (BL2). For example, the first bit line (BL1) may correspond to one of the first and second conductive lines (341, 342) (e.g., the first conductive line 341), and the second bit line (BL2) may correspond to the other of the first and second conductive lines (341, 342) (e.g., the second conductive line 342).

[0094] Cell strings (CS11, CS21, CS31) correspond to odd-numbered vertical channels (234, 236, 238) along the second direction, and cell strings (CS12, CS22, CS32) correspond to even-numbered vertical channels (235, 237, 239) along the second direction.

[0095] Although the vertical channels (234-239) are arranged in a row along the second direction, in order to avoid unnecessarily complicating the drawing, the cell strings (CS11, CS12, CS21, CS22, CS31, CS32) in FIG. 12 are illustrated in multiple rows and columns. For example, the direction in which the bit lines (BL1, BL2) extend is the column direction, and the direction in which the string select lines (SSL1, SSL2, SSL3) extend is the row direction. In FIG. 11, that is, the vertical channels (234-239) are illustrated in three rows and two columns.

[0096] The cell strings in each row may be commonly connected to a ground selection line (GSL) and may be connected to corresponding string selection lines among the first to third string selection lines (SSL1 to SSL3). The cell strings in each column may be connected to corresponding bit lines among the first and second bit lines (BL1, BL2).

[0097] Each cell string may include at least one ground selection transistor (GST) connected to a ground selection line (GSL), a plurality of memory cell transistors (MC1 to MC4) respectively connected to a plurality of word lines (WL1 to WL4), and a string selection transistor (SST1, SST2, or SST3) connected to a corresponding string selection line (SSL1, SSL2, or SSL3).

[0098] The ground selection transistors (GST) may correspond to the vertical channels (234-239) and portions of the first conductive layer 221 adjacent to the vertical channels (234-239). The ground selection lines (GSL) may correspond to the first conductive layer 221. Similarly, the first to fourth memory cell transistors (MC1-MC4) and word lines (WL1-WL4) may correspond to the second to fifth conductive layers (222-225) and the vertical channels (234-239).

[0099] The first string selection line (SSL1) may correspond to the conductive layer (the conductive layer located third along the second direction) separated by the second and fourth string selection line cuts (14, 16) among the conductive layers belonging to the sixth conductive layer 226 (the conductive layers separated by the first to fourth string selection line cuts (13 to 16) and the string selection line steers).

[0100] The second string selection line (SSL2) may correspond to the conductive layer separated by the first to fourth string selection line cuts (13-16) (the conductive layer located second along the second direction) among the conductive layers belonging to the sixth conductive layer 226 (conductive layers separated by the first to fourth string selection line cuts (13-16) and the string selection line steers).

[0101] The third string selection line (SSL3) may correspond to the conductive layer (the conductive layer located first along the second direction) separated by the first and third string selection line cuts (13, 15) among the conductive layers belonging to the sixth conductive layer 226 (conductive layers separated by the first to fourth string selection line cuts (13 to 16) and string selection line steers).

[0102] 1 to 11, the number of cell transistors included in one cell string is exemplified as six. However, the number of cell transistors included in one cell string is not limited. As the number of layers of the vertical structure increases, the number of cell transistors included in one cell string can increase.

[0103] In addition, the number of cell strings in which the cell transistors belonging to one cell string are used as ground selection transistors, memory cell transistors, or string selection transistors may be changed. Some of the cell transistors belonging to one cell string may be used as dummy memory cell transistors that do not store data.

[0104] 12 is a block diagram illustrating a nonvolatile memory device 500 according to an embodiment of the present invention. Referring to FIG. 12, the nonvolatile memory device 500 includes a memory cell array 510, a pass circuit unit 520, a block decoder 530, a row decoder 540, a page buffer 550, a data input and output circuit 560, a buffer 570, and a control logic 580.

[0105] The memory cell array 510 includes a plurality of memory blocks (511, 512). Each memory block includes a plurality of memory cells. For example, each memory block may include the memory block 200 described with reference to FIGS. 1 to 11. The memory block 200 may be repeatedly provided along the second direction to correspond to the plurality of memory blocks (511, 512).

[0106] 1, 2, 11 and 12, each memory block (e.g., 511) is connected to a ground selection line (GSL), first through fourth word lines (WL1-WL4), and first through third string selection lines (SSL1-SSL3). Each memory block is connected to a page buffer 550 via a plurality of bit lines (BL).

[0107] In the example structure of Figures 1 and 2, the bit lines (BL) may include first to sixteenth bit lines (BL1 to BL16). A plurality of memory blocks (511, 512) may be commonly connected to the plurality of bit lines (BL). For example, the first and second conductive lines (341, 342) may be extended in the second direction and commonly connected to the plurality of memory blocks.

[0108] As an example, each of the multiple memory blocks (BLK1 to BLKz) may be a unit of an erase operation. Memory cells belonging to each memory block may be erased simultaneously. As another example, each memory block may be divided into multiple sub-blocks. Each of the multiple sub-blocks may be a unit of an erase operation.

[0109] The path circuit 520 may include a plurality of path circuits (521, 522) corresponding to the plurality of memory blocks (511, 512), respectively. As an example, the structure of one path circuit 521 corresponding to one memory block 511 is shown.

[0110] The ground selection line (GSL) and the first to fourth word lines (WL1 to WL4) correspond to the first to fifth conductive layers (221 to 225), respectively. Each of the ground selection line (GSL) and the first to fourth word lines (WL1 to WL4) is connected to two pass transistors from the word line steers at both ends through two through vias. That is, the pass circuit 521 includes two pass transistors for each of the ground selection line (GSL) and the first to fourth word lines (WL1 to WL4).

[0111] The first to third string selection lines (SSL1 to SSL3) correspond to the sixth conductive layer 226. Each of the first to third string selection lines (SSL1 to SSL3) is connected to three pass transistors from the word line steers at both ends and the string selection line steer in the center through three through vias. That is, the pass circuit 521 includes three pass transistors for each of the first to third string selection lines (SSL1 to SSL3).

[0112] The block decoder 530 is connected to the block word lines (BLKWL, BLKWLs). The block decoder 530 operates in response to the control of the control logic 580. The block decoder 530 decodes the block address (BA) received from the buffer 570. The block decoder 530 activates a block word line (e.g., BLKWL) designated by the block address (BA) among the block word lines (BLKWL, BLKWLs) and turns on a pass transistor of the pass circuit 521 connected to the block word line (BLKWL).

[0113] When the pass transistor of the pass circuit 521 is turned on, the ground selection line (GSL), the first to fourth word lines (WL1 to WL4), and the first to third string selection lines (SSL1 to SSL3) of the memory block 511 connected to the pass circuit 521 are connected to the row decoder 540.

[0114] The row decoder 540 is connected to the memory block 511 via the pass circuit 521, the ground selection line (GSL), the first to fourth word lines (WL1 to WL4), and the first to third string selection lines (SSL1 to SSL3). The row decoder 540 operates under the control of the control logic 580.

[0115] The row decoder 540 may decode the row address (RA) received from the buffer 570 and control voltages applied to the ground selection line (GSL), the first to fourth word lines (WL1 to WL4), and the first to third string selection lines (SSL1 to SSL3) based on the decoded row address.

[0116] The page buffer 550 is connected to the memory cell array 510 via first to sixteenth bit lines (BL1 to BL16). The page buffer 550 is connected to a data input and output circuit 560 via a data line (DL). The page buffer 550 operates under the control of a control logic 580.

[0117] During a write operation, the page buffer 550 may store data to be written to the memory cell transistors. Based on the stored data, the page buffer 550 may apply voltages to the first through sixteenth bit lines (BL1 to BL16). During a read operation, a write operation, or a read for verifying an erase operation, the page buffer 550 may detect voltages on the first through sixteenth bit lines (BL1 to BL16) and store the detection results.

[0118] The data input and output circuit 560 is connected to the page buffer 550 via a plurality of data lines (DL). The data input and output circuit 560 may receive a column address (CA) from the buffer 570. The data input and output circuit 560 may output data read by the page buffer 550 to the buffer 570 according to the column address (CA). The data input and output circuit 560 may transfer data received from the buffer 570 to the page buffer 550 depending on the column address (CA).

[0119] The buffer 570 can receive a command (CMD) and an address (ADDR) and exchange data (DATA) with an external device via a first channel (CH1). The buffer 570 can operate under the control of the control logic 580. The buffer 570 can transmit the command (CMD) to the control logic 580. The buffer 570 can transmit a block address (BA) of the address (ADDR) to the block decoder 530, a row address (RA) to the row decoder 540, and a column address (CA) to the data input and output circuit 560. The buffer 570 can exchange data (DATA) with the data input and output circuit 560.

[0120] The control logic 580 can exchange a control signal (CTRL) with an external device via a second channel (CH2). The control logic 580 can control the buffer 570 to route a command (CMD), an address (ADDR), and data (DATA). The control logic 580 can decode the command (CMD) received from the buffer 570 and control the non-volatile memory device 500 based on the decoded command.

[0121] The control logic 580 may include a voltage generator 580. The voltage generator 580 may generate various voltages to be applied to the ground selection line (GSL), the first through fourth word lines (WL1 through WL4), and the first through third string selection lines (SSL1 through SSL3). The control logic 580 may transmit the various voltages generated by the voltage generator 580 to the row decoder 540.

[0122] The above-described contents are specific embodiments for carrying out the present invention. The present invention includes not only the above-described embodiments, but also embodiments that can be simply modified or easily changed. The present invention should also include techniques that can be easily modified and carried out using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined not only by the claims described below, but also by equivalents to the claims of the present invention. [Explanation of symbols]

[0123] 110: First active region 120, 130, 140: Pass transistor 121, 131, 141: Gate 122, 132, 142: insulating film 123, 133, 143: First junction 124, 134, 144: Second junction 181, 182, 183: Peripheral circuit vias 210: Second active region 211 to 215: first to fifth conductive layers 221 to 225: 1st to 5th insulating layers 216: Sixth insulating layer 226: Sixth conductive layer 226a, 226b: Partially conductive layer 230, 231-239: Vertical channels 241 to 264: Memory cell vias 271-290: Upper conductive layer 311~331: Through vias 341, 342: Conductive lines 351: Conductive line via 11, 12: Word line cut 13,14,15,16: String selection line cut

Claims

1. 1. A non-volatile memory device, comprising: a peripheral circuit including a first active region and an element formed on the first active region; and a memory block including a second active region on the peripheral circuit; The memory block includes: a vertical structure including a pair of a first insulating layer and a first conductive layer extending along a first direction on the second active region and stacked in a second direction perpendicular to a top surface of the second active region; a second insulating layer on the vertical structure; a second conductive layer and a third conductive layer on the second insulating layer, the second conductive layer and the third conductive layer being spaced apart from each other and facing each other along the first direction; a first vertical channel extending through the second conductive layer, the second insulating layer, and the vertical structure in the second direction; a second vertical channel penetrating the third conductive layer, the second insulating layer, and the vertical structure in the second direction; the first conductive layer comprises a metallic material, and the second conductive layer and the third conductive layer comprise polysilicon; the second conductive layer and the third conductive layer are coupled to a region of the second insulating layer exposed between the second conductive layer and the third conductive layer, a first through via penetrating the vertical structure and the second active region; A non-volatile memory device.

2. The non-volatile memory device of claim 1 , wherein the first through via is electrically connected to at least one of the elements of the peripheral circuit.

3. the second conductive layer is connected to a second through via that penetrates the second active region on a side of the second conductive layer opposite to a side on which the first through via is located; 3. The non-volatile memory device of claim 1, wherein the third conductive layer is connected to a third through via that penetrates the second active region on a side of the third conductive layer opposite to the side on which the first through via is located.

4. The memory block includes: a fourth conductive layer on the second insulating layer facing and spaced apart from the second conductive layer along a third direction perpendicular to the first direction; a fifth conductive layer on the second insulating layer, the fifth conductive layer facing and spaced apart from the third conductive layer along the third direction and facing and spaced apart from the fourth conductive layer along the first direction; a third vertical channel penetrating the fourth conductive layer, the second insulating layer, and the vertical structure in the second direction; a fourth vertical channel penetrating the fifth conductive layer, the second insulating layer, and the vertical structure in the second direction; the fourth conductive layer and the fifth conductive layer include polysilicon; 2. The non-volatile memory device of claim 1, wherein the fourth conductive layer and the fifth conductive layer are connected to a second through via that penetrates the vertical structure and the second active region in a region of the second insulating layer exposed between the fourth conductive layer and the fifth conductive layer.

5. the fourth conductive layer is connected to a third through via penetrating the second active region on a side of the fourth conductive layer opposite to a side on which the second through via is located; 5. The non-volatile memory device of claim 4, wherein the fifth conductive layer is connected to a fourth through via that penetrates the second active region on a side of the fifth conductive layer opposite to where the second through via is located.

6. 6. The non-volatile memory device according to claim 4, wherein a first boundary where the second conductive layer and the fourth conductive layer face each other, and a second boundary where the third conductive layer and the fifth conductive layer face each other, have a corrugated shape.

7. The memory block includes: at least one first vertical dummy channel penetrating the second insulating layer and the vertical structure in the second direction from a first boundary where the second conductive layer and the fourth conductive layer face each other; 6. The non-volatile memory device of claim 4, further comprising at least one second vertical dummy channel penetrating the second insulating layer and the vertical structure in the second direction from a second boundary where the third conductive layer and the fifth conductive layer face each other.

8. The memory block includes: a sixth conductive layer on the second insulating layer facing and spaced apart from the fourth conductive layer along the third direction; a seventh conductive layer on the second insulating layer, the seventh conductive layer facing and spaced apart from the fifth conductive layer along the third direction and facing and spaced apart from the sixth conductive layer along the first direction; a fifth vertical channel penetrating the sixth conductive layer, the second insulating layer, and the vertical structure in the second direction; a sixth vertical channel penetrating the seventh conductive layer, the second insulating layer, and the vertical structure in the second direction; the sixth conductive layer and the seventh conductive layer include polysilicon; 5. The non-volatile memory device of claim 4, wherein the sixth conductive layer and the seventh conductive layer are coupled to a region of the second insulating layer exposed between the sixth conductive layer and the seventh conductive layer, the vertical structure, and a third through via penetrating the second active region.

9. the sixth conductive layer is connected to a fourth through via that penetrates the second active region on a side of the sixth conductive layer opposite to a side on which the third through via is located; 9. The non-volatile memory device of claim 8, wherein the seventh conductive layer is connected to a fifth through via that penetrates the second active region on a side of the seventh conductive layer opposite to where the third through via is located.

10. the first vertical channel, the third vertical channel, and the fifth vertical channel are divided into a plurality of groups extending along the third direction; 9. The non-volatile memory device of claim 8, wherein each of the plurality of groups includes twelve vertical channels arranged in two alternating columns along the third direction.

11. 11. The non-volatile memory device of claim 10, wherein a first boundary between the second conductive layer and the fourth conductive layer and a second boundary between the fourth conductive layer and the sixth conductive layer have a corrugation to maintain a distance between a nearest adjacent vertical channel among the twelve vertical channels above a threshold value.

12. the first vertical channel, the third vertical channel, and the fifth vertical channel are divided into a plurality of groups extending along the third direction; 9. The non-volatile memory device of claim 8, wherein each of the plurality of groups includes 14 vertical channels arranged in two alternating columns along the third direction.

13. one of the fourteen vertical channels is located at a first boundary between the second conductive layer and the fourth conductive layer; 13. The non-volatile memory device of claim 12, wherein another of the 14 vertical channels is located at a second boundary between the fourth conductive layer and the sixth conductive layer.

14. 14. The non-volatile memory device of claim 1, wherein the first conductive layer comprises tungsten.

15. 1. A non-volatile memory device, comprising: a peripheral circuit including a first active region and an element formed on the first active region; and a memory block including a second active region on the peripheral circuit; The memory block includes: a vertical structure including a pair of a first insulating layer and a first conductive layer extending along a first direction on the second active region and stacked in a second direction perpendicular to a top surface of the second active region; a second insulating layer on the vertical structure; a second conductive layer and a third conductive layer on the second insulating layer, the second conductive layer and the third conductive layer being spaced apart from each other and facing each other along the first direction; a third insulating layer on the second conductive layer; and a fourth conductive layer on the third insulating layer; and a fourth insulating layer on the third conductive layer; and a fifth conductive layer on the fourth insulating layer; and a first vertical channel penetrating the fourth conductive layer, the third insulating layer, the second conductive layer, the second insulating layer, and the vertical structure in the second direction; a second vertical channel penetrating the fifth conductive layer, the fourth insulating layer, the third conductive layer, the second insulating layer, and the vertical structure in the second direction; the first conductive layer, the second conductive layer, and the third conductive layer comprise a metallic material, and the fourth conductive layer and the fifth conductive layer comprise polysilicon; the second conductive layer and the third conductive layer are coupled to a first through via that penetrates a region of the second insulating layer exposed between the second conductive layer and the third conductive layer, the vertical structure, and the second active region; the fourth conductive layer and the fifth conductive layer are coupled to a second through via that penetrates a region of the second insulating layer exposed between the second conductive layer and the third conductive layer, the vertical structure, and the second active region; A non-volatile memory device.

16. The memory block includes: a fourth conductive layer on the second insulating layer, the fourth conductive layer facing and spaced apart from the third conductive layer along the first direction; a third vertical channel penetrating the fourth conductive layer, the second insulating layer, and the vertical structure in the second direction; the fourth conductive layer includes polysilicon; 2. The non-volatile memory device of claim 1, wherein the third conductive layer and the fourth conductive layer are coupled to a second through via that penetrates a region of the second insulating layer exposed between the third conductive layer and the fourth conductive layer, the vertical structure, and the second active region.

17. 1. A non-volatile memory device, comprising: a first active area and a peripheral circuit including at least three pass transistors formed on the first active area; A memory block, The memory block includes: a second active area on the peripheral circuitry; a vertical structure including a pair of a first insulating layer and a first conductive layer extending along a first direction on the second active region and stacked in a second direction perpendicular to a top surface of the second active region; a second insulating layer on the vertical structure; a second conductive layer and a third conductive layer on the second insulating layer, the second conductive layer and the third conductive layer being spaced apart from each other and facing each other along the first direction; a first vertical channel extending through the second conductive layer, the second insulating layer, and the vertical structure in the second direction; a second vertical channel penetrating the third conductive layer, the second insulating layer, and the vertical structure in the second direction; the first conductive layer comprises a metallic material, and the second conductive layer and the third conductive layer comprise polysilicon; The at least three pass transistors supply a common voltage to the second conductive layer and the third conductive layer through at least three through vias that penetrate the second active region.

18. The at least three through vias include: a first through via extending through an exposed area of ​​the second insulating layer between the second conductive layer and the third conductive layer, the vertical structure, and the second active area; a second through via that passes through the second active region on a side of the second conductive layer opposite to the side on which the first through via is located; 20. The non-volatile memory device of claim 17, further comprising a third through via that passes through the second active region on a side of the third conductive layer opposite to a side on which the first through via is located.

19. the second conductive layer and the third conductive layer are a string selection line; the second conductive layer forms a first string select transistor coupled with the first vertical channel to the string select line; 19. The non-volatile memory device of claim 17 or 18, wherein the third conductive layer forms a second string select transistor coupled with the second vertical channel to the string select line.

20. 1. A non-volatile memory device, comprising: a first active region and a peripheral circuit including an element formed on the first active region; a second active region on the peripheral circuit, and a memory block including memory cells formed on the second active region; The memory block includes: a vertical structure including a pair of a first insulating layer and a first conductive layer extending along a first direction on the second active region and stacked in a second direction perpendicular to a top surface of the second active region; a second insulating layer on the vertical structure; a second conductive layer and a third conductive layer on the second insulating layer, the second conductive layer and the third conductive layer being spaced apart from each other and facing each other along the first direction; fourth and fifth conductive layers on the second insulating layer, the fourth and fifth conductive layers being spaced apart from each other along the first direction and parallel to the second and third conductive layers in a third direction perpendicular to the first and second directions; sixth and seventh conductive layers on the second insulating layer, the sixth and seventh conductive layers being spaced apart from each other along the first direction and parallel to the fourth and fifth conductive layers in the third direction; a vertical channel extending through the vertical structure in the second direction; the first conductive layer comprises a metallic material, and the second, third, fourth, fifth, and sixth conductive layers comprise polysilicon; the second conductive layer and the third conductive layer are coupled to a first through via that penetrates a region of the second insulating layer exposed between the second conductive layer and the third conductive layer, the vertical structure, and the second active region; the fourth conductive layer and the fifth conductive layer are coupled to a second through via that penetrates a region of the second insulating layer exposed between the fourth conductive layer and the fifth conductive layer, the vertical structure, and the second active region; The sixth conductive layer and the seventh conductive layer are connected to a region of the second insulating layer exposed between the sixth conductive layer and the seventh conductive layer, the vertical structure, and a third through via penetrating the second active region.

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