Semiconductor Device

Abstract

This semiconductor device includes: a semiconductor chip having a principal surface; an insulating layer formed on the principal surface; a functional device formed on the semiconductor chip and / or the insulating layer; a low potential terminal formed on the insulating layer and electrically connected to the functional device; a high potential terminal which is formed on the insulating layer so as to be spaced apart from the low potential terminal, and which is electrically connected to the functional device; and a seal conductor which is, when observed in plan view, embedded in the insulating layer like a wall so as to partition a region containing the functional device, the low potential terminal, and the high potential terminal from other regions, and which is electrically isolated from the semiconductor chip, the functional device, the low potential terminal, and the high potential terminal.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device provided with a shield conductor. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, an active element, a plurality of interlayer insulating layers, a plurality of metal electrodes, and a moisture-resistant ring (sealing conductor). The active element is formed on the semiconductor substrate. The plurality of interlayer insulating layers are stacked on the semiconductor substrate. The plurality of metal electrodes are formed on the uppermost interlayer insulating layer. The moisture-resistant ring is embedded in the plurality of interlayer insulating layers so as to surround the active element and the plurality of metal electrodes in a plan view. The moisture-resistant ring is grounded to the semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-261613 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device disclosed in Patent Document 1, due to the structure in which the sealing conductor is grounded to the semiconductor substrate, when a voltage is applied to the metal electrodes, undesired conduction may occur between the metal electrodes and the sealing conductor. The withstand voltage of the semiconductor device decreases due to this type of conduction. Examples of undesired conduction include leakage current and discharge.

[0005] An embodiment of the present invention provides a semiconductor device having a structure including a seal conductor, which can improve the withstand voltage. [Means for solving the problem]

[0006] One embodiment of the present invention provides a semiconductor device including a semiconductor chip having a main surface, an insulating layer formed on the main surface, a functional device formed on at least one of the semiconductor chip and the insulating layer, a low potential terminal formed on the insulating layer and electrically connected to the functional device, a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the functional device, and a sealing conductor embedded in the insulating layer in a wall shape so as to separate an area including the functional device, the low potential terminal, and the high potential terminal from other areas in a planar view, and electrically isolated from the semiconductor chip, the functional device, the low potential terminal, and the high potential terminal.

[0007] According to this semiconductor device, when a voltage is applied to the low potential terminal and the high potential terminal, undesired conduction between the high potential terminal and the seal conductor can be suppressed. Also, undesired conduction between the low potential terminal and the seal conductor can be suppressed. Also, undesired conduction between the functional device and the seal conductor can be suppressed. Therefore, the withstand voltage can be improved. One embodiment of the present invention provides a semiconductor device including a semiconductor chip having a main surface, an insulating layer formed on the main surface, a functional device formed on at least one of the semiconductor chip and the insulating layer, a low potential terminal formed on the insulating layer and electrically connected to the functional device, a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the functional device, and a sealing conductor embedded in the insulating layer in a wall shape so as to separate an area including the functional device, the low potential terminal, and the high potential terminal from other areas in a planar view.

[0008] One embodiment of the present invention provides a semiconductor device including a semiconductor chip having a main surface, an insulating layer formed on the main surface, a low potential pattern formed in the insulating layer, a high potential pattern formed in the insulating layer so as to face the low potential pattern in a normal direction of the main surface, a dummy pattern formed around the high potential pattern in the insulating layer, including a conductor, and shielding an electric field between the low potential pattern and the high potential pattern, a low potential terminal formed on the insulating layer and electrically connected to the low potential pattern, a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the high potential pattern, and a seal conductor embedded in the insulating layer in a wall shape so as to separate an area including the low potential pattern, the high potential pattern, the dummy pattern, the low potential terminal, and the high potential terminal from other areas in a planar view, and electrically separated from the semiconductor chip, the low potential pattern, the high potential pattern, the dummy pattern, the low potential terminal, and the high potential terminal.

[0009] According to this semiconductor device, when a voltage is applied to the low potential terminal and the high potential terminal, the dummy pattern can suppress electric field concentration on the high potential pattern. Furthermore, according to this semiconductor device, when a voltage is applied to the low potential terminal and the high potential terminal, undesired conduction between the high potential pattern (high potential terminal) and the seal conductor can be suppressed. Also, undesired conduction between the low potential pattern (low potential terminal) and the seal conductor can be suppressed. Also, undesired conduction between the dummy pattern and the seal conductor can be suppressed. Therefore, the withstand voltage can be improved.

[0010] One embodiment of the present invention provides a semiconductor device including a semiconductor chip having a main surface, an insulating layer formed on the main surface, a low potential pattern formed in the insulating layer, a high potential pattern formed in the insulating layer so as to face the low potential pattern in a normal direction of the main surface, a dummy pattern formed around the high potential pattern in the insulating layer, including a conductor, and shielding an electric field between the low potential pattern and the high potential pattern, a low potential terminal formed on the insulating layer and electrically connected to the low potential pattern, a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the high potential pattern, and a seal conductor embedded in the insulating layer in a wall shape so as to separate an area including the low potential pattern, the high potential pattern, the dummy pattern, the low potential terminal, and the high potential terminal from other areas in a planar view. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view of a semiconductor module in which a semiconductor device according to a first embodiment of the present invention is incorporated. [Diagram 2] FIG. 2 is a diagram for explaining the operation of the semiconductor module shown in FIG. [Diagram 3] FIG. 3 is a voltage waveform diagram used in the explanation of FIG. [Figure 4] FIG. 4 is a perspective view showing the semiconductor device shown in FIG. [Diagram 5] FIG. 5 is a plan view of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. [Figure 10] FIG. 10 is an enlarged view of the region X shown in FIG. [Figure 11] FIG. 11 is an enlarged view of region XI shown in FIG. [Figure 12] FIG. 12 is an enlarged view of region XII shown in FIG. [Figure 13] FIG. 13 is an enlarged view of a region XIII shown in FIG. 8, showing an isolation structure according to the first embodiment. [Figure 14A] FIG. 14A is an enlarged view of a region XIII shown in FIG. 8, showing an isolation structure according to the second embodiment. [Figure 14B] FIG. 14B is an enlarged view of a region XIII shown in FIG. 8, showing an isolation structure according to the third embodiment. [Figure 14C] FIG. 14C is an enlarged view of a region XIII shown in FIG. 8, showing an isolation structure according to the fourth embodiment. [Figure 14D] FIG. 14D is an enlarged view of a region XIII shown in FIG. 8, showing an isolation structure according to the fifth embodiment. [Figure 15] FIG. 15 is a graph showing the average instantaneous breakdown voltage. [Figure 16] FIG. 16 shows the electric field distribution in the vicinity of the high-potential coil investigated by simulation. [Figure 17] FIG. 17 is a diagram showing the electric field distribution of the first high potential dummy pattern investigated by simulation. [Figure 18] FIG. 18 shows the electric field distribution of the floating dummy pattern investigated by simulation. [Figure 19] FIG. 19 is a plan view corresponding to FIG. 7, showing a semiconductor device according to a second embodiment of the present invention. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. [Figure 21] FIG. 21 is a cross-sectional view of a region corresponding to FIG. 8, showing a semiconductor device according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Fig. 1 is a plan view of a semiconductor module 1 incorporating a semiconductor device 5 according to a first embodiment of the present invention. In Fig. 1, the central part of a package body 2 is shown in a see-through manner to clarify the internal structure.

[0013] 1, in this embodiment, the semiconductor module 1 is made of a small outline package (SOP). The semiconductor module 1 is not limited to an SOP, and may be made of a quad for non-lead package (QFN), dual flat package (DFP), dual inline package (DIP), quad flat package (QFP), single inline package (SIP), or small outline J-leaded package (SOJ), or any of a variety of similar packages.

[0014] In this embodiment, the semiconductor module 1 is a composite module including a plurality of devices. The semiconductor module 1 includes a package body 2, a plurality of die pads 3, a plurality of lead terminals 4, a semiconductor device 5, a controller IC 6, a driver IC 7, and a plurality of conductors 17-20.

[0015] The semiconductor device 5 is a transformer chip that boosts and outputs an input electric signal. The controller IC 6 is an IC chip that drives and controls the semiconductor device 5. The driver IC 7 is an IC chip that generates an electric signal according to the electric signal from the semiconductor device 5 and drives and controls a load (e.g., a switching device). The controller IC 6 is a low-potential device with respect to the semiconductor device 5. The driver IC 7 is a high-potential device with respect to the semiconductor device 5.

[0016] The package body 2 includes a molded resin. The molded resin may include an epoxy resin. The package body 2 is formed in a rectangular parallelepiped shape. The package body 2 has a non-mounted surface 8 on one side, a mounting surface 9 on the other side, and side walls 10A to 10D connecting the non-mounted surface 8 and the mounting surface 9. The non-mounted surface 8 and the mounting surface 9 are formed in a quadrangular shape in a plan view seen from their normal direction Z. The mounting surface 9 is a surface that faces a connection target when the semiconductor module 1 is mounted on the connection target. An example of the connection target is a circuit board such as a PCB (printed circuit board).

[0017] The side walls 10A to 10D include a first side wall 10A, a second side wall 10B, a third side wall 10C, and a fourth side wall 10D. The first side wall 10A and the second side wall 10B extend along a first direction X and face a second direction Y perpendicular to the first direction X. The third side wall 10C and the fourth side wall 10D extend in the second direction Y and face the first direction X.

[0018] The multiple die pads 3 are arranged in the package body 2. In this embodiment, each of the multiple die pads 3 is formed in a rectangular parallelepiped shape. The multiple die pads 3 include a first die pad 3A and a second die pad 3B. The first die pad 3A is arranged on the first side wall 10A side. The second die pad 3B is arranged on the second side wall 10B side at a distance from the first die pad 3A.

[0019] The multiple lead terminals 4 are provided on the first side wall 10A side and the second side wall 10B side of the package body 2. Each lead terminal 4 has one end located inside the package body 2 and the other end located outside the package body 2. The other end of each lead terminal 4 is formed as an external connection part to be connected to a connection target.

[0020] The semiconductor device 5 is disposed on the first die pad 3A in the package body 2. In this embodiment, the semiconductor device 5 is formed in a rectangular shape in a plan view. The semiconductor device 5 is disposed on the first die pad 3A with its long side facing the first side wall 10A (second side wall 10B).

[0021] The semiconductor device 5 includes a plurality of low potential terminals 11 and a plurality of high potential terminals 12. The plurality of low potential terminals 11 are arranged at intervals along the long side of the semiconductor device 5 on the first sidewall 10A side. The plurality of high potential terminals 12 are arranged at intervals along the long side of the semiconductor device 5 on the second sidewall 10B side.

[0022] The controller IC 6 is disposed on the first die pad 3A in the package body 2. Specifically, the controller IC 6 is disposed on the first die pad 3A at a distance from the semiconductor device 5 toward the first sidewall 10A. In this embodiment, the controller IC 6 is formed in a rectangular shape in a plan view. The controller IC 6 is disposed on the first die pad 3A with its long side facing the first sidewall 10A (second sidewall 10B).

[0023] The controller IC 6 includes a plurality of first input pads 13 and a plurality of first output pads 14. The plurality of first input pads 13 are arranged at intervals along the long side of the controller IC 6 on the first side wall 10A side. The plurality of first output pads 14 are arranged at intervals along the long side of the controller IC 6 on the second side wall 10B side.

[0024] The driver IC 7 is disposed on the second die pad 3B in the package body 2. In this embodiment, the driver IC 7 is formed in a rectangular shape in a plan view. The driver IC 7 is disposed on the second die pad 3B with its long side facing the first side wall 10A (second side wall 10B).

[0025] The driver IC 7 includes a plurality of second input pads 15 and a plurality of second output pads 16. The plurality of second input pads 15 are arranged at intervals along the long side of the driver IC 7 on the first sidewall 10A side. The plurality of second output pads 16 are arranged at intervals along the long side of the driver IC 7 on the second sidewall 10B side.

[0026] The multiple conductors 17-20 selectively connect the multiple lead terminals 4, the semiconductor device 5, the controller IC 6, and the driver IC 7 within the package body 2. The multiple conductors 17-20 are each made of a bonding wire. The multiple conductors 17-20 include at least one of a copper wire, a gold wire, and an aluminum wire.

[0027] The multiple conductive wires 17-20 include a first conductive wire 17, a second conductive wire 18, a third conductive wire 19, and a fourth conductive wire 20. The first conductive wire 17 is connected to the lead terminal 4 on the first side wall 10A side and a first input pad 13 of the controller IC 6. The second conductive wire 18 is connected to the low potential terminal 11 of the semiconductor device 5 and a first output pad 14 of the controller IC 6. The third conductive wire 19 is connected to the high potential terminal 12 of the semiconductor device 5 and a second input pad 15 of the driver IC 7. The fourth conductive wire 20 is connected to the second output pad 16 of the driver IC 7 and the lead terminal 4 on the second side wall 10B side.

[0028] Fig. 2 is a diagram for explaining the operation of the semiconductor module 1 shown in Fig. 1. Fig. 3 is a voltage waveform diagram used in the explanation of Fig. 2.

[0029] 2, semiconductor device 5 includes transformer 21. Transformer 21 includes a primary-side low potential coil 22 (low potential conductor pattern) and a secondary-side high potential coil 23 (high potential conductor pattern) that face each other in the vertical direction. High potential coil 23 is disposed above low potential coil 22 and faces low potential coil 22.

[0030] The high potential coil 23 is AC-connected to the low potential coil 22 by magnetic coupling, and at the same time is DC-insulated from the low potential coil 22. In other words, the driver IC 7 is AC-connected to the controller IC 6 via the semiconductor device 5, and at the same time is DC-insulated from the controller IC 6 by the semiconductor device 5.

[0031] The low potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 wound in a spiral shape between the first inner end 24 and the first outer end 25. The high potential coil 23 includes a second inner end 27, a second outer end 28, and a second helical portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28.

[0032] The semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34. The first low potential wiring 31 connects the first inner end 24 of the low potential coil 22 to the corresponding low potential terminal 11. The second low potential wiring 32 connects the first outer end 25 of the low potential coil 22 to the corresponding low potential terminal 11. The first high potential wiring 33 connects the second inner end 27 of the high potential coil 23 to the corresponding high potential terminal 12. The second high potential wiring 34 connects the second outer end 28 of the high potential coil 23 to the corresponding high potential terminal 12.

[0033] The controller IC6 includes a first wiring 35 and a second wiring 36. The first wiring 35 is connected to the corresponding first input pad 13 and the first output pad 14. The second wiring 36 is connected to the corresponding first input pad 13 and the first output pad 14. The controller IC6 further includes a first switching device Sw1 and a second switching device Sw2. The first switching device Sw1 and the second switching device Sw2 are each formed of a transistor.

[0034] The first switching device Sw1 is disposed in the first wiring 35. The first switching device Sw1 controls the conduction and interruption of an electrical signal transmitted to the first wiring 35. The second switching device Sw2 is disposed in the second wiring 36. The second switching device Sw2 controls the conduction and interruption of an electrical signal transmitted to the second wiring 36.

[0035] The first input pad 13 on the first wiring 35 side is connected to ground via a first conducting wire 17. The first output pad 14 on the first wiring 35 side is electrically connected to the low potential terminal 11 on the first inner end 24 side via a second conducting wire 18. The first input pad 13 on the second wiring 36 side is electrically connected to a power supply 37 via the first conducting wire 17. The power supply 37 applies a voltage of, for example, 5V to the controller IC 6. The first output pad 14 on the second wiring 36 side is electrically connected to the low potential terminal 11 on the first outer end 25 side via the second conducting wire 18.

[0036] The driver IC 7 is electrically connected to the semiconductor device 5 via a plurality of third conducting wires 19. Specifically, the second input pad 15 of the driver IC 7 is electrically connected to the high potential terminal 12 on the second inner end 27 side via the third conducting wires 19. In addition, the second input pad 15 of the driver IC 7 is electrically connected to the high potential terminal 12 on the second outer end 28 side via the third conducting wires 19.

[0037] A reference voltage power supply 38, a power supply 39, and a SiC-MISFET (Metal Insulator Semiconductor field Effect Transistor) as an example of a load are connected to the driver IC7. The reference voltage power supply 38 applies a reference voltage of, for example, 1200V to the driver IC7. This reference voltage is also applied to the high potential coil 23 via the driver IC7. The power supply 39 applies a voltage of, for example, 15V to the driver IC7. The driver IC7 drives and controls the SiC-MISFET with 1200V as the reference voltage.

[0038] 3, the controller IC6 controls the on / off of the first switching device Sw1 and the second switching device Sw2 in a predetermined switching pattern to generate a pulse signal PS. In this example, the predetermined switching pattern includes a first application state (Sw1 on, Sw2 off) and a second application state (Sw1 off, Sw2 on). FIG. 3 shows an example in which a 5V pulse signal PS based on 0V (ground potential) is generated.

[0039] The pulse signal PS generated by the controller IC6 is input to the semiconductor device 5. The semiconductor device 5 transmits the pulse signal PS from the low potential coil 22 to the high potential coil 23. As a result, the pulse signal PS is boosted by an amount corresponding to the winding ratio (transformation ratio) of the low potential coil 22 and the high potential coil 23. Fig. 3 shows an example in which the pulse signal PS is boosted to 15V.

[0040] The boosted pulse signal PS is input to the driver IC7. The driver IC7 generates an electric signal according to the boosted pulse signal PS and drives and controls the SiC-MISFET. The values ​​shown in Figures 2 and 3 are merely examples. For example, the reference voltage on the secondary side (high potential side) may be 500V or more and 4000V or less.

[0041] FIG. 4 is a perspective view showing the semiconductor device 5 shown in FIG. 1. FIG. 5 is a plan view of the semiconductor device 5 shown in FIG. 4. FIG. 6 is a plan view showing a layer in which the low potential coil 22 is formed in the semiconductor device 5 shown in FIG. 4. FIG. 7 is a plan view showing a layer in which the high potential coil 23 is formed in the semiconductor device 5 shown in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 7. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 7. FIG. 10 is an enlarged view of region X shown in FIG. 7. FIG. 11 is an enlarged view of region XI shown in FIG. 7. FIG. 12 is an enlarged view of region XII shown in FIG. 7. FIG. 13 is an enlarged view of region XIII shown in FIG. 8, showing an isolation structure 130 according to the first embodiment.

[0042] 4 to 8, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide band gap semiconductor, and a compound semiconductor.

[0043] The wide band gap semiconductor is made of a semiconductor whose band gap exceeds that of silicon (about 1.12 eV). The band gap of the wide band gap semiconductor is preferably 2.0 eV or more. The wide band gap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride) and GaAs (gallium arsenide).

[0044] In this embodiment, the semiconductor chip 41 includes a semiconductor substrate made of silicon. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a semiconductor substrate made of silicon and an epitaxial layer made of silicon. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0045] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0046] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0047] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface in a plan view. The insulating main surface 52 extends parallel to the first main surface .

[0048] The insulating side walls 53A-53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A-53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A-44D. Specifically, the insulating side walls 53A-53D are formed flush with the chip side walls 44A-44D. The insulating side walls 53A-53D form ground surfaces flush with the chip side walls 44A-44D.

[0049] The insulating layer 51 has a multi-layer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 layers in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0050] Each of the interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the lowermost insulating layer 55 side and a second insulating layer 59 on the uppermost insulating layer 56 side. The first insulating layer 58 may include silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0051] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0052] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of layers of the interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be realized. In addition, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0053] The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21. In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51 at intervals from the insulating sidewalls 53A-53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0054] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side to the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. In the following, the structure of the first transformer 21A will be described as an example. The structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D are omitted because the description of the structure of the first transformer 21A applies mutatis mutandis.

[0055] 6 to 9, the first transformer 21A includes a low potential coil 22 and a high potential coil 23. The low potential coil 22 is formed in an insulating layer 51. The high potential coil 23 is formed in the insulating layer 51 so as to face the low potential coil 22 in the normal direction Z. In this embodiment, the low potential coil 22 and the high potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0056] The low potential coil 22 is formed on the lowermost insulating layer 55 (semiconductor chip 41) side within the insulating layer 51, and the high potential coil 23 is formed on the uppermost insulating layer 56 (insulating main surface 52) side of the low potential coil 22 within the insulating layer 51. In other words, the high potential coil 23 faces the semiconductor chip 41 with the low potential coil 22 in between. The low potential coil 22 and the high potential coil 23 may be disposed in any position. Furthermore, it is sufficient that the high potential coil 23 faces the low potential coil 22 with one or more interlayer insulating layers 57 in between.

[0057] The distance between the low potential coil 22 and the high potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is appropriately adjusted according to the dielectric strength and electric field strength between the low potential coil 22 and the high potential coil 23. In this embodiment, the low potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0058] The low potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape extending in an elliptical shape (oval shape) in a plan view. A portion forming the innermost periphery of the first spiral portion 26 defines a first inner region 66 having an elliptical shape in a plan view.

[0059] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0060] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 6 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0061] The low potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low potential coil 22 may have a laminated structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The body layer is embedded in the recess space defined by the barrier layer. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0062] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape extending in an elliptical shape (oval shape) in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0063] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical portion 29 exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26, or may be equal to the number of turns of the first helical portion 26.

[0064] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0065] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0066] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 7 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0067] The high potential coil 23 is preferably formed of the same conductive material as the low potential coil 22. That is, like the low potential coil 22, the high potential coil 23 preferably includes a barrier layer and a body layer.

[0068] 5, the semiconductor device 5 includes a plurality of (12 in this embodiment) low potential terminals 11 and a plurality of (12 in this embodiment) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0069] The low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the low potential terminals 11 are formed in a region on the insulating sidewall 53B side at intervals in the second direction Y from the transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0070] The low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E and a sixth low potential terminal 11F. In this embodiment, two of each of the low potential terminals 11A to 11F are formed. The number of the low potential terminals 11A to 11F is arbitrary.

[0071] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0072] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0073] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0074] The multiple high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the multiple low potential terminals 11. Specifically, the multiple high potential terminals 12 are formed in a region on the insulating sidewall 53A side at intervals from the multiple low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0075] The multiple high potential terminals 12 are formed in areas close to the corresponding transformers 21A to 21D in a plan view. The closeness of the high potential terminals 12 to the transformers 21A to 21D means that the distance between the high potential terminals 12 and the transformers 21 in a plan view is less than the distance between the low potential terminals 11 and the high potential terminals 12.

[0076] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A-21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A-21D in the first direction X in a plan view.

[0077] The multiple high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the multiple high potential terminals 12A to 12F are formed. The number of the multiple high potential terminals 12A to 12F is arbitrary.

[0078] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in a region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in a region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0079] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0080] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0081] 6 to 9, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0082] The first low potential wiring 31 and the second low potential wiring 32 fix the low potential coil 22 of the first transformer 21A and the low potential coil 22 of the second transformer 21B to the same potential. The first low potential wiring 31 and the second low potential wiring 32 also fix the low potential coil 22 of the third transformer 21C and the low potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low potential wiring 31 and the second low potential wiring 32 fix all the low potential coils 22 of the transformers 21A to 21D to the same potential.

[0083] The first high potential wiring 33 and the second high potential wiring 34 fix the high potential coil 23 of the first transformer 21A and the high potential coil 23 of the second transformer 21B to the same potential. The first high potential wiring 33 and the second high potential wiring 34 also fix the high potential coil 23 of the third transformer 21C and the high potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high potential wiring 33 and the second high potential wiring 34 fix all the high potential coils 23 of the transformers 21A to 21D to the same potential.

[0084] The multiple first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The multiple first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The structure of the other first low potential wirings 31 will be omitted, as the description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis.

[0085] The first low potential wiring 31 includes a through wiring 71, a low potential connection wiring 72, a pull-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0086] The through wiring 71, the low potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low potential coil 22, etc. In other words, the through wiring 71, the low potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably each include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0087] The through wiring 71 penetrates the interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape extending along the normal direction Z. In this embodiment, the through wiring 71 is formed in a region between the lowermost insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low potential coil 22.

[0088] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 are each formed of the same conductive material as the low potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 each include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0089] The first electrode layer 78 forms an upper end of the through wiring 71. The second electrode layer 79 forms a lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0090] The multiple wiring plug electrodes 80 are embedded in the multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to each other, and electrically connect the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 each have a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0091] The number of layers of the multiple wiring plug electrodes 80 matches the number of layers of the multiple interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 penetrating the multiple interlayer insulating layers 57 may be formed.

[0092] The low potential connecting wire 72 is formed in the first inner region 66 of the first transformer 21A (low potential coil 22) in the same interlayer insulating layer 57 as the low potential coil 22. The low potential connecting wire 72 is formed in an island shape and faces the high potential terminal 12 (first high potential terminal 12A) in the normal direction Z. It is preferable that the low potential connecting wire 72 has a planar area larger than the planar area of ​​the wiring plug electrode 80. The low potential connecting wire 72 is electrically connected to the first inner end 24 of the low potential coil 22.

[0093] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the lowermost insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in a region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in a region between the semiconductor chip 41 and the low potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0094] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0095] The multiple pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The multiple substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0096] 9, the second low potential wirings 32 are electrically connected to the corresponding low potential terminals 11E, 11F and the first outer ends 25 of the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The second low potential wirings 32 each have a similar structure. In the following, the structure of the second low potential wiring 32 connected to the fifth low potential terminal 11E and the first transformer 21A (second transformer 21B) will be described as an example. The structure of the other second low potential wirings 32 will be omitted, since the description of the structure of the second low potential wiring 32 connected to the first transformer 21A (second transformer 21B) applies mutatis mutandis.

[0097] Like the first low potential wiring 31, the second low potential wiring 32 includes a through wiring 71, a low potential connecting wiring 72, a lead-out wiring 73, a first connecting plug electrode 74, a second connecting plug electrode 75, a pad plug electrode 76, and a substrate plug electrode 77. The second low potential wiring 32 has a similar structure to the first low potential wiring 31, except that the low potential connecting wiring 72 is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22).

[0098] The low potential connection wiring 72 of the second low potential wiring 32 is formed around the low potential coil 22 in the same interlayer insulating layer 57 as the low potential coil 22. Specifically, the low potential connection wiring 72 is formed in a region between two adjacent low potential coils 22 in a plan view. The pad plug electrode 76 is formed in a region between the low potential terminal 11 (fifth low potential terminal 11E) and the low potential connection wiring 72 in the uppermost insulating layer 56, and is electrically connected to the low potential terminal 11 and the low potential connection wiring 72.

[0099] 8, the multiple first high potential wirings 33 are electrically connected to the corresponding high potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high potential coils 23). The multiple first high potential wirings 33 each have a similar structure. In the following, the structure of the first high potential wiring 33 connected to the first high potential terminal 12A and the first transformer 21A will be described as an example. The structure of the other first high potential wirings 33 will be omitted, since the description of the structure of the first high potential wiring 33 connected to the first transformer 21A applies mutatis mutandis.

[0100] The first high potential wiring 33 includes a high potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high potential connection wiring 81 and the pad plug electrode 82 are preferably formed of the same conductive material as the low potential coil 22, etc. In other words, the high potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0101] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 in the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at a distance from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. This increases the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81, and increases the dielectric strength voltage of the insulating layer 51.

[0102] The multiple pad plug electrodes 82 are formed in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81 in the uppermost insulating layer 56, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. Each of the multiple pad plug electrodes 82 has a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0103] 9, the second high potential wirings 34 are electrically connected to the corresponding high potential terminals 12E, 12F and the second outer ends 28 of the corresponding transformers 21A to 21D (high potential coils 23), respectively. The second high potential wirings 34 each have a similar structure. In the following, the structure of the second high potential wiring 34 connected to the fifth high potential terminal 12E and the first transformer 21A (second transformer 21B) will be described as an example. The structure of the other second high potential wirings 34 will be omitted, since the description of the structure of the second high potential wiring 34 connected to the first transformer 21A (second transformer 21B) applies mutatis mutandis.

[0104] The second high potential wiring 34, like the first high potential wiring 33, includes a high potential connecting wiring 81 and a pad plug electrode 82. The second high potential wiring 34 has a similar structure to the first high potential wiring 33, except that the high potential connecting wiring 81 is electrically connected to the second outer terminal 28 of the first transformer 21A (high potential coil 23) and the second outer terminal 28 of the second transformer 21B (high potential coil 23).

[0105] The high-potential connection wiring 81 of the second high-potential wiring 34 is formed around the high-potential coil 23 in the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in a region between two adjacent high-potential coils 23 in a plan view and faces the high-potential terminal 12 (fifth high-potential terminal 12E) in the normal direction Z. The high-potential connection wiring 81 is formed spaced apart from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z.

[0106] A plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (fifth high potential terminal 12E) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81, respectively.

[0107] Referring to FIGS. 8 and 9, the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the withstand voltage insulation to be achieved.

[0108] Referring to FIGS. 7 to 12, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. In FIGS. 10 to 12, the dummy pattern 85 is indicated by hatching. The dummy pattern 85 includes a conductor. The dummy pattern 85 is preferably formed of the same conductive material as the low potential coil 22 or the like. That is, the dummy pattern 85 preferably includes a barrier layer and a main body layer, similar to the low potential coil 22 or the like.

[0109] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high potential coil 23 and the low potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high potential coil 23.

[0110] In this embodiment, the dummy pattern 85 is routed in dense lines so as to partially cover and partially expose the area surrounding one or more high potential coils 23 in a plan view. In this embodiment, the dummy pattern 85 is routed at a line density per unit area equal to the line density of the high potential coil 23. The line density of the dummy pattern 85 being equal to the line density of the high potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high potential coil 23.

[0111] The dummy pattern 85 is preferably formed in a region closer to the high potential coil 23 than the low potential terminal 11 in a plan view. The dummy pattern 85 being closer to the high potential coil 23 in a plan view means that the distance between the dummy pattern 85 and the high potential coil 23 is less than the distance between the dummy pattern 85 and the low potential terminal 11.

[0112] The depth position of the dummy pattern 85 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high potential coil 23 than the low potential coil 22 in the normal direction Z. The dummy pattern 85 being closer to the high potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low potential coil 22.

[0113] In this case, it is possible to appropriately suppress electric field concentration on the high potential coil 23. The smaller the distance between the dummy pattern 85 and the high potential coil 23 in the normal direction Z, the more the electric field concentration on the high potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high potential coil 23. In this case, it is possible to further appropriately suppress electric field concentration on the high potential coil 23.

[0114] The dummy patterns 85 are preferably formed around the high potential coils 23 so as to be located in the regions between the adjacent high potential coils 23 in a plan view. In this case, undesired electric field concentration on the high potential coils 23 can be suppressed by utilizing the regions between the adjacent high potential coils 23.

[0115] The dummy pattern 85 is preferably interposed in a region between the low potential terminal 11 and the high potential coil 23 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential coil 23 caused by electric field concentration in the high potential coil 23 can be suppressed. The dummy pattern 85 is preferably interposed in a region between the low potential terminal 11 and the high potential terminal 12 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential terminal 12 caused by electric field concentration in the high potential coil 23 can be suppressed.

[0116] In this embodiment, the dummy pattern 85 is formed along the multiple high potential coils 23 in a plan view, and is interposed in a region between adjacent multiple high potential coils 23. Moreover, the dummy pattern 85 collectively surrounds a region including the multiple high potential coils 23 and the multiple high potential terminals 12 in a plan view. Moreover, the dummy pattern 85 is interposed in a region between the multiple low potential terminals 11A to 11F and the multiple high potential coils 23 in a plan view. Moreover, the dummy pattern 85 is interposed in a region between the multiple low potential terminals 11A to 11F and the multiple high potential terminals 12A to 12F in a plan view.

[0117] 7 to 12, dummy pattern 85 includes a plurality of dummy patterns having different electrical states. Dummy pattern 85 includes high-potential dummy pattern 86. High-potential dummy pattern 86 is formed in insulating layer 51 so as to be located around transformers 21A to 21D in plan view. High-potential dummy pattern 86 is formed in a pattern (discontinuous pattern) different from high-potential coil 23 and low-potential coil 22, and is independent of transformers 21A to 21D. In other words, high-potential dummy pattern 86 does not function as transformers 21A to 21D.

[0118] In this embodiment, the high-potential dummy pattern 86 is routed in dense lines so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. In this embodiment, the high-potential dummy pattern 86 is routed at a line density per unit area equal to the line density of the high-potential coil 23. The line density of the high-potential dummy pattern 86 being equal to the line density of the high-potential coil 23 means that the line density of the high-potential dummy pattern 86 falls within a range of ±20% of the line density of the high-potential coil 23.

[0119] The high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D, and suppresses electric field concentration on the high-potential coil 23. Specifically, the high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23, thereby moving the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. This suppresses electric field concentration on the high-potential coil 23 caused by the electric field leaking above the high-potential coil 23.

[0120] A voltage exceeding the voltage applied to the low potential coil 22 is applied to the high potential dummy pattern 86. This makes it possible to suppress the voltage drop between the high potential coil 23 and the high potential dummy pattern 86, thereby suppressing electric field concentration on the high potential coil 23. It is preferable that the voltage applied to the high potential coil 23 is applied to the high potential dummy pattern 86. In other words, it is preferable that the high potential dummy pattern 86 is fixed to the same potential as the high potential coil 23. This makes it possible to reliably suppress the voltage drop between the high potential coil 23 and the high potential dummy pattern 86, thereby making it possible to appropriately suppress electric field concentration on the high potential coil 23.

[0121] The depth position of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0122] In this case, it is possible to appropriately suppress electric field concentration on the high potential coil 23. The smaller the distance between the high potential dummy pattern 86 and the high potential coil 23 in the normal direction Z, the more the electric field concentration on the high potential coil 23 can be suppressed. It is preferable that the high potential dummy pattern 86 is formed in the same interlayer insulating layer 57 as the high potential coil 23. In this case, it is possible to further appropriately suppress electric field concentration on the high potential coil 23.

[0123] The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential terminal 11 in a plan view. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in a plan view means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential terminal 11.

[0124] The high-potential dummy pattern 86 is preferably formed around the multiple high-potential coils 23 so as to be located in the region between the multiple adjacent high-potential coils 23 in a plan view. In this case, undesired electric field concentration on the multiple high-potential coils 23 can be suppressed by utilizing the region between the multiple adjacent high-potential coils 23.

[0125] The high-potential dummy pattern 86 is preferably interposed in a region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, undesired conduction between the low-potential terminal 11 and the high-potential coil 23 caused by electric field concentration in the high-potential coil 23 can be suppressed. The high-potential dummy pattern 86 is preferably interposed in a region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, undesired conduction between the low-potential terminal 11 and the high-potential terminal 12 caused by electric field concentration in the high-potential coil 23 can be suppressed.

[0126] In this embodiment, the high potential dummy pattern 86 is formed along the multiple high potential coils 23 in a plan view, and is interposed in the region between the multiple adjacent high potential coils 23. Moreover, the high potential dummy pattern 86 collectively surrounds the region including the multiple high potential coils 23 and the multiple high potential terminals 12 in a plan view. Moreover, the high potential dummy pattern 86 is interposed in the region between the multiple low potential terminals 11A to 11F and the multiple high potential coils 23 in a plan view. Moreover, the high potential dummy pattern 86 is interposed in the region between the multiple low potential terminals 11A to 11F and the multiple high potential terminals 12A to 12F in a plan view.

[0127] The high potential dummy pattern 86 is routed around the high potential terminals 12E, 12F in a region between adjacent high potential coils 23 in a plan view so as to expose the region directly below the high potential terminals 12E, 12F. A part of the high potential dummy pattern 86 may face the high potential terminals 12A to 12F in the normal direction Z. In this case, the high potential terminals 12E, 12F, like the high potential dummy pattern 86, shield the electric field to suppress the electric field leaking to the upper side of the high potential coil 23. In other words, the high potential terminals 12E, 12F are formed as a shield conductor layer that suppresses the electric field concentration on the high potential coil 23 together with the high potential dummy pattern 86.

[0128] It is preferable that the high potential dummy pattern 86 is formed in a terminated shape. In this case, it is possible to prevent a current loop circuit (closed circuit) from being formed in the high potential dummy pattern 86. This suppresses noise caused by the current flowing through the high potential dummy pattern 86. As a result, it is possible to suppress undesirable electric field concentration caused by noise, and at the same time, it is possible to suppress fluctuations in the electrical characteristics of the transformers 21A to 21D.

[0129] The high potential dummy pattern 86 specifically includes a first high potential dummy pattern 87 and a second high potential dummy pattern 88. The first high potential dummy pattern 87 is formed in a region between the plurality of transformers 21A to 21D (the plurality of high potential coils 23) adjacent to each other in a planar view. The second high potential dummy pattern 88 is formed in a region outside the region between the plurality of transformers 21A to 21D (the plurality of high potential coils 23) adjacent to each other in a planar view.

[0130] Hereinafter, the region between the adjacent first transformer 21A (high potential coil 23) and second transformer 21B (high potential coil 23) is referred to as a first region 89. Moreover, the region between the second transformer 21B (high potential coil 23) and third transformer 21C (high potential coil 23) is referred to as a second region 90. Moreover, the region between the third transformer 21C (high potential coil 23) and fourth transformer 21D (high potential coil 23) is referred to as a third region 91.

[0131] In this embodiment, the first high potential dummy pattern 87 is electrically connected to the high potential terminal 12 (fifth high potential terminal 12E) via the second high potential wiring 34. Specifically, the first high potential dummy pattern 87 includes a first connection portion 92 connected to the second high potential wiring 34. The position of the first connection portion 92 is arbitrary. As a result, the first high potential dummy pattern 87 is fixed to the same potential as the multiple high potential coils 23.

[0132] Specifically, the first high potential dummy pattern 87 includes a first pattern 93 formed in a first region 89, a second pattern 94 formed in a second region 90, and a third pattern 95 formed in a third region 91. As a result, the first high potential dummy pattern 87 suppresses the electric field leaking to the upper side of the high potential coil 23 in the first region 89, the second region 90, and the third region 91, and suppresses electric field concentration on the multiple adjacent high potential coils 23.

[0133] In this embodiment, the first pattern 93, the second pattern 94, and the third pattern 95 are integrally formed and fixed to the same potential. The first pattern 93, the second pattern 94, and the third pattern 95 may be separated as long as they are fixed to the same potential.

[0134] 7 and 10, the first pattern 93 is connected to the second high potential wiring 34 via the first connection portion 92. The first pattern 93 is routed in a dense line shape so as to cover a part of the first region 89 in a plan view. The first pattern 93 is formed in the first region 89 at a distance from the high potential terminal 12 (the fifth high potential terminal 12E) in a plan view, and does not face the high potential terminal 12 in the normal direction Z. The first pattern 93 is also formed at a distance from the low potential connection wiring 72 in a plan view, and does not face the low potential connection wiring 72 in the normal direction Z. This increases the insulation distance between the first pattern 93 and the low potential connection wiring 72, and increases the dielectric strength of the insulating layer 51.

[0135] The first pattern 93 includes a first circumferential line 96, a second circumferential line 97, and a plurality of first intermediate lines 98. The first circumferential line 96 extends in a band shape along the periphery of the high potential coil 23 of the first transformer 21A. In this embodiment, the first circumferential line 96 is formed in a ring shape having an open end in the first region 89 in a plan view. The width of the open end of the first circumferential line 96 is less than the width of the high potential coil 23 along the second direction Y.

[0136] The width of the first circumferential line 96 may be 0.1 μm or more and 5 μm or less. The width of the first circumferential line 96 is preferably 1 μm or more and 3 μm or less. The width of the first circumferential line 96 is defined by the width in a direction perpendicular to the direction in which the first circumferential line 96 extends. The width of the first circumferential line 96 is preferably equal to the width of the high potential coil 23. The width of the first circumferential line 96 being equal to the width of the high potential coil 23 means that the width of the first circumferential line 96 falls within a range of ±20% of the width of the high potential coil 23.

[0137] The first pitch between the first outer circumferential line 96 and the high potential coil 23 (first transformer 21A) may be 0.1 μm or more and 5 μm or less. The first pitch is preferably 1 μm or more and 3 μm or less. The first pitch is preferably equal to the second winding pitch of the high potential coil 23. The first pitch being equal to the first winding pitch means that the first pitch falls within a range of ±20% of the first winding pitch.

[0138] The second circumferential line 97 extends in a band shape along the periphery of the high potential coil 23 of the second transformer 21B. In this embodiment, the second circumferential line 97 is formed in a ring shape having an open end in the first region 89 in a plan view. The width of the open end of the second circumferential line 97 is less than the width of the high potential coil 23 along the second direction Y. The open end of the second circumferential line 97 faces the open end of the first circumferential line 96 along the first direction X.

[0139] The width of the second circumferential line 97 may be 0.1 μm or more and 5 μm or less. The width of the second circumferential line 97 is preferably 1 μm or more and 3 μm or less. The width of the second circumferential line 97 is defined by the width in a direction perpendicular to the direction in which the second circumferential line 97 extends. The width of the second circumferential line 97 is preferably equal to the width of the high potential coil 23. The width of the second circumferential line 97 being equal to the width of the high potential coil 23 means that the width of the second circumferential line 97 falls within a range of ±20% of the width of the high potential coil 23.

[0140] The second pitch between the second outer circumferential line 97 and the high potential coil 23 (second transformer 21B) may be 0.1 μm or more and 5 μm or less. The second pitch is preferably 1 μm or more and 3 μm or less. The second pitch is preferably equal to the second winding pitch of the high potential coil 23. The second pitch being equal to the second winding pitch means that the second pitch falls within a range of ±20% of the second winding pitch.

[0141] The multiple first intermediate lines 98 extend in a band shape in the region between the first circumferential line 96 and the second circumferential line 97 in the first region 89. The multiple first intermediate lines 98 include at least one (in this embodiment, one) first connection line 99 that electrically connects the first circumferential line 96 and the second circumferential line 97.

[0142] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple first intermediate lines 98 include only one first connection line 99. The position of the first connection line 99 is arbitrary. At least one of the multiple first intermediate lines 98 is formed with a slit 100 that interrupts the current loop circuit. The position of the slit 100 is appropriately adjusted depending on the design of the multiple first intermediate lines 98.

[0143] The multiple first intermediate lines 98 are preferably formed in a band shape extending along the opposing direction of the multiple high potential coils 23. In this embodiment, the multiple first intermediate lines 98 are each formed in a band shape extending in the first direction X and are formed at intervals in the second direction Y. The multiple first intermediate lines 98 are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0144] The multiple first intermediate lines 98 specifically include multiple first lead-out portions 101 and multiple second lead-out portions 102. The multiple first lead-out portions 101 are drawn out in stripes from the first periphery line 96 toward the second periphery line 97. The tips of the multiple first lead-out portions 101 are formed at intervals from the first periphery line 96 toward the second periphery line 97.

[0145] The multiple second drawer portions 102 are drawn out in a striped pattern from the second outer periphery line 97 toward the first outer periphery line 96. The tips of the multiple second drawer portions 102 are formed at intervals from the second outer periphery line 97 toward the first outer periphery line 96. In this embodiment, the multiple second drawer portions 102 are formed alternately with the multiple first drawer portions 101 at intervals in the second direction Y in a manner that sandwiches one first drawer portion 101 therebetween.

[0146] The multiple second lead portions 102 may sandwich the multiple first lead portions 101. Also, a group including the multiple second lead portions 102 may be formed adjacent to a group including the multiple first lead portions 101. The slits 100, the multiple first lead portions 101, and the multiple second lead portions 102 suppress the formation of a current loop circuit in the first pattern 93.

[0147] The width of the first intermediate line 98 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the first intermediate line 98 is preferably 1 μm or more and 3 μm or less. The width of the first intermediate line 98 is preferably equal to the width of the high potential coil 23. The width of the first intermediate line 98 being equal to the width of the high potential coil 23 means that the width of the first intermediate line 98 falls within a range of ±20% of the width of the high potential coil 23.

[0148] The third pitch between two adjacent first intermediate lines 98 may be 0.1 μm or more and 5 μm or less. The third pitch is preferably 1 μm or more and 3 μm or less. The third pitch is defined by the distance between adjacent first intermediate lines 98 in the second direction Y. The third pitches are preferably equal to each other. The third pitch being equal to each other means that the third pitch falls within a range of ±20% of the third pitch. The third pitch is preferably equal to the second winding pitch of the high potential coil 23. The third pitch being equal to the second winding pitch means that the third pitch falls within a range of ±20% of the second winding pitch.

[0149] 7 and 11, the second pattern 94 is electrically connected to the high potential terminal 12 via the first high potential wiring 33. In this embodiment, the second pattern 94 is electrically connected to the second high potential wiring 34 (the fifth high potential terminal 12E) via the second peripheral line 97 of the first pattern 93. The second pattern 94 is routed in a dense line shape so as to cover the second region 90.

[0150] The second pattern 94 includes the second circumferential line 97, the third circumferential line 103, and a plurality of second intermediate lines 104. The third circumferential line 103 extends in a band shape along the periphery of the high potential coil 23 of the third transformer 21C. In this embodiment, the third circumferential line 103 is formed in a ring shape having an open end in the third region 91 in a plan view. The width of the open end of the third circumferential line 103 is less than the width of the high potential coil 23 of the third transformer 21C along the second direction Y.

[0151] The width of the third circumferential line 103 may be 0.1 μm or more and 5 μm or less. The width of the third circumferential line 103 is preferably 1 μm or more and 3 μm or less. The width of the third circumferential line 103 is defined by the width in a direction perpendicular to the direction in which the third circumferential line 103 extends. The width of the third circumferential line 103 is preferably equal to the width of the high potential coil 23. The width of the third circumferential line 103 being equal to the width of the high potential coil 23 means that the width of the third circumferential line 103 falls within a range of ±20% of the width of the high potential coil 23.

[0152] The fourth pitch between the third outer circumferential line 103 and the high potential coil 23 (third transformer 21C) may be 0.1 μm or more and 5 μm or less. The fourth pitch is preferably 1 μm or more and 3 μm or less. The fourth pitch is preferably equal to the second winding pitch of the high potential coil 23. The fourth pitch being equal to the second winding pitch means that the fourth pitch falls within a range of ±20% of the second winding pitch.

[0153] The multiple second intermediate lines 104 extend in a band shape in the region between the second circumferential line 97 and the third circumferential line 103 in the second region 90. The multiple second intermediate lines 104 include at least one (in this embodiment, one) second connection line 105 that electrically connects the second circumferential line 97 and the third circumferential line 103.

[0154] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple second intermediate lines 104 include only one second connection line 105. The second connection line 105 may have a width greater than the width of the other second intermediate lines 104. The position of the second connection line 105 is arbitrary. At least one of the multiple second intermediate lines 104 has a slit 106 formed therein to interrupt the current loop circuit. The position of the slit 106 is adjusted as appropriate depending on the design of the multiple second intermediate lines 104.

[0155] The second intermediate lines 104 are preferably formed in a band shape extending along the opposing direction of the high potential coils 23. In this embodiment, the second intermediate lines 104 are each formed in a band shape extending in the first direction X and are formed at intervals in the second direction Y. The second intermediate lines 104 are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0156] The second intermediate lines 104 specifically include a plurality of third lead-out portions 107 and a plurality of fourth lead-out portions 108. The third lead-out portions 107 are drawn out in stripes from the second periphery line 97 toward the third periphery line 103. The tips of the third lead-out portions 107 are formed at intervals from the third periphery line 103 toward the second periphery line 97.

[0157] The multiple fourth drawer portions 108 are drawn out in stripes from the third periphery line 103 toward the second periphery line 97. The tips of the multiple fourth drawer portions 108 are formed at intervals from the second periphery line 97 toward the third periphery line 103. In this embodiment, the multiple fourth drawer portions 108 are formed alternately with the multiple third drawer portions 107 at intervals in the second direction Y in a manner that sandwiches one third drawer portion 107 therebetween.

[0158] The plurality of fourth lead portions 108 may sandwich the plurality of third lead portions 107. Also, a group including the plurality of fourth lead portions 108 may be formed adjacent to a group including the plurality of third lead portions 107. The slits 106, the plurality of third lead portions 107, and the plurality of fourth lead portions 108 suppress the formation of a current loop circuit in the second pattern 94.

[0159] The width of the second intermediate line 104 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the second intermediate line 104 is preferably 1 μm or more and 3 μm or less. The width of the second intermediate line 104 is preferably equal to the width of the high potential coil 23. The width of the second intermediate line 104 being equal to the width of the high potential coil 23 means that the width of the second intermediate line 104 falls within a range of ±20% of the width of the high potential coil 23.

[0160] The fifth pitch between two adjacent second intermediate lines 104 may be 0.1 μm or more and 5 μm or less. The fifth pitch is preferably 1 μm or more and 3 μm or less. The fifth pitch is defined by the distance between adjacent second intermediate lines 104 in the second direction Y. The fifth pitches are preferably equal to each other. The fifth pitches being equal to each other means that the fifth pitch falls within a range of ±20% of the fifth pitch. The fifth pitch is preferably equal to the second winding pitch of the high potential coil 23. The fifth pitch being equal to the second winding pitch means that the fifth pitch falls within a range of ±20% of the second winding pitch.

[0161] 7 and 12, the third pattern 95 is electrically connected to the second high potential wiring 34. In this embodiment, the third pattern 95 is electrically connected to the second high potential wiring 34 via the second pattern 94 and the first pattern 93. The third pattern 95 is routed in a dense line shape so as to cover a part of the third region 91. The third pattern 95 is formed in the third region 91 at a distance from the high potential terminal 12 (sixth high potential terminal 12F) in a plan view, and does not face the high potential terminal 12 in the normal direction Z.

[0162] The third pattern 95 is formed at a distance from the low potential connecting wiring 72 in a plan view, and does not face the low potential connecting wiring 72 in the normal direction Z. This increases the insulation distance between the third pattern 95 and the low potential connecting wiring 72 in the normal direction Z, and increases the dielectric strength of the insulating layer 51.

[0163] The third pattern 95 includes the third periphery line 103, the fourth periphery line 109, and a plurality of third intermediate lines 110. The fourth periphery line 109 extends in a band shape along the periphery of the high potential coil 23 of the fourth transformer 21D. In this embodiment, the fourth periphery line 109 is formed in a ring shape having an open end in the third region 91 in a plan view. The width of the open end of the fourth periphery line 109 is less than the width of the high potential coil 23 of the fourth transformer 21D along the second direction Y. The open end of the fourth periphery line 109 faces the open end of the third periphery line 103 along the first direction X.

[0164] The width of the fourth circumferential line 109 may be 0.1 μm or more and 5 μm or less. The width of the fourth circumferential line 109 is preferably 1 μm or more and 3 μm or less. The width of the fourth circumferential line 109 is defined by the width in a direction perpendicular to the direction in which the fourth circumferential line 109 extends. The width of the fourth circumferential line 109 is preferably equal to the width of the high potential coil 23. The width of the fourth circumferential line 109 being equal to the width of the high potential coil 23 means that the width of the fourth circumferential line 109 falls within a range of ±20% of the width of the high potential coil 23.

[0165] The sixth pitch between the fourth outer circumferential line 109 and the high potential coil 23 (fourth transformer 21D) may be 0.1 μm or more and 5 μm or less. The sixth pitch is preferably 1 μm or more and 3 μm or less. The sixth pitch is preferably equal to the second winding pitch of the high potential coil 23. The sixth pitch being equal to the second winding pitch means that the sixth pitch falls within a range of ±20% of the second winding pitch.

[0166] The multiple third intermediate lines 110 extend in a band shape in the region between the third circumferential line 103 and the fourth circumferential line 109 in the third region 91. The multiple third intermediate lines 110 include at least one (in this embodiment, one) third connection line 111 that electrically connects the third circumferential line 103 and the fourth circumferential line 109.

[0167] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple third intermediate lines 110 include only one third connection line 111. The position of the third connection line 111 is arbitrary. At least one of the multiple third intermediate lines 110 has a slit 112 that interrupts the current loop circuit. The position of the slit 112 is appropriately adjusted depending on the design of the multiple third intermediate lines 110.

[0168] The multiple third intermediate lines 110 are preferably formed in a band shape extending along the opposing direction of the multiple high potential coils 23. In this embodiment, the multiple third intermediate lines 110 are each formed in a band shape extending in the first direction X, and are formed at intervals in the second direction Y. The multiple third intermediate lines 110 are formed in a stripe shape as a whole in a plan view.

[0169] In this embodiment, the third intermediate lines 110 include a plurality of fifth lead portions 113 and a plurality of sixth lead portions 114. The fifth lead portions 113 are drawn out in stripes from the third periphery line 103 toward the fourth periphery line 109. The tips of the fifth lead portions 113 are formed at intervals from the fourth periphery line 109 toward the third periphery line 103.

[0170] The multiple sixth lead portions 114 are drawn out in a striped pattern from the fourth periphery line 109 toward the third periphery line 103. The tips of the multiple sixth lead portions 114 are formed at intervals from the third periphery line 103 toward the fourth periphery line 109. In this embodiment, the multiple sixth lead portions 114 are formed alternately with the multiple fifth lead portions 113 at intervals in the second direction Y in a manner that sandwiches one fifth lead portion 113 therebetween.

[0171] The plurality of sixth lead portions 114 may sandwich the plurality of fifth lead portions 113. Furthermore, a group including the plurality of sixth lead portions 114 may be formed adjacent to a group including the plurality of fifth lead portions 113. The slits 112, the plurality of fifth lead portions 113, and the plurality of sixth lead portions 114 suppress the formation of a current loop circuit in the third pattern 95.

[0172] The width of the third intermediate line 110 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the third intermediate line 110 is preferably 1 μm or more and 3 μm or less. The width of the third intermediate line 110 is preferably equal to the width of the high potential coil 23. The width of the third intermediate line 110 being equal to the width of the high potential coil 23 means that the width of the third intermediate line 110 falls within a range of ±20% of the width of the high potential coil 23.

[0173] The seventh pitch between two adjacent third intermediate lines 110 may be 0.1 μm or more and 5 μm or less. The seventh pitch is preferably 1 μm or more and 3 μm or less. The seventh pitch is defined by the distance between adjacent third intermediate lines 110 in the second direction Y. The seventh pitches are preferably equal to each other. The seventh pitches being equal to each other means that the seventh pitch falls within a range of ±20% of the seventh pitch. The seventh pitch is preferably equal to the second winding pitch of the high potential coil 23. The seventh pitch being equal to the second winding pitch means that the seventh pitch falls within a range of ±20% of the second winding pitch.

[0174] 7 to 12, in this embodiment, the second high potential dummy pattern 88 is electrically connected to the high potential terminal 12 via the first high potential dummy pattern 87. The second high potential dummy pattern 88 specifically includes a second connection portion 115 connected to the first high potential dummy pattern 87. The position of the second connection portion 115 is arbitrary. As a result, the second high potential dummy pattern 88 is fixed to the same potential as the multiple high potential coils 23.

[0175] The second high potential dummy pattern 88 suppresses the electric field leaking above the high potential coil 23 in the area outside the first area 89, the second area 90, and the third area 91, and suppresses electric field concentration on the multiple high potential coils 23. In this embodiment, the second high potential dummy pattern 88 collectively surrounds the area including the multiple high potential coils 23 and the multiple high potential terminals 12A to 12F in a planar view. In this embodiment, the second high potential dummy pattern 88 is formed in an oval ring shape (elliptical ring shape) in a planar view.

[0176] As a result, the second high potential dummy pattern 88 is interposed in a region between the multiple low potential terminals 11A-11F and the multiple high potential coils 23 in a plan view. The second high potential dummy pattern 88 is also interposed in a region between the multiple low potential terminals 11A-11F and the multiple high potential terminals 12A-12F in a plan view.

[0177] The second high potential dummy pattern 88 includes a plurality of (six in this embodiment) high potential lines 116A, 116B, 116C, 116D, 116E, and 116F. The number of high potential lines is adjusted according to the electric field to be relaxed. The multiple high potential lines 116A to 116F are formed in this order at intervals in a direction away from the multiple high potential coils 23.

[0178] The multiple high potential lines 116A to 116F collectively surround the multiple high potential coils 23 in a planar view. Specifically, the multiple high potential lines 116A to 116F collectively surround an area including the multiple high potential coils 23 and the multiple high potential terminals 12A to 12F in a planar view. In this embodiment, the multiple high potential lines 116A to 116F are formed in an oval ring shape (elliptical ring shape) in a planar view.

[0179] Each of the high potential lines 116A to 116F includes a slit 117 that interrupts a current loop circuit. The position of the slit 117 is appropriately adjusted depending on the design of the high potential lines 116A to 116F.

[0180] The width of the high potential lines 116A to 116F may be 0.1 μm or more and 5 μm or less. The width of the high potential lines 116A to 116F is preferably 1 μm or more and 3 μm or less. The width of the high potential lines 116A to 116F is defined by the width in a direction perpendicular to the direction in which the high potential lines 116A to 116F extend. The width of the high potential lines 116A to 116F is preferably equal to the width of the high potential coil 23. The width of the high potential lines 116A to 116F being equal to the width of the high potential coil 23 means that the width of the high potential lines 116A to 116F falls within a range of ±20% of the width of the high potential coil 23.

[0181] The eighth pitch between two adjacent high potential lines 116A-116F may be 0.1 μm or more and 5 μm or less. The eighth pitch is preferably 1 μm or more and 3 μm or less. The eighth pitches are preferably equal to each other. The eighth pitches being equal to each other means that the eighth pitch falls within a range of ±20% of the eighth pitch.

[0182] The ninth pitch between the adjacent first high potential dummy pattern 87 and second high potential dummy pattern 88 may be 0.1 μm or more and 5 μm or less. The ninth pitch is preferably 1 μm or more and 3 μm or less. The ninth pitch is preferably equal to the second winding pitch of the high potential coil 23. The ninth pitch being equal to the second winding pitch means that the ninth pitch is within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the multiple high potential lines 116A to 116F are arbitrary and are adjusted according to the electric field to be relaxed.

[0183] 7 to 12, dummy pattern 85 includes floating dummy pattern 121 formed in an electrically floating state in insulating layer 51 so as to be located around transformers 21A to 21D in a plan view. Floating dummy pattern 121 is formed in a pattern (discontinuous pattern) different from high potential coil 23 and low potential coil 22, and is independent of transformers 21A to 21D. In other words, floating dummy pattern 121 does not function as transformers 21A to 21D.

[0184] In this embodiment, the floating dummy pattern 121 is laid out in a dense line shape so as to partially cover and partially expose the area around the high potential coil 23 in a plan view. The floating dummy pattern 121 may be formed to have ends or to have no ends.

[0185] The floating dummy pattern 121 is routed at a line density per unit area equal to that of the high potential coil 23. The line density of the floating dummy pattern 121 being equal to that of the high potential coil 23 means that the line density of the floating dummy pattern 121 falls within a range of ±20% of the line density of the high potential coil 23.

[0186] Moreover, the floating dummy pattern 121 is routed at a line density per unit area equal to that of the high potential dummy pattern 86. The line density of the floating dummy pattern 121 being equal to that of the high potential dummy pattern 86 means that the line density of the floating dummy pattern 121 falls within a range of ±20% of the line density of the high potential dummy pattern 86.

[0187] The floating dummy pattern 121 shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D, and suppresses electric field concentration on the high potential coil 23. Specifically, the floating dummy pattern 121 disperses the electric field leaking above the high potential coil 23 in a direction away from the high potential coil 23. This makes it possible to suppress electric field concentration on the high potential coil 23.

[0188] Furthermore, the floating dummy pattern 121 disperses the electric field leaking out above the high-potential dummy pattern 86 around the high-potential dummy pattern 86 in a direction away from the high-potential coil 23 and the high-potential dummy pattern 86. This makes it possible to suppress electric field concentration on the high-potential dummy pattern 86 and, at the same time, to appropriately suppress electric field concentration on the high-potential coil 23.

[0189] The depth position of the floating dummy pattern 121 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The floating dummy pattern 121 is preferably formed in a region closer to the high potential coil 23 than the low potential coil 22 in the normal direction Z. The floating dummy pattern 121 being closer to the high potential coil 23 in the normal direction Z means that the distance between the floating dummy pattern 121 and the high potential coil 23 in the normal direction Z is less than the distance between the floating dummy pattern 121 and the low potential coil 22.

[0190] In this case, it is possible to appropriately suppress electric field concentration on the high potential coil 23. The smaller the distance between the floating dummy pattern 121 and the high potential coil 23 in the normal direction Z, the more the electric field concentration on the high potential coil 23 can be suppressed. It is preferable that the floating dummy pattern 121 is formed in the same interlayer insulating layer 57 as the high potential coil 23. In this case, it is possible to further appropriately suppress electric field concentration on the high potential coil 23.

[0191] The floating dummy pattern 121 is preferably interposed in a region between the low potential terminal 11 and the high potential coil 23 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential coil 23 caused by electric field concentration in the high potential coil 23 can be suppressed. The floating dummy pattern 121 is preferably interposed in a region between the low potential terminal 11 and the high potential terminal 12 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential terminal 12 caused by electric field concentration in the high potential coil 23 can be suppressed.

[0192] In this embodiment, the floating dummy pattern 121 is formed along the multiple high potential coils 23 in a planar view. Specifically, the floating dummy pattern 121 collectively surrounds an area including the multiple high potential coils 23 and the multiple high potential terminals 12 in a planar view. In this embodiment, the floating dummy pattern 121 collectively surrounds an area including the multiple high potential coils 23 and the multiple high potential terminals 12 across the high potential dummy pattern 86 (second high potential dummy pattern 88) in a planar view.

[0193] As a result, the floating dummy pattern 121 is interposed in a region between the plurality of low potential terminals 11A-11F and the plurality of high potential coils 23 in a plan view. The floating dummy pattern 121 is also interposed in a region between the plurality of low potential terminals 11A-11F and the plurality of high potential terminals 12A-12F in a plan view.

[0194] The number of floating lines is arbitrary and is adjusted according to the electric field to be relaxed. In this embodiment, the floating dummy pattern 121 includes a plurality of (six in this embodiment) floating lines 122A, 122B, 122C, 122D, 122E, and 122F. The plurality of floating lines 122A to 122F are formed in this order at intervals in a direction away from the plurality of high potential coils 23.

[0195] The floating lines 122A-122F collectively surround the high potential coils 23 in plan view. More specifically, the floating lines 122A-122F collectively surround an area including the high potential coils 23 and the high potential terminals 12A-12F across the high potential dummy pattern 86 in plan view. In this embodiment, the floating lines 122A-122F are formed in an oval ring shape in plan view.

[0196] The width of the floating lines 122A-122F may be 0.1 μm or more and 5 μm or less. The width of the floating lines 122A-122F is preferably 1 μm or more and 3 μm or less. The width of the floating lines 122A-122F is defined by the width in a direction perpendicular to the direction in which the floating lines 122A-122F extend.

[0197] The tenth pitch between two adjacent floating lines 122A-122F may be 0.1 μm or more and 5 μm or less. The tenth pitch is preferably 1 μm or more and 3 μm or less. The width of the floating lines 122A-122F is preferably equal to the width of the high potential coil 23. The width of the floating lines 122A-122F being equal to the width of the high potential coil 23 means that the width of the floating lines 122A-122F falls within a range of ±20% of the width of the high potential coil 23.

[0198] The 11th pitch between the floating dummy pattern 121 and the high potential dummy pattern 86 (second high potential dummy pattern 88) may be 0.1 μm or more and 5 μm or less. The 11th pitch is preferably 1 μm or more and 3 μm or less. The 11th pitches are preferably equal to each other. The 11th pitches being equal to each other means that the 11th pitch falls within a range of ±20% of the 11th pitch.

[0199] The 11th pitch is preferably equal to the second winding pitch of the high potential coil 23. The 11th pitch between the floating lines 122A-122F being equal to the second winding pitch means that the 11th pitch falls within a range of ±20% of the second winding pitch. For clarity, Figs. 10-12 show an example in which the 11th pitch exceeds the second winding pitch.

[0200] The 12th pitch between the floating dummy pattern 121 and the high potential dummy pattern 86 is preferably equal to the second winding pitch. The 12th pitch being equal to the second winding pitch means that the 12th pitch is within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the multiple floating lines 122A-122F are adjusted according to the electric field to be relaxed, and are not limited to specific values.

[0201] 8 and 9, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed by utilizing a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (lowermost insulating layer 55). In FIGS. 8 and 9, the second functional device 60 is shown in a simplified manner by a dashed line drawn on the surface layer portion of the first main surface 42.

[0202] The second functional device 60 is electrically connected to the low potential terminal 11 via a low potential wiring, and is electrically connected to the high potential terminal 12 via a high potential wiring. The low potential wiring has a similar structure to the first low potential wiring 31 (second low potential wiring 32) except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high potential wiring has a similar structure to the first high potential wiring 33 (second high potential wiring 34) except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A specific description of the low potential wiring and high potential wiring related to the second functional device 60 will be omitted.

[0203] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more devices of the passive device, the semiconductor rectifier device, and the semiconductor switching device are selectively combined. The circuit network may form a part or the whole of an integrated circuit.

[0204] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifier device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0205] 8 and 9, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 suppresses the intrusion of moisture and cracks from the outer region 63 into the device region 62.

[0206] The device region 62 is a region including the first functional device 45 (multiple transformers 21), the second functional device 60, the multiple low potential terminals 11, the multiple high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0207] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (the multiple transformers 21), the second functional device 60, the multiple low potential terminals 11, the multiple high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path connected to the device region 62.

[0208] The seal conductor 61 is formed in a band shape along the insulating side walls 53 to 53D in a plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in a plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in a plan view.

[0209] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending between the upper end and the lower end in a wall shape. In this embodiment, the upper end of the seal conductor 61 is formed on the semiconductor chip 41 side with a gap therebetween from the insulating principal surface 52, and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed on the upper end side with a gap therebetween from the semiconductor chip 41.

[0210] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the multiple low potential terminals 11 and the multiple high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (multiple transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0211] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or a plurality (a plurality in this embodiment) of seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed of the same conductive material as the low potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0212] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 matches the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0213] As long as one annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture or cracks entering the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless shape (annular shape).

[0214] The multiple seal via conductors 65 are formed in the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the seal plug conductor 64. The multiple seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or greater than the planar area of ​​the seal plug conductor 64.

[0215] The width of the sealing conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the sealing conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the sealing conductor 61 is defined by the width in a direction perpendicular to the direction in which the sealing conductor 61 extends.

[0216] 8, 9 and 13, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 to electrically isolate the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0217] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0218] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion in which the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0219] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body portion 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0220] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. Specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 with a gap therebetween from the chip sidewalls 44A to 44D.

[0221] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 may be a field insulating film 131 or may have various forms as shown in FIGS. 14A to 14D.

[0222] Fig. 14A is an enlarged view of a region XIII shown in Fig. 8, showing an isolation structure 130 according to a second embodiment. With reference to Fig. 14A, the isolation structure 130 may have a laminated structure including an insulating film 133 formed on the first main surface 42 and a conductive film 134 formed on the insulating film 133. In this case, either or both of the insulating film 133 and the conductive film 134 may be exposed from the chip sidewalls 44A to 44D.

[0223] The insulating film 133 may contain silicon oxide or silicon nitride. The insulating film 133 may be a field insulating film 131. The insulating film 133 may have a thickness of 0.1 μm or more and 5 μm or less. The conductor film 134 contains polysilicon or metal, and is formed in an electrically floating state. The conductor film 134 may have a thickness of 0.1 μm or more and 5 μm or less. A connection portion 132 with the seal conductor 61 is formed in the conductor film 134.

[0224] Fig. 14B is an enlarged view of a region XIII shown in Fig. 8, showing an isolation structure 130 according to a third embodiment. Referring to Fig. 14B, the isolation structure 130 includes a trench 135 formed in the first main surface 42, and a buried body 136 buried in the trench 135. In this case, the trench 135 and the buried body 136 are exposed from the chip side walls 44A to 44D. The buried body 136 is buried in the trench 135 so as to be electrically isolated from the semiconductor chip 41. Specifically, the buried body 136 is buried in the trench 135 so as to be in an electrically floating state.

[0225] In this embodiment, the buried body 136 is made of an insulator 137. That is, the isolation structure 130 is made of a trench insulation structure. The trench insulation structure may be a shallow trench isolation (STI). The depth of the trench 135 may be 0.1 μm or more and 5 μm or less. The buried body 136 may contain silicon oxide or silicon nitride. The buried body 136 may have a main surface that protrudes upward from the first main surface 42. The buried body 136 may have a main surface that is located closer to the bottom wall of the trench 135 than the first main surface 42. The buried body 136 may have a main surface that is continuous with the first main surface 42. The connection portion 132 with the seal conductor 61 is formed in the buried body 136.

[0226] Fig. 14C is an enlarged view of a region XIII shown in Fig. 8, showing an isolation structure 130 according to a fourth embodiment. Referring to Fig. 14C, the isolation structure 130 includes a trench 135 formed in the first main surface 42, and a buried body 136 buried in the trench 135. In this case, the trench 135 and the buried body 136 are exposed from the chip side walls 44A to 44D. The buried body 136 is buried in the trench 135 so as to be electrically isolated from the semiconductor chip 41. Specifically, the buried body 136 is buried in the trench 135 so as to be in an electrically floating state.

[0227] In this embodiment, the buried body 136 includes an insulating film 138 formed on the wall surface of the trench 135, and a conductor 139 buried in the trench 135 with the insulating film 138 sandwiched therebetween. The conductor 139 is electrically insulated from the semiconductor chip 41 by the insulating film 138, and is buried in an electrically floating state. That is, the isolation structure 130 is made of a trench insulating structure. The trench insulating structure may be an STI.

[0228] The depth of the trench 135 may be 0.1 μm or more and 5 μm or less. The insulating film 138 may include silicon oxide or silicon nitride. The thickness of the insulating film 138 may be 0.1 μm or more and 2 μm or less. The conductor 139 includes polysilicon or metal, and is buried in an electrically floating state. The conductor 139 may have a main surface that protrudes upward from the first main surface 42. The conductor 139 may have a main surface that is located closer to the bottom wall side of the trench 135 than the first main surface 42. The conductor 139 may have a main surface that is continuous with the first main surface 42. The connection portion 132 with the seal conductor 61 is formed in the conductor 139.

[0229] FIG. 14D is an enlarged view of an area XIII shown in FIG. 8, showing an isolation structure 130 according to a fifth embodiment. Referring to FIG. 14D, the isolation structure 130 is made of a part of the insulating layer 51. The isolation structure 130 may include a bottom insulating layer 55 and one or more interlayer insulating layers 57. In this embodiment, the isolation structure 130 is made of the bottom insulating layer 55. In this embodiment, the seal conductor 61 does not have a seal via conductor 65, and has a lower end portion made of a seal plug conductor 64. The connection portion 132 of the isolation structure 130 is made of a connection portion between the insulating layer 51 (bottom insulating layer 55) and the lower end portion of the seal conductor 61 (seal plug conductor 64).

[0230] 8 and 9, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0231] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may include silicon oxide. The first inorganic insulating layer 141 preferably includes USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may include silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high potential coil 23 can be increased.

[0232] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of the USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0233] The first inorganic insulating layer 141 may contain at least one of BPSG (boron doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron and phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0234] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the high potential terminal 12.

[0235] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0236] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low potential coil 22 and the high potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. According to these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high potential coil 23.

[0237] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0238] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high potential terminal openings 149 that expose the plurality of high potential terminals 12 (high potential pad openings 144). The second portion 147 may have an overlap portion that rises onto the periphery (overlap portion) of the high potential pad opening 144.

[0239] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the multiple high potential coils 23, the multiple high potential terminals 12, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121.

[0240] If the organic insulating layer 145 is not formed, the filler contained in the package body 2 (mold resin) may cause damage to the multiple high potential coils 23, the multiple high potential terminals 12, the seal conductor 61, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121. This type of damage is called a filler attack.

[0241] The organic insulating layer 145 protects the multiple high potential coils 23, the multiple high potential terminals 12, the seal conductor 61, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121 from the filler contained in the package body 2 (molded resin). The slit between the first portion 146 and the second portion 147 functions as an anchor portion for the package body 2 (molded resin).

[0242] A part of the package body 2 (molded resin) enters the slit between the first portion 146 and the second portion 147 and is connected to the inorganic insulating layer 140. This enhances the adhesion of the package body 2 (molded resin) to the semiconductor device 5. Of course, the first portion 146 and the second portion 147 may be integrally formed. The organic insulating layer 145 may include only one of the first portion 146 and the second portion 147. In this case, however, attention must be paid to filler attack.

[0243] Fig. 15 is a graph showing the average instantaneous dielectric breakdown voltage. In Fig. 15, the vertical axis shows the average instantaneous dielectric breakdown voltage [KV·rms], and the horizontal axis shows the item. The higher the average instantaneous dielectric breakdown voltage, the higher the withstand voltage of the insulating layer 51. Fig. 15 shows a first bar graph G1, a second bar graph G2, a third bar graph G3, and a fourth bar graph G4.

[0244] The first bar graph G1 shows the average instantaneous dielectric breakdown voltage of the semiconductor device 5 according to the first structure. In the semiconductor device 5 according to the first structure, the dummy pattern 85 is not formed. The second bar graph G2 shows the average instantaneous dielectric breakdown voltage of the semiconductor device 5 according to the second structure. In the semiconductor device 5 according to the second structure, the dummy pattern 85 including only the second high potential dummy pattern 88 is formed.

[0245] The third bar graph G3 shows the average instantaneous breakdown voltage of the semiconductor device 5 according to the third structure. In the semiconductor device 5 according to the third structure, a dummy pattern 85 including only the floating dummy pattern 121 and the second high potential dummy pattern 88 is formed. The fourth bar graph G4 shows the average instantaneous breakdown voltage of the semiconductor device 5 according to the fourth structure. In the semiconductor device 5 according to the fourth structure, a dummy pattern 85 including the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121 is formed.

[0246] With reference to the first bar graph G1 and the second bar graph G2, the average instantaneous breakdown voltage increased by 11.2% by forming the second high potential dummy pattern 88. With reference to the second bar graph G2 and the third bar graph G3, the average instantaneous breakdown voltage increased by 13.2% by forming the floating dummy pattern 121 in addition to the second high potential dummy pattern 88.

[0247] With reference to the third bar graph G3 and the fourth bar graph G4, the average instantaneous breakdown voltage increased by 6.2% by forming the first high potential dummy pattern 87 in addition to the second high potential dummy pattern 88 and the floating dummy pattern 121. With reference to the first bar graph G1 and the fourth bar graph G4, the average instantaneous breakdown voltage increased by 13.37% by forming the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121.

[0248] Fig. 16 is a diagram showing equipotential lines (electric field distribution) in the vicinity of the high potential coil 23, which were investigated by simulation. Fig. 16 shows the electric field distribution of the semiconductor device 5 according to the first structure described above. Referring to Fig. 16, in the case of the semiconductor device 5 according to the first structure, the equipotential lines wrap around the upper side of the high potential coil 23 and are concentrated on the periphery of the high potential coil 23. In other words, it can be seen that in the case of the semiconductor device 5 according to the first structure, the electric field is concentrated on the periphery of the high potential coil 23. The average instantaneous breakdown voltage is reduced by this type of electric field concentration.

[0249] Fig. 17 is a diagram showing equipotential lines (electric field distribution) in the vicinity of the first high potential dummy pattern 87 investigated by simulation. Fig. 17 shows the electric field distribution of the semiconductor device 5 according to the above-mentioned fourth structure. Referring to Fig. 17, in the case of the semiconductor device 5 according to the fourth structure, the equipotential lines bypass the high potential coil 23 and the first high potential dummy pattern 87 and leak out above the first high potential dummy pattern 87. That is, in the case of the semiconductor device 5 according to the fourth structure, the electric field is not concentrated in the high potential coil 23. This makes it possible to increase the average instantaneous breakdown voltage.

[0250] Although specific illustration is omitted, the second high potential dummy pattern 88 also has the same effect as the first high potential dummy pattern 87. That is, in the vicinity of the second high potential dummy pattern 88, the equipotential lines bypass the high potential coil 23 and the second high potential dummy pattern 88 and leak out to the upper side of the second high potential dummy pattern 88. This makes it possible to suppress electric field concentration on the high potential coil 23, thereby increasing the average instantaneous breakdown voltage.

[0251] Fig. 18 is a diagram showing the electric field distribution in the vicinity of the floating dummy pattern 121 investigated by simulation. Fig. 18 shows the electric field distribution of the semiconductor device 5 according to the above-mentioned fourth structure. Referring to Fig. 18, in the case of the semiconductor device 5 according to the fourth structure, the equipotential lines leak out from the region between the adjacent floating dummy patterns 121 to the upper side of the high potential coil 23. That is, in the case of the semiconductor device 5 according to the fourth structure, the electric field leaking out to the upper side of the high potential coil 23 is thinned out by the floating dummy pattern 121. This makes it possible to suppress the electric field concentration on the high potential coil 23, thereby making it possible to increase the average instantaneous breakdown voltage.

[0252] Specifically, the equipotential lines leak out from the region between the adjacent floating dummy patterns 121 to the upper side of the high potential dummy pattern 86. That is, in the case of the semiconductor device 5 according to the fourth structure, the electric field leaking out to the upper side of the high potential dummy pattern 86 is thinned out by the floating dummy pattern 121.

[0253] In the dummy pattern 85 including the high-potential dummy pattern 86 and the floating dummy pattern 121, the high-potential dummy pattern 86 moves the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. On the other hand, the floating dummy pattern 121 disperses the electric field leaking above the high-potential dummy pattern 86 in a direction away from the high-potential coil 23 and the high-potential dummy pattern 86 in a region away from the high-potential coil 23. This makes it possible to appropriately suppress electric field concentration on the high-potential coil 23, thereby making it possible to appropriately increase the average instantaneous breakdown voltage.

[0254] In this way, it was found that by forming the dummy pattern 85 including the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121, it is possible to suppress the electric field concentration on the high potential coil 23 and improve the average instantaneous breakdown voltage. In addition, from the results of Figures 16, 17, and 18, it was found that the dummy pattern 85 needs to include at least one of the first high potential dummy pattern 87, the floating dummy pattern 121, and the second high potential dummy pattern 88.

[0255] As described above, the semiconductor device 5 includes the semiconductor chip 41, the insulating layer 51, the first functional device 45, the low potential terminal 11, the high potential terminal 12, and the seal conductor 61. The insulating layer 51 is formed on the first main surface 42 of the semiconductor chip 41. The first functional device 45 is formed in the insulating layer 51. The low potential terminal 11 is formed on the insulating layer 51, and is electrically connected to the first functional device 45.

[0256] The high potential terminal 12 is formed on the insulating layer 51 at a distance from the low potential terminal 11, and is electrically connected to the first functional device 45. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape so as to separate an area including the first functional device 45, the low potential terminal 11, and the high potential terminal 12 from other areas in a plan view, and is electrically isolated from the semiconductor chip 41, the first functional device 45, the low potential terminal 11, and the high potential terminal 12.

[0257] According to this structure, when a voltage is applied to the low potential terminal 11 and the high potential terminal 12, undesired conduction between the high potential terminal 12 and the seal conductor 61 can be suppressed. Also, undesired conduction between the low potential terminal 11 and the seal conductor 61 can be suppressed. Also, undesired conduction between the first functional device 45 and the seal conductor 61 can be suppressed. Therefore, the withstand voltage can be improved.

[0258] In this structure, it is preferable that the sealing conductor 61 is fixed in an electrically floating state. With this structure, it is possible to reliably prevent the sealing conductor 61 from forming a current path. Therefore, undesired conduction of the sealing conductor 61 can be appropriately prevented.

[0259] The seal conductor 61 is preferably embedded in the insulating layer 51 at a distance from the first main surface 42 of the semiconductor chip 41 in the normal direction Z. This structure makes it possible to properly electrically separate the seal conductor 61 from the semiconductor chip 41. Therefore, it is possible to properly suppress conduction between the semiconductor chip 41 and the seal conductor 61.

[0260] It is preferable that the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41 and the seal conductor 61. According to this structure, the isolation structure 130 can appropriately electrically isolate the seal conductor 61 from the semiconductor chip 41.

[0261] The isolation structure 130 may include a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41. The isolation structure 130 may include a trench 135 formed on the first main surface 42, and a buried body 136 buried in the trench 135. The buried body 136 is buried in the trench 135 so as to be electrically isolated from the semiconductor chip 41. Specifically, the buried body 136 is buried in the trench 135 so as to be in an electrically floating state. The isolation structure 130 may be formed by utilizing a part of the insulating layer 51.

[0262] The isolation structure 130 is preferably exposed from the chip sidewalls 44A-44D of the semiconductor chip 41. With this structure, even if the seal conductor 61 is formed shifted toward the chip sidewalls 44A-44D, the isolation structure 130 exposed from the chip sidewalls 44A-44D is formed on the periphery of the first main surface 42, so that the seal conductor 61 can be appropriately connected to the isolation structure 130.

[0263] The insulating side walls 53A to 53D of the insulating layer 51 are preferably continuous with the chip side walls 44A to 44D of the semiconductor chip 41. The insulating layer 51 is further preferably continuous with the outer end portion 130B of the isolation structure 130. With this structure, the insulating layer 51 and the isolation structure 130 can adequately insulate the seal conductor 61.

[0264] The seal conductor 61 is preferably formed in a ring shape in a plan view surrounding the first functional device 45, the low potential terminal 11, and the high potential terminal 12. With this structure, the seal conductor 61 can adequately protect the first functional device 45, the low potential terminal 11, and the high potential terminal 12.

[0265] The semiconductor device 5 includes an inorganic insulating layer 140 that covers the seal conductor 61 on the insulating layer 51. The inorganic insulating layer 140 has a low potential pad opening 143 and a high potential pad opening 144 formed in an area outside the seal conductor 61. The low potential pad opening 143 exposes the low potential terminal 11, and the high potential pad opening 144 exposes the high potential terminal 12. With this structure, the inorganic insulating layer 140 can protect the seal conductor 61 and at the same time, can improve the insulation of the seal conductor 61 from the outside.

[0266] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140 so as to sandwich the inorganic insulating layer 140 and cover the seal conductor 61. According to this structure, the organic insulating layer 145 can protect the seal conductor 61 and, at the same time, can further improve the insulation of the seal conductor 61 from the outside.

[0267] The first functional device 45 may include a transformer 21 (passive device) formed in the insulating layer 51. The transformer 21 includes a low potential coil 22 (low potential pattern) formed in the insulating layer 51, and a high potential coil 23 (high potential pattern) formed in the insulating layer 51 so as to face the low potential coil 22 in the normal direction Z. The high potential coil 23 faces the semiconductor chip 41 with the low potential coil 22 in between. The low potential coil 22 is electrically connected to the low potential terminal 11, and the high potential coil 23 is electrically connected to the high potential terminal 12.

[0268] According to this structure, when a voltage is applied to the transformer 21 via the low potential terminal 11 and the high potential terminal 12, undesired conduction between the high potential terminal 12 and the seal conductor 61 can be suppressed. Also, when a voltage is applied to the transformer 21 via the low potential terminal 11 and the high potential terminal 12, undesired conduction between the low potential terminal 11 and the seal conductor 61 can be suppressed. Also, when a voltage is applied to the transformer 21 via the low potential terminal 11 and the high potential terminal 12, undesired conduction between the transformer 21 and the seal conductor 61 can be suppressed.

[0269] The semiconductor device 5 further includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 covers the second functional device 60. The low potential terminal 11 and the high potential terminal 12 are electrically connected to the second functional device 60. The seal conductor 61 separates an area including the second functional device 60 from other areas in a plan view, and is electrically isolated from the second functional device 60.

[0270] This structure makes it possible to suppress undesired conduction between the second functional device 60 and the seal conductor 61 when a voltage is applied to the low potential terminal 11 and the high potential terminal 12. Therefore, the semiconductor device 5 can achieve an effect between the second functional device 60 and the seal conductor 61 similar to the effect achieved between the first functional device 45 and the seal conductor 61.

[0271] The semiconductor device 5 also includes a dummy pattern 85 formed in the insulating layer 51 so as to be located around the high potential coil 23 in a plan view. The dummy pattern 85 shields the electric field formed between the low potential coil 22 and the high potential coil 23, and suppresses electric field concentration on the high potential coil 23. This suppresses electric field concentration on the high potential coil 23, and improves the dielectric strength voltage (average instantaneous breakdown voltage). Furthermore, the semiconductor device 5 can suppress undesired conduction between the dummy pattern 85 and the seal conductor 61 when a voltage is applied to the low potential terminal 11 and the high potential terminal 12. Therefore, the effect of improving the dielectric strength by the dummy pattern 85 and the seal conductor 61 can be appropriately achieved.

[0272] In this embodiment, the dummy pattern 85 is interposed in the region between the multiple adjacent high potential coils 23 in a plan view. This makes it possible to suppress electric field concentration on the multiple high potential coils 23 by utilizing the region between the multiple adjacent high potential coils 23.

[0273] In this embodiment, the dummy pattern 85 is located in a region between the low potential terminal 11 and the high potential coil 23 in a plan view. This makes it possible to suppress undesired conduction between the low potential terminal 11 and the high potential coil 23 caused by electric field concentration in the high potential coil 23.

[0274] In this embodiment, the dummy pattern 85 is disposed in a region between the low potential terminal 11 and the high potential terminal 12 in a plan view. This makes it possible to suppress undesired conduction between the low potential terminal 11 and the high potential terminal 12 caused by electric field concentration of the high potential coil 23.

[0275] In this embodiment, the dummy pattern 85 is disposed in a region between the sealing conductor 61 and the high potential coil 23 in a plan view. This makes it possible to suppress undesired conduction between the sealing conductor 61 and the high potential coil 23 caused by electric field concentration in the high potential coil 23.

[0276] In this embodiment, the dummy pattern 85 is disposed in a region between the sealing conductor 61 and the high potential terminal 12 in a plan view. This makes it possible to suppress undesired conduction between the sealing conductor 61 and the high potential terminal 12 caused by electric field concentration of the high potential coil 23.

[0277] In this embodiment, the dummy pattern 85 includes a high-potential dummy pattern 86 formed around the high-potential coil 23 in a plan view. The high-potential dummy pattern 86 suppresses the electric field leaking to the upper side of the high-potential coil 23 in the region around the high-potential coil 23. This makes it possible to appropriately suppress electric field concentration on the high-potential coil 23 in the region around the high-potential coil 23.

[0278] The dummy pattern 85 includes a first high-potential dummy pattern 87 that is interposed in a region between adjacent high-potential coils 23 in a plan view. The first high-potential dummy pattern 87 suppresses the electric field leaking to the upper side of the high-potential coils 23 in the region between adjacent high-potential coils 23. This makes it possible to appropriately suppress electric field concentration on the high-potential coils 23 in the region between adjacent high-potential coils 23.

[0279] The dummy pattern 85 also includes a second high-potential dummy pattern 88 located in a region outside the region between adjacent high-potential coils 23 in a plan view. The second high-potential dummy pattern 88 suppresses the electric field leaking to the upper side of the high-potential coils 23 in the region outside the region between adjacent high-potential coils 23. This makes it possible to appropriately suppress electric field concentration on the high-potential coils 23 in the region outside the region between adjacent high-potential coils 23.

[0280] The dummy pattern 85 also includes a floating dummy pattern 121 formed in an electrically floating state around the high-potential coil 23 in a plan view. The floating dummy pattern 121 shields the electric field between the low-potential coil 22 and the high-potential coil 23 so as to disperse the electric field leaking above the high-potential coil 23. This makes it possible to suppress electric field concentration on the high-potential coil 23.

[0281] Furthermore, the floating dummy pattern 121 disperses the electric field leaking to the upper side of the high-potential dummy pattern 86 around the high-potential dummy pattern 86. This makes it possible to suppress electric field concentration on the high-potential dummy pattern 86 and at the same time to appropriately suppress electric field concentration on the high-potential coil 23. In this structure, it is preferable that the sealing conductor 61 is formed in an electrically floating state. In this case, the sealing conductor 61 does not cause a voltage drop between the floating dummy pattern 121 and the sealing conductor 61. Therefore, undesired conduction between the dummy pattern 85 and the sealing conductor 61 can be appropriately suppressed.

[0282] 16, it is preferable that the dummy pattern 85 includes all of the first high potential dummy pattern 87, the floating dummy pattern 121, and the second high potential dummy pattern 88. However, the average instantaneous breakdown voltage can also be improved by using a dummy pattern 85 that includes any one or two of the first high potential dummy pattern 87, the floating dummy pattern 121, and the second high potential dummy pattern 88.

[0283] That is, a dummy pattern 85 having only the first high potential dummy pattern 87 may be adopted. Also, a dummy pattern 85 having only the second high potential dummy pattern 88 may be adopted. Also, a dummy pattern 85 having only the floating dummy pattern 121 may be adopted.

[0284] Also, a dummy pattern 85 having only the first high potential dummy pattern 87 and the second high potential dummy pattern 88 may be employed. Also, a dummy pattern 85 having only the first high potential dummy pattern 87 and the floating dummy pattern 121 may be employed. Also, a dummy pattern 85 having only the second high potential dummy pattern 88 and the floating dummy pattern 121 may be employed.

[0285] In addition, the first high potential dummy pattern 87 may be changed to a floating dummy pattern 121. In addition, the first high potential dummy pattern 87 and the second high potential dummy pattern 88 may be changed to the floating dummy pattern 121.

[0286] Such a floating dummy pattern 121 is formed by separating the first high potential dummy pattern 87 and the second high potential dummy pattern 88 from the high potential connecting wiring 81 (high potential terminals 12A to 12F). Since the floating dummy pattern 121 is formed in an electrically floating state, no voltage drop occurs between the floating dummy pattern 121 and the high potential coil 23. Therefore, the floating dummy pattern 121 can suppress the electric field concentration on the high potential coil 23 while suppressing an increase in the electric field strength between the floating dummy pattern 121 and the high potential coil 23. However, it should be noted that in the case of the floating dummy pattern 121, an electric field leaking out to the upper side of the high potential coil 23 exists.

[0287] Furthermore, the floating dummy pattern 121 may be changed to the second high potential dummy pattern 88. In this case, however, the distance between the low potential terminal 11 (sealing conductor 61) and the second high potential dummy pattern 88 becomes shorter, and as a result, the electric field strength between the low potential terminal 11 (sealing conductor 61) and the second high potential dummy pattern 88 becomes stronger. It should be noted that an increase in the electric field strength may cause undesirable electric field concentration in the high potential coil 23 and the second high potential dummy pattern 88.

[0288] FIG. 19 is a plan view corresponding to FIG. 7, showing a semiconductor device 161 according to a second embodiment of the present invention. FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. 19. In the following, structures corresponding to those described for the semiconductor device 5 are given the same reference numerals, and descriptions thereof will be omitted. FIG. 20 shows an example in which an isolation structure 130 (field insulating film 131) according to the first embodiment is formed (see also FIG. 13). However, in the semiconductor device 161 according to the second embodiment, any one of the isolation structures 130 according to the second to fifth embodiment may be formed instead of the isolation structure 130 according to the first embodiment (see also FIGS. 14A to 14D).

[0289] 19 and 20, the dummy pattern 85 of the semiconductor device 161 further includes a low-potential dummy pattern 162. In Fig. 19, the low-potential dummy pattern 162 is indicated by a thick line. The low-potential dummy pattern 162 is preferably formed of the same conductive material as the low-potential coil 22, etc. In other words, the low-potential dummy pattern 162 preferably includes a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0290] The low-potential dummy pattern 162 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the low-potential dummy pattern 162 does not function as the transformers 21A to 21D. A voltage lower than the voltage applied to the high-potential terminal 12 is applied to the low-potential dummy pattern 162. It is preferable that the voltage applied to the low-potential terminal 11 (i.e., the reference voltage) is applied to the low-potential dummy pattern 162. In other words, it is preferable that the low-potential dummy pattern 162 is fixed to the same potential as the low-potential terminal 11. The low-potential dummy pattern 162 includes a connection portion 163 connected to any second electrode layer 79.

[0291] The low-potential dummy pattern 162 is formed around the low-potential terminal 11 in a plan view. Specifically, the low-potential dummy pattern 162 is formed in a region closer to the low-potential terminal 11 than the high-potential coil 23 (high-potential terminal 12) in a plan view. The low-potential dummy pattern 162 being close to the low-potential terminal 11 in a plan view means that the distance between the low-potential dummy pattern 162 and the low-potential terminal 11 in a plan view is less than the distance between the low-potential dummy pattern 162 and the high-potential coil 23 (high-potential terminal 12).

[0292] The depth position of the low-potential dummy pattern 162 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The low-potential dummy pattern 162 is preferably formed in a region in the insulating layer 51 close to the low-potential terminal 11 with respect to the low-potential coil 22 in the normal direction Z. The low-potential dummy pattern 162 close to the low-potential terminal 11 in the normal direction Z means that the distance between the low-potential dummy pattern 162 and the low-potential terminal 11 in the normal direction Z is less than the distance between the low-potential dummy pattern 162 and the low-potential coil 22. The low-potential dummy pattern 162 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23.

[0293] The low potential dummy pattern 162 is preferably located in a region between the low potential terminal 11 and the high potential coil 23 in a plan view. The low potential dummy pattern 162 is preferably located in a region between the low potential terminal 11 and the high potential terminal 12 in a plan view.

[0294] In this embodiment, the low-potential dummy pattern 162 is routed at a line density per unit area equal to the line density of the high-potential coil 23. The line density of the low-potential dummy pattern 162 being equal to the line density of the high-potential coil 23 means that the line density of the low-potential dummy pattern 162 falls within a range of ±20% of the line density of the high-potential coil 23.

[0295] It is preferable that the low-potential dummy pattern 162 is formed in a terminated shape. This structure can appropriately prevent a current loop circuit from being formed in the low-potential dummy pattern 162. This can suppress noise caused by the current flowing through the low-potential dummy pattern 162, thereby suppressing undesired electric field concentration caused by noise and appropriately suppressing fluctuations in the electrical characteristics of the transformers 21A to 21D.

[0296] In this embodiment, the low potential dummy pattern 162 is formed in a band shape extending in the first direction X. The low potential dummy pattern 162 crosses the plurality of low potential terminals 11A-11F in plan view. As a result, the low potential dummy pattern 162 is interposed in the region between the low potential terminals 11A-11F and the high potential coil 23 in plan view. The low potential dummy pattern 162 is also interposed in the region between the low potential terminals 11A-11F and the high potential terminals 12A-12F in plan view.

[0297] In this embodiment, the low potential dummy pattern 162 includes a plurality of (three in this embodiment) low potential lines 164A, 164B, and 164C. The plurality of low potential lines 164A to 164C are formed at intervals in this order from the low potential terminals 11A to 11F side toward the high potential terminals 12A to 12F side. The plurality of low potential lines 164A to 164C are electrically connected to any of the low potential connection wirings 72.

[0298] The multiple low potential lines 164A to 164C are each formed in a belt shape extending in the first direction X in a plan view. That is, the multiple low potential lines 164A to 164C are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0299] The width of the low potential lines 164A to 164C may be 0.1 μm or more and 5 μm or less. The width of the low potential lines 164A to 164C is preferably 1 μm or more and 3 μm or less. The width of the low potential lines 164A to 164C is defined by the width in a direction perpendicular to the direction in which the low potential lines 164A to 164C extend. The width of the low potential lines 164A to 164C is preferably equal to the width of the high potential coil 23. The width of the low potential lines 164A to 164C being equal to the width of the high potential coil 23 means that the width of the low potential lines 164A to 164C falls within a range of ±20% of the width of the high potential coil 23.

[0300] The 13th pitch between two adjacent low potential lines 164A to 164C may be 0.1 μm or more and 5 μm or less. The 13th pitch is preferably 1 μm or more and 3 μm or less. The 13th pitches are preferably equal to each other. The 13th pitches being equal to each other means that the 13th pitch is within a range of ±20% of the 13th pitch. These structures can suppress bias of the electric field in the insulating layer 51, thereby suppressing undesirable electric field concentration. The number, width and pitch of the low potential lines 164A to 164C are adjusted according to the electric field to be relaxed, and are not limited to specific values.

[0301] The semiconductor device 161 further includes a main surface insulating layer 165 that covers the insulating main surface 52 of the insulating layer 51. The main surface insulating layer 165 collectively covers, on the insulating main surface 52, the low potential terminals 11A-11F, the high potential terminals 12A-12F, the organic insulating layer 145, the inorganic insulating layer 140 (second inorganic insulating layer 142), and the like.

[0302] The main surface insulating layer 165 has a second dielectric breakdown strength BS2 (BS2≦BS1) that is equal to or less than the first dielectric breakdown strength BS1 of the insulating layer 51. Specifically, the second dielectric breakdown strength BS2 is less than the first dielectric breakdown strength BS1 (BS2 <BS1)である。

[0303] Specifically, the insulating layer 51 includes silicon oxide and / or silicon nitride, and has a first dielectric breakdown strength BS1 of 1 MV / cm or more and 15 MV / cm or less. The first dielectric breakdown strength BS1 is preferably 5 MV / cm or more and 15 MV / cm or less. The insulating layer 51 may include an insulating material other than silicon oxide and silicon nitride, so long as it has a first dielectric breakdown strength BS1 of 1 MV / cm or more. Meanwhile, the second dielectric breakdown strength BS2 may be 0.1 MV / cm or more and 1 MV / cm or less. The second dielectric breakdown strength BS2 may be 0.1 MV / cm or more and 0.5 MV / cm or less.

[0304] In this embodiment, the main surface insulating layer 165 is made of a resin layer. The main surface insulating layer 165 may include at least one of an epoxy resin layer, a polyimide resin layer, and a polybenzoxazole resin layer. The main surface insulating layer 165 may be formed of a part of a molded resin. When the main surface insulating layer 165 is formed of a part of a molded resin, the main surface insulating layer 165 may be formed of a part of the package body 2. In other words, the main surface insulating layer 165 may include a portion that covers the insulating main surface 52 of the insulating layer 51 in the package body 2 in a state where the package body 2 is sealed.

[0305] The electric field strength between the low potential terminals 11A to 11F and the high potential dummy pattern 86 is governed by the distance between the low potential dummy pattern 162 and the high potential dummy pattern 86. Therefore, the electric field strength between the low potential terminals 11A to 11F and the high potential dummy pattern 86 in the insulating layer 51 is increased by the low potential dummy pattern 162.

[0306] On the other hand, the electric field strength in the main surface insulating layer 165 decreases due to the increase in the electric field strength in the insulating layer 51. In other words, the low-potential dummy pattern 162 intentionally increases the electric field strength in the insulating layer 51 having a relatively high first dielectric breakdown strength BS1, while at the same time decreasing the electric field strength in the main surface insulating layer 165 having a relatively low second dielectric breakdown strength BS2. This allows the dielectric strength of the main surface insulating layer 165 to be relatively improved.

[0307] As described above, the semiconductor device 161 can achieve the same effects as those described for the semiconductor device 5. The semiconductor device 161 also includes the low-potential dummy pattern 162. This can improve the dielectric strength of the main surface insulating layer 165. The semiconductor device 161 also includes the seal conductor 61, which separates the region including the low-potential dummy pattern 162 from other regions in a plan view, and is electrically separated from the low-potential dummy pattern 162. This structure can suppress undesired conduction between the low-potential dummy pattern 162 and the seal conductor 61 when a voltage is applied to the low-potential terminal 11 and the high-potential terminal 12. This can increase the dielectric strength.

[0308] FIG. 21 is a cross-sectional view of a region corresponding to FIG. 8, showing a semiconductor device 191 according to a third embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 5 are denoted by the same reference numerals, and description thereof will be omitted. FIG. 21 shows an example in which an isolation structure 130 (field insulating film 131) according to the first embodiment is formed (see also FIG. 13). However, in the semiconductor device 191 according to the third embodiment, any one of the isolation structures 130 according to the second to fifth embodiment may be formed instead of the isolation structure 130 according to the first embodiment (see also FIGS. 14A to 14D).

[0309] The semiconductor device 5 according to the first embodiment has a plurality of transformers 21A-21D, each of which has a low potential coil 22 and a high potential coil 23. In contrast, the semiconductor device 191 according to the third embodiment includes a plurality of capacitors 192 instead of the plurality of transformers 21A-21D. The arrangement of the plurality of capacitors 192 is similar to the arrangement of the plurality of transformers 21A-21D. In FIG. 21, only one capacitor 192 is shown.

[0310] The capacitor 192 includes a flat low potential electrode 193 (low potential pattern) and a flat high potential electrode 194 (high potential pattern) instead of the low potential coil 22 and the high potential coil 23. The low potential electrode 193 is electrically connected to the low potential terminal 11 via the first low potential wiring 31. The low potential electrode 193 is electrically connected to the lead-out wiring 73 via the second connection plug electrode 75.

[0311] The low potential electrode 193 may have any planar shape. The low potential electrode 193 may be formed in a polygonal shape such as a triangular shape or a rectangular shape, a circular shape, or an elliptical shape in a planar view. The low potential electrode 193 is electrically connected to the corresponding low potential terminal 11 via the corresponding first low potential wiring 31.

[0312] The high potential electrode 194 faces the low potential electrode 193 in the normal direction Z, and accumulates charge between the high potential electrode 194 and the low potential electrode 193. The high potential electrode 194 is electrically connected to the high potential terminal 12 via the first high potential wiring 33. The high potential electrode 194 is electrically connected to the high potential terminal 12 via a pad plug electrode 82.

[0313] The high potential electrode 194 may have any planar shape. The high potential electrode 194 may be formed in a polygonal shape such as a triangular shape or a rectangular shape, a circular shape, or an elliptical shape in a planar view. The high potential electrode 194 is electrically connected to the corresponding high potential terminal 12 via the corresponding first high potential wiring 33.

[0314] As described above, the semiconductor device 191 can achieve the same effects as those described for the semiconductor device 5. The semiconductor device 191 may include the low-potential dummy pattern 162 according to the second embodiment.

[0315] The present invention can be embodied in other forms.

[0316] In each of the above-described embodiments, the semiconductor device 5, 161, 191 may include an isolation structure 130 having a structure in which at least two of the isolation structures 130 according to the first to fifth embodiment examples are combined in any mode.

[0317] In the above-described embodiments, examples have been described in which the first functional device 45 and the second functional device 60 are formed. However, a configuration may be adopted in which the first functional device 45 is not included and only the second functional device 60 is included. In this case, the dummy pattern 85 may be removed. With this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects associated with the dummy pattern 85).

[0318] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the sealing conductor 61. Also, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the sealing conductor 61.

[0319] In addition, in each of the above-described embodiments, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0320] In addition, in each of the above-described embodiments, an example has been described in which the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required, and may be removed.

[0321] In addition, in each of the above-described embodiments, an example has been described in which the first functional device 45 is a multi-channel type including a plurality of transformers 21. However, a first functional device 45 of a single-channel type including a single transformer 21 may be adopted.

[0322] Examples of features extracted from this specification and the drawings are given below. The following [A1] to [A19] provide a semiconductor device that can improve the breakdown voltage in a structure including a sealing conductor.

[0323] [A1] A semiconductor device comprising: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a functional device formed on at least one of the semiconductor chip and the insulating layer; a low potential terminal formed on the insulating layer and electrically connected to the functional device; a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the functional device; and a seal conductor embedded in the insulating layer in a wall shape so as to separate an area including the functional device, the low potential terminal, and the high potential terminal from other areas in a planar view, and electrically separated from the semiconductor chip, the functional device, the low potential terminal, and the high potential terminal.

[0324] According to this semiconductor device, when a voltage is applied to the low potential terminal and the high potential terminal, undesired conduction between the high potential terminal and the seal conductor can be suppressed. Also, undesired conduction between the low potential terminal and the seal conductor can be suppressed. Also, undesired conduction between the functional device and the seal conductor can be suppressed. Therefore, the withstand voltage can be improved.

[0325] [A2] The semiconductor device according to A1, wherein the sealing conductor is fixed in an electrically floating state.

[0326] [A3] The semiconductor device according to A1 or A2, wherein the sealing conductor is embedded in the insulating layer at a distance from the semiconductor chip in a normal direction to the main surface.

[0327] [A4] The semiconductor device according to any one of A1 to A3, further including an isolation structure interposed between the semiconductor chip and the sealing conductor to electrically isolate the sealing conductor from the semiconductor chip.

[0328] [A5] The semiconductor device according to A4, wherein the isolation structure includes an insulating film formed on the main surface of the semiconductor chip.

[0329] [A6] The semiconductor device according to A4, wherein the isolation structure includes a trench formed in the main surface, and a buried body buried in the trench so as to be electrically isolated from the semiconductor chip.

[0330] [A7] The semiconductor device according to A4, wherein the isolation structure is made of a part of the insulating layer.

[0331] [A8] The semiconductor device according to any one of A4 to A7, wherein the isolation structure is exposed from a sidewall of the semiconductor chip.

[0332] [A9] The semiconductor device according to any one of A1 to A8, wherein the insulating layer has an insulating sidewall continuous with a sidewall of the semiconductor chip.

[0333] [A10] The semiconductor device according to any one of A1 to A9, wherein the sealing conductor is formed in a ring shape surrounding the functional device, the low potential terminal, and the high potential terminal in a plan view.

[0334] [A11] The semiconductor device according to any one of A1 to A10, further comprising an inorganic insulating layer on the insulating layer covering the sealing conductor and having a plurality of pad openings through which the low potential terminal and the high potential terminal are respectively exposed.

[0335] [A12] The semiconductor device according to A11, further comprising an organic insulating layer formed on the inorganic insulating layer so as to sandwich the inorganic insulating layer and cover the seal conductor.

[0336] [A13] A semiconductor device described in any one of A1 to A12, wherein the functional device includes a low potential pattern formed in the insulating layer and a high potential pattern formed in the insulating layer opposite the low potential pattern in a normal direction to the main surface, the low potential terminal being connected to the low potential pattern, and the high potential terminal being electrically connected to the high potential pattern.

[0337] [A14] The semiconductor device according to A13, wherein the high potential pattern faces the semiconductor chip with the low potential pattern interposed therebetween.

[0338] [A15] The semiconductor device according to A13 or A14, wherein the functional device is a transformer including a low potential coil as the low potential pattern and a high potential coil as the high potential pattern.

[0339] [A16] The semiconductor device according to A13 or A14, wherein the functional device is a capacitor including a low potential electrode as the low potential pattern and a high potential electrode as the high potential pattern.

[0340] [A17] The semiconductor device according to any one of A1 to A12, wherein the functional device includes at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device, and is formed on the main surface of the semiconductor chip.

[0341] [A18] The semiconductor device according to any one of A1 to A12, wherein the functional device includes a first functional device formed in the insulating layer and a second functional device formed in the semiconductor chip.

[0342] [A19] A semiconductor device comprising: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a low potential pattern formed in the insulating layer; a high potential pattern formed in the insulating layer so as to face the low potential pattern in a normal direction of the main surface; a dummy pattern formed around the high potential pattern in the insulating layer, including a conductor, and shielding an electric field between the low potential pattern and the high potential pattern; a low potential terminal formed on the insulating layer and electrically connected to the low potential pattern; a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the high potential pattern; and a seal conductor embedded in the insulating layer in a wall shape so as to separate an area including the low potential pattern, the high potential pattern, the dummy pattern, the low potential terminal, and the high potential terminal from other areas in a plan view, and electrically separated from the semiconductor chip, the low potential pattern, the high potential pattern, the dummy pattern, the low potential terminal, and the high potential terminal.

[0343] According to this semiconductor device, when a voltage is applied to the low potential terminal and the high potential terminal, the dummy pattern can suppress electric field concentration on the high potential pattern. Furthermore, according to this semiconductor device, when a voltage is applied to the low potential terminal and the high potential terminal, undesired conduction between the high potential pattern (high potential terminal) and the seal conductor can be suppressed. Also, undesired conduction between the low potential pattern (low potential terminal) and the seal conductor can be suppressed. Also, undesired conduction between the dummy pattern and the seal conductor can be suppressed. Therefore, the withstand voltage can be improved.

[0344] This application corresponds to Japanese Patent Application No. 2019-217565 filed with the Japan Patent Office on November 29, 2019, the entire disclosure of which is incorporated herein by reference. Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as being limited to these specific examples, and the scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0345] 5. Semiconductor Devices 11 Low potential terminal 12 High potential terminal 21 Transformer 22 Low potential coil 23 High potential coil 41 Semiconductor Chip 42 First main surface 44A First chip side wall 44B 2nd chip side wall 44C 3rd chip sidewall 44D 4th chip sidewall 45 First Functional Device 51 Insulating layer 53A First insulating side wall 53B Second insulating side wall 53C 3rd insulating side wall 53D 4th insulating side wall 60 Second Function Device 61 Sealed Conductor 85 Dummy Pattern 130 Separation structure 131 Field Insulation Film 135 Trench 136 Buried Body 140 Inorganic insulating layer 145 Organic Insulating Layer 161 Semiconductor Devices 191 Semiconductor Devices 192 Capacitor 193 Low potential electrode 194 High Potential Electrode

Claims

1. a semiconductor chip having a major surface; an insulating layer formed on the main surface; a functional device formed on at least one of the semiconductor chip and the insulating layer; a low potential terminal formed on the insulating layer and electrically connected to the functional device; a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the functional device; a seal conductor embedded in the insulating layer in a wall shape so as to separate an area including the functional device, the low potential terminal, and the high potential terminal from other areas in a plan view; an isolation structure including an insulating film formed on the main surface of the semiconductor chip, the insulating film being interposed along the seal conductor between the semiconductor chip and the seal conductor and electrically isolating the seal conductor from the semiconductor chip; 13. A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the shield conductor is fixed in an electrically floating state.

3. 3. The semiconductor device according to claim 1, wherein the sealing conductor is embedded in the insulating layer at a distance from the semiconductor chip in a normal direction to the main surface.

4. The semiconductor device according to claim 1 , wherein said isolation structure is made of a part of said insulating layer.

5. 5. The semiconductor device according to claim 1, wherein the isolation structure is exposed from a sidewall of the semiconductor chip.

6. 6. The semiconductor device according to claim 1, wherein the insulating layer has an insulating sidewall continuous with a sidewall of the semiconductor chip.

7. 7. The semiconductor device according to claim 1, wherein the sealing conductor is formed in a ring shape surrounding the functional device, the low potential terminal, and the high potential terminal in a plan view.

8. The semiconductor device according to any one of claims 1 to 7, further comprising an inorganic insulating layer covering the seal conductor on the insulating layer and having a plurality of pad openings exposing the low potential terminal and the high potential terminal, respectively.

9. 9. The semiconductor device according to claim 8, further comprising an organic insulating layer formed on said inorganic insulating layer so as to cover said seal conductor with said inorganic insulating layer sandwiched therebetween.

10. the functional device includes a low potential pattern formed in the insulating layer, and a high potential pattern formed in the insulating layer so as to face the low potential pattern in a normal direction of the main surface, the low potential terminal is connected to the low potential pattern; 10. The semiconductor device according to claim 1, wherein the high potential terminal is electrically connected to the high potential pattern.

11. 11. The semiconductor device according to claim 10, wherein the high potential pattern faces the semiconductor chip with the low potential pattern therebetween.

12. 12. The semiconductor device according to claim 10, wherein the functional device is a transformer including a low potential coil as the low potential pattern and a high potential coil as the high potential pattern.

13. 12. The semiconductor device according to claim 10, wherein the functional device is a capacitor including a low potential electrode as the low potential pattern and a high potential electrode as the high potential pattern.

14. 10. The semiconductor device according to claim 1, wherein the functional device includes at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device, and is formed on the main surface of the semiconductor chip.

15. 10. The semiconductor device according to claim 1, wherein the functional device includes a first functional device formed in the insulating layer, and a second functional device formed in the semiconductor chip.

16. a semiconductor chip having a major surface; an insulating layer formed on the main surface; a low potential pattern formed in the insulating layer; a high potential pattern formed in the insulating layer so as to face the low potential pattern in a normal direction of the main surface; a dummy pattern formed around the high potential pattern in the insulating layer, the dummy pattern including a conductor, and shielding an electric field between the low potential pattern and the high potential pattern; a low potential terminal formed on the insulating layer and electrically connected to the low potential pattern; a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the high potential pattern; a seal conductor embedded in the insulating layer in a wall shape so as to separate an area including the low potential pattern, the high potential pattern, the dummy pattern, the low potential terminal, and the high potential terminal from other areas in a plan view; an isolation structure including an insulating film formed on the main surface of the semiconductor chip, the insulating film being interposed along the seal conductor between the semiconductor chip and the seal conductor and electrically isolating the seal conductor from the semiconductor chip; 13. A semiconductor device comprising:

17. A semiconductor chip having a major surface; an insulating layer formed on the main surface; a functional device formed on at least one of the semiconductor chip and the insulating layer; a low potential terminal formed on the insulating layer and electrically connected to the functional device; a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the functional device; a seal conductor embedded in the insulating layer in a wall shape so as to separate an area including the functional device, the low potential terminal, and the high potential terminal from other areas in a plan view; an isolation structure interposed between the semiconductor chip and the sealing conductor, electrically isolating the sealing conductor from the semiconductor chip, the isolation structure including a trench formed in the main surface and a buried body buried in the trench so as to be electrically isolated from the semiconductor chip; 13. A semiconductor device comprising:

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