Selective passivation contact battery and method for producing same

Abstract

The present invention provides a selective passivation contact cell and a manufacturing method thereof. The selective passivation contact cell includes a substrate, a first silicon oxide layer and a first polycrystalline silicon layer are sequentially stacked on one surface of the substrate, the substrate surface includes a non-metal contact region and at least two metal contact regions, and a second silicon oxide layer and a second polycrystalline silicon layer are sequentially stacked on the surface of the first polycrystalline silicon layer away from the substrate at the metal contact region, and a first electrode is provided on the second polycrystalline silicon layer, and the thickness of the first polycrystalline silicon layer located at the metal contact region is greater than the thickness of the first polycrystalline silicon layer located at the non-metal contact region. The selective passivation contact cell has a simple structure, a simple manufacturing process, and high efficiency by forming a thick polycrystalline silicon layer in the metal contact region to prevent corrosion by metal slurry and a thin polycrystalline silicon layer in the non-metal contact region to reduce light absorption.

Description

[Technical field]

[0001] The present invention relates to the technical field of solar energy cells, and in particular to a selective passivation contact cell and a method for fabricating the same. [Background technology]

[0002] With the continuous development of solar cell technology, solar cell efficiency is already approaching the theoretical limit. N-type i-TOPCon solar cells have been ranked among the highly efficient cells due to their excellent rear passivation contact structure, with an area cell efficiency of 25.8%. The average efficiency of large-area industrial cells has already reached more than 24%.

[0003] CN111540794A discloses a P-type passivation contact solar cell, which is arranged in sequence from the light receiving surface to the backlight surface with a front grid line, a front epitaxial layer, an N-type diffusion layer, a P-type substrate silicon, a back epitaxial layer and a back grid line, the front epitaxial layer includes a front contact passivation layer and a front coating passivation layer, the front contact passivation layer is arranged on the metal area on the front surface of the P-type passivation contact solar cell, the front coating passivation layer is arranged on the non-metal area on the front surface, the front contact passivation layer includes a phosphorus-doped polycrystalline silicon layer and a first silicon dioxide layer in sequence from the light receiving surface to the backlight surface. This invention reduces the recombination speed of the connection point between the metal and the semiconductor, improving the power generation efficiency of the cell, and the metal area only occupies a small part of the entire surface of the solar cell, improving the power generation efficiency of the cell sheet.

[0004] CN209104161U discloses a selective passivation contact solar cell, which includes a silicon sheet and a positive electrode on the surface of the silicon sheet, and a first anti-reflection film layer, a doped polysilicon layer and a passivation tunneling layer are sequentially provided between the positive electrode and the silicon sheet, and the positive electrode contacts the passivation tunneling layer through the first anti-reflection film layer and the doped polysilicon layer. The passivation tunneling layer, the doped polysilicon layer and the first anti-reflection film layer of this utility model are disposed between the positive electrode and the silicon sheet, which effectively exerts a passivation effect without blocking the non-electrode area, thereby reducing the absorption of solar energy by the conventional doped silicon layer and improving the efficiency of the solar cell.

[0005] CN108807565A discloses a passivation contact electrode structure, which includes a doped semiconductor layer deposited on a crystalline silicon substrate and a copper electrode in the doped semiconductor layer, the doped semiconductor layer being either polycrystalline silicon, microcrystalline silicon or microcrystalline silicon carbon alloy, and having a thickness of 5-100 nm. A solar cell includes the passivation contact electrode structure on the back or both sides of a crystalline silicon substrate. The electrode structure passivates the contacts of all metal electrodes, thereby reducing the surface recombination efficiency of photocarriers and achieving a more thorough passivation effect.

[0006] In the prior art solar cell, the polysilicon layer in the passivation contact structure has serious parasitic absorption of light, and the thick polysilicon layer grown on the entire silicon sheet greatly reduces the light utilization rate of the cell and reduces the short circuit current of the cell. How to effectively reduce the recombination between metal and non-metal regions and ensure the light utilization rate of the cell is currently a problem that needs to be solved as soon as possible. Summary of the Invention

[0007] The present invention addresses the deficiencies of the prior art, and aims to provide a selective passivation contact cell and a method for fabricating the same, which has a thick polysilicon layer in the metal contact area to prevent corrosion by metal slurry, and a thin polysilicon layer in the non-metal contact area to reduce light absorption. In addition, a second silicon oxide layer is provided in the middle of the second polysilicon layer to protect the second polysilicon layer, which has the characteristics of simple structure, simple fabrication process, high efficiency, etc.

[0008] To achieve this objective, the present invention adopts the following technical solutions.

[0009] In a first aspect, the present invention provides a selective passivation contact cell comprising a substrate, a first silicon oxide layer and a first polycrystalline silicon layer stacked in sequence on a surface of one side of the substrate, the surface of the substrate comprising a non-metal contact region and at least two metal contact regions, a second silicon oxide layer and a second polycrystalline silicon layer further disposed in sequence on a surface of the first polycrystalline silicon layer away from the substrate at the metal contact region, the second polycrystalline silicon layer being provided with a first electrode, and a thickness of the first polycrystalline silicon layer located at the metal contact region is greater than a thickness of the first polycrystalline silicon layer located at the non-metal contact region.

[0010] The present invention provides a second silicon oxide layer, which can effectively control the etching rate and ensure the uniformity of the etching. The thickness of the first polysilicon layer located in the metal contact area is greater than that of the first polysilicon layer located in the non-metal contact area. The larger thickness of the first polysilicon layer in the metal contact area can effectively prevent the corrosion of metal slurry and increase the voltage and fill factor, while the smaller thickness of the first polysilicon layer in the non-metal contact area can effectively reduce the absorption of light and increase the current. The present invention can effectively improve the photoelectric efficiency of the battery, and has the characteristics of simple structure, simple manufacturing process, high efficiency, etc., effectively reduce the recombination of the metal-non-metal area, ensure the light utilization rate of the battery, and have good manufacturing duplication of the structure.

[0011] In a preferred technical solution of the present invention, the second polysilicon layer presents a grid line structure, and the grid line structure of the first electrode is the same as that of the second polysilicon layer.

[0012] The present invention, by using the second polysilicon layer laid as a gridline structure, matches the gridline structure of the first electrode, further optimizes the selective passivation contact structure, and enhances the light utilization efficiency of the cell.

[0013] As a preferred technical solution of the present invention, the selective passivation contact cell further includes a first passivation layer and a second passivation layer, the first passivation layer being located on the surface of the second polycrystalline silicon layer and on the surface of the first polycrystalline silicon layer in the non-metal contact region, and the second passivation layer being located on the surface of the substrate away from the first silicon oxide layer.

[0014] Preferably, the selective passivation contact cell further comprises a diffusion layer, the diffusion layer being located between the substrate and the first silicon oxide layer or between the substrate and the second passivation layer.

[0015] Preferably, at least two second electrodes are provided on the surface of the substrate away from the first silicon oxide layer. In a preferred technical solution of the present invention, the thickness of the first polycrystalline silicon layer located in the metal contact region is 10 to 450 nm, for example, 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm or 450 nm.

[0016] Preferably, the thickness of the first polycrystalline silicon layer located in the non-metal contact region is 1 to 150 nm, for example, 1, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm or 150 nm, preferably 10 to 25 nm.

[0017] In a preferred technical solution of the present invention, the thickness of the first silicon oxide layer is 0.5 to 5 nm, for example, 0.5 nm, 1.0 nm, 1.5 nm, 2.0 nm, 2.5 nm, 3.0 nm, 3.5 nm, 4.0 nm, 4.5 nm or 5.0 nm.

[0018] Preferably, the second silicon oxide layer has a thickness of 0.5 to 5 nm, for example, 0.5 nm, 1.0 nm, 1.5 nm, 2.0 nm, 2.5 nm, 3.0 nm, 3.5 nm, 4.0 nm, 4.5 nm or 5.0 nm.

[0019] Preferably, the second polycrystalline silicon layer has a thickness of 1 to 300 nm, for example, 1 nm, 30 nm, 60 nm, 90 nm, 120 nm, 150 nm, 180 nm, 210 nm, 240 nm, 270 nm or 300 nm.

[0020] In a preferred technical solution of the present invention, the thickness of the first passivation layer is 30 to 200 nm, for example, 30 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm or 200 nm.

[0021] Preferably, the thickness of the second passivation layer is 30 to 200 nm, for example, 30 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm or 200 nm.

[0022] Preferably, the first passivation layer includes at least one first passivation layer film.

[0023] Preferably, the material of the first passivation layer film includes one or a combination of at least two of silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, or silicon carbide.

[0024] Preferably, the second passivation layer includes at least one film of the second passivation layer.

[0025] Preferably, the material of the film of the second passivation layer includes one or a combination of at least two of silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, or silicon carbide.

[0026] In a second aspect, the present invention provides a method of manufacturing a selective passivation contact cell according to the first aspect, said method comprising the steps of: A first silicon oxide layer and a first polycrystalline silicon layer are formed on one surface of a substrate, and a thickness of the first polycrystalline silicon layer located in a metal contact region is made larger than a thickness of the first polycrystalline silicon layer located in a non-metal contact region by etching. A second silicon oxide layer and a second polycrystalline silicon layer are sequentially formed on a surface of the first polycrystalline silicon layer located in the metal contact region, and a first electrode is formed on the second polycrystalline silicon layer. This includes the steps:

[0027] The present invention uses the method of etching to make the thickness of the first polysilicon layer located in the metal contact region greater than that of the first polysilicon layer located in the non-metal contact region, effectively reducing the recombination of the metal-non-metal region, reducing the light absorption of the polysilicon layer in the non-metal contact region, and increasing the short circuit current of the battery.Compared with the polysilicon layers of different thicknesses deposited multiple times, the present invention uses the method of etching to deposit the polysilicon layer in one step, and obtains two polysilicon layers of different thicknesses through the etching method, which saves production costs.

[0028] As a preferred technical solution of the present invention, the method for producing the present invention is specifically described as follows: (I) performing surface modification on a surface of a substrate to form a diffusion layer on the surface of the substrate, and sequentially providing a first silicon oxide layer, a first polycrystalline silicon layer, a second silicon oxide layer and a second polycrystalline silicon layer on the surface of the diffusion layer or on a surface of the substrate away from the diffusion layer; (II) applying a barrier-type slurry pattern having the same shape as the first electrode on the surface of the second polycrystalline silicon layer, and etching the first polycrystalline silicon layer, so that the thickness of the first polycrystalline silicon layer located in the metal contact region is greater than the thickness of the first polycrystalline silicon layer located in the non-metal contact region; (III) depositing a protective film on a side of the selective passivation contact cell close to the second polycrystalline silicon layer, removing the thin film layer on the surface of the selective passivation contact cell away from the second polycrystalline silicon layer, and further removing the protective film after the removal; (IV) Depositing a first passivation layer and a second passivation layer and printing a first electrode and a second electrode. This includes the steps:

[0029] In addition, if there is no thin film layer on the surface of the selective passivation contact cell away from the second polycrystalline silicon layer, i.e., if there is no need to remove the thin film layer, step (III) can be omitted, and those skilled in the art can rationally select whether to perform step (III) according to the actual situation of the structure.

[0030] As a preferred technical solution of the present invention, in step (I), the surface modification includes doping with boron and / or doping with phosphorus.

[0031] In the present invention, a PN junction is formed by doping with boron.

[0032] Preferably, the square resistance of the diffusion layer is 80 to 250 ohm / sq, for example, 80 ohm / sq, 90 ohm / sq, 100 ohm / sq, 110 ohm / sq, 120 ohm / sq, 130 ohm / sq, 140 ohm / sq, 150 ohm / sq, 160 ohm / sq, 170 ohm / sq, 180 ohm / sq, 190 ohm / sq, 200 ohm / sq, 210 ohm / sq, 220 ohm / sq, 230 ohm / sq, 240 ohm / sq, or 250 ohm / sq.

[0033] Preferably, a cleaning process is performed on the surface of the substrate remote from the diffusion layer, the cleaning process including removing an oxide film by etching.

[0034] Preferably, the first polycrystalline silicon layer and / or the second polycrystalline silicon layer are formed by diffusion doping and high temperature annealing, preferably being diffusion doped with boron.

[0035] In a preferred technical solution of the present invention, in step (III), the thickness of the protective film is 2 to 200 nm, for example, 2 nm, 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm or 200 nm.

[0036] Preferably, the material of the protective film includes one or a combination of at least two of silicon oxide, silicon carbide, silicon oxynitride, and silicon nitride.

[0037] Preferably, in step (III), the method of removing the thin film layer comprises removing it with hydrofluoric acid.Preferably, the first electrode is sintered after printing.

[0038] Illustratively, a method for manufacturing the selective passivation contact battery is provided, the method comprising the steps of: (I) doping the surface of a substrate with phosphorus, forming a diffusion layer having a square resistivity of 80 to 250 ohm / sq on the surface of the substrate, sequentially providing a first silicon oxide layer, a first polycrystalline silicon layer, a second silicon oxide layer, and a second polycrystalline silicon layer on the surface of the diffusion layer, the first polycrystalline silicon layer and / or the second polycrystalline silicon layer being formed by phosphorus diffusion doping and high temperature annealing; (II) applying a barrier-type slurry pattern having the same shape as the first electrode to the surface of the second polycrystalline silicon layer, and etching the first polycrystalline silicon layer, so that the thickness of the first polycrystalline silicon layer located in the metal contact region is greater than the thickness of the first polycrystalline silicon layer located in the non-metal contact region; (III) depositing a protective film having a thickness of 2 to 200 nm on a side of the selective passivation contact cell close to the second polycrystalline silicon layer, and removing the thin film layer on the surface of the selective passivation contact cell away from the second polycrystalline silicon layer with hydrofluoric acid; (IV) Depositing a first passivation layer and a second passivation layer, and printing and sintering them to form a first electrode and a second electrode. This includes the steps:

[0039] Optionally, the selective passivation contact battery provided by the present invention can be used for the manufacture of P-Poly (P-type polycrystalline silicon) of a selective thickness on the surface of an N-type front contact battery, or a polycrystalline silicon structure with selective thickness on both sides, which can be reasonably selected and installed by those skilled in the art according to the type of battery. For an N-type back contact battery, a selective thickness N-Poly (N-type polycrystalline silicon) is manufactured on the surface of the battery, or a selective thickness P-Poly is manufactured on the back side of the battery, or both sides are polycrystalline silicon structures with selective thickness. For a P-type front contact battery, a selective thickness N-Poly is manufactured on the surface of the battery, or a selective thickness P-Poly is manufactured on the back side of the battery, or both sides are polycrystalline silicon structures with selective thickness. For a P-type back contact battery, a selective thickness P-Poly is manufactured on the surface of the P-type battery, or a selective thickness N-Poly is manufactured on the back side of the battery, or both sides are polycrystalline silicon structures with selective thickness.

[0040] The numerical ranges described in the present invention include not only the point values ​​recited above, but also any point values ​​between the above numerical ranges that are not recited, and for the sake of space and clarity, the present invention does not recite each and every specific point value included in the range.

[0041] The beneficial effects of the present invention compared with the prior art are as follows:

[0042] The present invention provides a second silicon oxide layer, which can effectively control the etching rate and ensure the uniformity of the etching. The thickness of the first polysilicon layer located in the metal contact area is greater than that of the first polysilicon layer located in the non-metal contact area. The larger thickness of the first polysilicon layer in the metal contact area can effectively prevent the corrosion of metal slurry and increase the voltage and fill factor, while the smaller thickness of the first polysilicon layer in the non-metal contact area can effectively reduce the absorption of light and increase the current. The present invention can effectively improve the photoelectric efficiency of the battery, and has the characteristics of simple structure, simple manufacturing process, high efficiency, etc., effectively reduce the recombination of the metal-non-metal area, ensure the light utilization rate of the battery, and have good manufacturing duplication of the structure. [Brief description of the drawings]

[0043] [Figure 1] FIG. 1 is a structural schematic diagram of a selective passivation contact cell provided by a specific embodiment of the present invention, in which a diffusion layer is located between a substrate and a first silicon oxide layer. [Diagram 2] FIG. 2 is a structural schematic diagram of a selective passivation contact cell provided by a specific embodiment of the present invention, in which a diffusion layer is located between a substrate and a second passivation layer. [Explanation of symbols]

[0044] 1 - substrate, 2 - first silicon oxide layer, 3 - first polycrystalline silicon layer, 4 - second silicon oxide layer, 5 - second polycrystalline silicon layer, 6 - first passivation layer, 7 - first electrode, 8 - diffusion layer, 9 - second passivation layer, 10 - second electrode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] In the description of the present invention, the orientation or positional relationship indicated by the terms "center", "vertical", "horizontal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., is based on the orientation or positional relationship shown in the drawings, and is merely for the convenience and simplification of the description of the present invention, and does not indicate or imply that the device or element to which it refers necessarily has a specific orientation, is constructed or operates in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are merely for the purpose of explanation, and cannot be understood as indicating or implying relative importance or the number of technical features to which it refers. Thus, a feature with a limitation such as "first" or "second" can explicitly or implicitly include one or more of the said features. Unless otherwise specified in the description of the present invention, "plurality" means two or more.

[0046] In the description of the present invention, unless otherwise clearly specified or limited, the terms "installed", "coupled" and "connected" should be understood in a broad sense, for example, may be a fixed connection, a removable connection, an integral connection, a mechanical connection, an electrical connection, a direct connection, an indirect connection via an intermediate medium, or internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific situation.

[0047] The technical solution of the present invention will be further described below through specific embodiments.

[0048] In a specific embodiment, the present invention provides a selective passivation contact cell, comprising a substrate 1, a first silicon oxide layer 2 and a first polycrystalline silicon layer 3 stacked in sequence on one surface of the substrate 1, the surface of the substrate 1 including a non-metal contact region and at least two metal contact regions, the metal contact region being located on a surface of the first polycrystalline silicon layer 3 away from the substrate 1, a second polycrystalline silicon layer 4 and a second polycrystalline silicon layer 5 being further disposed in sequence, the second polycrystalline silicon layer 5 being provided with a first electrode 7, the thickness of the first polycrystalline silicon layer 3 located in the metal contact region being greater than the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact region.

[0049] The present invention provides the second silicon oxide layer 4, which can effectively control the etching rate and ensure the uniformity of the etching. The thickness of the first polysilicon layer 3 located in the metal contact area is greater than that of the first polysilicon layer 3 located in the non-metal contact area. The larger thickness of the first polysilicon layer 3 in the metal contact area can effectively prevent the corrosion of the metal slurry and increase the voltage and fill factor. The smaller thickness of the first polysilicon layer 3 in the non-metal contact area can effectively reduce the absorption of light and increase the current. The present invention can effectively improve the photoelectric efficiency of the cell, and has the characteristics of simple structure, simple manufacturing process, high efficiency, etc., effectively reduce the recombination of the metal-non-metal area, ensure the utilization rate of the light of the cell, and the manufacturing duplication of this structure is good.

[0050] Furthermore, the second polysilicon layer 5 presents a grid line structure, and the grid line structure of the second polysilicon layer 5 is the same as that of the first electrode 7. With the second polysilicon layer 5 set as a grid line structure, the present invention can match with the grid line structure of the first electrode 7, further optimize the selective passivation contact structure, and improve the light utilization rate of the cell.

[0051] Furthermore, the selective passivation contact cell further includes a first passivation layer 6 and a second passivation layer 9, where the first passivation layer 6 is located on the surface of the second polycrystalline silicon layer 5 and on the surface of the first polycrystalline silicon layer 3 in the non-metal contact region, and the second passivation layer 9 is located on the surface of the substrate 1 away from the first silicon oxide layer 2.

[0052] In addition, the selective passivation contact cell further includes a diffusion layer 8, which is located between the substrate 1 and the first silicon oxide layer 2 as shown in FIG. 1, or between the substrate 1 and the second passivation layer 9 as shown in FIG. 2.

[0053] Furthermore, on the surface of the substrate 1 remote from the first silicon oxide layer 2, at least two second electrodes 10 are provided.

[0054] Furthermore, the thickness of the first polycrystalline silicon layer 3 located in the metal contact region is 10 to 450 nm, the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact region is 1 to 150 nm, and the thickness of the first silicon oxide layer 2 is 0.5 to 5 nm. The thickness of the second silicon oxide layer 4 is 0.5 to 5 nm, the thickness of the second polycrystalline silicon layer 5 is 1 to 300 nm, the thickness of the first passivation layer 6 is 30 to 200 nm, and the thickness of the second passivation layer 9 is 30 to 200 nm.

[0055] Furthermore, the first passivation layer 6 includes at least one film of the first passivation layer 6, and the film of the first passivation layer 6 includes one or a combination of at least two of silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, or silicon carbide, and the second passivation layer 9 includes at least one film of the second passivation layer 9, and the material of the film of the second passivation layer 9 includes one or a combination of at least two of silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, or silicon carbide.

[0056] In another embodiment, the present invention provides a method for manufacturing a selective passivation contact cell as described above, said method comprising: (I) doping the surface of the substrate 1 with boron, forming a boron diffusion layer 8 having a square resistance of 80 to 250 ohm / sq on the surface of the substrate 1, providing a first silicon oxide layer 2, a first polycrystalline silicon layer 3, a second silicon oxide layer 4 and a second polycrystalline silicon layer 5 in this order on the surface of the substrate 1 away from the diffusion layer 8, and forming the first polycrystalline silicon layer 3 and / or the second polycrystalline silicon layer 5 by phosphorus diffusion doping and high temperature annealing, or forming a boron diffusion layer 8 having a square resistance of 80 to 250 ohm / sq on the surface of the substrate 1, providing a first silicon oxide layer 2, a first polycrystalline silicon layer 3, a second silicon oxide layer 4 and a second polycrystalline silicon layer 5 in this order on the diffusion layer 8, and forming the first polycrystalline silicon layer 3 and / or the second polycrystalline silicon layer 5 by boron diffusion doping and high temperature annealing; (II) applying a barrier-type slurry pattern having the same shape as the first electrode 7 to the surface of the second polycrystalline silicon layer 5, and etching the first polycrystalline silicon layer 3, so that the thickness of the first polycrystalline silicon layer 3 located in the metal contact region is greater than the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact region; (III) depositing a protective film having a thickness of 2 to 200 nm on the side of the selective passivation contact cell close to the second polycrystalline silicon layer 5, removing the thin film layer on the surface of the selective passivation contact cell away from the second polycrystalline silicon layer 5 with hydrofluoric acid, and further removing the protective film after the removal; (IV) Depositing a first passivation layer 6 and a second passivation layer 9 and printing and sintering them to form a first electrode 7 and a second electrode 10. This includes the steps:

[0057] The selective passivation contact battery provided by the present invention can be used for the manufacture of P-Poly (P-type polycrystalline silicon) of a selective thickness on the surface of an N-type front contact battery, or a polycrystalline silicon structure with selective thickness on both sides, and those skilled in the art can reasonably select and install it according to the type of battery. For an N-type back contact battery, a selective thickness N-Poly (N-type polycrystalline silicon) is manufactured on the surface of the battery, or a selective thickness P-Poly is manufactured on the back side of the battery, or both sides are polycrystalline silicon structures with selective thickness. For a P-type front contact battery, a selective thickness N-Poly is manufactured on the surface of the battery, or a selective thickness P-Poly is manufactured on the back side of the battery, or both sides are polycrystalline silicon structures with selective thickness. For a P-type back contact battery, a selective thickness P-Poly is manufactured on the surface of the P-type battery, or a selective thickness N-Poly is manufactured on the back side of the battery, or both sides are polycrystalline silicon structures with selective thickness. EXAMPLES

[0058] This embodiment provides a selective passivation contact cell based on the selective passivation contact cell described in the detailed description of the invention, in which the surface of the substrate 1 includes two metal contact regions, a diffusion layer 8 is located between the substrate 1 and a first silicon oxide layer 2, and two second electrodes 10 are provided on the surface of the substrate 1 away from the first silicon oxide layer 2.

[0059] The thickness of the first polycrystalline silicon layer 3 located in the metal contact area is 230 nm, the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact area is 75 nm, and the thickness of the first silicon oxide layer 2 is 2.5 nm. The thickness of the second silicon oxide layer 4 is 2.5 nm. The thickness of the second polycrystalline silicon layer 5 is 150 nm. The thickness of the first passivation layer 6 is 115 nm. The thickness of the second passivation layer 9 is 115 nm.

[0060] The first passivation layer 6 includes one layer of the first passivation layer 6 film, and the material of the first passivation layer 6 film includes silicon oxide, and the second passivation layer 9 includes one layer of the second passivation layer 9 film, and the material of the second passivation layer 9 film includes silicon oxide.

[0061] This embodiment further provides a method for manufacturing the selective passivation contact battery, the method comprising: (I) The surface of the substrate 1 is doped with boron, and a diffusion layer 8 having a square resistance of 165 ohm / sq is formed on the surface of the substrate 1. A first silicon oxide layer 2, a first polycrystalline silicon layer 3, a second silicon oxide layer 4, and a second polycrystalline silicon layer 5 are sequentially formed on the surface of the diffusion layer 8, and the first polycrystalline silicon layer 3 and the second polycrystalline silicon layer 5 are both formed by boron diffusion doping; (II) applying a barrier-type slurry pattern having the same shape as the first electrode 7 to the surface of the second polycrystalline silicon layer 5, and etching the first polycrystalline silicon layer 3, so that the thickness of the first polycrystalline silicon layer 3 located in the metal contact region is greater than the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact region; (III) depositing a protective film having a thickness of 100 nm on the side of the selective passivation contact cell close to the second polycrystalline silicon layer 5, removing the thin film layer on the surface of the selective passivation contact cell away from the second polycrystalline silicon layer 5 with hydrofluoric acid, and then removing the protective film after the removal; (IV) Depositing a first passivation layer 6 and a second passivation layer 9 and printing and sintering them to form a first electrode 7 and a second electrode 10. This includes the steps: EXAMPLES

[0062] This example provides a selective passivation contact cell based on the selective passivation contact cell described in the specific embodiment, in which the surface of the substrate 1 includes three metal contact regions, a diffusion layer 8 is located between the substrate 1 and a second passivation layer 9, and three second electrodes 10 are provided on the surface of the substrate 1 away from the first silicon oxide layer 2.

[0063] The first polycrystalline silicon layer 3 located in the metal contact area has a thickness of 10 nm, the first polycrystalline silicon layer 3 located in the non-metal contact area has a thickness of 1 nm, and the first silicon oxide layer 2 has a thickness of 0.5 nm. The second silicon oxide layer 4 has a thickness of 0.5 nm. The second polycrystalline silicon layer 5 has a thickness of 1 nm. The first passivation layer 6 has a thickness of 30 nm. The second passivation layer 9 has a thickness of 30 nm.

[0064] The first passivation layer 6 includes two first passivation layer 6 films, the materials of which are silicon oxynitride and silicon carbide, respectively, and the second passivation layer 9 includes two second passivation layer 9 films, the materials of which are silicon oxynitride and silicon carbide, respectively.

[0065] This embodiment provides a method for manufacturing the selective passivation contact battery, the method comprising: (I) doping the surface of a substrate 1 with boron, forming a diffusion layer 8 having a square resistivity of 80 to 250 ohm / sq on the surface of the substrate 1, sequentially providing a first silicon oxide layer 2, a first polycrystalline silicon layer 3, a second silicon oxide layer 4, and a second polycrystalline silicon layer 5 on the surface of the substrate 1 away from the diffusion layer 8, forming the first polycrystalline silicon layer 3 by phosphorus diffusion doping, and forming the second polycrystalline silicon layer 5 by high temperature annealing; (II) applying a barrier-type slurry pattern having the same shape as the first electrode 7 to the surface of the second polycrystalline silicon layer 5, and etching the first polycrystalline silicon layer 3, so that the thickness of the first polycrystalline silicon layer 3 located in the metal contact region is greater than the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact region; (III) depositing a protective film having a thickness of 200 nm on the side of the selective passivation contact cell close to the second polycrystalline silicon layer 5, removing the thin film layer on the surface of the selective passivation contact cell away from the second polycrystalline silicon layer 5 with hydrofluoric acid, and then removing the protective film after the removal; (IV) Depositing a first passivation layer 6 and a second passivation layer 9 and printing and sintering them to form a first electrode 7 and a second electrode 10. This includes the steps: EXAMPLES

[0066] This example provides a selective passivation contact cell based on the selective passivation contact cell described in the specific embodiment, in which the surface of the substrate 1 includes four metal contact regions, a diffusion layer 8 is located between the substrate 1 and a first silicon oxide layer 2, and four second electrodes 10 are provided on the surface of the substrate 1 away from the first silicon oxide layer 2.

[0067] The thickness of the first polycrystalline silicon layer 3 located in the metal contact area is 450 nm, the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact area is 150 nm, and the thickness of the first silicon oxide layer 2 is 5 nm. The thickness of the second silicon oxide layer 4 is 5 nm. The thickness of the second polycrystalline silicon layer 5 is 300 nm. The thickness of the first passivation layer 6 is 200 nm. The thickness of the second passivation layer 9 is 200 nm.

[0068] The first passivation layer 6 includes three first passivation layer 6 films, and the materials of the first passivation layer 6 films are silicon oxide, aluminum oxide, and silicon nitride, respectively. The second passivation layer 9 includes three second passivation layer 9 films, and the materials of the second passivation layer 9 films include aluminum oxide, silicon oxynitride, and silicon carbide.

[0069] This embodiment provides a method for manufacturing the selective passivation contact battery, the method comprising: (I) doping the surface of the substrate 1 with boron, forming a diffusion layer 8 having a square resistance of 80 to 250 ohm / sq on the surface of the substrate 1, sequentially depositing a first silicon oxide layer 2, a first polycrystalline silicon layer 3, a second silicon oxide layer 4, and a second polycrystalline silicon layer 5 on the surface of the diffusion layer 8, forming the first polycrystalline silicon layer 3 by high-temperature annealing, and forming the second polycrystalline silicon layer 5 by boron diffusion doping; (II) applying a barrier-type slurry pattern having the same shape as the first electrode 7 to the surface of the second polycrystalline silicon layer 5, and etching the first polycrystalline silicon layer 3, so that the thickness of the first polycrystalline silicon layer 3 located in the metal contact region is greater than the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact region; (III) depositing a protective film having a thickness of 200 nm on the side of the selective passivation contact cell close to the second polycrystalline silicon layer 5, removing the thin film layer on the surface of the selective passivation contact cell away from the second polycrystalline silicon layer 5 with hydrofluoric acid, and then removing the protective film after the removal; (IV) Depositing a first passivation layer 6 and a second passivation layer 9 and printing and sintering them to form a first electrode 7 and a second electrode 10. The comparative example 1 includes the steps of:

[0070] This comparative example provides a selective passivation contact cell. The difference between this comparative example and the first embodiment is that the thickness of the first polysilicon layer 3 located in the metal contact area is equal to the thickness of the first polysilicon layer 3 located in the non-metal contact area, and the thickness of the first polysilicon layer 3 located in the metal contact area is 230 nm. The other structures are completely the same as those of the first embodiment.

[0071] This comparative example further provides a method for manufacturing the selective passivation contact battery, the method comprising: (I) The surface of the substrate 1 is doped with boron, and a diffusion layer 8 having a square resistance of 165 ohm / sq is formed on the surface of the substrate 1. A first silicon oxide layer 2, a first polycrystalline silicon layer 3, a second silicon oxide layer 4, and a second polycrystalline silicon layer 5 are sequentially formed on the surface of the diffusion layer 8, and the first polycrystalline silicon layer 3 and the second polycrystalline silicon layer 5 are both formed by boron diffusion doping; (II) applying a barrier-type slurry pattern having the same shape as the first electrode 7 to the surface of the second polycrystalline silicon layer 5, and etching the first polycrystalline silicon layer 3, so that the thickness of the first polycrystalline silicon layer 3 located in the metal contact region is equal to the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact region; (III) depositing a protective film having a thickness of 100 nm on the side of the selective passivation contact cell close to the second polycrystalline silicon layer 5, removing the thin film layer on the surface of the selective passivation contact cell away from the second polycrystalline silicon layer 5 with hydrofluoric acid, and then removing the protective film after the removal; (IV) Depositing a first passivation layer 6 and a second passivation layer 9 and printing and sintering them to form a first electrode 7 and a second electrode 10. The comparative example 2 includes the steps of:

[0072] This comparative example provides a selective passivation contact cell. The difference between this comparative example and the first embodiment is that the second silicon oxide layer 4 is not provided, and the other structures are completely the same as those of the first embodiment. Comparative Example 3

[0073] This comparative example provides a selective passivation contact cell, and the difference between this comparative example and the first embodiment is that the first polysilicon layer is manufactured by deposition, and the manufacturing method includes: (I) The surface of the substrate 1 is doped with boron, a diffusion layer 8 with a square resistance of 165 ohm / sq is formed on the surface of the substrate 1, a first silicon oxide layer 2, a first polycrystalline silicon layer 3, a second silicon oxide layer 4, and a second polycrystalline silicon layer 5 are sequentially formed on the surface of the diffusion layer 8, and the first polycrystalline silicon layer 3 and the second polycrystalline silicon layer 5 are all formed by boron diffusion doping. The first polycrystalline silicon layer 3 is manufactured by deposition, and the thickness of the first polycrystalline silicon layer 3 located in the metal contact region is made equal to the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact region; (II) depositing a protective film having a thickness of 100 nm on the side of the selective passivation contact cell close to the second polycrystalline silicon layer 5, and removing the thin film layer on the surface of the selective passivation contact cell away from the second polycrystalline silicon layer 5 with hydrofluoric acid; (III) Depositing a first passivation layer 6 and a second passivation layer 9 and printing and sintering them to form a first electrode 7 and a second electrode 10. This includes the steps:

[0074] The solar cells obtained in the above Examples and Comparative Examples were subjected to a photoelectric conversion rate performance test, and the test method includes the following:

[0075] The fabricated solar cell was placed under a simulated light source of AM1.5 (the light source simulator model number is Newport Oriel 94043A), and the light source energy density was 100 mW / cm 2 The light source is calibrated using a reference crystalline silicon cell, and the JV curve of the solar cell is measured using FTC650. The light is directly incident on the surface of the solar cell, and the effective area of ​​the solar cell is 0.5 cm. 2 The test results are shown in Table 1.

[0076] [Table 1]

[0077] From the above table we can see the following:

[0078] Comparing Example 1 with Comparative Examples 1 and 2, the photoelectric conversion rate and short circuit current effect of Example 1 are superior to those of Comparative Examples 1 and 2, so that the present invention can effectively control the etching rate and ensure the uniformity of etching by providing the second silicon oxide layer 4. Furthermore, the thickness of the first polycrystalline silicon layer 3 located in the metal contact region is greater than the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact region, and the large thickness of the first polycrystalline silicon layer 3 in the metal contact region can effectively prevent the corrosion of the metal slurry and increase the voltage and fill factor, while the small thickness of the first polycrystalline silicon layer 3 in the non-metal contact region can effectively reduce the absorption of light and increase the current. The present invention can effectively improve the photoelectric efficiency of the battery, and has the characteristics of simple structure, simple manufacturing process, high efficiency, etc., effectively reduce the recombination of the metal-non-metal region, guarantee the utilization rate of the battery to light, and the manufacturing duplication of this structure is good.

[0079] Comparing Example 1 with Comparative Example 3, the photoelectric conversion rate and short circuit current effect of Example 1 are better than those of Comparative Example 3. Therefore, the present invention uses the method of etching to make the thickness of the first polycrystalline silicon layer 3 located in the metal contact area greater than the thickness of the first polycrystalline silicon layer 3 located in the non-metal contact area, effectively reducing the recombination of the metal-non-metal area, reducing the light absorption of the polycrystalline silicon layer in the non-metal contact area, and increasing the battery short circuit current. Compared with depositing polycrystalline silicon layers of different thicknesses multiple times, the present invention uses the method of etching to deposit a polycrystalline silicon layer in only one step, and two types of polycrystalline silicon layers with different thicknesses can be obtained by the etching method, which saves production costs.

[0080] The above content is only a specific embodiment of the present invention, and the claims of the present invention are not limited thereto. It will be obvious to those skilled in the art that any modification or replacement that can be easily conceived by any person skilled in the art within the technical scope disclosed in the present invention is within the claims and disclosure scope of the present invention. The following is a summary of the claims as originally filed: [1] A method for manufacturing a semiconductor device comprising: a substrate, a first silicon oxide layer and a first polycrystalline silicon layer being sequentially stacked on a surface of one side of the substrate; the surface of the substrate includes a non-metallic contact region and at least two metallic contact regions; a second silicon oxide layer and a second polysilicon layer are sequentially formed on a surface of the first polysilicon layer located in the metal contact region away from the substrate, and a first electrode is formed on the second polysilicon layer; The thickness of the first polysilicon layer located in the metal contact region is greater than the thickness of the first polysilicon layer located in the non-metal contact region. A selective passivation contact battery comprising: [2] The second polysilicon layer has a grid line structure, and the grid line structure of the first electrode is the same as the grid line structure of the second polysilicon layer. The selective passivation contact battery according to [1], [3] The selective passivation contact cell further includes a first passivation layer and a second passivation layer, the first passivation layer being located on a surface of the second polycrystalline silicon layer and on a surface of the first polycrystalline silicon layer in the non-metal contact region, and the second passivation layer being located on a surface of the substrate away from the first silicon oxide layer; a diffusion layer located between the substrate and the first silicon oxide layer; At least two second electrodes are provided on the surface of the substrate away from the first silicon oxide layer. The selective passivation contact battery according to [1] or [2], [4] The diffusion layer is located between the substrate and the second passivation layer. The selective passivation contact battery according to [3], [5] The first polycrystalline silicon layer located in the metal contact region has a thickness of 10 to 450 nm, and the first polycrystalline silicon layer located in the non-metal contact region has a thickness of 1 to 150 nm. The selective passivation contact battery according to [1], [6] The thickness of the first polycrystalline silicon layer located in the non-metallic region is 10 to 25 nm. The selective passivation contact battery according to [5], [7] The first silicon oxide layer has a thickness of 0.5 to 5 nm, and the second silicon oxide layer has a thickness of 0.5 to 5 nm; The second polycrystalline silicon layer has a thickness of 1 to 300 nm. The selective passivation contact battery according to [1], [8] The first passivation layer has a thickness of 30 to 200 nm, and the second passivation layer has a thickness of 30 to 200 nm. The selective passivation contact battery according to [3], [9] The first passivation layer includes at least one first passivation layer film, and the material of the first passivation layer film includes one or a combination of at least two of silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, or silicon carbide; The second passivation layer includes at least one second passivation layer film, and the material of the second passivation layer film includes one or a combination of at least two of silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, and silicon carbide. The selective passivation contact battery according to [8],

[10] A first silicon oxide layer and a first polycrystalline silicon layer are formed on a surface of one side of a substrate, and a thickness of the first polycrystalline silicon layer located in a metal contact region is made larger than a thickness of the first polycrystalline silicon layer located in a non-metal contact region by etching; a second silicon oxide layer and a second polycrystalline silicon layer are sequentially formed on a surface of the first polycrystalline silicon layer located in the metal contact region, and a first electrode is formed on the second polycrystalline silicon layer. The method for producing a selective passivation contact battery according to any one of [1] to [9],

[11] The manufacturing method comprises: (I) performing surface modification on a surface of a substrate to form a diffusion layer on the surface of the substrate, and sequentially providing a first silicon oxide layer, a first polycrystalline silicon layer, a second silicon oxide layer and a second polycrystalline silicon layer on the surface of the diffusion layer or on a surface of the substrate away from the diffusion layer; (II) applying a barrier-type slurry pattern having the same shape as the first electrode on the surface of the second polycrystalline silicon layer, and etching the first polycrystalline silicon layer, so that the thickness of the first polycrystalline silicon layer located in the metal contact region is greater than the thickness of the first polycrystalline silicon layer located in the non-metal contact region; (III) depositing a protective film on a side of the selective passivation contact cell close to the second polycrystalline silicon layer, removing the thin film layer on the surface of the selective passivation contact cell away from the second polycrystalline silicon layer, and further removing the protective film after the removal; (IV) specifically includes the steps of depositing a first passivation layer and a second passivation layer, and printing a first electrode and a second electrode. The manufacturing method described in

[10] ,

[12] In step (I), the surface modification comprises doping with boron and / or doping with phosphorus; The square resistance of the diffusion layer is 80 to 250 ohm / sq. performing a cleaning process on a surface of the substrate away from the diffusion layer, the cleaning process including removing an oxide film by etching; The first polycrystalline silicon layer and / or the second polycrystalline silicon layer are formed by boron diffusion doping and high temperature annealing. The manufacturing method according to

[11] ,

[13] In step (III), the protective film has a thickness of 2 to 200 nm; The material of the protective film includes one or a combination of at least two of silicon oxide, silicon carbide, silicon oxynitride, and silicon nitride; In step (III), the method for removing the thin film layer includes removing it with hydrofluoric acid, and the first electrode is sintered after printing. The manufacturing method according to

[11] ,

Claims

1. A selective passivation contact battery, comprising: The selective passivation contact cell includes a substrate, a first silicon oxide layer and a first polycrystalline silicon layer are sequentially stacked on one surface of the substrate, and the surface of the substrate includes a non-metallic contact region and at least two metallic contact regions; Each of the metal contact regions further includes a second silicon oxide layer and a second polysilicon layer disposed in that order on a surface of the first polysilicon layer away from the substrate, and a first electrode is disposed on the second polysilicon layer; a thickness of the first polycrystalline silicon layer located in the metal contact region is greater than a thickness of the first polycrystalline silicon layer located in the non-metal contact region; The selective passivation contact cell further includes a first passivation layer and a second passivation layer, the first passivation layer being located on a surface of the second polycrystalline silicon layer and on a surface of the first polycrystalline silicon layer in the non-metal contact region, and the second passivation layer being located on a surface of the substrate away from the first silicon oxide layer; The selective passivation contact cell further comprises a diffusion layer located between the substrate and the first silicon oxide layer, or a diffusion layer is located between the substrate and the second passivation layer; At least two second electrodes are provided on the surface of the substrate away from the first silicon oxide layer. A selective passivation contact battery comprising:

2. The second polysilicon layer has a grid line structure, and the grid line structure of the first electrode is the same as the grid line structure of the second polysilicon layer.

2. The selective passivation contact battery of claim 1 .

3. The first polysilicon layer located in the metal contact region has a thickness of 10 to 450 nm, and the first polysilicon layer located in the non-metal contact region has a thickness of 1 to 150 nm.

2. The selective passivation contact battery of claim 1 .

4. The thickness of the first polycrystalline silicon layer located in the non-metal contact region is 10 to 25 nm.

4. The selective passivation contact battery of claim 3.

5. The first silicon oxide layer has a thickness of 0.5 to 5 nm, and the second silicon oxide layer has a thickness of 0.5 to 5 nm; The second polycrystalline silicon layer has a thickness of 1 to 300 nm.

2. The selective passivation contact battery of claim 1 .

6. The first passivation layer has a thickness of 30 to 200 nm, and the second passivation layer has a thickness of 30 to 200 nm.

2. The selective passivation contact battery of claim 1 .

7. The first passivation layer includes at least one first passivation layer film, and the material of the first passivation layer film includes one or a combination of at least two of silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, or silicon carbide; The second passivation layer includes at least one second passivation layer film, and the material of the second passivation layer film includes one or a combination of at least two of silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, and silicon carbide.

7. The selective passivation contact battery of claim 6.

8. A first silicon oxide layer and a first polycrystalline silicon layer are formed on a surface of one side of a substrate, and a thickness of the first polycrystalline silicon layer located in a metal contact region is made larger than a thickness of the first polycrystalline silicon layer located in a non-metal contact region by etching. A second silicon oxide layer and a second polycrystalline silicon layer are sequentially formed on a surface of the first polycrystalline silicon layer located in the metal contact region, and a first electrode is formed on the second polycrystalline silicon layer. A method for producing a selective passivation contact battery according to any one of claims 1 to 7.

9. The manufacturing method includes: (I) performing surface modification on a surface of the substrate to form a diffusion layer on the surface of the substrate, and sequentially providing the first silicon oxide layer, the first polycrystalline silicon layer, the second silicon oxide layer, and the second polycrystalline silicon layer on the surface of the diffusion layer or on a surface of the substrate away from the diffusion layer; (II) applying a barrier-type slurry pattern having the same shape as the first electrode to a surface of the second polycrystalline silicon layer, and etching the first polycrystalline silicon layer, so that a thickness of the first polycrystalline silicon layer located in the metal contact region is greater than a thickness of the first polycrystalline silicon layer located in the non-metal contact region; (III) depositing a protective film on a side of the selective passivation contact cell close to the second polycrystalline silicon layer, removing a thin film layer on a surface of the selective passivation contact cell away from the second polycrystalline silicon layer, and then removing the protective film after the removal; (IV) depositing a first passivation layer and a second passivation layer, and printing the first electrode and the second electrode. The method according to claim 8 .

10. In step (I), the surface modification comprises doping with boron and / or doping with phosphorus; The square resistance of the diffusion layer is 80 to 250 ohm / sq. performing a cleaning process on a surface of the substrate away from the diffusion layer, the cleaning process including removing an oxide film by etching; The first polycrystalline silicon layer and / or the second polycrystalline silicon layer are formed by boron diffusion doping and high temperature annealing. The method according to claim 9 .

11. The method of claim 10, wherein in step (III), the protective film has a thickness of 2 to 200 nm; The material of the protective film includes one or a combination of at least two of silicon oxide, silicon carbide, silicon oxynitride, and silicon nitride; In the step (III), the method of removing the thin film layer includes removing it with hydrofluoric acid, and the first electrode is sintered after printing. The method according to claim 9 .

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