D / A conversion circuit and method

Abstract

An embodiment of the present application provides a D / A conversion circuit and method, the D / A conversion circuit including a conversion unit including a first code value receiving terminal for receiving a first code value and converting the first code value into an analog signal, a second code value receiving terminal for receiving a second code value, and a signal input terminal connected to the signal output terminal of the conversion unit, the first adjusting unit obtaining a first analog adjusted signal based on the second code value and adjusting the analog signal transmitted by the conversion unit based on the first analog adjusted signal to obtain a target signal. By using the conversion unit and the first adjusting unit, the present application can easily and effectively adjust different output voltage ranges.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present application relate to the field of integrated circuit design, and more particularly, but not exclusively, to D / A conversion circuits and methods. [Background technology]

[0002] A D / A converter (Digital-to-Analog), also called D / A or DAC, has the main function of converting a digital or discrete signal into an analog signal. A digital signal is a set of parallel coded signals generated by a digital signal system. A D / A converter converts the coded signals generated by the digital signal system into equivalent analog signals under the action of a reference voltage. The converted analog signals are then input into an analog signal system through filtering and amplification. Therefore, how to use a D / A converter to convert a digital signal into a more accurate analog signal has become an urgent problem to be solved. Summary of the Invention [Problem to be solved by the invention]

[0003] The D / A conversion circuit and method according to the embodiments of the present application mainly solve the technical problem of how to simply and effectively adjust the range of an analog voltage signal obtained by D / A conversion. [Means for solving the problem]

[0004] In a first aspect, according to an embodiment of the present application, there is provided a D / A conversion circuit including: a conversion unit including a first code value receiving terminal for receiving a first code value, and converting the first code value into an analog signal; a first adjustment unit including a second code value receiving terminal for receiving a second code value and a signal input terminal connected to a signal output terminal of the conversion unit, and obtaining a first analog adjustment signal based on the second code value, and adjusting the analog signal transmitted by the conversion unit based on the first analog adjustment signal to obtain a target signal.

[0005] Preferably, the D / A conversion circuit includes a third code value receiving terminal for receiving a third code value, and a signal input terminal connected to the signal output terminal of the first adjustment unit, and further includes a second adjustment unit for obtaining a second analog signal based on the third code value, and adjusting the analog signal transmitted by the conversion unit based on the second analog signal.

[0006] Preferably, the second adjustment unit includes n first resistor selection subunits, and a first resistor is provided between each two adjacent first resistor selection subunits, the first resistor being electrically connected to the adjacent first resistor selection subunits.

[0007] Preferably, the first resistor selection subunit includes a second resistor and a first switch element, a control terminal of the first switch element receives the third code value, a second connection terminal of the first switch element is connected to a first connection terminal of the second resistor, and a second connection terminal of the second resistor is connected to the first resistor.

[0008] Preferably, the first switch element includes a first inverter, a first PMOS transistor and a first NMOS transistor, the first inverter having an input terminal receiving the third code value and an output terminal respectively connected to a gate of the first PMOS transistor and a gate of the first NMOS transistor, the first PMOS transistor having a source connected to a positive terminal of a reference voltage, a drain connected to a drain of the first NMOS transistor, and a source of the first NMOS transistor connected to a negative terminal of a reference voltage.

[0009] Preferably, the conversion unit includes m second resistor selection subunits, and a third resistor is provided between each two adjacent second resistor selection subunits, the third resistor being electrically connected to the adjacent second resistor selection subunits.

[0010] Preferably, the second resistor selection subunit includes a fourth resistor and a second switch element, a control terminal of the second switch element receives the first code value, a second connection terminal of the second switch element is connected to a first connection terminal of the fourth resistor, and a second connection terminal of the fourth resistor is connected to the third resistor.

[0011] Preferably, the second switch element includes a second inverter, a second PMOS transistor and a second NMOS transistor, the second inverter having an input terminal receiving the first code value and an output terminal respectively connected to a gate of the second PMOS transistor and a gate of the second NMOS transistor, the second PMOS transistor having a source connected to a positive terminal of a reference voltage, a drain connected to a drain of the second NMOS transistor, and a source of the second NMOS transistor connected to a negative terminal of a reference voltage.

[0012] Preferably, the first adjusting unit includes k third resistor selection subunits, the third resistor selection subunits including a third switch element and a fifth resistor, and the third switch element is connected to the fifth resistor.

[0013] Preferably, the third switch element includes a third inverter, a third PMOS transistor and a third NMOS transistor, the third inverter having an input terminal receiving the second code value and an output terminal connected to the gate of the third PMOS transistor, the third PMOS transistor having a source connected to the drain of the third NMOS transistor and a drain connected to the source of the third NMOS transistor.

[0014] In a second aspect, according to an embodiment of the present application, there is further provided a D / A conversion method applied to the D / A conversion circuit of the first aspect, the D / A conversion method including the steps of receiving a first code value and converting the first code value into an analog signal, and adjusting the analog signal to obtain a target signal.

[0015] Preferably, the step of adjusting the analog signal and obtaining a target signal includes obtaining digital signals of a plurality of full code values, and adjusting analog signals corresponding to the digital signals of the plurality of full code values ​​to obtain a D / A adjustment list, and obtaining the target signal corresponding to the analog signal based on the D / A adjustment list. Effect of the Invention

[0016] The D / A conversion circuit according to the embodiment of the present application can realize the adjustment to the voltage range more simply and effectively by combining a conversion unit and a first adjustment unit. Specifically, the D / A conversion circuit can include a conversion unit and a first adjustment unit, the conversion unit includes a first code value receiving terminal for receiving a first code value, and can convert the first code value into an analog signal, and the first adjustment unit includes a second code value receiving terminal for receiving a second code value and a signal input terminal connected to a signal output terminal of the conversion unit, and can obtain a first analog adjustment signal according to the second code value, and adjust the analog signal transmitted by the conversion unit according to the first analog adjustment signal to obtain a target signal. In the present application, the conversion unit converts the received first code value into an analog signal, and then uses the first adjustment unit to adjust the analog signal, so that the finally obtained target signal can be more accurate and effective.

[0017] It should be understood that other features of the present invention and corresponding advantageous effects will be described in subsequent portions of the specification, and that at least some of the advantageous effects will be apparent from the description of the present invention. [Brief description of the drawings]

[0018] [Figure 1] 1 is a schematic diagram of a D / A conversion circuit according to an embodiment of the present application. [Diagram 2] FIG. 13 is a schematic configuration diagram of a D / A conversion circuit according to another embodiment of the present application. [Diagram 3] FIG. 13 is a schematic diagram illustrating a load in a D / A conversion circuit according to another embodiment of the present application. [Figure 4] FIG. 13 is a schematic configuration diagram of a conversion unit in a D / A conversion circuit according to another embodiment of the present application. [Diagram 5] 11 is a schematic configuration diagram of a second switch element in a D / A conversion circuit according to another embodiment of the present application. FIG. [Figure 6] FIG. 13 is a schematic configuration diagram of a second adjustment unit in a D / A conversion circuit according to another embodiment of the present application. [Figure 7] FIG. 11 is a schematic configuration diagram of a first switch element in a D / A conversion circuit according to another embodiment of the present application. [Figure 8] FIG. 11 is a schematic configuration diagram of a first adjustment unit in a D / A conversion circuit according to another embodiment of the present application. [Figure 9] 13 is a schematic configuration diagram of a third switch element in a D / A conversion circuit according to another embodiment of the present application. FIG. [Figure 10] 2 is a flowchart of a D / A conversion method according to an embodiment of the present application. [Figure 11] 1 is a schematic diagram illustrating the relationship between a digital signal and an analog signal in a D / A conversion method according to an embodiment of the present application. [Figure 12] 4 is a schematic diagram showing another relationship between a digital signal and an analog signal in a D / A conversion method according to an embodiment of the present application. FIG. [Figure 13] FIG. 2 is a schematic diagram illustrating further relationships between digital and analog signals in a D / A conversion method according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] In order to more clearly describe the technical means of the embodiments of the present application, the drawings necessary for describing the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without any creative work.

[0020] Conventional D / A converters are divided into current proportional, voltage proportional, charge proportional, etc. The current proportional type is a method of adding an accurate current source by simple or binary weighting, and has advantages such as high speed and large drive, but these advantages bring disadvantages such as a wide range of element values ​​and low consistency. The charge proportional type is a method of using a parallel capacitor array with binary weighting value and dividing a reference voltage, and has advantages such as high speed and high accuracy, but also has disadvantages such as a wide range of element values. The voltage proportional type is a method of adding voltage using a series resistance voltage division or parallel resistance voltage division, and has advantages such as simple structure and monotonicity, but these advantages also bring disadvantages such as a large area and low speed. As described above, the three types of D / A conversion technologies, i.e., current proportional, voltage proportional, and charge proportional, all have the characteristics of a single output voltage range and cannot be adjusted, and these technologies all have certain limitations when performing D / A conversion.

[0021] In response to the above problem, the inventor provides a D / A conversion circuit according to an embodiment of the present application, in which a first adjustment unit is introduced to adjust the voltage range obtained by D / A conversion more simply and effectively.

[0022] 1 is a schematic diagram of a D / A conversion circuit according to an embodiment of the present application. As can be seen from FIG. 1, the D / A conversion circuit 100 may include a conversion unit 110 and a first adjustment unit 120.

[0023] In one embodiment, the conversion unit 110 may include a first code value receiving terminal 111 for receiving a first code value, and converting the first code value into an analog signal. a The bit may be referred to as the first code value, V dac_ais the converted analog signal, which may be referred to as the output voltage of the conversion unit. The first code value may be a set of parallel coded signals generated by the digital signal system, or may be a binary code value. For example, the first code value may be a 2-bit binary code value, a 4-bit binary code value, an 8-bit binary code value, or a 16-bit binary code value, and the specific bit number is not specifically limited here, and may be selected according to the actual situation. In addition, the first code value may be a binary code value input by a user according to needs. For example, when a user wants to convert a digital signal 011 into an analog signal, the user can input 011 into the conversion unit 110, and the conversion unit 110 can obtain the analog signal that needs to be converted.

[0024] In an embodiment of the present invention, the conversion unit 110 may be composed of a plurality of switches and unit resistors, and the number of the switches and resistors is determined by the first code value, and the variation range of the first code value is 0 to 2. Na -1 and 2 Na N analog output voltages can be obtained, where N a may be the number of binary bits. For example, if the first code value is 1011, its corresponding N a is 4.

[0025] 1, the conversion unit 110, in addition to including a first code value receiving terminal 111, may further include a signal output terminal 112 and a positive and negative terminal of a reference voltage. REF+ and the negative terminal of the reference voltage is V REF- In the embodiment of the present invention, the positive and negative terminals of the reference voltage have a certain driving capability, that is, the positive and negative terminals of the reference voltage can provide an output current. The output voltage range of the analog signal corresponding to the conversion unit 110 is REF+ and V REF- It is determined by the size of the range between (V REF+ )-(V REF- ).

[0026] In another embodiment, the first code value generated by the digital signal system is m a "0" and n a may consist of m "1"s, where m a +n a =N a When the first code value has a "0", the internal switch of the conversion unit 110 connects the negative terminal V REF- , and when the first code value has a "1", the internal switch of the conversion unit 110 is connected to the positive terminal V REF+ The switch action causes V REF+ and V REF- There is a series of resistors connected in series and in parallel between the input and the output terminal 112 (V REF+ )-(V REF- ) to obtain an analog voltage signal proportional to the

[0027] One method is m a =N a , n a If m = 0, the output of the transform unit 110 is the minimum value, and the number of bits of the first code value is all 0. For example, m a = 4, n a If m = 0, the corresponding first code value is 0000. a =0, n a =N a , the output of the transform unit 110 is the maximum value, and the number of bits of the first code value is all 1. For example, m a =0, n a If = 4, the corresponding first code value is 1111. The least significant bit (LSB) of the transform unit 110 is N a The least significant bit is the least significant bit of the output.

number

number

[0028] In an embodiment of the present invention, the first adjusting unit 120 may include: a second code value receiving terminal 121 for receiving a second code value, and a signal input terminal 122 connected to the signal output terminal 112 of the conversion unit 110. The first adjusting unit 120 obtains a first analog adjusted signal according to the second code value, and adjusts the analog signal transmitted by the conversion unit 110 according to the first analog adjusted signal to obtain a target signal.

[0029] N shown in Figure 1 c The bits may be called second code values, and the second code values ​​may be a set of parallel encoded signals generated by a digital signal system, or may be binary code values. For example, the second code values ​​may be 2-bit binary code values, 8-bit binary code values, 16-bit binary code values, etc., and the specific number of bits is not specifically limited here and can be selected according to actual circumstances. In addition, the second code values ​​may be binary code values ​​input by a user according to needs.

[0030] In an embodiment of the present invention, the first adjusting unit 120 may be composed of a plurality of switches and unit resistors. As can be seen from FIG. 1, the first adjusting unit 120, in addition to including a second code value receiving terminal 121, may further include a signal input terminal 122 and a positive and negative terminal of a reference voltage. The positive terminal of the reference voltage is V REF+ and the negative terminal of the reference voltage is V REF- It is.

[0031] In one embodiment, the first input of the first adjustment unit 120 is N c is a binary code value of N bits, c The binary code value of the bit is the second code value. c The most significant bit of the (N) bit code value is for selecting the output range of the transform unit 110, and the remaining N c-1 bit is for adjusting the magnitude of the LSB voltage of the conversion unit 110. c- By adjusting 1 bit, 2 Nc-1 The voltage value of the least significant bit (LSB) can be obtained.

[0032] Alternatively, the other two inputs of the first adjustment unit 120 are the positive and negative terminals of the reference voltage V REF+ , V REF- In addition, the signal input terminal 122 of the first adjustment unit 120 receives the output voltage of the conversion unit 110. The analog signal output from the conversion unit 110 is N c After being processed by the first regulating unit 120 of 1 bit, it can output a flexibly regulated analog voltage. The output voltage of the first regulating unit 120 drives a capacitive load, or drives a resistive load, a capacitive load with a specific requirement for speed, etc. through a buffer circuit.

[0033] The D / A conversion circuit according to the embodiment of the present application can realize the adjustment to the voltage range more simply and effectively by combining a conversion unit and a first adjustment unit. Specifically, the D / A conversion circuit can include a conversion unit and a first adjustment unit, the conversion unit includes a first code value receiving terminal for receiving a first code value, and can convert the first code value into an analog signal, and the first adjustment unit includes a second code value receiving terminal for receiving a second code value and a signal input terminal connected to a signal output terminal of the conversion unit, and can obtain a first analog adjustment signal according to the second code value, and adjust the analog signal transmitted by the conversion unit according to the first analog adjustment signal to obtain a target signal. In the present application, the conversion unit converts the received first code value into an analog signal, and then the first adjustment unit can adjust the analog signal, so that the finally obtained target signal can be more accurate and effective.

[0034] 2 is a schematic diagram of a D / A conversion circuit according to another embodiment of the present application. The D / A conversion circuit 200 includes a conversion unit 210 and a first adjustment unit 220, and may further include a second adjustment unit 230.

[0035] In another embodiment, the second adjusting unit 220 further includes a third code value receiving terminal 231 for receiving a third code value, and a signal input terminal 232 connected to the signal output terminal 223 of the first adjusting unit 220. The second adjusting unit 220 obtains a second analog signal according to the third code value, and adjusts the analog signal transmitted by the conversion unit 210 according to the second analog signal.

[0036] One method is the N b The bit may be referred to as the third code value, V dac_b is the second analog signal after conversion, which may be called the output voltage signal of the second adjustment unit. The third code value may be a set of parallel encoded signals generated by a digital signal system, or may be a binary code value. For example, the third code value may be a 2-bit binary code value, a 4-bit binary code value, an 8-bit binary code value, or a 16-bit binary code value, and the specific bit number is not explicitly limited here and can be selected according to the actual situation.

[0037] In one embodiment, the second adjustment unit 230 may be composed of a plurality of switches and unit resistors, and the number of the switches and resistors is determined by the third code value, and the third code value has a variation range of 0 to 2. Nb -1 and 2 Nb N analog output voltages can be obtained, where N b 2, the second adjusting unit, in addition to including the third code value receiving terminal 231, may further include a signal output terminal 232 and a positive and negative terminal of a reference voltage, and the positive terminal of the reference voltage is V REF+ and the negative terminal of the reference voltage is VREF- It is.

[0038] In another embodiment, the first code value generated by the digital signal system is m b "0" and n b may consist of m "1"s, where m b +n b =N b When the third code value has a "0", the internal switch of the second regulating unit 230 is connected to the negative terminal V REF- , and when the third code value has a "1", the internal switch of the second regulating unit 230 is connected to the positive terminal V REF+ Through the series and parallel connection of resistors, the embodiment of the present invention can adjust the output voltage Vcc by the second adjustment unit 230. REF+ )-(V REF- ) can be obtained.

[0039] One method is m b =N b , n b If m = 0, the output of the second adjustment unit 230 is the minimum value, and the number of bits of the third code value at this time is all 0. For example, m b =3, n b If m = 0, the corresponding third code value is 000. b =0, n b =N b , the output of the second adjusting unit 230 is the maximum value, and the number of bits of the third code value is all 1. For example, m b =0, n b If = 3, the corresponding third code value is 111. The least significant bit (LSB) of the second adjustment unit 230 is N b The least significant bit of the bit is the minimum change in the output corresponding to the least significant bit.

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number

[0040] In an embodiment of the present invention, the first adjusting unit 220 may be composed of a plurality of switches and unit resistors. The first adjusting unit 220 may be called a summing circuit. The first input of the first adjusting unit 220 is c is a binary code value of N bits, c The binary code value of the bit is the second code value. c The most significant bit of the (N) bit code value is for selecting the output range of the transform unit 110, and the remaining N c -1 bit is for adjusting the magnitude of the LSB voltage of the conversion unit 210. c- By adjusting 1 bit, 2 Nc-1 The voltage value of the least significant bit (LSB) can be obtained.

[0041] Alternatively, the second and third inputs of the first adjustment unit 220 may be connected to the positive and negative terminals of the reference voltage V REF+ , V REF- and the fourth input and the fifth input of the first regulating unit 220 are the output voltage of the conversion unit 210 and the output voltage of the second regulating unit 230 respectively. The output voltage of the conversion unit 210 and the second regulating unit 230 are outputted, and outputted by the first regulating unit 220 after being processed by the first regulating unit 220, to output a flexibly regulated analog voltage. The output voltage of the first regulating unit 220 drives a capacitive load, or drives a resistive load, a capacitive load with a specific requirement for speed, etc. through a buffer circuit.

[0042] In another embodiment, the D / A conversion circuit 200 is connected to the first adjustment unit 220 and receives the target signal (V dac 3, the load 240 may include a resistor R Land capacitor C L and a resistor R L has a first connection terminal connected to the first adjustment unit 220 via a node D0, a second connection terminal connected to a node D1, and a capacitor C L The first connection terminal is connected to node D1, and the second connection terminal is grounded (GND). The load 240 may be determined by a sub-circuit, and in the case where a large capacitor or resistor load needs to be driven, a buffer circuit can be inserted between the load 240 in the embodiment of the present invention.

[0043] In addition, the conversion unit 210 in the D / A conversion circuit 200 can output as a master circuit, the second adjustment unit 230 can output as a slave circuit, and the first adjustment unit 220 can play the role of control adjustment. When the conversion unit 210 outputs an analog voltage having a certain range, in the embodiment of the present invention, the second adjustment unit 230 can be controlled to adjust the common mode voltage output from the conversion unit 210, and the common mode voltage can be within 2 Nb -One kind of adjustment can be realized. The first adjustment unit 220 can simultaneously adjust the minimum change amount LSB of the conversion unit 210 and the second adjustment unit 230. As another method, in the embodiment of the present invention, the conversion unit 210 can output as a slave circuit and the second adjustment unit 230 can output as a master circuit through adjustment, and the control action of the first adjustment unit 220 does not change.

[0044] As described above, the conversion unit 210 converts the first code value (N a The second adjusting unit 230 converts the third code value (N bThe first adjusting unit 220 converts the analog output of the conversion unit 210 (a binary code value of 10 bits) into a second analog voltage proportional to the positive and negative reference voltages. The first adjusting unit 220 adds the analog output of the conversion unit 210 and the analog output of the second adjusting unit 230 to obtain a final analog output voltage, i.e., obtain the target signal. The load 240 is the output drive level of the entire analog voltage, and is generally a capacitive load.

[0045] As can be seen from the above description, the conversion unit 210 may include a switch and a unitary resistor element, and its input is the first code value (N a bit code value signal) and the positive and negative terminals of the reference voltage V REF+ and V REF- The first code value (N a A "0" or "1" in the 1-bit code value signal turns it on, and V REF+ Or V REF- By the voltage division process of the internal resistors, the code value and the corresponding analog signal V dac_a Get the.

[0046] 4, the conversion unit may include m second resistor selection subunits 213. Between each two adjacent second resistor selection subunits 213, a third resistor 214 is provided, electrically connected to the adjacent second resistor selection subunits 213. The second resistor selection subunit also includes a fourth resistor 2131 and a second switch element 2132. The second switch element 2132 has a control terminal receiving the first code value, a second connection terminal connected to the first connection terminal of the fourth resistor 2131, and a second connection terminal connected to the third resistor 214.

[0047] Also, as can be seen from FIG. 4, the conversion unit 210 converts K0, K1, . . . , K Na-2 , K Na-1 A switch and resistor R A_0 , R A_1 , … , R A_Na-1 , R A_Na and resistor RB_0 , R B_1 , … , R B_Na-3 , R B_Na-2 where R A_i = 2R(i = 0, 1, …, N a -1, N a ), R B_i =R(i=0, 1, …, N a -3, N a -2), R is the unit resistance. N a Binary code value of bit a Na-1 a Na-2 ...a2a1a0 controls the selection of the corresponding switch. Na-1 a Na-2 If the bit of a2a1a0 is "0", the corresponding bits of K0, K1, ..., K Na-2 , K Na-1 V REF- Connected to a Na-1 a Na-2 If the bit in a2a1a0 is "1", the corresponding bits in K0, K1, ..., K Na-2 , K Na-1 V REF+ The K0 switch is connected to N a A three-terminal interface element controlled by the a0 bit of the code value of the V REF- The second terminal is connected to V REF+ The third terminal is connected to resistor R A_1 It is connected to the first terminal of resistor R A_1 The second terminal of the A_0 The first terminal of and resistor R B_0 It is connected to the first terminal of resistor R A_0 The second terminal of REF- It is connected to resistor R B_0 The second terminal of the resistor R A_2 The first terminal of and resistor R B_1 It is connected to the first terminal of resistor R A_2 The second terminal of the N aThe switch K1 is controlled by the a1 bit of the 1-bit code value. The first terminal of the switch K1 is connected to V REF- and the second terminal is connected to V REF+ It is connected to resistor R B_1 The second terminal of the resistor R A_3 The first terminal of and resistor R B_2 It is connected to the first terminal of resistor R A_3 The second terminal of the N a The switch K2 is controlled by the a2 bit of the 1-bit code value. The first terminal of the switch K2 is connected to V REF- and the second terminal is connected to V REF+ It is connected to resistor R B_2 The second terminal of resistor R is connected to node A3. The subsequent connections follow the previous connection rules. B_Na-3 The second terminal of is node A. Na-2 Also, node A Na-2 is the resistance R A_Na-1 The first terminal of and resistor R B_Na-2 It is connected to the first terminal of resistor R A_Na-1 The second terminal of the switch K Na-2 The third terminal of switch K Na-2 is N a Bit code value of a Na-2 Bit: Switch K Na-2 The first terminal is V REF- and the second terminal is connected to V REF+ It is connected to resistor R B_Na-2 The second terminal of is node A. Na-1 Also, node A Na-1 is the resistance R A_Na is connected to the first terminal of the next stage adder circuit. a The binary code value of the N bits is the first code value, a -1 is m.

[0048] 5, the second switch element 2132 may include a second inverter 201, a second PMOS transistor 202, and a second NMOS transistor 203. The second inverter 201 has an input terminal receiving the first code value and an output terminal respectively connected to the gate of the second PMOS transistor 202 and the gate of the second NMOS transistor 203. The second PMOS transistor 202 has a source connected to the positive terminal of a reference voltage, a drain connected to the drain of the second NMOS transistor 203, and a source of the second NMOS transistor 203 connected to the negative terminal of a reference voltage.

[0049] In one specific embodiment, the second switch element 2132 is a four-port switch, the drain of 202 is connected to the drain of 203, and the drain of 202 is connected to the drain of node A in FIG. i (i=0, 1, …, N a-i ) is connected to the source of 203. REF- The input of the inverter 201 is connected to a a of the bit code value Na is connected to.

[0050] In another embodiment, the second adjusting unit 230 may include a switch and a unitary resistor element, and its input is a third code value (N b bit code value control signal) and the positive and negative terminals of the reference voltage V REF+ and V REF- Including. N b A "0" or "1" in the code value of a bit turns on and the corresponding V REF+ Or V REF- The corresponding switch is controlled to connect to the analog voltage V dac_b Get the.

[0051] 6, the second adjustment unit 230 may include n first resistor selection subunits 234. A first resistor 235 is provided between each pair of adjacent first resistor selection subunits 234, and is electrically connected to the adjacent first resistor selection subunits 234. The first resistor selection subunit 234 also includes a second resistor 2341 and a first switch element 2342. The first switch element 2342 has a control terminal that receives the third code value, a second connection terminal that is connected to the first connection terminal of the second resistor 2341, and a second connection terminal of the second resistor 2341 that is connected to the first resistor 235.

[0052] Also, as can be seen from FIG. 6, the second adjustment unit 230 has K0, K1, . . . , K Nb-2 , K Nb-1 A switch and resistor R A_0 , R A_1 , … , R A_Nb-1 , R A_Nb and resistor R B_0 , R B_1 , … , R B_Nb-3 , R B_Nb-2 where R A_i = 2R(i = 0, 1, …, N b -1, N b ), R B_i =R(i=0, 1, …, N b -3, N b -2), R is the unit resistance. N b Binary code value of bit a Nb-1 a Nb-2 ...a2a1a0 controls the selection of the corresponding switch. Nb-1 a Nb-2 If the bit of a2a1a0 is "0", the corresponding bits of K0, K1, ..., K Nb-2 , K Nb-1 V REF- Connected to a Nb-1 a Nb-2 If the bit in a2a1a0 is "1", the corresponding bits in K0, K1, ..., K Nb-2 , K Nb-1 V REF+ The K0 switch is connected to N bA three-terminal interface element controlled by the a0 bit of the code value of the V REF- The second terminal is connected to V REF+ The third terminal is connected to resistor R A_1 It is connected to the first terminal of resistor R A_1 The second terminal of the A_0 The first terminal and resistor R B_0 It is connected to the first terminal of resistor R A_0 The second terminal of REF- It is connected to resistor R B_0 The second terminal of the resistor R A_2 The first terminal and resistor R B_1 It is connected to the first terminal of resistor R A_2 The second terminal of the N b The switch K1 is controlled by the a1 bit of the 1-bit code value. The first terminal of the switch K1 is connected to V REF- and the second terminal is connected to V REF+ It is connected to resistor R B_1 The second terminal of the resistor R A_3 The first terminal and resistor R B_2 It is connected to the first terminal of resistor R A_3 The second terminal of the N b The switch K2 is controlled by the a2 bit of the 1-bit code value. The first terminal of the switch K2 is connected to V REF- and the second terminal is connected to V REF+ It is connected to resistor R B_2 The second terminal of resistor R is connected to node A3. The subsequent connections follow the previous connection rules. B_Nb-3 The second terminal of is node A. Nb-2 Also, node A Nb-2 is the resistance R A_Nb-1 The first terminal and resistor R B_Nb-2 It is connected to the first terminal of resistor R A_Nb-1 The second terminal of the switch K Nb-2 The third terminal of switch K Nb-2 is N aBit code value of a Nb-2 Bit: Switch K Nb-2 The first terminal is V REF- and the second terminal is connected to V REF+ It is connected to resistor R B_Nb-2 The second terminal of is node A. Nb-1 Also, node A Nb-1 is the resistance R A_Nb and is connected to the second terminal of the next stage adder circuit. N b The binary code value of the N bits is the third code value. b -1 is n.

[0053] 7, the first switch element 2342 may include a first inverter 204, a first PMOS transistor 205, and a first NMOS transistor 206. The first inverter 204 has an input terminal receiving the third code value and an output terminal respectively connected to the gate of the first PMOS transistor 205 and the gate of the first NMOS transistor 206. The first PMOS transistor 205 has a source connected to the positive terminal of a reference voltage, a drain connected to the drain of the first NMOS transistor 206, and a source of the first NMOS transistor 206 connected to the negative terminal of a reference voltage.

[0054] In one specific embodiment, the first switch element 2342 may be a four-port switch. The drain 206 is connected to the drain 205 and corresponds to node A in FIG. i (i=0, 1, …, N b-i ) is connected to the source of 205. REF- The input of the inverter 204 is connected to b Bit code value of a Nb is connected to.

[0055] In another embodiment, the first adjusting unit 220 may be composed of a switch and a resistor, the input of which is the second code value (N c bit code value control signal) and the positive and negative terminals of the reference voltage V REF+ and V REF-And, N a Bit and N b and an N-bit analog output voltage. c A "0" or "1" in the code value of a bit turns on and the corresponding V REF+ Or V REF- After the first adjustment unit 220 adds the two analog voltages, the final target signal V dac , and the target signal may be referred to as an analog voltage.

[0056] 8, the first adjusting unit 220 may include k third resistor selection sub-units 224, each of which may include a third switch element 2241 and a fifth resistor 2242, and the third switch element 2241 is connected to the fifth resistor 2242. As can be seen from FIG. 8, the first adjusting unit 220 may include k third resistor selection sub-units 224, each of which may include K0, K1, ..., K Nc-2 Single-ended switch and K Nc-1 A switch and resistor R C_0 , R C_1 , … , R C_Nc-3 , R C_Nc-2 and resistor R C_a , R C_b where R C_a =R C_b =R, R C_i =2 i R(i=0, 1, N c -3, N c -2), R is the unit resistance. N c Binary code value of bit C Nc-1 C Nc-2 …C2C1C0 controls the corresponding switch. C Nc-2 …C2C1C0, if the bit is “0”, the corresponding switch K0, K1, …, K Nc-2 is turned off. C Nc-2 …C2C1C0, if the bit is “1”, the corresponding switch K0, K1, …, K Nc-2 is turned on and the resistor connected in parallel with it is shorted. C Nc-1 If the bit is "0", switch KNc-1 V REF - is connected. C Nc-1 If the bit is "1", switch K Nc-1 V REF+ Node C is connected to a is the resistance R C_a is connected to the first terminal of resistor R C_a The other terminal of the switch K0 is connected to a node A0. The node A0 is also connected to a first terminal of the switch K0, a resistor R C_0 The first terminal of the resistor R C_b K0 is connected to the first terminal of N c The bit code value is controlled by the C0 bit. Resistor R C_b The second terminal of b It is connected to resistor R C_0 The second terminal of the switch K0 is connected to the node A1. The node A1 is also connected to the second terminal of the switch K0, the first terminal of the switch K1, and the resistor R C_1 K1 is connected to the first terminal of N c The bit code value is controlled by the C1 bit. Resistor R C_1 The second terminal of is connected to node A2. The subsequent connections follow the previous connection rules. Node A Nc-3 Switch K Nc-4 The second terminal of switch K Nc-3 The first terminal of the resistor R C_Nc-3 It is connected to the first terminal of K Nc-3 is the C of the Nc-bit code value Nc-3 It is controlled by the resistor R C_Nc-3 The second terminal of is node A. Nc-2 Also, node A Nc-2 Switch K Nc-3 The second terminal of switch K Nc-2 The first terminal of the resistor R C_Nc-2 It is connected to the first terminal of K Nc-2 is the C of the Nc-bit code value Nc-2 It is controlled by the resistor R C_Nc-2 The second terminal of is node A. Nc-1 Also, node A Nc-1 Switch K Nc-3 The second terminal and switch K Nc-1The first terminal of switch K Nc-1 The second and third terminals of REF- and V REF+ where N c The binary code value of the N bits is the second code value. c -1 is k.

[0057] 9, the third switch element 2241 may include a third inverter 207, a third PMOS transistor 208, and a third NMOS transistor 209. The third inverter 207 has an input terminal receiving the second code value and an output terminal connected to the gate of the third PMOS transistor 208. The third PMOS transistor 208 has a source connected to the drain of the third NMOS transistor 209 and a drain connected to the source of the third NMOS transistor 209.

[0058] As can be seen from FIG. 9, the input of inverter 207 is N c c in code value i (i=0, 1, …, N c-2 ) and is also connected to the gate of an NMOS transistor 209. The output of the inverter 207 is connected to the gate of a PMOS transistor 208. The source of the PMOS transistor 208 is connected to the drain of the NMOS transistor 209 and is also connected to a node A in FIG. i (i=0, 1, …, N c-1 The drain of the PMOS transistor 208 is connected to the source of the NMOS transistor 209 and is connected to node A in FIG. i-1 (i=0, 1, …, N c-1 )

[0059] In an embodiment of the present invention, the output V of the second adjustment unit 230 is adjusted by changing the third code value. dac_b , and the change can be processed by the first adjustment unit 220 to obtain V dac_b Based on V dac_aSimilarly, V is increased or decreased by changing the second code value in the embodiment of the present invention. dac_a and V dac_b The minimum change amount of V and V can be changed at the same time. In this way, the final output is finally obtained, i.e., V dac_a +V dac_b =V dac can be obtained.

[0060] The D / A conversion circuit according to the embodiment of the present application can realize the adjustment to the voltage range more simply and effectively by combining a conversion unit and a first adjustment unit. Specifically, the D / A conversion circuit can include a conversion unit and a first adjustment unit, the conversion unit includes a first code value receiving terminal for receiving a first code value, and can convert the first code value into an analog signal, and the first adjustment unit includes a second code value receiving terminal for receiving a second code value and a signal input terminal connected to a signal output terminal of the conversion unit, and can obtain a first analog adjustment signal according to the second code value, and adjust the analog signal transmitted by the conversion unit according to the first analog adjustment signal to obtain a target signal. In the present application, the conversion unit converts the received first code value into an analog signal, and then the first adjustment unit can adjust the analog signal, so that the finally obtained target signal can be more accurate and effective. In addition, the embodiments of the present invention can not only make the conversion unit a master circuit and the second adjustment unit a slave circuit, but also make the second adjustment unit a master circuit and the first adjustment unit a slave circuit, so that the setting of the D / A conversion circuit can be made more flexible and the voltage range can be adjusted, and therefore the present invention can be applied to a real-time voltage calibration system.

[0061] 10 is a flowchart of a D / A conversion method according to an embodiment of the present application. The D / A conversion method may include steps S210 to S220.

[0062] In step S210, a first code value is received and the first code value is converted into an analog signal.

[0063] In an embodiment of the present invention, when there is no first adjustment unit and no second adjustment unit, the output of the conversion unit can be expressed by the following equation:

[0064]

number

[0065] In order to better understand the corresponding relationship between the digital code value and the analog code value, in the embodiment of the present invention, a diagram as shown in FIG. 11 is provided, and the output analog voltage is V REF+ The first code value (N a For each bit code value, the number of output analog voltages is 2 Na The symbol "A" in FIG.

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[0066] In addition, when adding the second and first adjustment units, the target signal (total V dac The output of the

[0067]

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[0068] In the above formula, the first term is the two ranges, high and low, controlled by the most significant bit of the second code value, and the second and third terms are the analog output voltages of the conversion unit, where the first term is:

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[0069] In another embodiment, the most significant bit C of the Nc bits Nc-1is controlled to be "0", the corresponding relationship between the digital code and the analog voltage is as shown in FIG. 12. By controlling the second adjusting unit, the output common-mode voltage value of the conversion unit is adjusted, and the magnitude and range of the adjusted common-mode voltage can be controlled by the third code value. The minimum change amount of the conversion unit and the minimum change amount of the second adjusting unit can be determined by the magnitude of the resistance value of the third adjusting unit. The value represented by the symbol "A" in FIG. 12 is

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[0070] In another embodiment, the second code value (N c The most significant bit of the bit code value C Nc-1 If is controlled to be "1", the first code value (N aThe correspondence between the second code value (N bit digital code) and the analog voltage is as shown in FIG. 13. At this time, the corresponding initial voltage is c The third code value (N b By controlling the bit code value, the magnitude of the output common-mode voltage of the conversion unit can be adjusted. The value represented by the symbol "A" in Figure 13 is

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[0071] Also, the value represented by the symbol "Y1" in FIG.

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[0072] In step S220, the analog signal is conditioned to obtain a target signal.

[0073] In another embodiment, the step of adjusting the analog signal and obtaining a target signal may include obtaining a digital signal of a plurality of full code values, and adjusting an analog signal corresponding to the digital signal of the plurality of full code values ​​to obtain a D / A adjustment list, and obtaining the target signal corresponding to the analog signal based on the D / A adjustment list.

[0074] As can be seen from the above description, in the embodiment of the present invention, when obtaining a target signal corresponding to a digital signal, a D / A adjustment list can be first constructed, and then a target signal corresponding to an analog signal can be searched for based on the D / A adjustment list. Here, the D / A adjustment list can be obtained by obtaining a number of full code value digital signals, and adjusting the analog signals corresponding to the number of full code value digital signals. For example, the first code value is Na=000, VOUT=0V, Na=001, VOUT=0.1V, N a =010, VOUT=0.2V, Na=011, VOUT=0.3V. The third code value Nb, Na=000, VOUT=0.2V, Na=001, VOUT=0.3V, Na=010, VOUT=0.4V, Na=011, VOUT=0.5V is adjusted. Based on this, the second code value Nc, Na=000, VOUT=0.2V, Na=001, VOUT=0.25V, Na=010, VOUT=0.3V, Na=011, VOUT=0.35V is adjusted. These data can form a D / A adjustment list.

[0075] As described above, the embodiments of the present application provide a D / A conversion circuit and method. The D / A conversion circuit can realize the adjustment to the voltage range more simply and effectively by combining a conversion unit and a first adjustment unit. Specifically, the D / A conversion circuit can include a conversion unit and a first adjustment unit, the conversion unit includes a first code value receiving terminal for receiving a first code value, and can convert the first code value into an analog signal, and the first adjustment unit includes a second code value receiving terminal for receiving a second code value and a signal input terminal connected to a signal output terminal of the conversion unit, and can obtain a first analog adjustment signal according to the second code value, and adjust the analog signal transmitted by the conversion unit according to the first analog adjustment signal to obtain a target signal. In the present application, the conversion unit converts the received first code value into an analog signal, and then the first adjustment unit can adjust the analog signal, so that the finally obtained target signal can be more accurate and effective.

[0076] As can be seen from the above, a person skilled in the art should understand that all or some steps in the above disclosed methods, systems, and functional modules / units in the systems may be implemented as software (which may be realized by executable computer program code of a computing system), firmware, hardware, and appropriate combinations thereof. In hardware embodiments, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components. For example, one physical component may have multiple functions, and one function or step may be performed cooperatively by multiple physical components. Some or all of the physical components may be implemented as software executed by a processor such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit such as a dedicated integrated circuit.

[0077] Also, as known to those skilled in the art, communication media typically includes computer readable instructions, data structures, computer program modules or other data in a modulated data signal such as a carrier or other transport mechanism, and may include any information delivery media. Thus, the present invention is not limited to any particular combination of hardware and software.

[0078] The above is a more detailed description of the embodiments of the present invention with reference to specific embodiments, but it is not to be understood that the specific implementation of the present invention is limited to these descriptions. Those skilled in the art can make some simple deductions or substitutions without departing from the spirit of the present invention. All of these should be considered to be within the protection scope of the present invention.

[0079] This application claims priority to a Chinese patent application with application number 202011627453.9 filed on December 31, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. a conversion unit including a first code value receiving terminal for receiving a first code value, the conversion unit converting the first code value into an analog signal; A D / A conversion circuit including: a second code value receiving terminal for receiving a second code value; a signal input terminal connected to a signal output terminal of the conversion unit for obtaining an analog signal converted by the conversion unit; and a first adjustment unit for adjusting the analog signal converted by the conversion unit to obtain a target signal which is a final analog signal, and outputting the target signal from the signal output terminal, the first adjustment unit includes a plurality of third switch elements which are an alternative switch and a single-ended switch, and a plurality of fifth resistors, the plurality of fifth resistors being connected in series, one end of the plurality of fifth resistors connected in series has one end connected to the signal input terminal of the first adjustment unit and the other end connected to the adjacent fifth resistor, the other end of the plurality of fifth resistors connected in series has one end connected to the adjacent fifth resistor and the other end connected to the alternative switch, the third switch elements are bridge-connected from both ends of each of the fifth resistors other than the fifth resistor at the other end, each of the third switch elements is turned on or off based on a code value of a bit other than the most significant bit of the second code value, and when the third switch element is on, the fifth resistor is short-circuited by the third switch element, a signal output terminal of the first adjustment unit is provided at a node between one end of the fifth resistor at the one end and the signal input terminal of the first adjustment unit; the alternative switch includes a first terminal, a second terminal and a third terminal, the first terminal of the alternative switch is connected to the other end of the fifth resistor at the other end, the second terminal is connected to a positive terminal of a reference voltage, and the third terminal is connected to a negative terminal of a reference voltage, the alternative switch is conductive between the first terminal and the second terminal or between the first terminal and the third terminal based on a most significant bit of the second code value; a second adjusting unit including a third code value receiving terminal for receiving a third code value and a signal input terminal connected to the signal output terminal of the first adjusting unit, the second adjusting unit obtaining a second analog signal according to the third code value and adjusting the analog signal transmitted by the conversion unit according to the second analog signal; The second adjustment unit includes n first resistor selection sub-units; Between each pair of adjacent first resistor selection subunits, a first resistor is provided, the first resistor being electrically connected to the adjacent first resistor selection subunits; the first resistor selection subunit includes a second resistor and a first switch element; a control terminal of the first switch element receiving the third code value; a second connection terminal of the first switch element is connected to a first connection terminal of the second resistor; a second connection terminal of the second resistor is connected to the first resistor; The conversion unit includes m second resistor selection sub-units; A third resistor is provided between each two adjacent second resistor selection subunits, the third resistor being electrically connected to the adjacent second resistor selection subunits; the second resistor selection subunit includes a fourth resistor and a second switch element; a control terminal of the second switch element receiving the first code value; a second connection terminal of the second switch element is connected to a first connection terminal of the fourth resistor; a second connection terminal of the fourth resistor being connected to the third resistor,

2. the first switch element includes a first inverter, a first PMOS transistor, and a first NMOS transistor; the first inverter has an input terminal for receiving the third code value and an output terminal respectively connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor; The first PMOS transistor has a source connected to a positive terminal of a reference voltage and a drain connected to a drain of the first NMOS transistor; The source of the first NMOS transistor is connected to the negative terminal of a reference voltage.

2. The D / A conversion circuit according to claim 1.

3. the second switch element includes a second inverter, a second PMOS transistor, and a second NMOS transistor; the second inverter has an input terminal for receiving the first code value and an output terminal respectively connected to the gate of the second PMOS transistor and the gate of the second NMOS transistor; the second PMOS transistor has a source connected to a positive terminal of a reference voltage and a drain connected to a drain of the second NMOS transistor; The source of the second NMOS transistor is connected to the negative terminal of a reference voltage.

2. The D / A conversion circuit according to claim 1.

4. the third switch element includes a third inverter, a third PMOS transistor, and a third NMOS transistor; the third inverter has an input terminal for receiving the second code value and an output terminal connected to the gate of the third PMOS transistor; the third PMOS transistor has a source connected to the drain of the third NMOS transistor and a drain connected to the source of the third NMOS transistor; 2. The D / A conversion circuit according to claim 1.

5. A D / A conversion method applied to the D / A conversion circuit according to any one of claims 1 to 4, comprising: receiving a first code value and converting the first code value to an analog signal; and conditioning the analog signal to obtain a signal of interest.

2. A D / A conversion method comprising:

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