Semiconductor device manufacturing method, semiconductor device, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device enabling suppression of deterioration of mobility of a carrier.SOLUTION: A manufacturing method of a semiconductor device of an embodiment, includes steps of: performing a first ion implantation that implants aluminum (Al) to a silicon carbide layer by a first project oersted range and a first dosage; performing a second ion implantation that implants a carbon (C) to the silicon carbide layer by a second dosage as a dose of ten times or more of a second project oersted range and the first dosage; performing a first heat treatment at 1600°C or more; performing an oxidation treatment for oxidating the silicon carbide; performing an etching processing for etching the silicon carbide layer under an atmosphere including hydrogen gas; forming a silicon oxide film on the silicon carbide layer; and forming a gate electrode on the silicon oxide film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device, a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has excellent physical properties, such as a band gap three times larger, a breakdown electric field strength about ten times larger, and a thermal conductivity about three times larger. By utilizing these properties, it is possible to realize semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] For example, when a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is formed using silicon carbide, problems such as a decrease in carrier mobility and fluctuations in threshold voltage occur. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-199922 A [Patent Document 2] JP 2014-143248 A [Patent Document 3] International Publication No. 2014 / 155651 [Non-patent literature]

[0005] [Non-Patent Document 1] K. Tachiki et al., “Formation of high-quality SiC(0001) / SiO2 structures by excluding oxidation process with H2 etching before SiO2 deposition and high-temperature N2 annealing”, Appl.Phys.Express 13,121002(2020). [Non-Patent Document 2] K. Tachiki et al., “Mobility improvement of 4H-SiC(0001)MOSFETs by three-step process of H2 etching, SiO2 deposition, and interface nitridation”, Appl.Phys.Express 14,031001(2021). Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor device capable of suppressing a decrease in carrier mobility. [Means for solving the problem]

[0007] A manufacturing method of a semiconductor device according to an embodiment includes performing a first ion implantation to implant aluminum (Al) into a silicon carbide layer in a first projected range and a first dose amount, performing a second ion implantation to implant carbon (C) into the silicon carbide layer in a second projected range and a second dose amount that is 10 times or more the first dose amount, performing a first heat treatment at 1600°C or higher, performing an oxidation treatment to oxidize the silicon carbide layer, performing an etching treatment to etch the silicon carbide layer in an atmosphere containing hydrogen gas, forming a silicon oxide film on the silicon carbide layer, and forming a gate electrode on the silicon oxide film. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 1 shows the crystal structure of a SiC semiconductor. [Diagram 3] FIG. 2 is a diagram showing element concentration distributions in the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is a schematic diagram showing a bonding state of nitrogen atoms in the semiconductor device according to the first embodiment. [Diagram 5] FIG. 2 is a process flow diagram of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 19] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 20] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 21] 5A to 5C are explanatory diagrams illustrating the operation and effect of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 22] FIG. 6 is a process flow diagram of a method for manufacturing a semiconductor device according to a second embodiment. [Diagram 23] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 24] FIG. 13 is a schematic diagram of a drive device according to a fifth embodiment. [Diagram 25] FIG. 13 is a schematic diagram of a vehicle according to a sixth embodiment. [Figure 26] FIG. 13 is a schematic diagram of a vehicle according to a seventh embodiment. [Figure 27] FIG. 13 is a schematic diagram of an elevator according to an eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described will be omitted as appropriate.

[0010] In the following description, n + , n, n - And, p + , p, p - When the notation "n" is used, it indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The types are simply n-type and p-type. + type, p - The type may be simply referred to as p-type. The impurity concentration of each region is represented by, for example, the impurity concentration value at the center of each region, unless otherwise specified.

[0011] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, Scanning Capacitance Microscopy (SCM). Distances such as the width and depth of the impurity region can be obtained by, for example, SIMS. Distances such as the width and depth of the impurity region can also be obtained from, for example, an SCM image.

[0012] The depth of the trench, the thickness of the insulating layer, etc. can be measured, for example, on a SIMS profile, a Transmission Electron Microscope (TEM) image, or a Scanning Electron Microscope (SEM) image.

[0013] The bonding states of silicon atoms, carbon atoms, nitrogen atoms, and oxygen atoms in the silicon carbide layer can be identified by, for example, X-ray photoelectron spectroscopy (XPS method). The concentrations of the various bonding states and the magnitude relationship of the concentrations can be determined by, for example, X-ray photoelectron spectroscopy (XPS method).

[0014] (First embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer, a gate electrode, a silicon oxide layer between the silicon carbide layer and the gate electrode, and a silicon oxide layer between the silicon carbide layer and the silicon oxide layer, the silicon oxide layer having a nitrogen concentration of 1×10 21 cm -3 The silicon carbide layer, the silicon oxide layer, and the region have a nitrogen concentration distribution having a peak in the region, and a wave number of 838 cm measured by an attenuated total reflection method (ATR method) of Fourier transform infrared spectroscopy (FTIR method) in a portion between the silicon oxide layer and a first position 100 nm away from the silicon oxide layer on the silicon carbide layer side. -1 Infrared absorption intensity at wavenumber 970cm -1 to the infrared absorption intensity is 1.0 or less, and the nitrogen concentration at a second position 1 nm away from the peak on the silicon oxide layer side is 1×1018 cm -3 and the concentration of carbon at the second location is 1×10 18 cm -3 or less, and the nitrogen concentration at a third position 1 nm away from the peak toward the silicon carbide layer is 1×10 18 cm -3 The following is the result.

[0015] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. The semiconductor device is a MOSFET 100. The MOSFET 100 is a Double Implantation MOSFET (DIMOSFET) in which a p-well and a source region are formed by ion implantation. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers.

[0016] The MOSFET 100 includes a silicon carbide layer 10, a gate insulating layer 28 (silicon oxide layer), a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, and an interface termination region 40 (region).

[0017] The silicon carbide layer 10 includes a drain region 12, a drift region 14 (first silicon carbide region), a p-well region 16 (second silicon carbide region), a source region 18, and a p-well contact region 20. The p-well region 16 has a channel portion 16a (portion).

[0018] The silicon carbide layer 10 is, for example, a single crystal of 4H-SiC. The silicon carbide layer 10 is located between a source electrode 34 and a drain electrode 36.

[0019] Figure 2 is a diagram showing the crystal structure of SiC semiconductor. A typical crystal structure of SiC semiconductor is a hexagonal system like 4H-SiC. One of the faces (top faces of the hexagonal prism) whose normal is the c-axis along the axial direction of the hexagonal prism is the (0001) face. A face equivalent to the (0001) face is called the silicon face (Si face) and is expressed as the {0001} face. Silicon atoms (Si) are arranged on the top surface of the silicon face.

[0020] The other face (top face of the hexagonal prism) whose normal is the c-axis along the axial direction of the hexagonal prism is the (000-1) face. The face equivalent to the (000-1) face is called the carbon face (C face) and is written as the {000-1} face. Carbon atoms (C) are arranged on the outermost surface of the carbon face.

[0021] On the other hand, the side surface of the hexagonal prism (cylinder surface) is an m-plane, which is equivalent to the (1-100) plane, i.e., a {1-100} plane. Also, the plane passing through a pair of non-adjacent ridges is an a-plane, which is equivalent to the (11-20) plane, i.e., a {11-20} plane. Both silicon atoms (Si) and carbon atoms (C) are arranged on the outermost surfaces of the m-plane and a-plane.

[0022] Hereinafter, an example will be described in which the front surface of silicon carbide layer 10 is inclined at an angle of 0 to 8 degrees with respect to the silicon surface, and the back surface is inclined at an angle of 0 to 8 degrees with respect to the carbon surface. The front surface of silicon carbide layer 10 has an off angle of 0 to 8 degrees with respect to the silicon surface.

[0023] The drain region 12 is + The drain region 12 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0024] The drift region 14 is provided on the drain region 12. The drift region 14 has an n - The drift region 14 is made of SiC of n-type. The drift region 14 contains, for example, nitrogen as an n-type impurity.

[0025] The n-type impurity concentration of the drift region 14 is lower than the n-type impurity concentration of the drain region 12. The n-type impurity concentration of the drift region 14 is, for example, 1×10 15 cm -3 More than 2×10 16 cm -3 The drift region 14 is, for example, an epitaxially grown layer of SiC formed on the drain region 12 by epitaxial growth.

[0026] The thickness of the drift region 14 is, for example, not less than 5 μm and not more than 100 μm.

[0027] The p-well region 16 is provided on a portion of the surface of the drift region 14. The p-well region 16 is located between the drift region 14 and the gate insulating layer 28. The p-well region 16 is made of p-type SiC.

[0028] The p-well region 16 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-well region 16 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0029] The depth of the p-well region 16 is, for example, not less than 0.4 μm and not more than 0.8 μm. The p-well region 16 functions as a channel region of the MOSFET 100.

[0030] The channel portion 16a is located between the gate insulating layer 28 and a first position (X1 in FIG. 1) that is 100 nm away from the gate insulating layer 28 toward the silicon carbide layer 10. The channel portion 16a is located in the p-well region 16.

[0031] In the channel portion 16a, a wave number of 838 cm is measured by the attenuated total reflection method (ATR method) of the Fourier transform infrared spectroscopy (FTIR method). -1 Infrared absorption intensity at wavenumber 970cm -1 The ratio of this to the infrared absorption intensity is 1.0 or less.

[0032] In the channel portion 16a, Z measured by Deep Level Transient Spectroscopy (DLTS) 1 / 2 The level density is 1×10 11 cm -3 The carbon vacancy density in the channel portion 16a is 1×10 11 cm -3 The following is the result.

[0033] The electron hole mobility of the channel portion 16a is, for example, 200 cm 2 / V·s or more. Hall mobility is the mobility of electrons measured by Hall Effect Measurement.

[0034] The source region 18 is provided on a part of the surface of the p-well region 16. The source region 18 is an n + The source region 18 is made of n-type SiC. The source region 18 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 18 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 It is less than cm.

[0035] The depth of the source region 18 is shallower than the depth of the p-well region 16. The depth of the source region 18 is, for example, not less than 0.2 μm and not more than 0.4 μm.

[0036] The p-well contact region 20 is provided on a part of the surface of the p-well region 16. The p-well contact region 20 is provided on the side of the source region 18. The p-well contact region 20 is + It is a type of SiC.

[0037] The p-well contact region 20 contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the p-well contact region 20 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0038] The depth of the p-well contact region 20 is shallower than the depth of the p-well region 16. The depth of the p-well contact region 20 is, for example, not less than 0.2 μm and not more than 0.4 μm.

[0039] The gate insulating layer 28 is provided between the silicon carbide layer 10 and the gate electrode 30. The gate insulating layer 28 is provided between the drift region 14 and the gate electrode 30, and between the p-well region 16 and the gate electrode 30. The gate insulating layer 28 is provided on the drift region 14 and the p-well region 16. The gate insulating layer 28 is continuously formed on the surfaces of the drift region 14 and the p-well region 16.

[0040] The gate insulating layer 28 includes silicon oxide. The gate insulating layer 28 is an example of a silicon oxide layer.

[0041] The gate insulating layer 28 has a thickness of, for example, 30 nm or more and 100 nm or less. The gate insulating layer 28 functions as a gate insulating layer for the MOSFET 100.

[0042] The interface termination region 40 is located between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 is located between the drift region 14 and the gate insulating layer 28, and between the p-well region 16 and the gate insulating layer 28. The interface termination region 40 contains nitrogen (N) as a terminating element that terminates dangling bonds of the silicon carbide layer 10. The interface termination region 40 is an example of a region.

[0043] The nitrogen concentration in the interface termination region 40 is, for example, 1×10 21 cm -3 That's all.

[0044] Fig. 3 is a diagram showing the element concentration distribution of the semiconductor device of the first embodiment. Fig. 3 is a diagram showing the element concentration distribution in the gate insulating layer 28, the interface termination region 40, and the silicon carbide layer 10. Fig. 3 shows the concentration distribution of nitrogen and carbon.

[0045] The nitrogen concentration distribution has a peak in the interface termination region 40. The peak nitrogen concentration is, for example, 1×10 22 cm -3 The full width at half maximum of the peak of the nitrogen concentration distribution is, for example, 1 nm or less. Nitrogen segregates at the interface between the silicon carbide layer 10 and the gate insulating layer 28.

[0046] The nitrogen concentration at the peak of the nitrogen concentration distribution is, for example, 1×10 21 cm -3 More than 4×10 23 cm -3 The following is the result.

[0047] The nitrogen concentration at the second position (X2 in FIG. 3) 1 nm away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28 side is 1×10 18 cm -3 The nitrogen concentration at a third position (X3 in FIG. 3) 1 nm away from the peak of the nitrogen concentration distribution on the silicon carbide layer 10 side is 1×10 18 cm -3 The following is the result.

[0048] 4A and 4B are schematic diagrams showing the bonding state of nitrogen atoms in the semiconductor device of the first embodiment, in which Fig. 4A shows the case where the nitrogen atom has three coordination numbers, and Fig. 4B shows the case where the nitrogen atom has four coordination numbers.

[0049] In the case of three-coordinated structure shown in Figure 4(a), the nitrogen atom bonds to three silicon atoms, and in the case of four-coordinated structure shown in Figure 4(b), the nitrogen atom bonds to four silicon atoms.

[0050] The amount of nitrogen atoms bonded to three silicon atoms is greater than the amount of nitrogen atoms bonded to four silicon atoms in interfacial termination region 40. In other words, the amount of nitrogen atoms with three coordinates is greater than the amount of nitrogen atoms with four coordinates in interfacial termination region 40.

[0051] For example, 90% or more of the nitrogen atoms present in the interface termination region 40 are tricoordinate nitrogen atoms. The concentration of tricoordinate nitrogen atoms is, for example, 1×10 21 cm -3 That's all.

[0052] The three-coordinate nitrogen atoms present in interface termination region 40 terminate dangling bonds on the surface of silicon carbide layer 10 .

[0053] The nitrogen atoms in interface termination region 40 replace the carbon atoms in the uppermost layer of silicon carbide layer 10. The nitrogen atoms in interface termination region 40 are bonded to silicon carbide layer 10 in a three-coordinated manner. The nitrogen atoms are at the positions of carbon atoms in the crystal structure of silicon carbide. The nitrogen atoms are tri-coordinated to the silicon atoms of silicon carbide layer 10.

[0054] The nitrogen atoms in the interface termination region 40 replace the carbon atoms in the bilayer constituting the uppermost layer of the silicon carbide layer 10. The termination element is ultimately bonded to the silicon carbide layer 10 in a three-coordinated manner. Excess silicon atoms and carbon atoms are released from the silicon carbide layer 10 toward the gate insulating layer 28. The nitrogen atoms are at the positions of the carbon atoms in the crystal structure of silicon carbide. Some of the silicon atoms on the uppermost surface enter the gate insulating layer 28, and the nitrogen atoms are in a three-coordinated manner with the silicon atoms of the silicon carbide layer 10.

[0055] Nitrogen atoms present in the bulk of silicon carbide layer 10 and substituting carbon sites in the crystal structure of silicon carbide have a four-coordinated structure. The four-coordinated nitrogen atoms function as an n-type dopant, thereby lowering the threshold voltage of the MOSFET.

[0056] The concentration of nitrogen atoms bonded to four silicon atoms at the third position X3 is 1×10 18 cm -3 In other words, the concentration of the 4-coordinate nitrogen atom at the third position X3 is 1 × 10 18 cm -3 The following is the result.

[0057] The carbon concentration distribution decreases from the interface termination region 40 toward the gate insulating layer 28. The carbon concentration at the second position X2 is 1×10 18 cm -3 The following is the result.

[0058] The concentration of the complex defects of carbon vacancies and nitrogen vacancies, which include carbon atoms bonded to oxygen atoms and nitrogen atoms bonded to oxygen atoms, at the second position X2 is, for example, 1×10 18 cm -3 The following is the result.

[0059] The complex defect of the carbon defect and the nitrogen defect has a CON bond state. The carbon and the nitrogen are formed by entering the silicon site of the silicon oxide of the gate insulating layer 28, and are adjacent to each other with one oxygen between them.

[0060] This complex defect is formed when a large amount of carbon and nitrogen are present during the formation of silicon oxide. A carbon defect that exists alone is formed when carbon occupies an oxygen site of silicon oxide. A nitrogen defect that exists alone is formed when nitrogen occupies an oxygen site of silicon oxide. Therefore, carbon defects and nitrogen defects that exist alone can be removed by oxidation.

[0061] However, complex defects are difficult to remove by oxidation and remain in silicon oxide, causing degradation of MOSFET characteristics. To form silicon oxide with fewer complex defects, it is preferable to use a manufacturing process that does not allow excess carbon and excess nitrogen to coexist in the silicon oxide.

[0062] The amount of nitrogen atoms bonding to four silicon atoms at a fourth position (X4 in FIG. 1) 5 nm away from gate insulating layer 28 toward silicon carbide layer 10 is, for example, 80% to 120% of the amount of nitrogen atoms bonding to four silicon atoms at a fifth position (X5 in FIG. 1) 5 μm away from gate insulating layer 28 toward silicon carbide layer 10. In other words, the amount of tetracoordinated nitrogen atoms at the fourth position X4 is 80% to 120% of the amount of tetracoordinated nitrogen atoms at the fifth position X5.

[0063] The concentration of nitrogen at the fourth position X4 is, for example, 1×10 18 cm -3 The concentration of nitrogen at the fifth position X5 is, for example, 1×10 18 cm -3 The nitrogen concentration at the fourth position X4 is, for example, 80% or more and 120% or less of the nitrogen concentration at the fifth position X5.

[0064] The fourth position X4 is located, for example, in the p-well region 16. The fifth position X5 is located, for example, in the drift region 14.

[0065] The gate electrode 30 is provided on the gate insulating layer 28. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the silicon carbide layer 10. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the drift region 14. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the p-well region 16.

[0066] The gate electrode 30 is, for example, polycrystalline silicon containing n-type or p-type impurities.

[0067] The interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is located between the gate electrode 30 and the source electrode 34. The interlayer insulating film 32 is, for example, a silicon oxide film.

[0068] The source electrode 34 is electrically connected to the source region 18 and the p-well contact region 20. The source electrode 34 also functions as a p-well electrode that applies a potential to the p-well region 16. The source electrode 34 is in contact with, for example, the source region 18 and the p-well contact region 20.

[0069] The source electrode 34 has a laminated structure of, for example, a Ni (nickel) barrier metal layer and an aluminum metal layer on the barrier metal layer. The nickel barrier metal layer and the silicon carbide layer may react to form nickel silicide (NiSi, Ni2Si, etc.). The nickel barrier metal layer and the aluminum metal layer may react to form an alloy.

[0070] The drain electrode 36 is provided on the side of the silicon carbide layer 10 opposite to the source electrode 34, that is, on the back surface side. The drain electrode 36 is electrically connected to the drain region 12. The drain electrode 36 contacts the drain region 12, for example.

[0071] The drain electrode 36 is, for example, nickel. The nickel may react with the drain region 12 to form nickel silicide (NiSi, Ni2Si, etc.).

[0072] In the first embodiment, the n-type impurity is, for example, nitrogen or phosphorus. It is also possible to use arsenic (As) or antimony (Sb) as the n-type impurity.

[0073] In the first embodiment, the p-type impurity is, for example, aluminum. As the p-type impurity, boron (B), gallium (Ga), and indium (In) can also be used.

[0074] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0075] The method for manufacturing a semiconductor device according to the first embodiment includes a first ion implantation step of implanting aluminum (Al) into a silicon carbide layer in a first projected range and a first dose amount, a second ion implantation step of implanting carbon (C) into the silicon carbide layer in a second projected range and a second dose amount that is 10 times or more the first dose amount, a first heat treatment step of 1600°C or more, an oxidation treatment step of oxidizing the silicon carbide layer, an etching treatment step of etching the silicon carbide layer in an atmosphere containing hydrogen gas, a silicon oxide film on the silicon carbide layer, and a gate electrode on the silicon oxide film. In addition, the method for manufacturing a semiconductor device according to the first embodiment includes a second heat treatment step in an atmosphere containing nitrogen after the formation of the silicon oxide film. The atmosphere is at least one atmosphere selected from the group consisting of a first atmosphere containing ammonia gas, a second atmosphere containing nitrogen gas and hydrogen gas, and a third atmosphere containing nitrogen gas and carbon dioxide gas.

[0076] Hereinafter, a case where the second heat treatment is performed in a first atmosphere containing ammonia gas (NH3) will be described as an example.

[0077] Fig. 5 is a process flow diagram of the method for manufacturing the semiconductor device of the first embodiment. Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, and Fig. 20 are explanatory diagrams of the method for manufacturing the semiconductor device of the first embodiment. Fig. 6, Fig. 7, Fig. 8, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, and Fig. 20 are cross-sectional views during the manufacturing process. Fig. 9 is a diagram showing the element distribution immediately after ion implantation.

[0078] As shown in FIG. 5, the method for manufacturing the semiconductor device according to the first embodiment includes the steps of preparing a silicon carbide layer (step S100), implanting aluminum ions (step S101), implanting carbon ions (step S102), implanting phosphorus ions (step S103), implanting aluminum ions (step S104), forming a carbon film (step S105), a first heat treatment (step S106), removing the carbon film (step S107), forming a field oxide film (step S108), forming a sacrificial oxide film (step S109), a hydrogen etching treatment (step S110), forming a silicon oxide film (step S111), a second heat treatment (step S112), a third heat treatment (step S113), forming a gate electrode (step S114), forming an interlayer insulating film (step S115), and forming source and drain electrodes (step S116).

[0079] In step S100, a silicon carbide layer 10 is prepared (FIG. 6). The silicon carbide layer 10 is + The drain region 12 and the n - The semiconductor device includes a drift region 14 of a type that is formed on the drain region 12 by, for example, an epitaxial growth method.

[0080] The drain region 12 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0081] The drift region 14 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drift region 14 is, for example, 1×10 15 cm -3 More than 2×10 16 cm -3 The thickness of the drift region 14 is, for example, not less than 5 μm and not more than 100 μm.

[0082] In step S101, for example, an insulating film is formed and the insulating film is patterned by photolithography and etching to form a first mask material 51. Then, using the first mask material 51 as an ion implantation mask, aluminum is ion-implanted into the drift region 14. The ion implantation forms a p-well region 16 (FIG. 7).

[0083] The ion implantation to form the p-well region 16 is an example of a first ion implantation. The aluminum ion implantation is performed with a first projected range and a first dose. The projected range is the average projected distance.

[0084] The first projected range is, for example, 0.1 μm to 0.6 μm. The first dose is, for example, 1×10 12 cm -2 More than 1×10 14 cm -2 The following is the result.

[0085] In step S102, carbon is ion-implanted into the p-well region 16 using the first mask material 51 as an ion implantation mask (FIG. 8). The carbon ion implantation into the p-well region 16 is an example of a second ion implantation. The carbon ion implantation is performed in a second projected range and with a second dose. Then, the first mask material 51 is removed.

[0086] The second projected range is, for example, 0.1 μm or more and 0.6 μm or less. The second projected range is, for example, 80% or more and 120% or less of the first projected range. The second dose is, for example, 10 times or more the first dose. The second dose is, for example, 10,000 times or less the first dose. The second dose is, for example, 1×10 15 cm -2 More than 1×10 18 cm -2 The following is the result.

[0087] Fig. 9 shows the concentration distribution of aluminum implanted into silicon carbide layer 10 by the first ion implantation, and the concentration distribution of carbon implanted into silicon carbide layer 10 by the second ion implantation. Fig. 9 shows the element distribution immediately after ion implantation.

[0088] 9, the second projected range Rp2 of the carbon ion implantation is located near the first projected range Rp1 of the aluminum ion implantation. Since the second dose of the carbon ion implantation is 10 times or more the first dose of the aluminum ion implantation, the carbon concentration distribution after the ion implantation completely covers, for example, the aluminum concentration distribution after the ion implantation.

[0089] The peak concentration of the aluminum distribution is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The peak concentration of the carbon distribution is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0090] In step S103, for example, an insulating film is formed and the insulating film is patterned by photolithography and etching to form a second mask material 52. Then, using the second mask material 52 as an ion implantation mask, phosphorus (P) is ion-implanted into the drift region 14 to form the source region 18 (FIG. 10). Thereafter, the second mask material 52 is removed.

[0091] In step S104, for example, an insulating film is formed and the insulating film is patterned by photolithography and etching to form a third mask material 53. Using the third mask material 53 as an ion implantation mask, aluminum is ion-implanted into the drift region 14 to form the p-well contact region 20 (FIG. 11).

[0092] Next, the third mask material 53 is removed (FIG. 12).

[0093] In step S105, a carbon film 54 is formed on the silicon carbide layer 10 (FIG. 13).

[0094] In step S106, a first heat treatment is performed. The first heat treatment is performed at 1600° C. or higher. The first heat treatment is performed, for example, at 2000° C. or lower. The first heat treatment is performed in a non-oxidizing atmosphere. The first heat treatment is performed, for example, in an inert gas atmosphere. The first heat treatment is performed, for example, in an argon gas atmosphere.

[0095] The first heat treatment activates the aluminum and phosphorus ions implanted into the silicon carbide layer 10. The first heat treatment is an activation annealing of the aluminum and phosphorus. Furthermore, the first heat treatment causes interstitial carbon formed by the carbon ion implantation into the silicon carbide layer 10 to fill carbon vacancies in the silicon carbide layer 10.

[0096] The carbon film 54 suppresses desorption of silicon and carbon from the silicon carbide layer 10 into the atmosphere during the first heat treatment. In addition, the carbon film 54 absorbs excess interstitial carbon in the silicon carbide layer 10 during the first heat treatment.

[0097] The first heat treatment is composed of a first step at a temperature of, for example, 1600° C. or higher and a second step at a temperature lower than the first step. The second step is, for example, at a temperature of 1000° C. or lower.

[0098] For example, in a first step, aluminum and phosphorus ions implanted into the silicon carbide layer 10 are activated, and the interstitial carbon fills the carbon vacancies. In a second step, for example at a low temperature, the excess interstitial carbon is expelled from the silicon carbide layer 10 and absorbed into the carbon film 54.

[0099] In step S107, the carbon film 54 is removed (FIG. 14). The carbon film 54 is removed by an ashing process using oxygen plasma. The carbon film 54 is removed in the oxygen plasma.

[0100] During the ashing process using oxygen plasma, the surface of silicon carbide layer 10 is oxidized. Ashing using oxygen plasma is one example of an oxidation process.

[0101] In step S108, a field oxide film 55 is formed on the silicon carbide layer 10 (FIG. 15). The field oxide film 55 contains oxygen. The field oxide film 55 is, for example, a silicon oxide film. The field oxide film 55 is deposited by, for example, a vapor phase deposition method. The field oxide film 55 is formed by, for example, a chemical vapor deposition method (CVD method) or a physical vapor deposition method (PVD method).

[0102] When depositing the field oxide film 55, the surface of the silicon carbide layer 10 is oxidized. The deposition process for depositing the field oxide film 55 is an example of an oxidation process. The field oxide film 55 functions as, for example, an element isolation region in a peripheral region (not shown).

[0103] Next, the field oxide film 55 is removed by using, for example, a wet etching method.

[0104] In step S109, a sacrificial oxide film 56 is formed on the silicon carbide layer 10 (FIG. 16). The sacrificial oxide film 56 is, for example, a silicon oxide film. The sacrificial oxide film 56 is formed by thermal oxidation of the surface of the silicon carbide layer 10.

[0105] When the sacrificial oxide film 56 is formed, the surface of the silicon carbide layer 10 is oxidized. The thermal oxidation process for forming the sacrificial oxide film 56 is an example of an oxidation process. By forming the sacrificial oxide film 56, for example, impurities and damage on the surface of the silicon carbide layer 10 are removed.

[0106] Next, the sacrificial oxide film 56 is removed by using, for example, a wet etching method.

[0107] In step S110, a hydrogen etching process is performed to etch the surface of the silicon carbide layer 10 in an atmosphere containing hydrogen gas (FIG. 17). The temperature of the hydrogen etching process is, for example, 1300° C. or more and 1500° C. or less. By the hydrogen etching process, the surface of the silicon carbide layer 10 is etched by, for example, 10 nm or more and 100 nm or less.

[0108] The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 90% or more. The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 95% or more. The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 100%. The atmosphere of the hydrogen etching process may contain, for example, argon gas.

[0109] In step S111, a silicon oxide film 57 is formed on the silicon carbide layer 10 (FIG. 18). The silicon oxide film 57 will eventually become the gate insulating layer .

[0110] The silicon oxide film 57 is formed by, for example, a vapor phase growth method at a low temperature and a low oxygen partial pressure. The silicon oxide film 57 is formed by, for example, a CVD method or a PVD method at a low temperature and a low oxygen partial pressure. The silicon oxide film 57 is a deposition film. The thickness of the silicon oxide film 57 is, for example, 30 nm or more and 100 nm or less.

[0111] The silicon oxide film 57 is formed by a CVD method using, for example, tetraethyl orthosilicate (TEOS) as a source gas. The silicon oxide film 57 is formed by a CVD method using, for example, dichlorosilane gas (SiH2Cl2) and dinitrogen monoxide gas (N2O) as source gas.

[0112] In step S112, a second heat treatment is performed in an atmosphere containing ammonia gas (NH3).

[0113] For example, ammonia gas (NH3) is supplied to a reactor in which the silicon carbide layer 10 is placed, and a heat treatment is performed.

[0114] The temperature of the second heat treatment is, for example, 1200° C. or more and 1600° C. or less.

[0115] The partial pressure of ammonia gas in the atmosphere for the second heat treatment is, for example, 90% or more.

[0116] The second heat treatment forms interface termination region 40 at the interface between silicon carbide layer 10 and the silicon oxide film (FIG. 19).

[0117] The second heat treatment also functions as a densifier anneal for the silicon oxide film, which becomes a high-density film.

[0118] In step S113, a third heat treatment is performed. The third heat treatment is performed in an atmosphere containing nitrogen oxide gas (NOx). The nitrogen oxide gas is, for example, nitric oxide gas (NO). The nitrogen oxide gas is, for example, dinitrogen monoxide gas (N2O).

[0119] For example, nitrogen oxide gas (NOx) is supplied to a reactor in which the silicon carbide layer 10 is placed, and heat treatment is performed.

[0120] The temperature of the third heat treatment is, for example, not less than 750° C. and not more than 1050° C. The temperature of the third heat treatment is, for example, lower than the temperature of the second heat treatment.

[0121] The partial pressure of the nitrogen oxide gas in the atmosphere for the third heat treatment is, for example, 10% or more.

[0122] The third heat treatment removes nitrogen from the silicon oxide film, forming a silicon oxide film with reduced nitrogen defects.

[0123] In step S114, the gate electrode 30 is formed on the gate insulating layer 28. The gate electrode 30 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0124] In step S115, the interlayer insulating film 32 is formed on the gate electrode 30 (FIG. 20). The interlayer insulating film 32 is, for example, a silicon oxide film.

[0125] In step S116, a source electrode 34 and a drain electrode 36 are formed. The source electrode 34 is formed on the source region 18 and the p-well contact region 20. The source electrode 34 is formed by, for example, sputtering nickel (Ni) and aluminum (Al).

[0126] The drain electrode 36 is formed on the back surface side of the silicon carbide layer 10. The drain electrode 36 is formed by, for example, sputtering nickel.

[0127] By the above manufacturing method, the MOSFET 100 shown in FIG. 1 is formed.

[0128] Next, the operation and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0129] The MOSFET 100 of the first embodiment can suppress a decrease in carrier mobility due to a reduced amount of carbon vacancies in the silicon carbide layer 10. Furthermore, in the manufacturing method of the MOSFET 100 of the first embodiment, the amount of carbon vacancies in the silicon carbide layer 10 is reduced by ion-implanting carbon in addition to ion-implanting aluminum and by subjecting the surface of the silicon carbide layer 10 to a hydrogen etching treatment after the oxidation treatment. This will be described in detail below.

[0130] When forming a MOSFET using silicon carbide, there is a problem of reduced carrier mobility. One of the factors that reduces carrier mobility is thought to be the intersurface state between the silicon carbide layer and the gate insulating layer. The interface state is thought to be generated by dangling bonds that exist on the surface of the silicon carbide layer.

[0131] The MOSFET 100 of the first embodiment includes an interface termination region 40 in which nitrogen is segregated between the silicon carbide layer 10 and the gate insulating layer 28. In the interface termination region 40, nitrogen atoms are bonded to silicon atoms in a three-coordinated manner, thereby reducing dangling bonds. Thus, a MOSFET in which a decrease in carrier mobility is suppressed is realized.

[0132] It is preferable that 90% or more of the nitrogen atoms present in the interface termination region 40 are tricoordinate nitrogen atoms, and more preferably 99% or more are tricoordinate nitrogen atoms. The concentration of tricoordinate nitrogen atoms is, for example, 1×10 21 cm -3 The concentration of 4-coordinate nitrogen atoms is, for example, 1×10 19 cm -3 The concentration of 4-coordinate nitrogen atoms is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 It is more preferable that:

[0133] From the viewpoint of suppressing the decrease in the carrier mobility of the MOSFET 100, the nitrogen concentration at the peak of the nitrogen concentration distribution in the interface termination region 40 is set to 1×1022 cm -3 It is preferable that the value is 5×10 or more. 22 cm -3 More preferably, it is equal to or greater than this.

[0134] If there is excess nitrogen, the nitrogen concentration at the peak of the nitrogen concentration distribution in the interface termination region 40 becomes a charge trap, so 23 cm -3 The following is preferred:

[0135] The nitrogen concentration at the peak of the nitrogen concentration distribution in the interface termination region 40 is 5.0×10 22 cm -3 ±5% is preferred. Peak nitrogen concentration is 5.0 x 10 22 cm -3 Within the range of ±5%, the MOSFET 100 exhibits good characteristics with little charge trapping.

[0136] The areal density of nitrogen in the interface termination region 40 is 1×10 14 cm -2 More than 2.5 x 10 15 cm -2 The surface density of nitrogen in the interface termination region 40 is preferably 1.4×10 15 cm -2 It is preferable that the area density of nitrogen is within the above range. When the area density of nitrogen is within the above range, the MOSFET 100 exhibits excellent characteristics with little charge trapping.

[0137] In addition, when silicon carbide is used to form a MOSFET, there are problems such as a decrease in carrier mobility and a change in threshold voltage. In addition, there are problems such as an increase in leakage current in the gate insulating layer and a decrease in reliability of the gate insulating layer. One of the factors causing the above problems is thought to be carbon defects and nitrogen defects present in the gate insulating layer.

[0138] It is believed that carbon defects and nitrogen defects form trap levels in the gate insulating layer, thereby causing the above problems.

[0139] In the MOSFET 100 of the first embodiment, the nitrogen concentration at the second position X2, which is 1 nm away from the peak of the nitrogen concentration distribution in the interface termination region 40 toward the gate insulating layer 28 side, is 1×10 18 cm -3 and the carbon concentration at the second position X2 is 1×10 18 cm -3 The MOSFET 100 has low concentrations of carbon and nitrogen in the gate insulating layer 28. Therefore, the amount of carbon defects and nitrogen defects in the gate insulating layer 28 is sufficiently reduced. This suppresses a decrease in carrier mobility, a change in threshold voltage, an increase in leakage current in the gate insulating layer, or a decrease in reliability of the gate insulating layer, which are caused by carbon defects or nitrogen defects.

[0140] The nitrogen concentration at a second position X2 1 nm away from the peak of the nitrogen concentration distribution in the interface termination region 40 toward the gate insulating layer 28 side is 1×10 17 cm -3 It is preferable that the value is less than 1×10 16 cm -3 It is more preferable that:

[0141] Another cause of the problem of reduced carrier mobility when forming a MOSFET using silicon carbide is believed to be the presence of carbon vacancies in silicon carbide layer 10.

[0142] For example, it is believed that the presence of carbon vacancies in the channel formation region of a MOSFET scatters carriers and reduces carrier mobility.

[0143] The MOSFET 100 of the first embodiment has a channel portion 16a between the gate insulating layer 28 and a first position X1 100 nm away from the gate insulating layer 28 on the silicon carbide layer 10 side, and has a Z 1 / 2 The level density is 1×10 11 cm -3 The following is the result.

[0144] Z measured by DLTS 1 / 2The level density corresponds to the density of carbon vacancies. Z 1 / 2 The level density is 1×10 11 cm -3 or less, the density of carbon vacancies under the gate insulating layer 28 is 1×10 11 cm -3 The density of carbon vacancies under the channel portion 16a of the gate insulating layer 28 is sufficiently reduced, so that a decrease in carrier mobility caused by carbon vacancies in the silicon carbide layer 10 is suppressed.

[0145] Z measured by DLTS 1 / 2 The level density is 5×10 10 cm -3 It is preferable that the value is less than 1×10 10 cm -3 More preferably, the density of carbon vacancies under the gate insulating layer 28 is less than 5×10 10 cm -3 It is preferable that the value is less than 1×10 10 cm -3 The following is even more preferable: The decrease in carrier mobility caused by carbon vacancies in silicon carbide layer 10 is further suppressed.

[0146] Measured by Attenuated Total Reflection (ATR) measurement using Fourier transform infrared spectroscopy (FTIR) at a wave number of 838 cm -1 The infrared absorption intensity at 838 cm corresponds to the density of carbon vacancies. -1 The infrared absorption at 838 cm corresponds to a residual product that is generated in the silicon carbide layer when the silicon carbide layer is oxidized. The residual product has Si-O bonds. -1 The infrared absorption of is due to the presence of Si-O bonds.

[0147] When the silicon carbide layer is oxidized, the silicon carbide lattice is distorted and carbon vacancies are formed, so that the density of carbon vacancies is high in the silicon carbide layer in the portion having a high density of residual products.

[0148] In the MOSFET 100 of the first embodiment, in a channel portion 16a between the gate insulating layer 28 and a first position X1 that is 100 nm away from the gate insulating layer 28 toward the silicon carbide layer 10, a wavelength of 838 cm is measured by an attenuated total reflection method (ATR method) of a Fourier transform infrared spectroscopy (FTIR method). -1 Infrared absorption intensity at wavenumber 970cm -1 The ratio of the infrared absorption intensity to the wave number of 970 cm is 1.0 or less. -1 The infrared absorption at 970 cm corresponds to the longitudinal optical phonon mode of silicon carbide. -1 The infrared absorption intensity at wave number 838 cm -1 It is used to normalize the intensity of infrared absorption.

[0149] The MOSFET 100 has a channel portion 16a of the p-well region 16 that has a wavenumber of 838 cm as measured by an attenuated total reflection method (ATR method) of a Fourier transform infrared spectroscopy (FTIR method). -1 Infrared absorption intensity at wavenumber 970cm -1 to the infrared absorption intensity is 1.0 or less, and the density of carbon vacancies is low in the p-well region 16 directly below the gate insulating layer 28. Therefore, a decrease in carrier mobility caused by carbon vacancies in the silicon carbide layer 10 is suppressed.

[0150] From the viewpoint of suppressing a decrease in the mobility of carriers, in the channel portion 16a of the p-well region 16, a wave number of 838 cm measured by an attenuated total reflection method (ATR method) of Fourier transform infrared spectroscopy (FTIR method) is set to 100 nm. -1 Infrared absorption intensity at wavenumber 970cm -1 The ratio of this to the infrared absorption intensity is preferably 0.5 or less, and more preferably 0.1 or less.

[0151] In MOSFET 100, the amount of nitrogen atoms bonding to four silicon atoms at a fourth position X4 located 5 nm away from gate insulating layer 28 toward silicon carbide layer 10 is 80% to 120% of the amount of nitrogen atoms bonding to four silicon atoms at a fifth position X5 located 5 μm away from gate insulating layer 28 toward silicon carbide layer 10. In other words, the amount of tetracoordinated nitrogen atoms at the fourth position X4 is 80% to 120% of the amount of tetracoordinated nitrogen atoms at the fifth position X5. The tetracoordinated nitrogen atoms function as donors.

[0152] The concentration of nitrogen at the fourth position, X4, is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is 2×10 16 cm -3 The concentration of nitrogen at the fifth position X5 is preferably 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is 2×10 16 cm -3 It is even more preferable that:

[0153] In the MOSFET 100, the density of carbon vacancies in the channel portion 16a is low, so that the density of carbon vacancies in the channel portion 16a is substantially equal to the density of carbon vacancies in the drift region 14. Therefore, the amount of nitrogen atoms with 4-coordinates filling the carbon vacancies in the channel portion 16a is substantially equal to the amount of nitrogen atoms with 4-coordinates filling the carbon vacancies in the drift region 14. Therefore, the amount of nitrogen atoms with 4-coordinates in the channel portion 16a is 80% or more and 120% or less of the amount of nitrogen atoms with 4-coordinates in the drift region 14.

[0154] In the MOSFET 100 of the first embodiment, the density of carbon vacancies in the channel portion 16a is sufficiently low. Therefore, the hole mobility of electrons in the channel portion 16a is 200 cm 2 / V·s or more. The hole mobility of electrons in the channel portion 16a is 350 cm2 / V s or more is preferable, and 450 cm 2 / V s or more is even more preferable.

[0155] The field effect mobility, which is an index of the on-current of a MOSFET, is determined by the proportion of mobile charge in the hole mobility. In other words, the field effect mobility is smaller than the hole mobility. At the MOS interface of silicon carbide, the proportion of mobile charge is low due to poor interface termination efficiency and a large number of defects in the substrate and gate insulating layer. Charges other than the mobile charge are trapped charges.

[0156] For example, it is possible to increase the proportion of mobile charges by optimizing the interface termination method and termination elements. However, if the Hall mobility is low, it is difficult to significantly improve the field effect mobility. To significantly improve the field effect mobility, it is necessary to increase the Hall mobility to 150 cm 2 It is desirable to improve this to more than / V s.

[0157] In the first embodiment, the density of carbon vacancies can be reduced, thereby significantly improving the hole mobility. The hole mobility can be, for example, 200 cm 2 / V s or more. By further reducing the density of carbon vacancies, 2 / V·s or more, even 450cm 2 / V s or higher can be achieved.

[0158] In the MOSFET 100 of the first embodiment, the nitrogen concentration at a third position X3 that is 1 nm away from the peak of the nitrogen concentration distribution in the interface termination region 40 toward the silicon carbide layer is 1×10 18 cm -3 The reason is as follows: Since the nitrogen concentration in the silicon carbide layer 10 in the vicinity of the gate insulating layer 28 is low, a high threshold voltage of the MOSFET 100 can be achieved.

[0159] The nitrogen concentration at a third position X3 1 nm away from the peak of the nitrogen concentration distribution in the interface termination region 40 toward the silicon carbide layer is 1×10 18 cm -3The concentration of nitrogen at the third position X3 is 1×10 17 cm -3 It is preferable that the value is less than 2×10 16 cm -3 It is more preferable that:

[0160] When manufacturing a MOSFET, the following three processes can be considered as manufacturing processes that generate carbon vacancies in the silicon carbide layer, which reduce carrier mobility.

[0161] The first process is ion implantation of impurities into the silicon carbide layer. Carbon vacancies and interstitial carbon are formed in the silicon carbide layer 10 due to the energy of the ion-implanted impurities. For example, in the p-well region, carbon vacancies and interstitial carbon are formed with a volume density approximately equal to the volume density of the implanted ions.

[0162] The second process is activation annealing to activate the impurities introduced into the silicon carbide layer by ion implantation. During activation annealing, the free energy of the silicon carbide layer system is reduced, and carbon vacancies and interstitial carbon are generated in the silicon carbide layer, increasing entropy. The higher the activation annealing temperature, the greater the amount of carbon vacancies and interstitial carbon generated. Since the formation of a silicon carbide layer by epitaxial growth is also a high-temperature process, the silicon carbide layer contains 10 13 cm -3 Carbon vacancies of the order of 1×10 14 cm -3 Carbon vacancies of the order are created.

[0163] The third process is a process for oxidizing the surface of the silicon carbide layer. For example, this can be an ashing process, a deposition process for depositing an oxide film, or a thermal oxidation process for forming a thermal oxide film. Another example is a process using nitrogen oxide gas to form an interface termination region. During oxidation, strain is induced in the surface of the silicon carbide layer, resulting in the formation of carbon vacancies and interstitial carbon in the silicon carbide layer. The surface is significantly distorted by oxidation, and the amount of carbon vacancies and interstitial carbon increases by 1×10 18 cm -3Carbon vacancies of the order are created.

[0164] In the method for manufacturing the MOSFET 100 of the first embodiment, after aluminum ion implantation is performed in the silicon carbide layer 10 to form the p-well region 16, carbon ion implantation is performed in the same region of the silicon carbide layer 10. The second dose of carbon is at least ten times the first dose of aluminum.

[0165] According to the manufacturing method of the MOSFET 100 of the first embodiment, a large amount of excess interstitial carbon is present in the p-well region 16 due to the carbon ion implantation. The carbon vacancies generated by the aluminum ion implantation are filled with the excess interstitial carbon by the heat treatment performed after the carbon ion implantation. Therefore, the amount of carbon vacancies in the p-well region 16 is reduced.

[0166] From the viewpoint of maintaining an appropriate p-type impurity concentration in the p-well region 16, the first dose of aluminum is set to 1×10 14 cm -2 From the viewpoint of reducing the amount of carbon vacancies in the p-well region 16, the second dose of carbon is preferably 1×10 15 cm -2 It is preferable that the concentration is 1×10 or more. 16 cm -2 More preferably, it is equal to or greater than this.

[0167] From the standpoint of reducing the amount of carbon vacancies in the p-well region 16, the second dose of carbon is preferably 100 times or more than the first dose of aluminum.

[0168] From the viewpoint of reducing the amount of carbon vacancies in the p-well region 16, the second projected range Rp2 of the carbon ion implantation is preferably 80% or more and 120% or less of the first projected range Rp1 of the aluminum ion implantation, and more preferably 90% or more and 110% or less.

[0169] By bringing the first projected range Rp1 and the second projected range Rp2 closer to each other, the carbon concentration distribution after ion implantation can easily completely cover the aluminum concentration distribution after ion implantation. The carbon concentration distribution after ion implantation completely covers the aluminum concentration distribution after ion implantation, thereby reducing the amount of carbon vacancies in the p-well region 16.

[0170] In order to maintain the depth of the p-well region 16 appropriately, the first projected range Rp1 and the second projected range Rp2 are preferably 0.6 μm or less.

[0171] In the manufacturing method of the MOSFET 100 of the first embodiment, a large amount of excess interstitial carbon is present in the silicon carbide layer 10 during the first heat treatment for activating aluminum introduced into the silicon carbide layer 10 by ion implantation. The presence of a large amount of interstitial carbon increases the entropy required to reduce the free energy of the silicon carbide layer 10. Therefore, an increase in carbon vacancies in the silicon carbide layer 10 due to the first heat treatment is suppressed.

[0172] In the manufacturing method of the MOSFET 100 of the first embodiment, the presence of a large amount of excess interstitial carbon in the silicon carbide layer 10 during the first heat treatment inhibits aluminum atoms from entering the carbon sites of silicon carbide. This promotes the entry of aluminum atoms into the silicon sites of silicon carbide. This improves the activation rate of aluminum.

[0173] In the method for manufacturing the MOSFET 100 of the first embodiment, a large amount of excess interstitial carbon is present in the silicon carbide layer 10 during the first heat treatment, so that an increase in the amount of carbon vacancies in the silicon carbide layer 10 is suppressed even if the first heat treatment is performed at a high temperature. This makes it possible to set the first heat treatment at a high temperature, thereby improving the activation rate of aluminum.

[0174] From the viewpoint of improving the activity rate of aluminum, the temperature of the first heat treatment is preferably 1850° C. or higher, more preferably 1900° C. or higher, and even more preferably 1950° C. or higher. From the viewpoint of carrying out an efficient process, the temperature of the first heat treatment is preferably 2000° C. or lower. From the viewpoint of the activity rate, no significant increase in the activity rate can be expected even if the temperature exceeds 2000° C.

[0175] The first heat treatment is preferably composed of a first step at 1600° C. or higher and a second step at a lower temperature than the first step. The second step is preferably at 1000° C. or lower. The heat treatment time of the second step is longer than that of the first step.

[0176] In the first step, the aluminum and phosphorus ions implanted into the silicon carbide layer 10 are activated, and the interstitial carbon fills the carbon vacancies. Even after the carbon vacancies are filled, there is still excess interstitial carbon. Then, in the second step at a low temperature, the excess interstitial carbon is expelled from the silicon carbide layer 10 and absorbed into the carbon film 54.

[0177] By performing the second step at a low temperature, an increase in carbon vacancies is suppressed. The second step makes it possible to reduce interstitial carbon in the silicon carbide layer 10. Therefore, an increase in carbon defects in the gate insulating layer 28 can be suppressed in the heat treatments after the first heat treatment.

[0178] Fig. 21 is an explanatory diagram of the action and effect of the method for manufacturing a semiconductor device according to the first embodiment, and is a diagram showing the relationship between the depth from the surface of a silicon carbide layer and the density of carbon vacancies.

[0179] As shown in FIG. 21, when carbon ion implantation is performed in addition to aluminum ion implantation, the carbon vacancy density can be reduced to 1E11 cm unless the silicon carbide layer is oxidized. -3However, when an oxidation treatment is performed after the ion implantation, the carbon vacancy density increases, for example, from the surface of the silicon carbide layer to a depth of 25 nm. This is believed to be because carbon vacancies are generated by strain generated on the surface of the silicon carbide layer due to the oxidation treatment.

[0180] Carbon vacancy density is 1E11cm -3 To achieve the above, the first heat treatment is preferably composed of a first step at 1600°C or higher and a second step at a lower temperature than the first step. The second step is preferably at 1000°C or lower. For example, the heat treatment time of the second step is longer than that of the first step. In the first step, interstitial carbon fills the carbon vacancies. Even when the carbon vacancies are filled, there is still excess interstitial carbon. Then, in the low-temperature second step, the excess interstitial carbon is expelled from the silicon carbide layer and absorbed into the carbon film covering the surface during annealing.

[0181] By increasing the temperature and time of the first heat treatment, the carbon vacancy density of the silicon carbide layer is increased to 1E10 cm -3 Even when oxidation treatment is performed, the carbon vacancy density can be reduced to 1E11 cm3 or less from the position 25 nm deep from the surface of the silicon carbide layer. -3 The carbon vacancy density is set to 1E10 cm or less from the position 50 nm deep. -3 It is possible to have the following:

[0182] 21, when carbon ion implantation is not performed in addition to aluminum ion implantation, the carbon vacancy density increases, for example, from the surface of the silicon carbide layer to a depth of 200 nm when an oxidation treatment is performed after the ion implantation. When carbon ion implantation is not performed, damage from the aluminum ion implantation remains, and the carbon vacancy density of the silicon carbide layer before the oxidation treatment is 1E14 cm -3 This is believed to be because the carbon vacancy density is so high that oxygen diffusion through the carbon vacancies is promoted, causing distortion of the silicon carbide deep into the silicon carbide layer. For example, even when the p-well region is formed by epitaxial growth rather than ion implantation, the carbon vacancy density in the silicon carbide layer is 1E13 cm-3 As described above, it is believed that the diffusion of oxygen via the carbon vacancies is promoted, distortion of the silicon carbide occurs in a deep region of the silicon carbide layer, and the density of carbon vacancies increases.

[0183] In the method for manufacturing the MOSFET 100 of the first embodiment, after the silicon carbide layer 10 is subjected to an oxidation treatment, the surface of the silicon carbide layer 10 is etched by a hydrogen etching treatment. The oxidation treatment is, for example, an ashing treatment using oxygen plasma for removing the carbon film 54, a deposition treatment for depositing the field oxide film 55, and a thermal oxidation treatment for forming the sacrificial oxide film 56.

[0184] The hydrogen etching process removes the areas with high carbon vacancy density, thereby reducing the carbon vacancy density at the surface of the silicon carbide layer 10. Thus, the amount of carbon vacancies in the p-well region 16 directly below the gate insulating layer 28 is reduced.

[0185] From the viewpoint of reducing the carbon vacancy density on the surface of silicon carbide layer 10, the amount of etching of the surface of silicon carbide layer 10 by hydrogen etching is at least 10 nm. It is preferably 15 nm or more, more preferably 25 nm or more, and even more preferably 50 nm or more. Since there is no change in the carbon vacancy density even if hydrogen etching of 100 nm or more is performed, etching of 100 nm or more is not necessarily required.

[0186] Carbon vacancy density is 1E17cm -3 So, the Hall mobility is 130 cm 2 / V s, and the carbon vacancy density is expected to be 1E16cm -3 So, the Hall mobility is 160 cm 2 / V s, and the carbon vacancy density is expected to be 1E15cm -3 So, the Hall mobility is 180cm 2 / V s, and the carbon vacancy density is expected to be 1E14 cm -3 So, the Hall mobility is 200 cm 2 / V s, and the carbon vacancy density is expected to be 1E13cm -3 So, the Hall mobility is 250 cm 2 / V s, and the carbon vacancy density is expected to be 1E12 cm -3 So, the Hall mobility is 300 cm 2 / V s, and the carbon vacancy density is expected to be 1E11cm -3 So, the Hall mobility is 350 cm 2 / V s, and the carbon vacancy density is expected to be 5E10cm -3 So, the Hall mobility is 400 cm 2 / V s, and the carbon vacancy density is expected to be 1E10cm -3 So, the Hall mobility is 450 cm 2 / V·s is expected.

[0187] If the amount of etching of the surface of the silicon carbide layer 10 by the hydrogen etching process is 15 nm or more, the hole mobility is 200 cm 2 / V s. The Hall mobility is about 200 cm 2 The value of 350 cm / V·s is difficult to achieve unless a large amount of carbon ion is implanted in addition to aluminum ion implantation, and hydrogen etching is performed after oxidation. If the etching amount is 25 nm or more, the Hall mobility is 350 cm 2 / V s. If the etching amount is 50 nm or more, the hole mobility is 450 cm 2 / V s is reached.

[0188] In the manufacturing method of the MOSFET 100 of the first embodiment, the gate insulating layer 28 is formed by a vapor phase epitaxy at a low temperature and a low oxygen partial pressure. Therefore, oxidation of the surface of the silicon carbide layer 10 is suppressed compared to thermal oxidation. Therefore, an increase in carbon vacancies in the silicon carbide layer 10 during the formation of the gate insulating layer 28 is suppressed.

[0189] Furthermore, in the method for manufacturing MOSFET 100 of the first embodiment, interface termination region 40 is formed by a second heat treatment in an atmosphere containing ammonia gas (NH3). By forming interface termination region 40 in an atmosphere containing ammonia gas without interfacial oxidation, an increase in carbon vacancies in silicon carbide layer 10 is suppressed.

[0190] Furthermore, since the second heat treatment does not involve oxidation, excess carbon is not released from the silicon carbide layer 10. This prevents excess carbon from diffusing into the gate insulating layer and forming carbon defects in the gate insulating layer.

[0191] It is preferable to adjust the conditions of the second heat treatment so as to form interface termination region 40 containing sufficient nitrogen. The second heat treatment is performed, for example, in a low-oxygen state where the oxygen partial pressure is 1 ppm or less. The second heat treatment is, for example, a high-temperature treatment at 1200°C or higher and 1600°C or lower. From the viewpoint of increasing the nitrogen concentration in interface termination region 40, the second heat treatment is preferably performed at 1300°C or higher, and more preferably at 1400°C or higher.

[0192] Even if nitrogen is introduced into the gate insulating layer, if carbon does not coexist in the gate insulating layer, complex defects (CON defects) due to nitrogen and carbon are not formed. Therefore, it is possible to perform the second heat treatment for a long time. Therefore, it is possible to prevent the interface termination region 40 from being filled with a sufficient amount of nitrogen, for example, 1×10 22 cm -3 The second heat treatment is performed, for example, at 1300° C. for 1 hour, or at 1400° C. for 30 minutes.

[0193] For example, it is possible to form interface termination region 40 with interfacial oxidation, such as by high-temperature treatment with nitric oxide (NO). In this case, carbon vacancies are formed in the silicon carbide layer due to strain generated at the surface of the silicon carbide layer during the interfacial oxidation. Therefore, even if the carbon vacancies are reduced before forming interface termination region 40, the carbon vacancies will increase again. In other words, when forming interface termination region 40 with interfacial oxidation, reducing the carbon vacancies before forming interface termination region 40 does not result in a final reduction in carbon vacancies.

[0194] Furthermore, when interface termination region 40 is formed by performing high-temperature treatment using nitric oxide (NO) or the like, which involves interface oxidation, the substrate is oxidized and excess carbon is released from silicon carbide layer 10. The released carbon diffuses into the gate insulating layer, causing a problem of a large amount of carbon defects being generated in the gate insulating layer.

[0195] Note that even if the second heat treatment is performed in a second atmosphere containing nitrogen gas and hydrogen gas, or a third atmosphere containing nitrogen gas and carbon dioxide gas, an increase in carbon vacancies in silicon carbide layer 10 can be suppressed.

[0196] In the method for manufacturing the MOSFET 100 of the first embodiment, after the second heat treatment for forming the interface termination region 40, a third heat treatment is performed in an atmosphere containing nitrogen oxide gas (NOx).

[0197] The third heat treatment removes nitrogen from the gate insulating layer 28. The third heat treatment forms a gate insulating layer 28 with reduced nitrogen defects.

[0198] In order to suppress oxidation of the surface of silicon carbide layer 10 due to the third heat treatment, the temperature of the third heat treatment is preferably lower than the temperature of the second heat treatment.

[0199] From the viewpoint of reducing nitrogen defects in the gate insulating layer 28, the temperature of the third heat treatment is preferably 800° C. or higher, more preferably 850° C. or higher, and further preferably 925° C. or higher.

[0200] From the viewpoint of reducing nitrogen defects in the gate insulating layer 28, the nitrogen oxide gas in the third heat treatment is preferably dinitrogen monoxide gas (N2O), which has a high oxidizing power.

[0201] Moreover, from the viewpoint of suppressing oxidation of silicon carbide layer 10, the temperature of the third heat treatment is preferably 1000° C. or less, and more preferably 950° C. or less.

[0202] In the method for manufacturing the MOSFET 100 of the first embodiment, the second heat treatment forms the interface termination region 40 containing sufficient nitrogen. The second heat treatment is preferably performed in a low-oxygen state with an oxygen partial pressure of 1 ppm or less, at a high temperature, and for a long time. The second heat treatment improves the oxidation resistance of the silicon carbide layer 10.

[0203] Therefore, even if the third heat treatment is performed at a high temperature of, for example, 1050° C., if the third heat treatment is performed for, for example, 5 minutes or less, oxidation of the surface of the silicon carbide layer 10 is suppressed. In order to reliably expel nitrogen from within the gate insulating layer 28, a long-term treatment at a low temperature is preferable, in which there is less concern about oxidation of the surface of the silicon carbide layer 10. For example, the third heat treatment is preferably a heat treatment using nitrous oxide gas (NO), at 950° C., and for 3 hours.

[0204] After the third heat treatment, for example, by measuring that no capacitance change occurs in the MOS capacitor of the gate, it can be confirmed that no oxidation has occurred on the surface of the silicon carbide layer 10. Alternatively, by directly observing a TEM image, it can be confirmed that no oxide layer has grown on the surface of the silicon carbide layer 10.

[0205] It can be said that the third heat treatment is performed on the basis that the second heat treatment improves the oxidation resistance of silicon carbide layer 10. If the second treatment is not performed appropriately, the surface of silicon carbide layer 10 will be oxidized by the third treatment. This is not preferable because carbon vacancies will be generated in silicon carbide layer 10 due to the oxidation.

[0206] In the manufacturing method for the MOSFET 100 of the first embodiment, oxidation of the surface of the silicon carbide layer after forming the gate insulating layer 28 is suppressed, thereby reducing the amount of carbon in the gate insulating layer 28 and also reducing the amount of carbon defects in the gate insulating layer 28.

[0207] Furthermore, in the method for manufacturing the MOSFET 100 of the first embodiment, an increase in carbon vacancies in the silicon carbide layer 10 is suppressed, thereby suppressing, for example, nitrogen atoms from entering the carbon vacancies and becoming donors when forming the interface termination region 40. Therefore, a decrease in the threshold voltage of the MOSFET 100 is suppressed.

[0208] As described above, according to the first embodiment, a semiconductor device capable of suppressing a decrease in carrier mobility by reducing the amount of carbon vacancies in a silicon carbide layer and a method for manufacturing the semiconductor device are realized.

[0209] Second embodiment The method for manufacturing a semiconductor device according to the second embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that a second heat treatment is performed in an atmosphere containing nitrogen before the formation of a silicon oxide film. Hereinafter, some of the contents that overlap with the first embodiment will not be described.

[0210] Hereinafter, a case where the second heat treatment is performed in a first atmosphere containing ammonia gas will be described as an example.

[0211] 22 is a process flow diagram of the method for manufacturing a semiconductor device according to the second embodiment. The MOSFET 100 shown in FIG.

[0212] As shown in FIG. 22, the method for manufacturing the semiconductor device according to the second embodiment includes the steps of preparing a silicon carbide layer (step S200), implanting aluminum ions (step S201), implanting carbon ions (step S202), implanting phosphorus ions (step S203), implanting aluminum ions (step S204), forming a carbon film (step S205), a first heat treatment (step S206), removing the carbon film (step S207), forming a field oxide film (step S208), forming a sacrificial oxide film (step S209), a hydrogen etching treatment (step S210), a second heat treatment (step S211), forming a silicon oxide film (step S212), a third heat treatment (step S213), a fourth heat treatment (step S214), forming a gate electrode (step S215), forming an interlayer insulating film (step S216), and forming source and drain electrodes (step S217).

[0213] In step S200, a silicon carbide layer 10 is prepared. The silicon carbide layer 10 has an n + The drain region 12 and the n - The drift region 14 is of a mold.

[0214] In step S201, a first mask material is formed. Then, using the first mask material as an ion implantation mask, aluminum is ion-implanted into the drift region 14. The p-well region 16 is formed by the ion implantation.

[0215] The ion implantation to form the p-well region 16 is an example of a first ion implantation. The aluminum ion implantation is performed in a first projected range and with a first dose.

[0216] In step S202, carbon is ion-implanted into the p-well region 16 using the first mask material as an ion implantation mask. The ion implantation of carbon into the p-well region 16 is an example of a second ion implantation. The ion implantation of carbon is performed in a second projected range and with a second dose. Then, the first mask material is removed.

[0217] In step S203, a second mask material is formed. Then, using the second mask material as an ion implantation mask, phosphorus, which is an n-type impurity, is ion-implanted into the drift region 14 to form the source region 18. Thereafter, the second mask material is removed.

[0218] In step S204, a third mask material is formed. Using the third mask material as an ion implantation mask, aluminum, which is a p-type impurity, is ion-implanted into the drift region 14 to form the p-well contact region 20. Thereafter, the third mask material is removed.

[0219] In step S205, a carbon film is formed on silicon carbide layer 10.

[0220] In step S206, a first heat treatment is performed. The first heat treatment is performed at 1600° C. or higher. The first heat treatment is performed in a non-oxidizing atmosphere. For example, the first heat treatment is performed in an inert gas atmosphere. For example, the first heat treatment is performed in an argon gas atmosphere.

[0221] The first heat treatment activates the aluminum and phosphorus ions implanted into the silicon carbide layer 10. The first heat treatment is an activation annealing for aluminum and phosphorus.

[0222] In step S207, the carbon film is removed by an ashing process using oxygen plasma.

[0223] In step S208, a field oxide film is formed on the silicon carbide layer 10. The field oxide film contains oxygen. The field oxide film is, for example, a silicon oxide film. The field oxide film is deposited by, for example, a vapor phase deposition method.

[0224] The field oxide is then removed.

[0225] In step S209, a sacrificial oxide film is formed on the silicon carbide layer 10. The sacrificial oxide film is, for example, a silicon oxide film. The sacrificial oxide film is formed by thermal oxidation of the surface of the silicon carbide layer.

[0226] Next, the sacrificial oxide film is removed.

[0227] In step S210, a hydrogen etching process is performed to etch the surface of silicon carbide layer 10 in an atmosphere containing hydrogen gas. By the hydrogen etching process, the surface of silicon carbide layer 10 is etched by, for example, 10 nm to 100 nm. The amount of etching is preferably 15 nm or more, more preferably 25 nm or more, and even more preferably 50 nm or more. In the manufacturing method of the semiconductor device of the second embodiment, etching more than 100 nm does not significantly change the effect of the hydrogen etching process, so etching more than 100 nm is not necessarily required.

[0228] In step S211, a second heat treatment is performed in an atmosphere containing ammonia gas (NH3).

[0229] The second heat treatment forms interface termination region 40 on the surface of silicon carbide layer 10.

[0230] In step S212, a silicon oxide film is formed on the silicon carbide layer 10. The silicon oxide film will ultimately become the gate insulating layer 28. The silicon oxide film is formed by, for example, a vapor phase growth method at a low temperature and a low oxygen partial pressure.

[0231] The silicon oxide film is preferably formed at a temperature of 600° C. or less, more preferably at a temperature of 500° C. or less, and further preferably at a temperature of 450° C. or less. By forming the silicon oxide film at a low temperature, oxidation of the surface of the silicon carbide layer is suppressed.

[0232] It is preferable that the silicon oxide film formed in step S212 is a silicon-rich silicon oxide film in its entirety by lowering the oxygen partial pressure during growth. 2-δ As such, 0.01≦δ≦0.1 is preferable. In other words, it is preferable to adjust the oxygen vacancy to 0.5% or more and 5% or less. If excess oxygen is present in the silicon oxide film, the silicon carbide layer may be oxidized during the subsequent high-temperature treatment, so it is preferable to make the silicon oxide film free of excess oxygen. By carrying out the third heat treatment, oxygen is supplied to the oxygen vacancies in the silicon oxide film, and ultimately, a good silicon oxide film without oxygen vacancies is obtained.

[0233] In step S213, a third heat treatment is performed. The third heat treatment is performed in an atmosphere containing an inert gas. The second heat treatment is performed in a non-oxidizing atmosphere in which the surface of the silicon carbide layer 10 is not oxidized.

[0234] For example, argon gas (Ar) or nitrogen gas (N2) is supplied to a reactor in which the silicon carbide layer 10 is placed, and heat treatment is performed.

[0235] The temperature of the third heat treatment is, for example, 1000° C. or more and 1400° C. or less.

[0236] The third heat treatment also functions as a densifier anneal for the silicon oxide film, which becomes a high-density film.

[0237] In step S214, a fourth heat treatment is performed in an atmosphere containing nitrogen oxide gas (NOx). The fourth heat treatment removes nitrogen from the silicon oxide film.

[0238] In step S215, the gate electrode 30 is formed on the gate insulating layer .

[0239] In step S216, the interlayer insulating film 32 is formed on the gate electrode 30.

[0240] In step S215, the source electrode 34 and the drain electrode 36 are formed.

[0241] By the above manufacturing method, the MOSFET 100 shown in FIG. 1 is formed.

[0242] As described above, according to the second embodiment, similarly to the first embodiment, a method for manufacturing a semiconductor device capable of suppressing a decrease in carrier mobility by reducing the amount of carbon vacancies in a silicon carbide layer is realized.

[0243] (Third embodiment) The method for manufacturing a semiconductor device according to the third embodiment includes a first ion implantation step of implanting aluminum (Al) into a silicon carbide layer, a first heat treatment at 1600°C or higher, an oxidation treatment step of oxidizing the silicon carbide layer, an etching treatment step of etching the silicon carbide layer by 25 nm or more in an atmosphere containing hydrogen gas, forming a silicon oxide film on the silicon carbide layer, and forming a gate electrode on the silicon oxide film. The method for manufacturing a semiconductor device according to the third embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that it does not include a second ion implantation step of implanting carbon (C) into the silicon carbide layer. Hereinafter, some of the contents that overlap with the first embodiment may be omitted.

[0244] 21 of the first embodiment, when carbon ion implantation is not performed in addition to aluminum ion implantation, when oxidation treatment is performed after ion implantation, the carbon vacancy density becomes high, for example, in a region 200 nm or more from the surface of the silicon carbide layer. This is thought to be because, when carbon ion implantation is not performed, the carbon vacancy density in the silicon carbide layer before oxidation treatment is high, which promotes diffusion of oxygen through the carbon vacancies and causes distortion of silicon carbide even in a deep region of the silicon carbide layer.

[0245] In the manufacturing method of the semiconductor device according to the third embodiment, after the silicon carbide layer 10 is subjected to an oxidation treatment, the surface of the silicon carbide layer 10 is etched by a hydrogen etching treatment. The amount of etching of the surface of the silicon carbide layer 10 by the hydrogen etching treatment is 25 nm or more. By etching the surface of the silicon carbide layer 10 by 25 nm or more, the carbon vacancy density is reduced to 1016 cm -3 By removing the regions with high carbon vacancy density, the carbon vacancy density at the surface of the silicon carbide layer 10 is reduced. Therefore, the amount of carbon vacancies in the p-well region 16 directly below the gate insulating layer 28 is reduced. This reduces the hole mobility to, for example, 160 cm 2 / V s or more.

[0246] From the viewpoint of reducing the carbon vacancy density on the surface of the silicon carbide layer 10, the amount of etching of the surface of the silicon carbide layer 10 by the hydrogen etching treatment is preferably 50 nm or more, more preferably 75 nm or more, and even more preferably 100 nm or more. And, most preferably, 200 nm or more. When the amount of etching is 50 nm or more, the hole mobility is, for example, 160 cm 2 / V s or more. When the etching amount is 200 nm or more, the hole mobility is, for example, 200 cm 2 / V s or more. Since there are a large number of carbon vacancies deep inside, they are removed by etching from the surface to the deep inside.

[0247] As described above, according to the third embodiment, a semiconductor device capable of suppressing a decrease in carrier mobility by reducing the amount of carbon vacancies in a silicon carbide layer and a method for manufacturing the semiconductor device are realized.

[0248] (Fourth embodiment) The semiconductor device of the fourth embodiment is different from the first embodiment in that the semiconductor device of the fourth embodiment is a trench-gate MOSFET having a gate electrode in a trench. In the following, some of the contents that overlap with the first embodiment will not be described.

[0249] 23 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. The semiconductor device according to the fourth embodiment is a MOSFET 200. The MOSFET 200 is a trench-gate MOSFET having a gate electrode in a trench. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers.

[0250] The MOSFET 200 includes a silicon carbide layer 10, a gate insulating layer 28 (silicon oxide layer), a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, an interface termination region 40, and a trench 50.

[0251] The silicon carbide layer 10 includes a drain region 12 , a drift region 14 , a p-well region 16 , a source region 18 , and a p-well contact region 20 .

[0252] The trench 50 penetrates the source region 18 and the p-well region 16, and reaches the drift region 14. The bottom surface of the trench 50 is located in the drift region 14.

[0253] A gate insulating layer 28 and a gate electrode 30 are provided in the trench 50. The side surface of the trench 50 is, for example, a plane having an off angle of 0 degrees or more and 8 degrees or less with respect to the m-plane.

[0254] The p-well region 16 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-well region 16 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 As in the manufacturing method of the first embodiment, carbon is introduced by ion implantation so as to cover the distribution of aluminum, as shown in FIG.

[0255] The depth of the p-well region 16 is, for example, not less than 0.4 μm and not more than 0.8 μm. The p-well region 16 functions as a channel region of the MOSFET 200.

[0256] The channel portion 16a is located between the gate insulating layer 28 and a first position (X1 in FIG. 23) that is 100 nm away from the gate insulating layer 28 toward the silicon carbide layer 10. The channel portion 16a is located in the p-well region 16.

[0257] In the channel portion 16a, a wave number of 838 cm is measured by the attenuated total reflection method (ATR method) of the Fourier transform infrared spectroscopy (FTIR method). -1 Infrared absorption intensity at wavenumber 970cm -1 to the infrared absorption intensity is 1.0 or less.

[0258] In the channel portion 16a, Z measured by DLTS 1 / 2 The level density is 1×10 11 cm -3 It is less than 5×10 10 cm -3 Less than or equal to 1×10 is preferred 10 cm -3 The following is more preferred:

[0259] The electron hole mobility of the channel portion 16a is, for example, 200 cm 2 / V·s or more. 350cm 2 / V s or more is preferable, and 450 cm 2 / V s or higher is more preferable.

[0260] The interface termination region 40 is located between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 is located between the drift region 14 and the p-well region 16 and the gate insulating layer 28. The interface termination region 40 contains nitrogen (N) as a terminating element that terminates dangling bonds of the silicon carbide layer 10. The interface termination region 40 is an example of a region.

[0261] The nitrogen concentration in the interface termination region 40 is 1×10 21 cm -3 That's all.

[0262] 3, the nitrogen concentration distribution has a peak in the interface termination region 40. The peak nitrogen concentration is, for example, 1×10 22 cm -3 The full width at half maximum of the peak of the nitrogen concentration distribution is, for example, 1 nm or less. Nitrogen segregates at the interface between the silicon carbide layer 10 and the gate insulating layer 28.

[0263] The nitrogen concentration at the peak of the nitrogen concentration distribution is, for example, 1×10 22 cm -3 That's all.

[0264] The nitrogen concentration at the second position X2, which is 1 nm away from the peak of the nitrogen concentration distribution on the gate insulating layer 28 side, is 1×10 18 cm -3 The nitrogen concentration at a third position X3 that is 1 nm away from the peak of the nitrogen concentration distribution on the silicon carbide layer 10 side is 1×10 18 cm -3 The concentration of nitrogen at the third position X3 is 1×10 17 cm -3 It is preferable that the value is less than 2×10 16 cm -3 It is more preferable that:

[0265] The amount of nitrogen atoms bonding to four silicon atoms at a fourth position (X4 in FIG. 23) 5 nm away from gate insulating layer 28 toward silicon carbide layer 10 is, for example, 80% to 120% of the amount of nitrogen atoms bonding to four silicon atoms at a fifth position (X5 in FIG. 23) 5 μm away from gate insulating layer 28 toward silicon carbide layer 10. In other words, the amount of tetracoordinated nitrogen atoms at the fourth position X4 is 80% to 120% of the amount of tetracoordinated nitrogen atoms at the fifth position X5.

[0266] The fourth location X4 is located in the p-well region 16. The fifth location X5 is located in the drift region 14.

[0267] The MOSFET 200 can be manufactured, for example, by forming the trench 50 after the first heat treatment and before the etching treatment in the manufacturing method of the first embodiment.

[0268] As described above, according to the fourth embodiment, a semiconductor device capable of suppressing a decrease in carrier mobility by reducing the amount of carbon vacancies in the silicon carbide layer is realized, similarly to the first, second, and third embodiments. In addition, since the fourth embodiment is a trench gate type, the channel density per unit area of ​​the chip is increased, and the on-resistance of the MOSFET is reduced.

[0269] Fifth embodiment The inverter circuit and the drive device of the fifth embodiment are an inverter circuit and a drive device including the semiconductor device of the first embodiment.

[0270] 24 is a schematic diagram of a driving device according to the fifth embodiment. The driving device 700 includes a motor 140 and an inverter circuit 150.

[0271] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c, which use the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

[0272] According to the fifth embodiment, the MOSFET 100 with improved characteristics is provided, and thus the characteristics of the inverter circuit 150 and the driving device 700 are improved.

[0273] Sixth embodiment The vehicle of the sixth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0274] 25 is a schematic diagram of a vehicle according to the sixth embodiment. The vehicle 800 according to the sixth embodiment is a railcar. The vehicle 800 includes a motor 140 and an inverter circuit 150.

[0275] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The wheels 90 of the vehicle 800 are rotated by the motor 140.

[0276] According to the sixth embodiment, the vehicle 800 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 800.

[0277] Seventh embodiment The vehicle of the seventh embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0278] 26 is a schematic diagram of a vehicle according to the seventh embodiment. The vehicle 900 according to the seventh embodiment is an automobile. The vehicle 900 includes a motor 140 and an inverter circuit 150.

[0279] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0280] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 causes the wheels 90 of the vehicle 900 to rotate.

[0281] According to the seventh embodiment, the vehicle 900 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 900.

[0282] Eighth embodiment The elevator of the eighth embodiment is an elevator including the semiconductor device of the first embodiment.

[0283] 27 is a schematic diagram of an elevator according to an eighth embodiment. The elevator 1000 according to the eighth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0284] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0285] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the hoist 616, causing the car 610 to rise and fall.

[0286] According to the eighth embodiment, the elevator 1000 has improved characteristics by including the MOSFET 100 with improved characteristics.

[0287] In the above, the first to fourth embodiments have been described using an example in which 4H—SiC is used as the crystal structure of silicon carbide, but the present invention can also be applied to silicon carbide having other crystal structures, such as 6H—SiC and 3C—SiC.

[0288] In addition, in the first to fourth embodiments, the gate insulating layer 28 is provided on the silicon surface or the m surface of the silicon carbide layer. However, the present invention can also be applied to the case where the gate insulating layer 28 is provided on other surfaces of silicon carbide, such as the carbon surface, the a-surface, or the (0-33-8) surface.

[0289] The present invention can also be applied to an n-channel type IGBT (Insulated Gate Bipolar Transistor).

[0290] In addition, in the fifth to eighth embodiments, the semiconductor device of the present invention is described as being applied to a vehicle or an elevator, but the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0291] In addition, in the fifth to eighth embodiments, the case where the semiconductor device of the first embodiment is applied has been described as an example, but it is also possible to apply, for example, the semiconductor device of the second, third or fourth embodiment.

[0292] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0293] 10 Silicon carbide layer 14 Drift region (first silicon carbide region) 16 p-well region (second silicon carbide region) 16a Channel part (part) 28 Gate insulation layer (silicon oxide layer) 30 Gate electrode 40 Interface termination area (area) 54 Carbon Film 57 Silicon oxide film 100 MOSFET (semiconductor device) 150 Inverter circuit 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 400 MOSFET (semiconductor device) 700 Drive Unit 800 vehicles 900 vehicles 1000 elevator Rp1 1st projected range Rp2 2nd projected range X1 1st position X2 2nd position X3 3rd position X4 4th position X5 5th position

Claims

1. performing a first ion implantation of aluminum (Al) into the silicon carbide layer in a first projected range and at a first dose; performing a second ion implantation of carbon (C) into the silicon carbide layer in a second projected range and at a second dose that is 10 times or more the first dose; A first heat treatment is performed at 1600° C. or more; performing an oxidation treatment for oxidizing the silicon carbide layer; performing an etching process for etching the silicon carbide layer in an atmosphere containing hydrogen gas; forming a silicon oxide film on the silicon carbide layer; A method of manufacturing a semiconductor device in which a gate electrode is formed on the silicon oxide film.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the silicon carbide layer is etched by 10 nm or more during the etching treatment.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the silicon carbide layer is etched by 15 nm or more during the etching process.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein the silicon carbide layer is etched by 25 nm or more during the etching process.

5. forming a carbon film on the silicon carbide layer after the first ion implantation and before the first heat treatment; 5. The method for manufacturing a semiconductor device according to claim 1, wherein the oxidation treatment is an ashing treatment for removing the carbon film in oxygen plasma.

6. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the oxidation treatment is a thermal oxidation treatment.

7. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the oxidation treatment is a deposition treatment for depositing an insulating film containing oxygen on the silicon carbide layer.

8. 8. The method for manufacturing a semiconductor device according to claim 1, wherein the etching temperature is 1300.degree. C. or more and 1500.degree. C. or less.

9. The first dose is 1×10 １４ cm －２ 9. The method for manufacturing a semiconductor device according to claim 1, wherein:

10. The second dose is 1×10 １５ cm －２ The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

11. 11. The method for manufacturing a semiconductor device according to claim 1, wherein the first projected range and the second projected range are 0.6 [mu]m or less.

12. 12. The method for manufacturing a semiconductor device according to claim 1, wherein the second projected range is 80% or more and 120% or less of the first projected range.

13. 13. The method for manufacturing a semiconductor device according to claim 1, wherein the first ion implantation and the second ion implantation are performed on the same region of the silicon carbide layer.

14. 14. The method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: forming the silicon oxide film and then performing a second heat treatment in an atmosphere containing nitrogen (N) before forming the gate electrode.

15. a silicon carbide layer; A gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; a silicon carbide layer and a silicon oxide layer, the silicon carbide layer and the silicon oxide layer being disposed between the silicon carbide layer and the silicon oxide layer, the nitrogen concentration of which is 1×10 ２１ cm －３ The above areas, a nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has a peak in the region; A wave number of 838 cm measured by an attenuated total reflection measurement method (ATR method) of Fourier transform infrared spectroscopy (FTIR method) in a portion between the silicon oxide layer and a first position 100 nm away from the silicon oxide layer on the silicon carbide layer side. －１ Infrared absorption intensity at wave number 970 cm －１ to the infrared absorption intensity is 1.0 or less, The concentration of nitrogen at a second position 1 nm away from the peak on the silicon oxide layer side is 1×10 １８ cm －３ and the concentration of carbon at the second location is 1×10 １８ cm －３ is as follows: The concentration of nitrogen at a third position 1 nm away from the peak on the silicon carbide layer side is 1×10 １８ cm －３ 1. A semiconductor device comprising:

16. The nitrogen concentration of the peak is 1×10 ２２ cm －３ 16. The semiconductor device according to claim 15.

17. the silicon carbide layer includes an n-type first silicon carbide region and a p-type second silicon carbide region located between the first silicon carbide region and the silicon oxide layer; The semiconductor device according to claim 15 or 16, wherein the portion is located within the second silicon carbide region.

18. 18. An inverter circuit comprising the semiconductor device according to claim 15.

19. A driving device comprising the semiconductor device according to any one of claims 15 to 17.

20. A vehicle comprising the semiconductor device according to any one of claims 15 to 17.

21. An elevator comprising the semiconductor device according to any one of claims 15 to 17.

Images