Quantum computers and quantum computing systems

Abstract

The present invention comprises a quantum bit control unit that controls a quantum bit array in which a plurality of quantum bits are arranged into a two-dimensional square lattice, and a common control line capable of controlling a plurality of quantum bit pairs configured by a pair of adjacent quantum bits. The quantum bit control unit controls some of the plurality of quantum bit pairs by means of a plurality of second-quantized gates which are given a restraint condition related to the product of operation and perform operation processing on the plurality of quantum bit pairs.

Description

[Technical field]

[0001] The present invention relates to a quantum computer and a quantum computing system. [Background technology]

[0002] A large number of quantum bits are required to realize a fault-tolerant quantum computer. To control the quantum bits on a circuit, control lines that change the gate voltage are required.

[0003] In a chip design in which a control line is provided for each quantum bit, the number of quantum bits that can be created is limited by the number of control lines when the scale is increased. To solve the scalability issue caused by the number of control lines, it becomes necessary to simultaneously control multiple quantum bits with one control line, as in Patent Document 1.

[0004] In the device of Patent Document 1, quantum bits are arranged in an array, and a common control line is provided for each column or row, and this control line controls the exchange interaction between two quantum bits to obtain a two-quantum gate. Because the control line is shared, a two-quantum gate is realized for all pairs of quantum bits in the same column or row, and this two-quantum gate for multiple quantum bits becomes a basic gate. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-027142 Summary of the Invention [Problem to be solved by the invention]

[0006] In silicon quantum dot arrays, changing the gate voltage or applying a DC magnetic field to operate the gate of a targeted bit can cause undesirable effects (phase rotation and decoherence) in quantum bits other than the targeted bit.

[0007] In Patent Document 1, the above problem is solved in terms of hardware by devising an apparatus configuration.

[0008] An object of the present invention is to perform gate operations on a target bit in a software manner in a quantum computer. [Means for solving the problem]

[0009] A quantum computer according to one embodiment of the present invention comprises a quantum bit array in which a plurality of quantum bits are arranged in a two-dimensional square lattice pattern, a quantum bit control unit that controls the quantum bit array, and a shared control line that can control a plurality of quantum bit pairs each composed of an adjacent pair of the quantum bits, wherein the quantum bit control unit controls some of the plurality of quantum bit pairs using a plurality of two-quantum gates that are given constraints regarding the product of an operation and perform arithmetic processing on the plurality of quantum bit pairs, and does not control the quantum bit pairs other than the some of the quantum bit pairs.

[0010] In addition, in the quantum computer according to one embodiment of the present invention, the interaction operated by the shared control line is an exchange interaction or an XY interaction, and the operation on the multiple quantum bit pairs serving as basic gates is a PSWAP gate or (iSWAP) α The PSWAP gate is a gate given by the power of the SWAP gate (equation 1-1) and satisfies (equation 1-2). The matrix expression of the PSWAP gate is given by (equation 1-3). The (iSWAP) α The matrix representation of the gate is given by (Equation 1-4), and the rotation angle α takes a real value between 0 and 2.

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[0015] According to one aspect of the present invention, in a quantum computer, gate operations on a target bit can be performed by software. [Brief description of the drawings]

[0016] [Figure 1] FIG. 13 is a diagram showing an example of a decomposition gate model of any two quantum gates using a PSWAP gate. [Diagram 2] This is a decomposition diagram of a unitary gate Ud whose eigenvectors are the magic basis of any two quantum gates. [Diagram 3] FIG. 13 is a diagram showing an example of decomposition of a unitary gate Ud having a magic basis as an eigenvector in a PSWAP gate. [Figure 4] 1A is a schematic diagram of the device structure of a quantum dot array, FIG. 1B is a diagram showing the coupling between quantum bits forming the array structure, and FIG. 1C is a diagram showing the index of the column / row number and the interaction coefficient J. [Figure 5A] FIG. 13 illustrates qubits affected by column PSWAP. [Figure 5B] FIG. 13 illustrates qubits affected by row PSWAP. [Figure 6] FIG. 1 is a diagram showing a system configuration for implementing the invention. [Figure 7] FIG. 1 is a diagram showing the difference between the prior art (a) and the present invention (b). [Figure 8](a) is a schematic diagram of the device structure of a quantum dot array, (b) is a schematic diagram of the part of the quantum dot array controlled by the exchange interaction control gate, (c) is a decomposition diagram of four column or row PSWAPs with constraints on the rotation angle of any two quantum gates, and (d) is a diagram showing four column or row PSWAPs that become equivalent circuits to the identity operator due to the constraints. [Figure 9A] This figure shows the general form of decomposition using four PSWAP gates with constraints on the unitary gate Ud whose eigenvectors are the magic basis. [Figure 9B] This figure shows the general form of decomposition using four PSWAP gates with constraints on the unitary gate Ud whose eigenvectors are the magic basis. [Figure 10] This figure shows the rotation angle parameters when any two quantum gates are decomposed into Rx, Ry, and four PSWAP gates with constraints. [Figure 11] This is an exploded view of the CZ gate with four column or row PSWAP constraints. [Figure 12] (a) is a decomposition diagram of the Control Unitary gate into a CNOT gate and one quantum gate, (b) is a decomposition diagram of the CZ gate into two PSWAP gates, and (c) is a decomposition diagram of the Control Unitary gate into four column or row PSWAPs with constraints. [Figure 13] This is an exploded view of four column or row PSWAPs with constraints on the PSWAP gates. [Figure 14] FIG. 1 shows a diagram illustrating embedding of quantum Fourier transform times into a lattice array, where (a) is a quantum Fourier transform circuit diagram using four quantum bits, (b) is a diagram showing a lattice-like four-qubit system, (c) is a diagram embedded in a lattice-like four-qubit system and is a quantum Fourier transform circuit equivalent to (a), and (d) is a two-quantum gate in the gate model of (c) and a usage flow of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] First, a description will be given of a mode for carrying out the invention.

[0018] As mentioned above, quantum bits are arranged in an array, and a common control line is provided for each column or row, and this control line controls the exchange interaction between two quantum bits to obtain a two-quantum gate. Since the control line is shared, a two-quantum gate is realized for all pairs of quantum bits in the same column or row, and this two-quantum gate for multiple quantum bits becomes a basic gate.

[0019] The exchange interaction Hamiltonian between the quantum bit in the lth column and the mth row and the quantum bit in the l+1th column and the mth row can be given as (Equation 2-1).

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[0022] Due to the uniformity of the semiconductor process, the shape of the quantum dots is expected to be uniform within the plane, and the parameters characterizing each quantum bit are predicted to be uniform. Therefore, since the values ​​of the exchange interaction coefficients are expected to be constant within rows and columns, it can be assumed that all exchange interaction coefficients are equal (equation 3).

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[0024] By applying a non-uniform magnetic field so that the microwave resonance frequency is different for each quantum bit, local selectivity can be obtained for a single quantum gate, making it possible to operate a desired single quantum gate on a desired single quantum bit.

[0025] In computer theory, a quantum device that has a quantum gate, which is an arbitrary unitary operator in 2N dimensions, and a measurement operation that converts quantum data into classical information, can be treated as a universal quantum computer. Realizing this universal quantum computer is necessary to realize quantum computing.

[0026] This section explains how to realize any 2N-dimensional unitary operation. It is known that any 2N-dimensional unitary operator can be decomposed into a product of one quantum gate and two quantum gates. One quantum gates are given by two-dimensional unitary operators, and two quantum gates are given by four-dimensional unitary operators. Therefore, to realize a quantum computer, it is necessary to create one quantum gate and two quantum gates that can create any 2N-dimensional unitary operator.

[0027] Generally, quantum computer hardware devices have device-specific physical properties, and the one-quantum gates and two-quantum gates that are easy to create vary from device to device due to these properties. Quantum gates can be defined from the Hamiltonian, which determines the energy structure of the device. In this case, quantum gates that can be created directly without combining multiple quantum gates are called Hamiltonian-native operators. If it is possible to create any unitary operator in any 2N dimensions by combining Hamiltonian-native operators, a universal quantum computer will be realized.

[0028] We assume a quantum device in which all quantum gates are individually given control lines and local two-quantum gates can be realized. In particular, for quantum devices in which the PSWAP gate, a two-quantum gate based on exchange interactions, is a Hamiltonian-native operation, it is known from Non-Patent Document 1 (H. Fan, V. Roychowdhury, and T. Szkopek, Phys. Rev. A72, 052323 (2005)) that any two-quantum gate can be decomposed as shown in (Equation 4).

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[0033] On the other hand, the PSWAP gate is given by (Equation 6) using the magic basis.

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[0035] [Table 1] Therefore, using the results in Table 1,d can be expressed as a product of PSWAP gates as in (7), and the equivalence of (4) can be proven.

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[0037] While general quantum algorithms and conventional methods require a local two-quantum gate for specific two quantum bits, the basic gate in the system assumed in this invention is a two-quantum gate for multiple quantum bit pairs. Therefore, it is necessary to realize a local two-quantum gate by combining two-quantum gates for multiple quantum bit pairs.

[0038] An operation on a pair of multiple quantum bits becomes a basic gate. In the present invention, a method for implementing an operation using such a two-quantum gate on a pair of multiple quantum bits is provided, in which a general quantum algorithm is equivalent to a two-quantum gate on a specific two-qubit pair.

[0039] First, we show a solution for the case where the quantum hardware system has exchange interactions and the column or row PSWAP is Hamiltonian native. We change the gate decomposition into three local PSWAP gates given by (Equation 4) to four column or row PSWAP gates as shown in (Equation 8-1). In this case, n is an integer and the global phase λ is expressed as (Equation 8-2). t is defined, and the rotation angles α, β, γ, and δ satisfy (Equation 8-3).

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[0049] [Table 2] where √σ x ,√σ y ,√σ z satisfies (Equation 10-1) and (Equation 10-2), and † denotes a Hermitian conjugate operator. A Clifford operator is an operator that can convert a Pauli operator to a Pauli operator, and a Pauli operator can be converted to a Pauli operator by multiplying it by a Clifford operator and its Hermitian conjugate operator. By combining the exchange of the two magic bases shown in (Table 2), a transformation from any magic base to another magic base can be created.

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[0053] [Table 3] Finally, the transformations of (8-1) and (9-5) can be made by magic basis to magic basis transformations using Clifford operators as shown in (Table 1), (Table 2), and (Table 3). Then, (8-1) can be generalized as (12).

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[0055] According to the present invention, a method is provided for implementing an operation equivalent to a two-quantum gate local to two specific quantum bits using an operation on a pair of multiple quantum bits.

[0056] The present invention is used for a system having a quantum device with a structure in which multiple quantum bits are controlled by one control wiring, such as column or row PSWAP. In particular, the quantum bits are arranged in a lattice, and the basic one-quantum gates that can operate on any quantum bit are limited to Rx(θ), Ry(θ), and Rz(θ), and the two-qubit gate is targeted for a quantum device in which the column or row PSWAP generated by the exchange interaction gates that occur simultaneously across each row or column is a Hamiltonian-native basic gate for two adjacent quantum bit pairs.

[0057] A system having a quantum device as described above has three components: a host computer that performs the process of decomposing an algorithm into a basic gate model based on the basic operations of Hamiltonian-native quantum devices and the process of converting it into a control signal pulse sequence description to realize the basic gate model; a quantum bit control unit that generates the control pulses; and a quantum bit array unit in which interacting quantum bits are arranged in an array and multiple quantum bits are controlled simultaneously by control wiring.

[0058] Next, an example of decomposition of a general two-quantum gate will be described.

[0059] The two-quantum gate decomposition method of Non-Patent Document 1 will be explained. The two-quantum gate of Si quantum dots is generated by exchange interaction. Therefore, the local PSWAP gate operated on the desired two-qubit pair becomes a Hamiltonian native gate.

[0060] It is known that a universal quantum computer can be constructed by combining one quantum gate such as Rx, Ry, and Rz. In this case, the decomposition of two quantum gates is appropriate as shown in (Equation 4) or the gate model in Figure 1.

[0061] Figure 1 shows that any two-quantum gate is equivalent to a circuit made up of a combinational circuit of three PSWAP gates and one quantum gate.

[0062] The decomposition of Figure 1 is based on the result of Figure 2 in Non-Patent Document 2 and the U d It can be shown using the decomposition shown in Figure 3 that

[0063] Figure 2 shows that any two quantum gates are U d Figure 3 shows that U d can be constructed as a product of three PSWAP gates and one quantum gate.

[0064] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. EXAMPLES

[0065] Figure 4(a) shows a quantum device in which quantum dots are arranged in an array. The quantum dots are arranged in a two-dimensional square lattice, and interactions (potential barriers) are formed between the quantum dots. The device also has a gate electrode made of a semiconductor (e.g., poly-Si). There are two types of gate electrodes: a quantum dot control gate and an exchange interaction control gate.

[0066] Exchange interaction control gates and quantum dot control gates are alternately arranged in two layers directly on the substrate. The exchange interaction control gates are used to control the operation of two quantum gates, and the quantum dot control gates are used to control the operation of one quantum gate. Figures 4(b) and (c) are schematic and generalized diagrams of the coupling between quantum bits when the quantum dots in the bottom layer of Figure 4(a) are used as quantum bits.

[0067] FIG. 4(b) shows the configuration of a quantum bit array and quantum bits arranged in M ​​rows and L columns.

[0068] The white circles indicate the positions of the qubits, and the solid lines indicate the coupling between the qubits.

[0069] In Fig. 4(c), the index between coupled qubits is illustrated. The bit in the mth row and lth column is indicated by {l,m}. The exchange interaction coefficient between qubits {l,m} and {l+1,m} is J {l,m},h The exchange interaction coefficients of the qubits {l,m} and {l,m+1} are J {l,m},v Let us assume that.

[0070] At this time, the basic two quantum gates are shown in Figures 5A and 5B.

[0071] Figure 5A shows the column PSWAP. Each white circle represents a quantum dot, and the solid lines represent the coupling between the phase qubits. The shaded areas represent the wiring that applies the exchange interaction. In the dotted squares, the shaded wiring causes the exchange interaction to work simultaneously for all qubit pairs, and the PSWAP gate is applied to all qubit pairs. Figure B5 is the same as Figure 5A with the vertical and horizontal reversed, and shows row PSWAP.

[0072] The overall configuration of a quantum computing system for operating a quantum bit array having the characteristics shown in FIGS. 4, 5A, and 5B is shown in FIG.

[0073] As shown in FIG. 6, the quantum computing system includes a quantum bit array 62 for performing quantum computation, a quantum bit control unit 61 for controlling quantum bits, and a host computer 60 for preparing instructions for quantum computation for the quantum bit control unit 61.

[0074] A description of a quantum algorithm using a gate model with any quantum gate is converted into a description using a gate model of a basic gate using the technique of the present invention, and this description using the gate model of the basic gate is further converted into a control signal pulse sequence description, which is then transmitted to a quantum bit control unit, enabling the quantum bits to be controlled and the quantum bit array to operate.

[0075] Examples of physical systems with such exchange interactions include nuclear spins, electron spins, quantum dots, NMR qubits, etc. Also available are devices with XY gates as two quantum gates, e.g. superconducting flux bits such as transmon qubits.

[0076] Specifically, the host computer 60 describes the quantum algorithm using a gate model. Next, it decomposes it into a product of one quantum unitary and two quantum unitaries with the magic basis as eigenvalues. Next, it determines the values ​​of the rotation angles α, β, γ, δ and the global phase λ of the four PSWAP gates using the eigenvalues ​​of the two quantum unitaries with the magic basis as eigenvalues. Next, it decomposes the one quantum unitary into basic operations that can be directly implemented in hardware. Next, it describes the basic gates using the gate model. Finally, it executes the gate model pulse sequence conversion function.

[0077] The quantum bit control unit 61 performs control signal pulse sequence description, and based on the control signal pulse sequence, the control device controls the quantum bit array 62. Then, the quantum bit array 62 operates.

[0078] Here, the host computer 60 is composed of a general arithmetic device that performs general arithmetic operations, and the quantum bit control unit 61 and the quantum bit array 62 are composed of quantum arithmetic devices that specialize in performing quantum mechanical operations.

[0079] The above configuration may be configured as an integrated computer, or any of the main memory, general processing unit, control unit, auxiliary memory unit, input unit, and output unit may be configured as other computers connected via a network.

[0080] General calculations are performed in the same manner as with a normal computer. Data is exchanged between the main memory and the general calculation unit, which is the calculation section, and calculations are carried out by repeating this process. The control unit directs the entire process. Programs executed by the general calculation unit are stored in the main memory, which is the storage unit. If the main memory does not have enough storage capacity, an auxiliary storage unit, which is also a storage unit, is used. An input device is used to input data, programs, etc., and an output device is used to output the results. Input devices include manual input devices such as keyboards as well as interfaces for network connections. These interfaces also serve as output devices.

[0081] Quantum operations are also carried out in a similar manner. Data is exchanged between the main memory, which is the storage unit, and the quantum processing device, which is the processing unit, and the operation is carried out by repeating this process. The control device directs the entire process. The programs executed by the quantum processing device are stored in the main memory, which is the storage unit.

[0082] The program is converted into a code to be used by the quantum processor using the general processor and stored in the main memory. The encoded program is sent from the main memory to the quantum processor, and the control device sends a control signal to the quantum processor according to the encoded program to execute the operation. The results of the operation by the quantum processor are sent to the main memory and are post-processed by the general processor as necessary.

[0083] FIG. 7 is a diagram showing the difference between the present invention and the prior art (Non-Patent Document 1).

[0084] In the prior art, as shown in Fig. 7(a), a gate decomposition is given for a system in which the interaction of two qubits is controlled by one exchange interaction control gate. In this case, there is no condition on the sum of the rotation angles of the three decomposed PSWAP gates. Therefore, the prior art method cannot be applied to a system in which the interaction of multiple qubit pairs is realized by one exchange interaction gate wiring, as shown in Fig. 7(b).

[0085] As shown in FIG. 7(b), it is an important feature of the present invention to set the number of columns or rows PSWAP to four and impose a constraint condition such as (Equation 8-3).

[0086] Next, a method for constructing any two-quantum gate using the column and row PSWAP proposed by the present invention will be described with reference to FIG.

[0087] Figure 8(a) is a schematic diagram of the device structure of a quantum dot array, Figure 8(b) is a schematic diagram of the portion of the quantum dot array controlled by the exchange interaction control gate, Figure 8(c) is a decomposition diagram of four column or row PSWAPs with constraints on the rotation angles of any two quantum gates, and Figure 8(d) shows four column or row PSWAPs that become equivalent circuits with the identity operator due to the constraints.

[0088] In Fig. 8(b), all qubit pairs (boxes around white circles in the left array) that exist in the same column on which the column PSWAP acts are shown. In Fig. 8(c), a gate model for a qubit pair for which a two-quantum gate is to be operated is shown. In Fig. 8(d), a gate model for a qubit pair that is not the subject of the operation is shown.

[0089] C in Fig. 8(c) 1 ,C 2 ,C 3 ,C 4 is an appropriate Clifford operator determined by referring to (Table 1), (Table 2), and (Table 3). In Fig. 8(c), the desired two-quantum gate U is realized by one qubit and four columns PSWAP.

[0090] In this case, one quantum gate and U satisfying (Equation 5-3) as shown in Figure 2 or (Equation 5-1) d and furthermore, any U d Since is given by the gate model shown in Figure 9, it can be shown that Figure 8(c) is equivalent to any two-quantum gate U.

[0091] On the other hand, for the qubit pairs that are not the target of the gate operation, the PSWAP gate with rotation angles α, β, γ, and δ is operated for the qubit pairs in Figure 8(d). In this case, there exist α, β, γ, and δ that satisfy (Equation 8-3), and (Equation 8-4) holds, so for these qubit pairs, this is equivalent to operating the identity operator gate, and the effect of the sequence PSWAP can be completely canceled.

[0092] As described above, the quantum computer of the present invention has a quantum bit array in which a plurality of quantum bits are arranged in a two-dimensional square lattice pattern, a quantum bit control unit that controls the quantum bit array, and a shared control line that can control a plurality of quantum bit pairs each consisting of an adjacent pair of quantum bits.

[0093] The quantum bit control unit is characterized in that it controls some of the quantum bit pairs using a plurality of two-quantum gates that are given constraints on the product of operations and perform operational processing on the multiple quantum bit pairs, and does not control any of the quantum bit pairs other than the some of the quantum bit pairs.

[0094] Here, the shared control line is an interaction control gate that controls the interaction between quantum bits of a quantum bit pair. The quantum bit array has quantum bit control gates that control a plurality of quantum bits.

[0095] Furthermore, the quantum bit control unit decomposes the plurality of 2-quantum gates into four 2-quantum gates, and controls some of the quantum bit pairs using the four 2-quantum gates.

[0096] In addition, the quantum bit control unit combines four 2-quantum gates and multiple 1-quantum gates, whose total rotation angle is an integer multiple of 2, and causes the 2-quantum gates to act on some of the multiple quantum bit pairs, while canceling the action of the 2-quantum gates on quantum bit pairs other than those few quantum bit pairs.

[0097] Here, the interaction operated by the shared control line is an exchange interaction or an XY interaction, and the operation on the multi-qubit pair that serves as the basic gate is a PSWAP gate or (iSWAP)α The PSWAP gate is a gate given by the power of the SWAP gate (equation 1-1), and satisfies (equation 1-2). Furthermore, the matrix expression of the PSWAP gate is given by (equation 1-3), and (iSWAP) α The gate is given by the matrix representation (number 1-4), and the rotation angle α takes a real value from 0 to 2.

[0098] The quantum bit control unit configures four PSWAP gates with constraints on the rotation angles of the four two-quantum gates to control some of the quantum bit pairs among the multiple quantum bit pairs, and configures a circuit equivalent to the identity operator by the constraints so that quantum bit pairs other than the some quantum bit pairs are not affected by the PSWAP gates. Here, the quantum bit control unit applies constraints so that the product of the four PSWAP gates becomes the identity operator.

[0099] Next, an example of decomposing a two-quantum gate generated randomly using the present invention will be shown. Any two-quantum gate can be decomposed as shown in (Equation 13) or the gate models in Figures 9A and 9B.

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[0101] Figure 10 shows the rotation angle parameters when any two quantum gates are decomposed by Rx, Ry, and four PSWAPs with constraints. EXAMPLES

[0102] In Example 2, we will show an example of decomposing a frequently occurring two-quantum gate. First, we will present a method of decomposing a CZ gate into four gates. The CZ gate is expressed as (Equation 14-1) using the magic basis and the one-quantum gate Uwz.

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[0112] In the third embodiment, embedding of quantum Fourier transform times into a lattice array will be described.

[0113] The effectiveness of the present invention will become clear by specifically showing a method for embedding an example of a famous quantum algorithm into quantum bits arranged in a lattice.

[0114] Here, we will show the quantum Fourier transform (QFT) with 4 qubits as an example of a quantum algorithm, as shown in Figure 14(a). It is an algorithm for solving QFT, and is a highly versatile quantum algorithm that is used in multiple algorithms, such as phase estimation algorithms, linear system solving by the Harrow, Hassidim and Lloyd method (HHL), and Shor's algorithm.

[0115] As an implementation form of QFT, we consider embedding the problem in a quantum device in which quantum dots are arranged in an array as the subject of the present invention, as shown in Fig. 14(b). In this case, two quantum gates exist only between two adjacent quantum gates, and the two quantum gates are realized by an exchange interaction Hamiltonian.

[0116] The control lines of the two-quantum gate are arranged in columns, and the basic two-quantum gate is a column or row PSWAP(θ) as shown in Figures 5A and 5B. The value of θ indicates the rotation angle of the Hamiltonian and is determined by the application time and strength of the exchange interaction. The longer the application time, the larger the value of θ, and the larger the strength of the exchange interaction, the larger the value of θ.

[0117] Due to the uniformity of the semiconductor process, the shape of the quantum dot is expected to be uniform within the surface, and it is assumed that the parameters characterizing each quantum bit are uniform, so that (Equation 3) holds true.

[0118] In the algorithm, two quantum gates are basically operated individually for the desired two quantum bits, so the use of the present invention is essential for quantum computers in which the column or row PSWAP(θ) is a basic two quantum gate. Conversely, when two or more two quantum gates are the "same gate" when the algorithm is created, and two or more pairs of two quantum bit pairs to be targeted exist in the same column or row, processing is possible without using the present invention.

[0119] In this case, the condition for two quantum gates to be the "same gate" is that the rotation angle θ of the PSWAP(θ) gate when decomposed by (Equation 8-1) is equal. It is known that any Control Unitary gate can be decomposed into two CNOT gates and three one-quantum gates. Furthermore, the CNOT gate can be decomposed into two PSWAP(1 / 2) gates.

[0120] Therefore, even if the control unitary gate operates on a different unitary bit depending on the state of the control bit, it can be considered as "the same gate" from the viewpoint of the rotation angle of the PSWAP gate. In the case of "the same gate", a one-quantum gate can have various gates, but the rotation angle of the PSWAP gate, which is a two-quantum gate, is the same. On the other hand, PSWAP(θ) gates generally have different rotation angles θ, so they are not "the same gate".

[0121] Control Unitary gates can be regarded as the same gate, so they can be executed simultaneously, as shown in Fig. 14(d). On the other hand, even if it is a SWAP gate, if the operation is not performed on the entire column, the proposed method must be used as shown in the figure. The details of the SWAP gate decomposition method in this case were explained in Example 2.

[0122] In algorithms other than QFT, Control Unitary gates can be the same gate, so they can be executed simultaneously. However, when implementing general algorithms, they are often not the same gate. In particular, if you want to operate SWAP gates, PSWAP gates, etc. locally on a desired pair of quantum bits, you need to use the method of the present invention.

[0123] Here, we will show an example of QFT. When considering executing the QFT circuit of FIG. 14(a) using a quantum bit array arranged in a lattice as shown in FIG. 14(b), it can be implemented with an equivalent circuit as shown in FIG. 14(c). FIG. 14(c) clearly shows the identity operation created by using the method of the present invention. 2Quantum Operation (3) CROT(π / 2 3 ) gate and (4)CROT(π / 2) gate can be considered "the same gate" because the rotation angles are equal when decomposed into a PSWAP gate.

[0124] Figure 14(d) shows the operation procedure of the two quantum gates (1) to (4) in Figure 14(a) and Figure 14(c) on the quantum bit array layout diagram in Figure 14(b). The method proposed by the present invention is used for all two quantum gate operations except for (3) and (4).

[0125] Specifically, in Fig. 14(d), first, the proposed method of the present invention is used to calculate gates (1) and (2) separately. Next, the proposed method is used to execute a SWAP gate. Next, (3) and (4) are calculated simultaneously by column PSWAP. The CROT gate can be treated as the "same gate".

[0126] Next, we use the proposed method to implement the SWAP gate. Finally, we use the proposed method to calculate gates (5) and (6) individually.

[0127] In the above embodiment, a computational method is provided for implementing a two-quantum gate in a system in which multiple quantum bit pairs are operated by a shared control line, and any desired two-quantum gate is implemented by decomposing it into four or more two-quantum gates with constraints imposed on the product of operations.

[0128] Using the above-mentioned calculation method, a quantum algorithm is described as a gate model using basic gates, and then a calculation processing system is constructed that has three components: a classical calculation device that converts this gate model using basic gates into a pulse sequence of control signals for a quantum computer; a signal section that generates control signals; and a quantum calculation device that operates via a control line that shares multiple quantum bit pairs.

[0129] The interaction operated by the shared control line is the exchange interaction or the XY interaction, and the operation on the multi-qubit pair that is the basic gate is the PSWAP gate or (iSWAP) α Construct a system that serves as a gate.

[0130] Here, the PSWAP gate is a gate given by the power of the SWAP gate (equation 1-1), and satisfies (equation 1-2). Furthermore, the matrix representation of the PSWAP gate is given by (equation 1-3), and the rotation angle α takes a real value between 0 and 2. Also, (iSWAP) α The gate is given by the matrix expression (Equation 1-4), and the rotation angle α takes a real value between 0 and 2.

[0131] Thus, the present invention provides a technique for realizing a desired gate for any two desired quantum bits in a system in which multiple quantum bit pairs are operated by a shared control line.

[0132] In conventional quantum devices, one basic gate operation was basically realized by one control line. However, when integrating quantum bits and increasing the scale, it is necessary to realize multiple quantum bits simultaneously by one control line. In particular, in a system operated by a control line that shares multiple quantum bit pairs, the basic gate's two-quantum gate is an arithmetic operation for multiple quantum bit pairs. In general, quantum algorithms are written using operations for a specific pair of two-quantum gates, so in a system operated by a control line that shares a quantum bit pair, it is necessary to execute a specific pair of two-quantum gates by using a two-quantum gate for multiple quantum bit pairs that are basic gates.

[0133] Therefore, in the present invention, by using a combination of a two-quantum gate and a one-quantum gate for multiple quantum bit pairs whose total rotation angle is an integer multiple of two, a desired two-quantum gate is realized for a desired one-to-two quantum bit, and processing is performed to cancel the effect of the two-quantum gate on quantum bit pairs other than the desired one.

[0134] According to the present invention, it is possible to provide a method for implementing an operation equivalent to a two-quantum gate localized to two specific quantum bits by using an operation on a pair of multiple quantum bits. [Explanation of symbols]

[0135] 60 Host Computer 61 Quantum bit control unit 62 qubit array

Claims

1. A quantum bit array in which a plurality of quantum bits are arranged in a two-dimensional square lattice; A quantum bit control unit that controls the quantum bit array; a shared control line capable of controlling a plurality of quantum bit pairs each formed of a pair of adjacent quantum bits; The quantum bit control unit includes: A quantum computer characterized by controlling some of the quantum bit pairs by a plurality of two-quantum gates that perform calculation processing on the plurality of quantum bit pairs and are given constraints on the product of calculations, and not controlling the quantum bit pairs other than the some of the quantum bit pairs.

2. The shared control line is an interaction control gate for controlling an interaction between quantum bits of the quantum bit pair; The quantum bit array includes:

2. The quantum computer according to claim 1, further comprising a quantum bit control gate for controlling a plurality of said quantum bits.

3. The quantum bit control unit includes: Decomposing the plurality of two-quantum gates into four two-quantum gates, 2. The quantum computer according to claim 1, wherein four of the two-quantum gates are used to control a part of the quantum bit pairs.

4. The quantum bit control unit includes: The quantum computer according to claim 3, characterized in that a combination of four of the two-quantum gates and a plurality of one-quantum gates, whose sum of rotation angles is an integer multiple of two, is performed on a portion of the plurality of quantum bit pairs, and the action of the two-quantum gate is cancelled out on the quantum bit pairs other than the portion of the quantum bit pairs.

5. The interaction operated by the shared control line is an exchange interaction or an XY interaction, The operation on the plurality of quantum bit pairs serving as basic gates is a PSWAP gate or (iSWAP) α It is composed of a gate-like system, The PSWAP gate is a gate given by a power of the SWAP gate (equation 1-1), and satisfies (equation 1-2), The matrix expression of the PSWAP gate is given by (Equation 1-3), and the (iSWAP) α 5. The quantum computer according to claim 4, wherein the matrix representation of the gate is given by (Equation 1-4), and the rotation angle α takes a real value from 0 to 2. [Number 1-1] [Number 1-2] [Number 1-3] [Number 1-4]

6. The quantum bit control unit includes: The four two-quantum gates are configured to have the constraint condition imposed on the rotation angle to form four PSWAP gates, thereby controlling some of the quantum bit pairs among the plurality of quantum bit pairs; 6. The quantum computer according to claim 5, wherein a circuit equivalent to an identity operator is configured by the constraint so that the quantum bit pairs other than the partial quantum bit pairs are not affected by the PSWAP gate.

7. The quantum bit control unit includes:

7. The quantum computer according to claim 6, wherein the constraint is imposed so that a product of four of the PSWAP gates becomes the identity operator.

8. A quantum computer according to claim 7; A host computer that gives an instruction for quantum computing to the quantum bit control unit, The host computer includes: Converting a quantum algorithm based on a gate model using quantum gates into a gate model using basic gates, converting the gate model of the fundamental gate into a control signal pulse sequence; sending said control signal pulse sequence to said quantum bit controller; The quantum bit control unit includes: A quantum computing system, comprising: a quantum bit array; a control signal pulse sequence; and a quantum bit array.

9. The host computer includes: A process of decomposing the unitary quantum equation into a product of a single quantum unitary and a double quantum unitary whose eigenvalues ​​are the magic basis; determining values ​​of the rotation angles of the four PSWAP gates using the eigenvalues ​​of the two quantum unitaries; A process of decomposing the one quantum unitary into elementary operations that can be directly implemented in hardware; By executing 9. The quantum computing system of claim 8, wherein the quantum algorithm is converted into the gate model of the elementary gates.

10. The host computer includes: a general arithmetic unit for performing general arithmetic operations; The quantum bit control unit includes:

9. The quantum computing system according to claim 8, which is configured by a quantum computing device that performs quantum mechanical operations.

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